Address
Address Worstcases
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- Click on the main header (e.g., "Setup" or "Hold") to view more details about how the margin was derived
- Click on the second-level header (e.g., "Margin," "Measurement," or "Pass/Fail") to sort the table by that column
- * Indicates that this measurement column from BER Eye, not PRBS Waveform
Address Worstcases
| |
Signal/Dram |
Status |
Corner |
|
|
Setup |
Hold |
Pulse Width |
tDIVW_1bit |
Min Slew Rate |
Max Slew Rate |
Voltage Margin between Signal and Eye-Mask |
Peak Voltage |
Overshoot |
Undershoot |
Overshoot Area |
Undershoot Area |
|
|---|
| # |
Signal |
Accessed DRAM |
Pass/Fail |
Case |
tUI [ps] |
Widest horizontal eye [mV] |
Reference voltage used [mV] |
Measurement [ps] |
Output Variation [ps] |
Base Requirement [ps] |
Margin [ps] |
Measurement [ps] |
Output Variation [ps] |
Base Requirement [ps] |
Margin [ps] |
Measurement [ps] |
Output Variation [ps] |
Base Requirement [ps] |
Margin [ps] |
Measurement [ps] |
Output Variation [ps] |
Base Requirement [ps] |
Margin [ps] |
Measurement [V/ns] |
Limit [V/ns] |
Margin [V/ns] |
Measurement [V/ns] |
Limit [V/ns] |
Margin [V/ns] |
Margin [mV] |
Above/Below Reference Voltage [mV] |
Above/Below Reference Voltage Required [mV] |
Above/Below Reference Voltage Margin [mV] |
Measurement [mV] |
Limit [mV] |
Margin [mV] |
Measurement [mV] |
Limit [mV] |
Margin [mV] |
Measurement [V*ns] |
Limit [V*ns] |
Margin [V*ns] |
Measurement [V*ns] |
Limit [V*ns] |
Margin [V*ns] |
Monotonic |
| 1 |
LPDDR4_CA0_4 |
U7.H2 |
Pass |
Typ |
1250.0 |
232.1 |
233.1 |
602.8 |
-8.0 |
-188.0 |
407.3 |
588.0 |
-8.0 |
-188.0 |
392.5 |
1238.9 |
-16.0 |
-688.0 |
535.4 |
N/A |
N/A |
N/A |
N/A |
4.000 |
1.000 |
3.000 |
5.522 |
7.000 |
1.478 |
136.842 |
232.6 |
105.0 |
127.6 |
0.0 |
300.0 |
300.0 |
45.7 |
300.0 |
254.3 |
0.000 |
0.100 |
0.100 |
0.005 |
0.100 |
0.095 |
Pass |
| 2 |
LPDDR4_CA1_4 |
U7.J2 |
Pass |
Typ |
1250.0 |
231.1 |
233.1 |
613.3 |
-8.0 |
-188.0 |
417.8 |
584.1 |
-8.0 |
-188.0 |
388.6 |
1244.6 |
-16.0 |
-688.0 |
541.1 |
N/A |
N/A |
N/A |
N/A |
4.200 |
1.000 |
3.200 |
5.181 |
7.000 |
1.819 |
134.844 |
233.9 |
105.0 |
128.9 |
0.0 |
300.0 |
300.0 |
30.0 |
300.0 |
270.0 |
0.000 |
0.100 |
0.100 |
0.003 |
0.100 |
0.097 |
Pass |
| 3 |
LPDDR4_CA2_4 |
U7.H9 |
Pass |
Typ |
1250.0 |
232.4 |
233.1 |
603.9 |
-8.0 |
-188.0 |
408.4 |
582.1 |
-8.0 |
-188.0 |
386.6 |
1238.0 |
-16.0 |
-688.0 |
534.5 |
N/A |
N/A |
N/A |
N/A |
3.816 |
1.000 |
2.816 |
5.255 |
7.000 |
1.745 |
123.776 |
233.0 |
105.0 |
128.0 |
0.0 |
300.0 |
300.0 |
25.6 |
300.0 |
274.4 |
0.000 |
0.100 |
0.100 |
0.003 |
0.100 |
0.097 |
Pass |
| 4 |
LPDDR4_CA3_4 |
U7.H10 |
Pass |
Typ |
1250.0 |
236.3 |
233.1 |
581.9 |
-8.0 |
-188.0 |
386.4 |
604.6 |
-8.0 |
-188.0 |
409.1 |
1240.9 |
-16.0 |
-688.0 |
537.4 |
N/A |
N/A |
N/A |
N/A |
3.815 |
1.000 |
2.815 |
4.756 |
7.000 |
2.244 |
131.969 |
233.4 |
105.0 |
128.4 |
0.0 |
300.0 |
300.0 |
41.1 |
300.0 |
258.9 |
0.000 |
0.100 |
0.100 |
0.005 |
0.100 |
0.095 |
Pass |
| 5 |
LPDDR4_CA4_4 |
U7.H11 |
Pass |
Typ |
1250.0 |
229.8 |
233.1 |
589.3 |
-8.0 |
-188.0 |
393.8 |
601.3 |
-8.0 |
-188.0 |
405.8 |
1242.9 |
-16.0 |
-688.0 |
539.4 |
N/A |
N/A |
N/A |
N/A |
4.011 |
1.000 |
3.011 |
5.075 |
7.000 |
1.925 |
134.060 |
236.6 |
105.0 |
131.6 |
0.0 |
300.0 |
300.0 |
43.9 |
300.0 |
256.1 |
0.000 |
0.100 |
0.100 |
0.005 |
0.100 |
0.095 |
Pass |
| 6 |
LPDDR4_CA5_4 |
U7.J11 |
Pass |
Typ |
1250.0 |
230.3 |
233.1 |
609.9 |
-8.0 |
-188.0 |
414.4 |
586.1 |
-8.0 |
-188.0 |
390.6 |
1243.9 |
-16.0 |
-688.0 |
540.4 |
N/A |
N/A |
N/A |
N/A |
4.161 |
1.000 |
3.161 |
5.120 |
7.000 |
1.880 |
135.447 |
233.8 |
105.0 |
128.8 |
0.0 |
300.0 |
300.0 |
23.9 |
300.0 |
276.1 |
0.000 |
0.100 |
0.100 |
0.003 |
0.100 |
0.097 |
Pass |
| 7 |
LPDDR4_CS_4 |
U7.H4 |
Pass |
Typ |
1250.0 |
233.2 |
233.1 |
580.4 |
-8.0 |
-188.0 |
384.9 |
603.8 |
-8.0 |
-188.0 |
408.3 |
1233.2 |
-16.0 |
-688.0 |
529.7 |
N/A |
N/A |
N/A |
N/A |
3.840 |
1.000 |
2.840 |
4.859 |
7.000 |
2.141 |
88.474 |
236.0 |
105.0 |
131.0 |
0.0 |
300.0 |
300.0 |
51.9 |
300.0 |
248.1 |
0.000 |
0.100 |
0.100 |
0.009 |
0.100 |
0.091 |
Pass |
| 8 |
LPDDR4_CA0_4 |
U7.H2 |
Pass |
Slow |
1250.0 |
244.6 |
244.6 |
602.1 |
-8.0 |
-188.0 |
406.6 |
587.8 |
-8.0 |
-188.0 |
392.3 |
1239.5 |
-16.0 |
-688.0 |
536.0 |
N/A |
N/A |
N/A |
N/A |
3.957 |
1.000 |
2.957 |
5.201 |
7.000 |
1.799 |
148.557 |
244.2 |
105.0 |
139.2 |
0.0 |
300.0 |
300.0 |
43.7 |
300.0 |
256.3 |
0.000 |
0.100 |
0.100 |
0.005 |
0.100 |
0.095 |
Pass |
| 9 |
LPDDR4_CA1_4 |
U7.J2 |
Pass |
Slow |
1250.0 |
244.8 |
244.6 |
612.3 |
-8.0 |
-188.0 |
416.8 |
583.1 |
-8.0 |
-188.0 |
387.6 |
1243.8 |
-16.0 |
-688.0 |
540.3 |
N/A |
N/A |
N/A |
N/A |
4.129 |
1.000 |
3.129 |
4.900 |
7.000 |
2.100 |
145.505 |
245.3 |
105.0 |
140.3 |
0.0 |
300.0 |
300.0 |
28.4 |
300.0 |
271.6 |
0.000 |
0.100 |
0.100 |
0.003 |
0.100 |
0.097 |
Pass |
| 10 |
LPDDR4_CA2_4 |
U7.H9 |
Pass |
Slow |
1250.0 |
243.4 |
244.6 |
602.9 |
-8.0 |
-188.0 |
407.4 |
581.0 |
-8.0 |
-188.0 |
385.5 |
1238.4 |
-16.0 |
-688.0 |
534.9 |
N/A |
N/A |
N/A |
N/A |
3.738 |
1.000 |
2.738 |
4.936 |
7.000 |
2.064 |
137.512 |
244.5 |
105.0 |
139.5 |
0.0 |
300.0 |
300.0 |
25.3 |
300.0 |
274.7 |
0.000 |
0.100 |
0.100 |
0.004 |
0.100 |
0.096 |
Pass |
| 11 |
LPDDR4_CA3_4 |
U7.H10 |
Pass |
Slow |
1250.0 |
247.1 |
244.6 |
580.9 |
-8.0 |
-188.0 |
385.4 |
604.1 |
-8.0 |
-188.0 |
408.6 |
1240.1 |
-16.0 |
-688.0 |
536.6 |
N/A |
N/A |
N/A |
N/A |
3.696 |
1.000 |
2.696 |
4.485 |
7.000 |
2.515 |
144.783 |
244.9 |
105.0 |
139.9 |
0.0 |
300.0 |
300.0 |
39.6 |
300.0 |
260.4 |
0.000 |
0.100 |
0.100 |
0.005 |
0.100 |
0.095 |
Pass |
| 12 |
LPDDR4_CA4_4 |
U7.H11 |
Pass |
Slow |
1250.0 |
242.0 |
244.6 |
588.1 |
-8.0 |
-188.0 |
392.6 |
600.3 |
-8.0 |
-188.0 |
404.8 |
1242.5 |
-16.0 |
-688.0 |
539.0 |
N/A |
N/A |
N/A |
N/A |
3.859 |
1.000 |
2.859 |
4.769 |
7.000 |
2.231 |
145.962 |
248.3 |
105.0 |
143.3 |
0.0 |
300.0 |
300.0 |
42.7 |
300.0 |
257.3 |
0.000 |
0.100 |
0.100 |
0.005 |
0.100 |
0.095 |
Pass |
| 13 |
LPDDR4_CA5_4 |
U7.J11 |
Pass |
Slow |
1250.0 |
244.9 |
244.6 |
609.1 |
-8.0 |
-188.0 |
413.6 |
586.2 |
-8.0 |
-188.0 |
390.7 |
1244.2 |
-16.0 |
-688.0 |
540.7 |
N/A |
N/A |
N/A |
N/A |
4.108 |
1.000 |
3.108 |
4.785 |
7.000 |
2.215 |
146.330 |
245.4 |
105.0 |
140.4 |
0.0 |
300.0 |
300.0 |
22.6 |
300.0 |
277.4 |
0.000 |
0.100 |
0.100 |
0.003 |
0.100 |
0.097 |
Pass |
| 14 |
LPDDR4_CS_4 |
U7.H4 |
Pass |
Slow |
1250.0 |
244.5 |
244.6 |
579.5 |
-8.0 |
-188.0 |
384.0 |
603.1 |
-8.0 |
-188.0 |
407.6 |
1232.2 |
-16.0 |
-688.0 |
528.7 |
N/A |
N/A |
N/A |
N/A |
3.544 |
1.000 |
2.544 |
4.567 |
7.000 |
2.433 |
102.858 |
247.7 |
105.0 |
142.7 |
0.0 |
300.0 |
300.0 |
55.6 |
300.0 |
244.4 |
0.000 |
0.100 |
0.100 |
0.009 |
0.100 |
0.091 |
Pass |
| 15 |
LPDDR4_CA0_4 |
U7.H2 |
Pass |
Fast |
1250.0 |
232.4 |
234.3 |
602.0 |
-8.0 |
-188.0 |
406.5 |
587.9 |
-8.0 |
-188.0 |
392.4 |
1238.6 |
-16.0 |
-688.0 |
535.1 |
N/A |
N/A |
N/A |
N/A |
3.897 |
1.000 |
2.897 |
5.207 |
7.000 |
1.793 |
138.773 |
233.4 |
105.0 |
128.4 |
0.0 |
300.0 |
300.0 |
43.8 |
300.0 |
256.2 |
0.000 |
0.100 |
0.100 |
0.005 |
0.100 |
0.095 |
Pass |
| 16 |
LPDDR4_CA1_4 |
U7.J2 |
Pass |
Fast |
1250.0 |
231.4 |
234.3 |
612.5 |
-8.0 |
-188.0 |
417.0 |
583.7 |
-8.0 |
-188.0 |
388.2 |
1243.7 |
-16.0 |
-688.0 |
540.2 |
N/A |
N/A |
N/A |
N/A |
4.056 |
1.000 |
3.056 |
5.004 |
7.000 |
1.996 |
136.957 |
234.8 |
105.0 |
129.8 |
0.0 |
300.0 |
300.0 |
29.0 |
300.0 |
271.0 |
0.000 |
0.100 |
0.100 |
0.003 |
0.100 |
0.097 |
Pass |
| 17 |
LPDDR4_CA2_4 |
U7.H9 |
Pass |
Fast |
1250.0 |
232.5 |
234.3 |
603.8 |
-8.0 |
-188.0 |
408.3 |
582.7 |
-8.0 |
-188.0 |
387.2 |
1237.3 |
-16.0 |
-688.0 |
533.8 |
N/A |
N/A |
N/A |
N/A |
3.789 |
1.000 |
2.789 |
5.045 |
7.000 |
1.955 |
125.595 |
233.8 |
105.0 |
128.8 |
0.0 |
300.0 |
300.0 |
24.4 |
300.0 |
275.6 |
0.000 |
0.100 |
0.100 |
0.003 |
0.100 |
0.097 |
Pass |
| 18 |
LPDDR4_CA3_4 |
U7.H10 |
Pass |
Fast |
1250.0 |
237.1 |
234.3 |
582.2 |
-8.0 |
-188.0 |
386.7 |
604.6 |
-8.0 |
-188.0 |
409.1 |
1241.2 |
-16.0 |
-688.0 |
537.7 |
N/A |
N/A |
N/A |
N/A |
3.855 |
1.000 |
2.855 |
4.657 |
7.000 |
2.343 |
134.208 |
234.1 |
105.0 |
129.1 |
0.0 |
300.0 |
300.0 |
40.1 |
300.0 |
259.9 |
0.000 |
0.100 |
0.100 |
0.005 |
0.100 |
0.095 |
Pass |
| 19 |
LPDDR4_CA4_4 |
U7.H11 |
Pass |
Fast |
1250.0 |
231.8 |
234.3 |
588.7 |
-8.0 |
-188.0 |
393.2 |
601.5 |
-8.0 |
-188.0 |
406.0 |
1243.3 |
-16.0 |
-688.0 |
539.8 |
N/A |
N/A |
N/A |
N/A |
3.956 |
1.000 |
2.956 |
4.908 |
7.000 |
2.092 |
136.553 |
237.0 |
105.0 |
132.0 |
0.0 |
300.0 |
300.0 |
42.3 |
300.0 |
257.7 |
0.000 |
0.100 |
0.100 |
0.005 |
0.100 |
0.095 |
Pass |
| 20 |
LPDDR4_CA5_4 |
U7.J11 |
Pass |
Fast |
1250.0 |
231.6 |
234.3 |
608.8 |
-8.0 |
-188.0 |
413.3 |
585.9 |
-8.0 |
-188.0 |
390.4 |
1243.2 |
-16.0 |
-688.0 |
539.7 |
N/A |
N/A |
N/A |
N/A |
4.000 |
1.000 |
3.000 |
4.909 |
7.000 |
2.091 |
138.190 |
234.6 |
105.0 |
129.6 |
0.0 |
300.0 |
300.0 |
22.4 |
300.0 |
277.6 |
0.000 |
0.100 |
0.100 |
0.003 |
0.100 |
0.097 |
Pass |
| 21 |
LPDDR4_CS_4 |
U7.H4 |
Pass |
Fast |
1250.0 |
236.3 |
234.3 |
580.8 |
-8.0 |
-188.0 |
385.3 |
603.7 |
-8.0 |
-188.0 |
408.2 |
1234.6 |
-16.0 |
-688.0 |
531.1 |
N/A |
N/A |
N/A |
N/A |
3.801 |
1.000 |
2.801 |
4.860 |
7.000 |
2.140 |
89.491 |
237.5 |
105.0 |
132.5 |
0.0 |
300.0 |
300.0 |
46.0 |
300.0 |
254.0 |
0.000 |
0.100 |
0.100 |
0.008 |
0.100 |
0.092 |
Pass |