Differential Nets
Differential Nets Worstcases
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- Click on the main header (e.g., "Setup" or "Hold") to view more details about how the margin was derived
- Click on the second-level header (e.g., "Margin," "Measurement," or "Pass/Fail") to sort the table by that column
- * Indicates that this measurement column from BER Eye, not PRBS Waveform
Differential Nets Worstcases
| |
Signal/Driver/Receicer |
Status |
Corner |
Overshoot |
Undershoot |
Overshoot Area |
Undershoot Area |
Vix |
Vinse Peak-to-peak |
Vinse High |
Vinse Low |
|
|---|
| # |
Signal |
Driver.Pins |
Receiver.Pins |
Operation |
Pass/Fail |
Case |
Measurement [mV] |
Limit [mV] |
Margin [mV] |
Measurement [mV] |
Limit [mV] |
Margin [mV] |
Measurement [V*ns] |
Limit [V*ns] |
Margin [V*ns] |
Measurement [V*ns] |
Limit [V*ns] |
Margin [V*ns] |
Measurement [mV] |
Limit [mV] |
Margin [mV] |
Measurement [mV] |
Limit [mV] |
Margin [mV] |
Measurement [mV] |
Limit [mV] |
Margin [mV] |
Measurement [mV] |
Limit [mV] |
Margin [mV] |
Monotonic |
| 1 |
LPDDR4_CK_4_P |
U6.J1&K1 |
U7.J8&J9 |
Write rank(1,1) |
Pass |
Typ |
0.0 |
300.0 |
300.0 |
39.1 |
300.0 |
260.9 |
0.000 |
0.100 |
0.100 |
0.002 |
0.100 |
0.098 |
12.350 |
152.650 |
140.3 |
602.6 |
210.0 |
392.6 |
338.700 |
105.000 |
233.7 |
256.0 |
105.0 |
151.0 |
Pass |
| 2 |
LPDDR4_DQS0_4_P |
U7.D3&E3 |
U6.D1&E1 |
Read rank(1,1) |
Pass |
Typ |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
364.2 |
180.0 |
184.2 |
177.900 |
90.0 |
87.9 |
185.5 |
90.000 |
95.5 |
N/A |
| 3 |
LPDDR4_DQS0_4_P |
U6.D1&E1 |
U7.D3&E3 |
Write rank(1,1) |
Pass |
Typ |
0.0 |
300.0 |
300.0 |
23.0 |
300.0 |
277.0 |
0.000 |
0.100 |
0.100 |
0.002 |
0.100 |
0.098 |
16.700 |
119.500 |
102.8 |
594.8 |
180.0 |
414.8 |
332.9 |
90.000 |
242.9 |
256.300 |
90.0 |
166.3 |
Pass |
| 4 |
LPDDR4_DQS1_4_P |
U7.D10&E10 |
U6.T1&R1 |
Read rank(1,1) |
Pass |
Typ |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
363.3 |
180.0 |
183.3 |
176.400 |
90.0 |
86.4 |
185.400 |
90.000 |
95.4 |
N/A |
| 5 |
LPDDR4_DQS1_4_P |
U6.T1&R1 |
U7.D10&E10 |
Write rank(1,1) |
Pass |
Typ |
0.0 |
300.0 |
300.0 |
22.1 |
300.0 |
277.9 |
0.000 |
0.100 |
0.100 |
0.003 |
0.100 |
0.098 |
27.5 |
119.4 |
91.9 |
591.4 |
180.0 |
411.4 |
333.1 |
90.000 |
243.1 |
259.0 |
90.0 |
169.0 |
Pass |
| 6 |
LPDDR4_CK_4_P |
U6.J1&K1 |
U7.J8&J9 |
Write rank(1,1) |
Pass |
Slow |
0.0 |
300.0 |
300.0 |
35.9 |
300.0 |
264.1 |
0.000 |
0.100 |
0.100 |
0.002 |
0.100 |
0.098 |
9.950 |
146.25 |
136.3 |
569.3 |
210.0 |
359.3 |
300.4 |
105.000 |
195.4 |
265.4 |
105.0 |
160.4 |
Pass |
| 7 |
LPDDR4_DQS0_4_P |
U7.D3&E3 |
U6.D1&E1 |
Read rank(1,1) |
Pass |
Slow |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
356.4 |
180.0 |
176.4 |
177.400 |
90.0 |
87.4 |
177.7 |
90.000 |
87.7 |
N/A |
| 8 |
LPDDR4_DQS0_4_P |
U6.D1&E1 |
U7.D3&E3 |
Write rank(1,1) |
Pass |
Slow |
0.0 |
300.0 |
300.0 |
23.2 |
300.0 |
276.8 |
0.000 |
0.100 |
0.100 |
0.002 |
0.100 |
0.098 |
12.700 |
114.0 |
101.3 |
567.0 |
180.0 |
387.0 |
295.400 |
90.0 |
205.4 |
265.7 |
90.0 |
175.7 |
Pass |
| 9 |
LPDDR4_DQS1_4_P |
U7.D10&E10 |
U6.T1&R1 |
Read rank(1,1) |
Pass |
Slow |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
355.0 |
180.0 |
175.0 |
176.100 |
90.0 |
86.1 |
177.600 |
90.000 |
87.6 |
N/A |
| 10 |
LPDDR4_DQS1_4_P |
U6.T1&R1 |
U7.D10&E10 |
Write rank(1,1) |
Pass |
Slow |
0.0 |
300.0 |
300.0 |
22.3 |
300.0 |
277.7 |
0.000 |
0.100 |
0.100 |
0.002 |
0.100 |
0.098 |
24.350 |
113.950 |
89.6 |
563.6 |
180.0 |
383.6 |
295.100 |
90.0 |
205.1 |
268.7 |
90.0 |
178.7 |
Pass |
| 11 |
LPDDR4_CK_4_P |
U6.J1&K1 |
U7.J8&J9 |
Write rank(1,1) |
Pass |
Fast |
0.0 |
300.0 |
300.0 |
34.4 |
300.0 |
265.6 |
0.000 |
0.100 |
0.100 |
0.002 |
0.100 |
0.098 |
13.050 |
155.850 |
142.8 |
619.7 |
210.0 |
409.7 |
368.7 |
105.0 |
263.7 |
252.0 |
105.0 |
147.0 |
Pass |
| 12 |
LPDDR4_DQS0_4_P |
U7.D3&E3 |
U6.D1&E1 |
Read rank(1,1) |
Pass |
Fast |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
386.6 |
180.0 |
206.6 |
188.3 |
90.0 |
98.3 |
197.600 |
90.000 |
107.6 |
N/A |
| 13 |
LPDDR4_DQS0_4_P |
U6.D1&E1 |
U7.D3&E3 |
Write rank(1,1) |
Pass |
Fast |
0.0 |
300.0 |
300.0 |
20.9 |
300.0 |
279.1 |
0.000 |
0.100 |
0.100 |
0.002 |
0.100 |
0.098 |
16.850 |
126.450 |
109.6 |
630.1 |
180.0 |
450.1 |
371.2 |
90.0 |
281.2 |
255.900 |
90.0 |
165.9 |
Pass |
| 14 |
LPDDR4_DQS1_4_P |
U7.D10&E10 |
U6.T1&R1 |
Read rank(1,1) |
Pass |
Fast |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
385.5 |
180.0 |
205.5 |
186.8 |
90.0 |
96.8 |
197.600 |
90.000 |
107.6 |
N/A |
| 15 |
LPDDR4_DQS1_4_P |
U6.T1&R1 |
U7.D10&E10 |
Write rank(1,1) |
Pass |
Fast |
0.0 |
300.0 |
300.0 |
20.3 |
300.0 |
279.7 |
0.000 |
0.100 |
0.100 |
0.002 |
0.100 |
0.098 |
28.650 |
126.55 |
97.9 |
628.3 |
180.0 |
448.3 |
370.100 |
90.0 |
280.1 |
258.100 |
90.0 |
168.1 |
Pass |