CLK-DQS Skew
CLK-DQS Skew Worstcases
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CLK-DQS Skew Worstcases
| |
Signal/Dram |
Status |
Corner |
DQSS - Earliest DQS |
DQSS - Latest DQS |
tDSS |
tDSH |
|---|
| # |
Signal |
Accessed DRAM |
DRAM CLK Pins |
DRAM DQS Pins |
Pass/Fail |
Case |
Allowed Early DQS Skew [ps] |
DQS Arrival Time [ps] |
CLK Arrival Time [ps] |
Max Early DQS Launch Skew [ps] |
Margin [ps] |
Allowed Late DQS Skew [ps] |
DQS Arrival Time [ps] |
CLK Arrival Time [ps] |
Max Late DQS Launch Skew [ps] |
Margin [ps] |
Measurement [ps] |
Earliest DQS Launch Skew [ps] |
Base Requirement [ps] |
Margin [ps] |
Measurement [ps] |
Latest DQS Launch Skew [ps] |
Base Requirement [ps] |
Margin [ps] |
| 1 |
LPDDR4_DQS0_4_P |
U7 |
J8&J9 |
D3&E3 |
Pass |
Typ |
312.5 |
21181.0 |
21212.0 |
8.0 |
273.2 |
312.5 |
7431.0 |
7462.0 |
8.0 |
335.5 |
N/A |
-8.0 |
-250.0 |
N/A |
593.9 |
-8.0 |
-250.0 |
335.9 |
| 2 |
LPDDR4_DQS1_4_P |
U7 |
J8&J9 |
D10&E10 |
Pass |
Typ |
312.5 |
2441.0 |
2462.0 |
8.000 |
282.8 |
312.5 |
3691.0 |
3712.0 |
8.0 |
326.0 |
N/A |
-8.000 |
-250.0 |
N/A |
603.3 |
-8.0 |
-250.0 |
345.3 |
| 3 |
LPDDR4_DQS0_4_P |
U7 |
J8&J9 |
D3&E3 |
Pass |
Slow |
312.5 |
21227.0 |
21258.0 |
8.0 |
273.3 |
312.5 |
7478.0 |
7508.0 |
8.0 |
335.3 |
N/A |
-8.0 |
-250.0 |
N/A |
594.0 |
-8.000 |
-250.0 |
336.0 |
| 4 |
LPDDR4_DQS1_4_P |
U7 |
J8&J9 |
D10&E10 |
Pass |
Slow |
312.5 |
21237.0 |
21258.0 |
8.000 |
283.5 |
312.5 |
6238.0 |
6258.0 |
8.0 |
325.3 |
N/A |
-8.000 |
-250.0 |
N/A |
604.1 |
-8.0 |
-250.0 |
346.1 |
| 5 |
LPDDR4_DQS0_4_P |
U7 |
J8&J9 |
D3&E3 |
Pass |
Fast |
312.5 |
2409.0 |
2440.0 |
8.0 |
273.5 |
312.5 |
3659.0 |
3690.0 |
8.0 |
335.3 |
N/A |
-8.0 |
-250.0 |
N/A |
593.9 |
-8.0 |
-250.0 |
335.9 |
| 6 |
LPDDR4_DQS1_4_P |
U7 |
J8&J9 |
D10&E10 |
Pass |
Fast |
312.5 |
2419.0 |
2440.0 |
8.0 |
283.0 |
312.5 |
19919.0 |
19940.0 |
8.0 |
325.7 |
N/A |
-8.0 |
-250.0 |
N/A |
603.3 |
-8.0 |
-250.0 |
345.3 |