Setup Info

Design: 3TI098000001_R0.HYP

VX2.14 build 24257734

Date: Jan-21-2025 9h-08m

Setup Information

Interface Setup

Parameter Value
1 DDR Interface LPDDR4
2 Crosstalk Enabled
3 Power-Aware Disabled
4 IC Corners Fast, Typ, Slow
5 Probing location Controller - at Die, DRAM - at Die
6 Total Run Time 0 Days, 00 Hours, 05 Minutes 59 Seconds

Rank Setup

Rank Ref. Des. IBIS File Component Timing Model Speed Grade
1 Controller U6 AM625-Q1.ibs AM62_AMC C:\MentorGraphics\HLVX.2.14\SDD_HOME\hyperlynx64\Libs\lpddr4_ctl.v DDR_1600
2 Rank[1,1] U7 is43-46lq16512a_32512a.ibs IS46LQ16512A-046BLA3 C:\MentorGraphics\HLVX.2.14\SDD_HOME\hyperlynx64\Libs\lpddr4_dram.v DDR_1866

IBIS Model Selectors

Rank CLK Addr CTL
1 Controller lpddr4_ocd_40p_40n_diff lpddr4_ocd_40p_40n lpddr4_ocd_40p_40n
2 Rank[1,1] CK_IN_ODT40_4267 CA_IN_ODT40_4267 CS_IN_ODT40_4267

ODT Setup Information

ODT - Write to Slot 1

Rank DQS DQ DM
1 Controller lpddr4_ocd_40p_40n_diff, lpddr4_ocd_40p_40n, lpddr4_ocd_40p_40n,
2 Rank[1,1] DQS_IN_ODT40_4267 DQ_IN_ODT40_4267 DQ_IN_ODT40_4267

ODT - Read from Slot 1

Rank DQS DQ DM
1 Controller lpddr4_odt_40_diff, lpddr4_odt_40, lpddr4_odt_40,
2 Rank[1,1] DQS_OUT_VDDQ30_ODTDIS_PD40_4267 DQ_OUT_VDDQ30_ODTDIS_PD40_4267 DQ_OUT_VDDQ30_ODTDIS_PD40_4267