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 /**
 *  \file     Eth_Cfg.c
 *
 *  \brief    This file contains generated LinkTime configuration file
 *            for ETH MCAL driver
 */

/*******************************************************************************
    Project         : TDA4AEN_MCAL
    Date            : 2026-03-14 09:17:10
    SW Ver          : 10.1.0
    Module Rele Ver : AUTOSAR 4.3.1 0

    This file is generated by EB Tresos
    Do not modify this file,otherwise the software may behave in unexpected way.
*******************************************************************************/

/*******************************************************************************
 * Standard Header Files
 ******************************************************************************/
#include "Eth_Cfg.h"

/*******************************************************************************
 * Constants for LinkTime Configuration
 ******************************************************************************/
#define  ETH_START_SEC_CONST_UNSPECIFIED
#include "Eth_MemMap.h"

/**
 * \brief Cpsw register configuration
 */
CONST(Eth_CpswConfigType, ETH_VAR_NO_INIT) Eth_CpswCfg[1U] =
{
    {
        /* phyMacAddr           */ 0x43000200U,
        /* aleAddr              */ 0x803e000U,
        /* cptsAddr             */ 0x803d000U,
        /* mdioAddr             */ 0x8000f00U,
        /* ctrlAddr             */ 0x8020000U,
        /* cppiClockFreqHz      */ 250000000U,
        /* enableMdioIrq        */ TRUE,
        /* mdioBusFreqHz        */ 2200000U,
        /* mdioOpMode           */ ETH_MDIO_OPMODE_NORMAL,
        /* cptsRefClockFreq     */ 4U,
    }
};

#define  ETH_STOP_SEC_CONST_UNSPECIFIED
#include "Eth_MemMap.h"
#define  ETH_START_SEC_VAR_NO_INIT_UNSPECIFIED_128
#include "Eth_MemMap.h"


/**
 *  \brief Free queue for egress fifo
 *  @{
 */
VAR(uint64, ETH_VAR_NO_INIT_128) Eth_RingMem_Ctrl_0_Fq_Egress_0[4U];
/* @} */

/**
 *  \brief Free queue for ingress fifo
 *  @{
 */
VAR(uint64, ETH_VAR_NO_INIT_128) Eth_RingMem_Ctrl_0_Fq_Ingress_0[4U];
/* @} */


#define  ETH_STOP_SEC_VAR_NO_INIT_UNSPECIFIED_128
#include "Eth_MemMap.h"

#define  ETH_START_SEC_VAR_NO_INIT_UNSPECIFIED
#include "Eth_MemMap.h"

/**
 *  \brief Dma ring dynamic variable
 */
VAR(Eth_Udma_RingDynType, ETH_VAR_NO_INIT) Eth_RingDyn_Ctrl_0[2U];


#define  ETH_STOP_SEC_VAR_NO_INIT_UNSPECIFIED
#include "Eth_MemMap.h"

#define  ETH_START_SEC_VAR_NO_INIT_UNSPECIFIED_128
#include "Eth_MemMap.h"

/**
 *  \brief Egress data buffer memory
 */
VAR(uint8, ETH_VAR_NO_INIT_128) Eth_Ctrl_0_Egress_BufferMem_0[6144U];

/**
 *  \brief Egress DMA descriptor memory
 */
VAR(Eth_DescType, ETH_VAR_NO_INIT_128) Eth_Ctrl_0_Egress_Descriptor_0[4U];

#define  ETH_STOP_SEC_VAR_NO_INIT_UNSPECIFIED_128
#include "Eth_MemMap.h"

#define ETH_START_SEC_VAR_NO_INIT_8
#include "Eth_MemMap.h"

/**
 *  \brief Egress buffer state memory
 */
VAR(uint8, ETH_VAR_NO_INIT) Eth_Ctrl_0_Egress_BufferState_0[4U];

#define ETH_STOP_SEC_VAR_NO_INIT_8
#include "Eth_MemMap.h"

#define  ETH_START_SEC_VAR_NO_INIT_UNSPECIFIED
#include "Eth_MemMap.h"

/**
 *  \brief Egress queue descriptor memory
 */
VAR(Eth_QueueType, ETH_VAR_NO_INIT) Eth_Ctrl_0_Egress_Queue_0[1U];

#define  ETH_STOP_SEC_VAR_NO_INIT_UNSPECIFIED
#include "Eth_MemMap.h"

#define  ETH_START_SEC_VAR_NO_INIT_UNSPECIFIED_128
#include "Eth_MemMap.h"

/**
 *  \brief Ingress data buffer memory
 */
VAR(uint8, ETH_VAR_NO_INIT_128) Eth_Ctrl_0_Ingress_BufferMem_0[6144U];

/**
 *  \brief Ingress DMA descriptor memory
 */
VAR(Eth_DescType, ETH_VAR_NO_INIT_128) Eth_Ctrl_0_Ingress_Descriptor_0[4U];

#define  ETH_STOP_SEC_VAR_NO_INIT_UNSPECIFIED_128
#include "Eth_MemMap.h"

#define ETH_START_SEC_VAR_NO_INIT_8
#include "Eth_MemMap.h"

/**
 *  \brief Ingress buffer state memory
 */
VAR(uint8, ETH_VAR_NO_INIT) Eth_Ctrl_0_Ingress_BufferState_0[4U];

#define ETH_STOP_SEC_VAR_NO_INIT_8
#include "Eth_MemMap.h"

#define  ETH_START_SEC_VAR_NO_INIT_UNSPECIFIED
#include "Eth_MemMap.h"

/**
 *  \brief Ingress queue descriptor memory
 */
VAR(Eth_QueueType, ETH_VAR_NO_INIT) Eth_Ctrl_0_Ingress_Queue_0[1U];

#define  ETH_STOP_SEC_VAR_NO_INIT_UNSPECIFIED
#include "Eth_MemMap.h"

#define  ETH_START_SEC_CONST_UNSPECIFIED
#include "Eth_MemMap.h"

/**
 *  \brief Dma Ring configuration
 */
CONST(Eth_Udma_RingCfgType, ETH_VAR_NO_INIT) Eth_Udma_RingCfg_0[2U] =
{
    {
        /* memPtr               */ Eth_RingMem_Ctrl_0_Fq_Egress_0,
        /* hwId                 */ 13U,
        /* size                 */ 4U,
        /* priority             */ 0U
    },
    {
        /* memPtr               */ Eth_RingMem_Ctrl_0_Fq_Ingress_0,
        /* hwId                 */ 113U,
        /* size                 */ 4U,
        /* priority             */ 0U
    },
};


/**
 *  \brief Dma Event configuration
 */
CONST(Eth_Udma_EventCfgType, ETH_VAR_NO_INIT) Eth_EventCfg_Ctrl_0[2U] =
{
    {
        /* coreIntrNum          */ 68U,
        /* virtIntrNum          */ 172U,
        /* IrIntrNum            */ ETH_INVALID_IRQ_ID
    },
    {
        /* coreIntrNum          */ 69U,
        /* virtIntrNum          */ 173U,
        /* IrIntrNum            */ ETH_INVALID_IRQ_ID
    }
};

/**
 *  \brief Dma Ring Event configuration
 */
CONST(Eth_Udma_RingEventCfgType, ETH_VAR_NO_INIT) Eth_RingEventCfg_Ctrl_0[2U] =
{
    {
        /* ringIdx              */ 0U,
        /* eventIdx             */ 0U,
        /* virtBitNum           */ 0U,
        /* globalEvent          */ 785U,
        /* srcOffset            */ 4608U
    },
    {
        /* ringIdx              */ 1U,
        /* eventIdx             */ 1U,
        /* virtBitNum           */ 0U,
        /* globalEvent          */ 786U,
        /* srcOffset            */ 5533U
    },
};

/**
 *  \brief Dma Egress fifo map to DMA ring configuration
 */
CONST(Eth_FifoRingMapCfgType, ETH_VAR_NO_INIT) Eth_EgressFifoRingMap_Ctrl_0[1U] =
{
    {
        /* ringCqIdx            */ 0U,
        /* ringFqIdx            */ 0U
    },
};

/**
 *  \brief Dma Ingress fifo map to DMA ring configuration
 */
CONST(Eth_FifoRingMapCfgType, ETH_VAR_NO_INIT) Eth_IngressFifoRingMap_Ctrl_0[1U] =
{
    {
        /* cqRingIdx            */ 1U,
        /* fqRingIdx            */ 1U
    },
};

/**
 *  \brief Dma Tx channel configuration
 */
CONST(Eth_ChannelCfgType, ETH_VAR_NO_INIT) Eth_TxChannelCfg_Ctrl_0[1U] =
{
    {
        /* tdCqRingIdx          */ 2U,
        /* chId                 */ 13U
    },
};

/**
 *  \brief Dma Rx channel configuration
 */
CONST(Eth_ChannelCfgType, ETH_VAR_NO_INIT) Eth_RxChannelCfg_Ctrl_0[1U] =
{
    {
        /* tdCqRingIdx          */ 2U,
        /* chId                 */ 14U
    },
};

/**
 *  \brief Dma channel flow configuration
 */
CONST(Eth_ChannelFlowCfgType, ETH_VAR_NO_INIT) Eth_RxFlowCfg_Ctrl_0[1U] =
{
    {
        /* flowNum              */ 1U,
        /* startFlowId          */ 14U
    },
};

/**
 *  \brief Dma flow configuration
 */
CONST(Eth_FlowCfgType, ETH_VAR_NO_INIT) Eth_FlowCfg_Ctrl_0[1U] =
{
    {
        /* cqRingIdx            */ 1U,
        /* fqRingIdx            */ 1U,
        /* flowId               */ 14U
    },
};

/**
 *  \brief Eth Egress fifo configuration
 */
CONST(Eth_FifoHandleType, ETH_VAR_NO_INIT) Eth_FiFoEgressCfg_Ctrl_0[1U] =
{
    {
        /* fifoBufferPtr        */ Eth_Ctrl_0_Egress_BufferMem_0,
        /* descPtr              */ Eth_Ctrl_0_Egress_Descriptor_0,
        /* queuePtr             */ Eth_Ctrl_0_Egress_Queue_0,
        /* bufferState          */ Eth_Ctrl_0_Egress_BufferState_0,
        /* fifoNum              */ 4U,
        /* elemSize             */ 1536U,
        /* pktSize              */ 1522U,
        /* totalSize            */ 6144U
    },
};

/**
 *  \brief Eth Ingress fifo configuration
 */
CONST(Eth_FifoHandleType, ETH_VAR_NO_INIT) Eth_FiFoIngressCfg_Ctrl_0[1U] =
{
    {
        /* fifoBufferPtr        */ Eth_Ctrl_0_Ingress_BufferMem_0,
        /* descPtr              */ Eth_Ctrl_0_Ingress_Descriptor_0,
        /* queuePtr             */ Eth_Ctrl_0_Ingress_Queue_0,
        /* bufferState          */ Eth_Ctrl_0_Ingress_BufferState_0,
        /* fifoNum              */ 4U,
        /* elemSize             */ 1536U,
        /* pktSize              */ 1522U,
        /* totalSize            */ 6144U
    },
};

/**
 *  \brief Eth Egress Fifo priority assignment
 */
CONST(uint8, ETH_VAR_NO_INIT) Eth_EgressFifoPriorityAsignment_0[8U] =
{
    0U,
    0U,
    0U,
    0U,
    0U,
    0U,
    0U,
    0U,
};

/**
 *  \brief Eth Ingress Fifo priority assignment
 */
CONST(uint8, ETH_VAR_NO_INIT) Eth_IgressFifoPriorityAsignment_0[8U] =
{
    0U,
    0U,
    0U,
    0U,
    0U,
    0U,
    0U,
    0U,
};

/**
 *  \brief Eth DMA configuration
 */
CONST(Eth_Udma_CfgType, ETH_VAR_NO_INIT) Eth_UdmaCfg_Ctrl_0[1U] =
{
    {
        /* eventCfgPtr              */ (Eth_Udma_EventCfgType *)Eth_EventCfg_Ctrl_0,
        /* ringCfgPtr               */ (Eth_Udma_RingCfgType *)Eth_Udma_RingCfg_0,
        /* ringDynPtr               */ (Eth_Udma_RingDynType *)Eth_RingDyn_Ctrl_0,
        /* ringEvenCfgPtr           */ (Eth_Udma_RingEventCfgType *)Eth_RingEventCfg_Ctrl_0,
        /* egressFifoCfgPtr         */ (Eth_FifoHandleType *)Eth_FiFoEgressCfg_Ctrl_0,
        /* ingressFifoCfgPtr        */ (Eth_FifoHandleType *)Eth_FiFoIngressCfg_Ctrl_0,
        /* egressFifoRingMapCfgPtr  */ (Eth_FifoRingMapCfgType *)Eth_EgressFifoRingMap_Ctrl_0,
        /* ingressFifoRingMapCfgPtr */ (Eth_FifoRingMapCfgType *)Eth_IngressFifoRingMap_Ctrl_0,
        /* egressFifoPrioAssignCfgPtr  */ (uint8 *)Eth_EgressFifoPriorityAsignment_0,
        /* ingressFifoPrioAssignCfgPtr */ (uint8 *)Eth_IgressFifoPriorityAsignment_0,
        /* txChanCfgPtr             */ (Eth_ChannelCfgType *)Eth_TxChannelCfg_Ctrl_0,
        /* rxChanCfgPtr             */ (Eth_ChannelCfgType *)Eth_RxChannelCfg_Ctrl_0,
        /* rxChanFlowCfgPtr         */ (Eth_ChannelFlowCfgType *)Eth_RxFlowCfg_Ctrl_0,
        /* flowCfgPtr               */ (Eth_FlowCfgType *)Eth_FlowCfg_Ctrl_0,
        /* startTxNum               */ 13U,
        /* startRxNum               */ 14U,
        /* totalEventNum            */ 2U,
        /* totalRingNum             */ 2U,
        /* totalRingEventNum        */ 2U,
        /* txThresholdNum           */ 1U,
        /* rxThresholdNum           */ 1U,
        /* totalEgressFifoNum       */ 1U,
        /* totalInressFifoNum       */ 1U,
        /* totalTxChanNum           */ 1U,
        /* totalRxChanNum           */ 1U,
        /* totalFlowNum             */ 1U,
        /* txCoreIrq                */ 68U,
        /* rxCoreIrq                */ 69U,
        /* rxMtuLength              */ 1522U,
        /* EthDmaRingCfgOps         */ (Eth_DmaRingCfg)NULL_PTR
    }
};


/**
 *  \brief Eth dem event configuration
 */
CONST(uint16, ETH_VAR_NO_INIT) Eth_DemEventCfg_0[11u] =
{
    /* E_HARDWARE_ERROR             */ ETH_DEM_NO_EVENT,
    /* E_LATECOLLISION              */ ETH_DEM_NO_EVENT,
    /* E_MULTIPLECOLLISION          */ ETH_DEM_NO_EVENT,
    /* E_SINGLECOLLISION            */ ETH_DEM_NO_EVENT,
    /* E_ALIGNMENT                  */ ETH_DEM_NO_EVENT,
    /* E_OVERSIZEFRAME              */ ETH_DEM_NO_EVENT,
    /* E_UNDERSIZEFRAME             */ ETH_DEM_NO_EVENT,
    /* E_CRC                        */ ETH_DEM_NO_EVENT,
    /* E_RX_FRAMES_LOST             */ ETH_DEM_NO_EVENT,
    /* E_ACCESS                     */ ETH_DEM_NO_EVENT,
    /* E_TX_INTERNAL                */ ETH_DEM_NO_EVENT,
};


/**
 *  \brief Eth controller configuraion
 */
CONST(Eth_ControlerConfigType, ETH_VAR_NO_INIT) EthConfig_0 =
{
    /* ctrlIdx                      */ EthConf_EthCtrlConfig_EthConfig_0,
    /* enetType                     */ ETH_ENETTYPE_CPSW3G,
    /* macPort                      */ ETH_PORT_MAC_PORT_1,
    /* macAddrHigh                  */ 0x827dc3d7U,
    /* macAddrLow                   */ 0xce12U,
    /* useDefaultMac                */ FALSE,
    /* connType                     */ ETH_MAC_CONN_TYPE_RGMII_FORCE_100_FULL,
    /* loopback                     */ FALSE,
    /* hwLoopTimeout                */ 32000U,
    /* enableTxIrq                  */ TRUE,
    /* enableRxIrq                  */ TRUE,
    /* isPacketMemCacheable         */ TRUE,
    /* isRingMemCacheable           */ TRUE,
    /* isDescMemCacheable           */ TRUE,
    /* enableVirtualMac             */ FALSE,
    /* demEventNum                  */ 11U,
    /* enableRxIrqPacing            */ FALSE,
    /* enableTxIrqPacing            */ FALSE,
    /* totalHwTimerNum              */ 0U,
    /* rxHwTimerIdx                 */ 255U,
    /* txHwTimerIdx                 */ 255U,
    /* demEventCfg                  */ (uint16 *)Eth_DemEventCfg_0,
    /* cpswCfg                      */ (Eth_CpswConfigType *)Eth_CpswCfg,
    /* dmaCfgPtr                    */ (Eth_Udma_CfgType *)Eth_UdmaCfg_Ctrl_0,
    /* hwTimerCfgPtr                */ (Eth_HwTimerConfigType*)NULL_PTR,
    /* hwTimerDynPtr                */ (boolean*)NULL_PTR,
    /* mdioWriteLowDelayNsec        */ (Eth_MdioDelayNsecFunc)&Eth_GetMdioWriteLowDelayNsec_0,
    /* mdioWriteHighDelayNsec       */ (Eth_MdioDelayNsecFunc)&Eth_GetMdioWriteHighDelayNsec_0,
    /* mdioReadLowDelayNsec         */ (Eth_MdioDelayNsecFunc)&Eth_GetMdioReadLowDelayNsec_0,
    /* mdioReadHighDelayNsec        */ (Eth_MdioDelayNsecFunc)&Eth_GetMdioReadHighDelayNsec_0,
};

#define  ETH_STOP_SEC_CONST_UNSPECIFIED
#include "Eth_MemMap.h"
#define  ETH_START_SEC_VAR_NO_INIT_UNSPECIFIED_128
#include "Eth_MemMap.h"


/**
 *  \brief Free queue for egress fifo
 *  @{
 */
VAR(uint64, ETH_VAR_NO_INIT_128) Eth_RingMem_Ctrl_1_Fq_Egress_0[4U];
/* @} */

/**
 *  \brief Free queue for ingress fifo
 *  @{
 */
VAR(uint64, ETH_VAR_NO_INIT_128) Eth_RingMem_Ctrl_1_Fq_Ingress_0[4U];
/* @} */


#define  ETH_STOP_SEC_VAR_NO_INIT_UNSPECIFIED_128
#include "Eth_MemMap.h"

#define  ETH_START_SEC_VAR_NO_INIT_UNSPECIFIED
#include "Eth_MemMap.h"

/**
 *  \brief Dma ring dynamic variable
 */
VAR(Eth_Udma_RingDynType, ETH_VAR_NO_INIT) Eth_RingDyn_Ctrl_1[2U];


#define  ETH_STOP_SEC_VAR_NO_INIT_UNSPECIFIED
#include "Eth_MemMap.h"

#define  ETH_START_SEC_VAR_NO_INIT_UNSPECIFIED_128
#include "Eth_MemMap.h"

/**
 *  \brief Egress data buffer memory
 */
VAR(uint8, ETH_VAR_NO_INIT_128) Eth_Ctrl_1_Egress_BufferMem_0[6144U];

/**
 *  \brief Egress DMA descriptor memory
 */
VAR(Eth_DescType, ETH_VAR_NO_INIT_128) Eth_Ctrl_1_Egress_Descriptor_0[4U];

#define  ETH_STOP_SEC_VAR_NO_INIT_UNSPECIFIED_128
#include "Eth_MemMap.h"

#define ETH_START_SEC_VAR_NO_INIT_8
#include "Eth_MemMap.h"

/**
 *  \brief Egress buffer state memory
 */
VAR(uint8, ETH_VAR_NO_INIT) Eth_Ctrl_1_Egress_BufferState_0[4U];

#define ETH_STOP_SEC_VAR_NO_INIT_8
#include "Eth_MemMap.h"

#define  ETH_START_SEC_VAR_NO_INIT_UNSPECIFIED
#include "Eth_MemMap.h"

/**
 *  \brief Egress queue descriptor memory
 */
VAR(Eth_QueueType, ETH_VAR_NO_INIT) Eth_Ctrl_1_Egress_Queue_0[1U];

#define  ETH_STOP_SEC_VAR_NO_INIT_UNSPECIFIED
#include "Eth_MemMap.h"

#define  ETH_START_SEC_VAR_NO_INIT_UNSPECIFIED_128
#include "Eth_MemMap.h"

/**
 *  \brief Ingress data buffer memory
 */
VAR(uint8, ETH_VAR_NO_INIT_128) Eth_Ctrl_1_Ingress_BufferMem_0[6144U];

/**
 *  \brief Ingress DMA descriptor memory
 */
VAR(Eth_DescType, ETH_VAR_NO_INIT_128) Eth_Ctrl_1_Ingress_Descriptor_0[4U];

#define  ETH_STOP_SEC_VAR_NO_INIT_UNSPECIFIED_128
#include "Eth_MemMap.h"

#define ETH_START_SEC_VAR_NO_INIT_8
#include "Eth_MemMap.h"

/**
 *  \brief Ingress buffer state memory
 */
VAR(uint8, ETH_VAR_NO_INIT) Eth_Ctrl_1_Ingress_BufferState_0[4U];

#define ETH_STOP_SEC_VAR_NO_INIT_8
#include "Eth_MemMap.h"

#define  ETH_START_SEC_VAR_NO_INIT_UNSPECIFIED
#include "Eth_MemMap.h"

/**
 *  \brief Ingress queue descriptor memory
 */
VAR(Eth_QueueType, ETH_VAR_NO_INIT) Eth_Ctrl_1_Ingress_Queue_0[1U];

#define  ETH_STOP_SEC_VAR_NO_INIT_UNSPECIFIED
#include "Eth_MemMap.h"

#define  ETH_START_SEC_CONST_UNSPECIFIED
#include "Eth_MemMap.h"

/**
 *  \brief Dma Ring configuration
 */
CONST(Eth_Udma_RingCfgType, ETH_VAR_NO_INIT) Eth_Udma_RingCfg_1[2U] =
{
    {
        /* memPtr               */ Eth_RingMem_Ctrl_1_Fq_Egress_0,
        /* hwId                 */ 14U,
        /* size                 */ 4U,
        /* priority             */ 0U
    },
    {
        /* memPtr               */ Eth_RingMem_Ctrl_1_Fq_Ingress_0,
        /* hwId                 */ 112U,
        /* size                 */ 4U,
        /* priority             */ 0U
    },
};


/**
 *  \brief Dma Event configuration
 */
CONST(Eth_Udma_EventCfgType, ETH_VAR_NO_INIT) Eth_EventCfg_Ctrl_1[2U] =
{
    {
        /* coreIntrNum          */ 70U,
        /* virtIntrNum          */ 174U,
        /* IrIntrNum            */ ETH_INVALID_IRQ_ID
    },
    {
        /* coreIntrNum          */ 71U,
        /* virtIntrNum          */ 175U,
        /* IrIntrNum            */ ETH_INVALID_IRQ_ID
    }
};

/**
 *  \brief Dma Ring Event configuration
 */
CONST(Eth_Udma_RingEventCfgType, ETH_VAR_NO_INIT) Eth_RingEventCfg_Ctrl_1[2U] =
{
    {
        /* ringIdx              */ 0U,
        /* eventIdx             */ 0U,
        /* virtBitNum           */ 0U,
        /* globalEvent          */ 787U,
        /* srcOffset            */ 4608U
    },
    {
        /* ringIdx              */ 1U,
        /* eventIdx             */ 1U,
        /* virtBitNum           */ 0U,
        /* globalEvent          */ 788U,
        /* srcOffset            */ 5533U
    },
};

/**
 *  \brief Dma Egress fifo map to DMA ring configuration
 */
CONST(Eth_FifoRingMapCfgType, ETH_VAR_NO_INIT) Eth_EgressFifoRingMap_Ctrl_1[1U] =
{
    {
        /* ringCqIdx            */ 0U,
        /* ringFqIdx            */ 0U
    },
};

/**
 *  \brief Dma Ingress fifo map to DMA ring configuration
 */
CONST(Eth_FifoRingMapCfgType, ETH_VAR_NO_INIT) Eth_IngressFifoRingMap_Ctrl_1[1U] =
{
    {
        /* cqRingIdx            */ 1U,
        /* fqRingIdx            */ 1U
    },
};

/**
 *  \brief Dma Tx channel configuration
 */
CONST(Eth_ChannelCfgType, ETH_VAR_NO_INIT) Eth_TxChannelCfg_Ctrl_1[1U] =
{
    {
        /* tdCqRingIdx          */ 2U,
        /* chId                 */ 14U
    },
};

/**
 *  \brief Dma Rx channel configuration
 */
CONST(Eth_ChannelCfgType, ETH_VAR_NO_INIT) Eth_RxChannelCfg_Ctrl_1[1U] =
{
    {
        /* tdCqRingIdx          */ 2U,
        /* chId                 */ 13U
    },
};

/**
 *  \brief Dma channel flow configuration
 */
CONST(Eth_ChannelFlowCfgType, ETH_VAR_NO_INIT) Eth_RxFlowCfg_Ctrl_1[1U] =
{
    {
        /* flowNum              */ 1U,
        /* startFlowId          */ 13U
    },
};

/**
 *  \brief Dma flow configuration
 */
CONST(Eth_FlowCfgType, ETH_VAR_NO_INIT) Eth_FlowCfg_Ctrl_1[1U] =
{
    {
        /* cqRingIdx            */ 1U,
        /* fqRingIdx            */ 1U,
        /* flowId               */ 13U
    },
};

/**
 *  \brief Eth Egress fifo configuration
 */
CONST(Eth_FifoHandleType, ETH_VAR_NO_INIT) Eth_FiFoEgressCfg_Ctrl_1[1U] =
{
    {
        /* fifoBufferPtr        */ Eth_Ctrl_1_Egress_BufferMem_0,
        /* descPtr              */ Eth_Ctrl_1_Egress_Descriptor_0,
        /* queuePtr             */ Eth_Ctrl_1_Egress_Queue_0,
        /* bufferState          */ Eth_Ctrl_1_Egress_BufferState_0,
        /* fifoNum              */ 4U,
        /* elemSize             */ 1536U,
        /* pktSize              */ 1522U,
        /* totalSize            */ 6144U
    },
};

/**
 *  \brief Eth Ingress fifo configuration
 */
CONST(Eth_FifoHandleType, ETH_VAR_NO_INIT) Eth_FiFoIngressCfg_Ctrl_1[1U] =
{
    {
        /* fifoBufferPtr        */ Eth_Ctrl_1_Ingress_BufferMem_0,
        /* descPtr              */ Eth_Ctrl_1_Ingress_Descriptor_0,
        /* queuePtr             */ Eth_Ctrl_1_Ingress_Queue_0,
        /* bufferState          */ Eth_Ctrl_1_Ingress_BufferState_0,
        /* fifoNum              */ 4U,
        /* elemSize             */ 1536U,
        /* pktSize              */ 1522U,
        /* totalSize            */ 6144U
    },
};

/**
 *  \brief Eth Egress Fifo priority assignment
 */
CONST(uint8, ETH_VAR_NO_INIT) Eth_EgressFifoPriorityAsignment_1[8U] =
{
    0U,
    0U,
    0U,
    0U,
    0U,
    0U,
    0U,
    0U,
};

/**
 *  \brief Eth Ingress Fifo priority assignment
 */
CONST(uint8, ETH_VAR_NO_INIT) Eth_IgressFifoPriorityAsignment_1[8U] =
{
    0U,
    0U,
    0U,
    0U,
    0U,
    0U,
    0U,
    0U,
};

/**
 *  \brief Eth DMA configuration
 */
CONST(Eth_Udma_CfgType, ETH_VAR_NO_INIT) Eth_UdmaCfg_Ctrl_1[1U] =
{
    {
        /* eventCfgPtr              */ (Eth_Udma_EventCfgType *)Eth_EventCfg_Ctrl_1,
        /* ringCfgPtr               */ (Eth_Udma_RingCfgType *)Eth_Udma_RingCfg_1,
        /* ringDynPtr               */ (Eth_Udma_RingDynType *)Eth_RingDyn_Ctrl_1,
        /* ringEvenCfgPtr           */ (Eth_Udma_RingEventCfgType *)Eth_RingEventCfg_Ctrl_1,
        /* egressFifoCfgPtr         */ (Eth_FifoHandleType *)Eth_FiFoEgressCfg_Ctrl_1,
        /* ingressFifoCfgPtr        */ (Eth_FifoHandleType *)Eth_FiFoIngressCfg_Ctrl_1,
        /* egressFifoRingMapCfgPtr  */ (Eth_FifoRingMapCfgType *)Eth_EgressFifoRingMap_Ctrl_1,
        /* ingressFifoRingMapCfgPtr */ (Eth_FifoRingMapCfgType *)Eth_IngressFifoRingMap_Ctrl_1,
        /* egressFifoPrioAssignCfgPtr  */ (uint8 *)Eth_EgressFifoPriorityAsignment_1,
        /* ingressFifoPrioAssignCfgPtr */ (uint8 *)Eth_IgressFifoPriorityAsignment_1,
        /* txChanCfgPtr             */ (Eth_ChannelCfgType *)Eth_TxChannelCfg_Ctrl_1,
        /* rxChanCfgPtr             */ (Eth_ChannelCfgType *)Eth_RxChannelCfg_Ctrl_1,
        /* rxChanFlowCfgPtr         */ (Eth_ChannelFlowCfgType *)Eth_RxFlowCfg_Ctrl_1,
        /* flowCfgPtr               */ (Eth_FlowCfgType *)Eth_FlowCfg_Ctrl_1,
        /* startTxNum               */ 13U,
        /* startRxNum               */ 13U,
        /* totalEventNum            */ 2U,
        /* totalRingNum             */ 2U,
        /* totalRingEventNum        */ 2U,
        /* txThresholdNum           */ 1U,
        /* rxThresholdNum           */ 1U,
        /* totalEgressFifoNum       */ 1U,
        /* totalInressFifoNum       */ 1U,
        /* totalTxChanNum           */ 1U,
        /* totalRxChanNum           */ 1U,
        /* totalFlowNum             */ 1U,
        /* txCoreIrq                */ 70U,
        /* rxCoreIrq                */ 71U,
        /* rxMtuLength              */ 1522U,
        /* EthDmaRingCfgOps         */ (Eth_DmaRingCfg)NULL_PTR
    }
};


/**
 *  \brief Eth dem event configuration
 */
CONST(uint16, ETH_VAR_NO_INIT) Eth_DemEventCfg_1[11u] =
{
    /* E_HARDWARE_ERROR             */ ETH_DEM_NO_EVENT,
    /* E_LATECOLLISION              */ ETH_DEM_NO_EVENT,
    /* E_MULTIPLECOLLISION          */ ETH_DEM_NO_EVENT,
    /* E_SINGLECOLLISION            */ ETH_DEM_NO_EVENT,
    /* E_ALIGNMENT                  */ ETH_DEM_NO_EVENT,
    /* E_OVERSIZEFRAME              */ ETH_DEM_NO_EVENT,
    /* E_UNDERSIZEFRAME             */ ETH_DEM_NO_EVENT,
    /* E_CRC                        */ ETH_DEM_NO_EVENT,
    /* E_RX_FRAMES_LOST             */ ETH_DEM_NO_EVENT,
    /* E_ACCESS                     */ ETH_DEM_NO_EVENT,
    /* E_TX_INTERNAL                */ ETH_DEM_NO_EVENT,
};


/**
 *  \brief Eth controller configuraion
 */
CONST(Eth_ControlerConfigType, ETH_VAR_NO_INIT) EthConfig_1 =
{
    /* ctrlIdx                      */ EthConf_EthCtrlConfig_EthConfig_1,
    /* enetType                     */ ETH_ENETTYPE_CPSW3G,
    /* macPort                      */ ETH_PORT_MAC_PORT_2,
    /* macAddrHigh                  */ 0x2000000U,
    /* macAddrLow                   */ 0x2204U,
    /* useDefaultMac                */ FALSE,
    /* connType                     */ ETH_MAC_CONN_TYPE_RGMII_FORCE_1000_FULL,
    /* loopback                     */ FALSE,
    /* hwLoopTimeout                */ 32000U,
    /* enableTxIrq                  */ TRUE,
    /* enableRxIrq                  */ TRUE,
    /* isPacketMemCacheable         */ TRUE,
    /* isRingMemCacheable           */ TRUE,
    /* isDescMemCacheable           */ TRUE,
    /* enableVirtualMac             */ FALSE,
    /* demEventNum                  */ 11U,
    /* enableRxIrqPacing            */ FALSE,
    /* enableTxIrqPacing            */ FALSE,
    /* totalHwTimerNum              */ 0U,
    /* rxHwTimerIdx                 */ 255U,
    /* txHwTimerIdx                 */ 255U,
    /* demEventCfg                  */ (uint16 *)Eth_DemEventCfg_1,
    /* cpswCfg                      */ (Eth_CpswConfigType *)Eth_CpswCfg,
    /* dmaCfgPtr                    */ (Eth_Udma_CfgType *)Eth_UdmaCfg_Ctrl_1,
    /* hwTimerCfgPtr                */ (Eth_HwTimerConfigType*)NULL_PTR,
    /* hwTimerDynPtr                */ (boolean*)NULL_PTR,
    /* mdioWriteLowDelayNsec        */ (Eth_MdioDelayNsecFunc)&Eth_GetMdioWriteLowDelayNsec_1,
    /* mdioWriteHighDelayNsec       */ (Eth_MdioDelayNsecFunc)&Eth_GetMdioWriteHighDelayNsec_1,
    /* mdioReadLowDelayNsec         */ (Eth_MdioDelayNsecFunc)&Eth_GetMdioReadLowDelayNsec_1,
    /* mdioReadHighDelayNsec        */ (Eth_MdioDelayNsecFunc)&Eth_GetMdioReadHighDelayNsec_1,
};

#define  ETH_STOP_SEC_CONST_UNSPECIFIED
#include "Eth_MemMap.h"

#define  ETH_START_SEC_CONST_UNSPECIFIED
#include "Eth_MemMap.h"

/**
 *  \brief Eth controller configuraion set
 */

CONST(Eth_ConfigType, ETH_VAR_NO_INIT) EthConfigSet_0 =
{
  {
    (Eth_ControlerConfigType*)&EthConfig_0,
    (Eth_ControlerConfigType*)&EthConfig_1,
  }
};

#define  ETH_STOP_SEC_CONST_UNSPECIFIED
#include "Eth_MemMap.h"

#define  ETH_START_SEC_VAR_INIT_UNSPECIFIED
#include "Eth_MemMap.h"

/**
 *  \brief Eth  controller configuraion set pointer
 */
P2CONST(Eth_ConfigType, ETH_VAR_NO_INIT, ETH_APPL_CONST) Eth_CfgPtr;

#define  ETH_STOP_SEC_VAR_INIT_UNSPECIFIED
#include "Eth_MemMap.h"

/*******************************************************************************
 *  End of File: Eth_Lcfg.c
 ******************************************************************************/