------Layer #(Type) [Exec ID , Data ID] --[Ni x inW x inH] => [No x outW x outH] [Ni/G] [dataflowType] [preFetch, preFetchAlign, firstTransferRemainder, procSize, inPlaneSize] [dmaFreq] [dmaFreqWt] [kernelFreq] [In Data Ids] -----
------  1(TIDL_DataConvertLayer) [1, 1] --[1 x 192 x  192] => [1 x 192 x  192] *** [1] ***[ COL] ***[0, 0, 0, 147456, 147456]**** [1], [0],[1] -[0 ]---
  IN: DDR, DMA,  24000(147456),  24000(147456),    1(    1),  24400( 148480),   0,        0 ||||  L2, DMA,  240c0(147648),  240c0(147648),    1(    1),  24100( 147712),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,  12040( 73792),  12000( 73728),    1(    1),  12080(  73856),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  2(TIDL_ConvolutionLayer) [2, 2] --[1 x 192 x  192] => [4 x 96 x  96] *** [1] ***[ROW_L] ***[384, 384, 0, 64512, 73728]**** [2], [1],[2] -[1 ]---
  IN:MSMC, DMA,  12040( 73792),  12000( 73728),    1(    1),  12080(  73856),   0,        0 ||||  L2, DMA,  1f9c0(129472),  1f9c0(129472),    1(    1),  1fa80( 129664),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   4840( 18496),   4800( 18432),    4(    4),  12100(  73984),   0,    12100 
  WT:DDR_PERSIST, DMA,     12(    18),     12(    18),    4(    4),     80(    128),   0,        0 ||||MSMC, DMA,     12(    18),     12(    18),    4(    4),     80(    128),   0,    12080 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  3(TIDL_ConvolutionLayer) [3, 3] --[4 x 96 x  96] => [32 x 96 x  96] *** [4] ***[ROW_L] ***[388, 416, 194, 18016, 18432]**** [1], [1],[1] -[2 ]---
  IN:MSMC, DMA,   4840( 18496),   4800( 18432),    4(    4),  12100(  73984),   0,    12100 ||||  L2, DMA,   4840( 18496),   4840( 18496),    4(    4),  16700(  91904),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   4840( 18496),   4800( 18432),   20(   32),  90800( 591872),   0,        0 
  WT:DDR_PERSIST, DMA,     48(    72),     48(    72),   20(   32),    a00(   2560),   0,       80 ||||MSMC, DMA,     c0(   192),     48(    72),   20(   32),   1900(   6400),   0,    90800 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  4(TIDL_ConvolutionLayer) [4, 4] --[32 x 96 x  96] => [32 x 96 x  96] *** [1] ***[ COL] ***[0, 0, 0, 18432, 18432]**** [8], [1],[8] -[3 ]---
  IN:MSMC, DMA,   4840( 18496),   4800( 18432),   20(   32),  90800( 591872),   0,        0 ||||  L2, DMA,   4800( 18432),   4800( 18432),    8(    8),  24080( 147584),   0,        0 
 OUT:MSMC, CPU,   4840( 18496),   4800( 18432),    8(    8),  24200( 147968),   0,    91700 |||| DDR, DMA,   4800( 18432),   4800( 18432),   20(   32),  90400( 590848),   0,        0 
  WT:DDR_PERSIST, DMA,     14(    20),     14(    20),   c0(  192),    f00(   3840),   0,      a80 ||||MSMC, DMA,     14(    20),     14(    20),   c0(  192),    f00(   3840),   0,    90800 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  5(TIDL_ConvolutionLayer) [5, 5] --[32 x 96 x  96] => [16 x 96 x  96] *** [32] ***[ROW_L] ***[0, 0, 0, 3296, 18432]**** [6], [1],[6] -[4 ]---
  IN: DDR, DMA,   4800( 18432),   4800( 18432),   20(   32),  90400( 590848),   0,        0 ||||  L2, DMA,   19c0(  6592),   19c0(  6592),   20(   32),  36c00( 224256),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   4840( 18496),   4800( 18432),   10(   16),  48400( 295936),   0,        0 
  WT:DDR_PERSIST, DMA,     40(    64),     40(    64),   10(   16),    480(   1152),   0,     1980 ||||MSMC, DMA,     40(    64),     40(    64),   10(   16),    480(   1152),   0,    48400 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  6(TIDL_ConvolutionLayer) [6, 6] --[16 x 96 x  96] => [96 x 96 x  96] *** [16] ***[ROW_L] ***[0, 0, 0, 2624, 18432]**** [8], [1],[8] -[5 ]---
  IN:MSMC, DMA,   4840( 18496),   4800( 18432),   10(   16),  48400( 295936),   0,        0 ||||  L2, DMA,   14c0(  5312),   14c0(  5312),   10(   16),  18a00( 100864),   0,        0 
 OUT:MSMC, CPU,    a40(  2624),    a40(  2624),   60(   96),  7b000( 503808),   0,    49300 |||| DDR, DMA,   5c40( 23616),   4800( 18432),   60(   96), 229c00(2268160),   0,        0 
  WT:DDR_PERSIST, DMA,     20(    32),     20(    32),   60(   96),    f00(   3840),   0,     1e00 ||||MSMC, DMA,     20(    32),     20(    32),   60(   96),    f00(   3840),   0,    48400 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  7(TIDL_ConvolutionLayer) [7, 7] --[96 x 96 x  96] => [96 x 48 x  48] *** [1] ***[ COL] ***[0, 0, 0, 18432, 18432]**** [16], [1],[16] -[6 ]---
  IN: DDR, DMA,   5c40( 23616),   4800( 18432),   60(   96), 229c00(2268160),   0,        0 ||||  L2, DMA,   4800( 18432),   4800( 18432),    c(   12),  36080( 221312),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1240(  4672),   1200(  4608),   60(   96),  6d800( 448512),   0,     6d80 
  WT:DDR_PERSIST, DMA,     14(    20),     14(    20),  480( 1152),   5a00(  23040),   0,     2d00 ||||MSMC, DMA,     14(    20),     14(    20),  480( 1152),   5a00(  23040),   0,        0 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  8(TIDL_ConvolutionLayer) [8, 8] --[96 x 48 x  48] => [24 x 48 x  48] *** [96] ***[ROW_L] ***[0, 0, 0, 1120, 4608]**** [5], [1],[5] -[7 ]---
  IN:MSMC, DMA,   1240(  4672),   1200(  4608),   60(   96),  6d800( 448512),   0,     6d80 ||||  L2, DMA,    8c0(  2240),    8c0(  2240),   60(   96),  35600( 218624),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1240(  4672),   1200(  4608),   18(   24),  1b600( 112128),   0,        0 
  WT:DDR_PERSIST, DMA_ONCE,     c0(   192),     c0(   192),   18(   24),   1300(   4864),   0,     8700 ||||MSMC, DMA_ONCE,     c0(   192),     c0(   192),   18(   24),   1300(   4864),   0,    f0c00 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  9(TIDL_ConvolutionLayer) [9, 9] --[24 x 48 x  48] => [144 x 48 x  48] *** [24] ***[ROW_L] ***[0, 0, 0, 4608, 4608]**** [1], [1],[1] -[8 ]---
  IN:MSMC, DMA,   1240(  4672),   1200(  4608),   18(   24),  1b600( 112128),   0,        0 ||||  L2, DMA,   1240(  4672),   1240(  4672),   18(   24),  1b680( 112256),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1240(  4672),   1200(  4608),   90(  144),  a4400( 672768),   0,    1b600 
  WT:DDR_PERSIST, DMA,     30(    48),     30(    48),   90(  144),   1f80(   8064),   0,     9a00 ||||MSMC, DMA,     30(    48),     30(    48),   90(  144),   1f80(   8064),   0,    bfa00 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  10(TIDL_ConvolutionLayer) [10, 10] --[144 x 48 x  48] => [144 x 48 x  48] *** [1] ***[ COL] ***[0, 0, 0, 4608, 4608]**** [36], [1],[36] -[9 ]---
  IN:MSMC, DMA,   1240(  4672),   1200(  4608),   90(  144),  a4400( 672768),   0,    1b600 ||||  L2, DMA,   1200(  4608),   1200(  4608),    8(    8),   9080(  36992),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1240(  4672),   1200(  4608),   90(  144),  a4400( 672768),   0,    1b600 
  WT:DDR_PERSIST, DMA,     14(    20),     14(    20),  6c0( 1728),   8700(  34560),   0,     b980 ||||MSMC, DMA,     14(    20),     14(    20),  6c0( 1728),   8700(  34560),   0,    bfa00 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  11(TIDL_ConvolutionLayer) [11, 11] --[144 x 48 x  48] => [24 x 48 x  48] *** [144] ***[ROW_L] ***[0, 0, 0, 736, 4608]**** [7], [1],[7] -[10 ]---
  IN:MSMC, DMA,   1240(  4672),   1200(  4608),   90(  144),  a4400( 672768),   0,    1b600 ||||  L2, DMA,    5c0(  1472),    5c0(  1472),   90(  144),  34b00( 215808),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1240(  4672),   1200(  4608),   18(   24),  1b600( 112128),   0,    1b600 
  WT:DDR_PERSIST, DMA,    120(   288),    120(   288),   18(   24),   1c00(   7168),   0,    14080 ||||MSMC, DMA,    140(   320),    120(   288),   18(   24),   1f00(   7936),   0,    bfa00 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  12(TIDL_EltWiseLayer) [12, 12] --[48 x 48 x  48] => [24 x 48 x  48] *** [48] ***[ COL] ***[0, 0, 0, 4608, 4608]**** [2], [0],[2] -[8 11 ]---
  IN:MSMC, DMA,   1240(  4672),   1200(  4608),   18(   24),  1b600( 112128),   0,        0 ||||  L2, DMA,   1260(  4704),   1260(  4704),   18(   24),  37200( 225792),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1240(  4672),   1200(  4608),   18(   24),  1b600( 112128),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  13(TIDL_ConvolutionLayer) [13, 13] --[24 x 48 x  48] => [144 x 48 x  48] *** [24] ***[ROW_L] ***[0, 0, 0, 4608, 4608]**** [1], [1],[1] -[12 ]---
  IN:MSMC, DMA,   1240(  4672),   1200(  4608),   18(   24),  1b600( 112128),   0,        0 ||||  L2, DMA,   1240(  4672),   1240(  4672),   18(   24),  1b680( 112256),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1240(  4672),   1200(  4608),   90(  144),  a4400( 672768),   0,        0 
  WT:DDR_PERSIST, DMA,     30(    48),     30(    48),   90(  144),   1f80(   8064),   0,    15c80 ||||MSMC, DMA,     30(    48),     30(    48),   90(  144),   1f80(   8064),   0,    a4400 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  14(TIDL_ConvolutionLayer) [14, 14] --[144 x 48 x  48] => [144 x 24 x  24] *** [1] ***[ COL] ***[0, 0, 0, 4608, 4608]**** [6], [1],[6] -[13 ]---
  IN:MSMC, DMA,   1240(  4672),   1200(  4608),   90(  144),  a4400( 672768),   0,        0 ||||  L2, DMA,   1200(  4608),   1200(  4608),   30(   48),  36080( 221312),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    4c0(  1216),    480(  1152),   90(  144),  2ac00( 175104),   0,        0 
  WT:DDR_PERSIST, DMA,     14(    20),     14(    20),  360(  864),   4380(  17280),   0,    17c00 ||||MSMC, DMA,     14(    20),     14(    20),  360(  864),   4380(  17280),   0,    a4400 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  15(TIDL_ConvolutionLayer) [15, 15] --[144 x 24 x  24] => [32 x 24 x  24] *** [144] ***[ROW_L] ***[0, 0, 0, 736, 1152]**** [2], [1],[2] -[14 ]---
  IN:MSMC, DMA,    4c0(  1216),    480(  1152),   90(  144),  2ac00( 175104),   0,        0 ||||  L2, DMA,    5c0(  1472),    5c0(  1472),   90(  144),  33c80( 212096),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    4c0(  1216),    480(  1152),   20(   32),   9800(  38912),   0,        0 
  WT:DDR_PERSIST, DMA,    120(   288),    120(   288),   20(   32),   2500(   9472),   0,    1bf80 ||||MSMC, DMA,    140(   320),    120(   288),   20(   32),   2900(  10496),   0,    2ac00 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  16(TIDL_ConvolutionLayer) [16, 16] --[32 x 24 x  24] => [192 x 24 x  24] *** [32] ***[ROW_L] ***[0, 0, 0, 1152, 1152]**** [1], [1],[1] -[15 ]---
  IN:MSMC, DMA,    4c0(  1216),    480(  1152),   20(   32),   9800(  38912),   0,        0 ||||  L2, DMA,    4c0(  1216),    4c0(  1216),   20(   32),   9880(  39040),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    4c0(  1216),    480(  1152),   c0(  192),  39000( 233472),   0,     9800 
  WT:DDR_PERSIST, DMA,     40(    64),     40(    64),   c0(  192),   3600(  13824),   0,    1e480 ||||MSMC, DMA,     40(    64),     40(    64),   c0(  192),   3600(  13824),   0,    42800 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  17(TIDL_ConvolutionLayer) [17, 17] --[192 x 24 x  24] => [192 x 24 x  24] *** [1] ***[ COL] ***[0, 0, 0, 1152, 1152]**** [48], [1],[48] -[16 ]---
  IN:MSMC, DMA,    4c0(  1216),    480(  1152),   c0(  192),  39000( 233472),   0,     9800 ||||  L2, DMA,    480(  1152),    480(  1152),    8(    8),   2480(   9344),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    4c0(  1216),    480(  1152),   c0(  192),  39000( 233472),   0,     9800 
  WT:DDR_PERSIST, DMA,     14(    20),     14(    20),  480( 1152),   5a00(  23040),   0,    21a80 ||||MSMC, DMA,     14(    20),     14(    20),  480( 1152),   5a00(  23040),   0,    42800 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  18(TIDL_ConvolutionLayer) [18, 18] --[192 x 24 x  24] => [32 x 24 x  24] *** [192] ***[ROW_L] ***[0, 0, 0, 544, 1152]**** [3], [1],[3] -[17 ]---
  IN:MSMC, DMA,    4c0(  1216),    480(  1152),   c0(  192),  39000( 233472),   0,     9800 ||||  L2, DMA,    440(  1088),    440(  1088),   c0(  192),  33300( 209664),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    4c0(  1216),    480(  1152),   20(   32),   9800(  38912),   0,     9800 
  WT:DDR_PERSIST, DMA,    180(   384),    180(   384),   20(   32),   3100(  12544),   0,    27480 ||||MSMC, DMA,    1c0(   448),    180(   384),   20(   32),   3900(  14592),   0,    42800 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  19(TIDL_EltWiseLayer) [19, 19] --[64 x 24 x  24] => [32 x 24 x  24] *** [64] ***[ COL] ***[0, 0, 0, 1152, 1152]**** [2], [0],[2] -[15 18 ]---
  IN:MSMC, DMA,    4c0(  1216),    480(  1152),   20(   32),   9800(  38912),   0,        0 ||||  L2, DMA,    4c8(  1224),    4c8(  1224),   20(   32),  13200(  78336),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    4c0(  1216),    480(  1152),   20(   32),   9800(  38912),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  20(TIDL_ConvolutionLayer) [20, 20] --[32 x 24 x  24] => [192 x 24 x  24] *** [32] ***[ROW_L] ***[0, 0, 0, 1152, 1152]**** [1], [1],[1] -[19 ]---
  IN:MSMC, DMA,    4c0(  1216),    480(  1152),   20(   32),   9800(  38912),   0,        0 ||||  L2, DMA,    4c0(  1216),    4c0(  1216),   20(   32),   9880(  39040),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    4c0(  1216),    480(  1152),   c0(  192),  39000( 233472),   0,     9800 
  WT:DDR_PERSIST, DMA,     40(    64),     40(    64),   c0(  192),   3600(  13824),   0,    2a580 ||||MSMC, DMA,     40(    64),     40(    64),   c0(  192),   3600(  13824),   0,    42800 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  21(TIDL_ConvolutionLayer) [21, 21] --[192 x 24 x  24] => [192 x 24 x  24] *** [1] ***[ COL] ***[0, 0, 0, 1152, 1152]**** [48], [1],[48] -[20 ]---
  IN:MSMC, DMA,    4c0(  1216),    480(  1152),   c0(  192),  39000( 233472),   0,     9800 ||||  L2, DMA,    480(  1152),    480(  1152),    8(    8),   2480(   9344),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    4c0(  1216),    480(  1152),   c0(  192),  39000( 233472),   0,     9800 
  WT:DDR_PERSIST, DMA,     14(    20),     14(    20),  480( 1152),   5a00(  23040),   0,    2db80 ||||MSMC, DMA,     14(    20),     14(    20),  480( 1152),   5a00(  23040),   0,    42800 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  22(TIDL_ConvolutionLayer) [22, 22] --[192 x 24 x  24] => [32 x 24 x  24] *** [192] ***[ROW_L] ***[0, 0, 0, 544, 1152]**** [3], [1],[3] -[21 ]---
  IN:MSMC, DMA,    4c0(  1216),    480(  1152),   c0(  192),  39000( 233472),   0,     9800 ||||  L2, DMA,    440(  1088),    440(  1088),   c0(  192),  33300( 209664),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    4c0(  1216),    480(  1152),   20(   32),   9800(  38912),   0,     9800 
  WT:DDR_PERSIST, DMA,    180(   384),    180(   384),   20(   32),   3100(  12544),   0,    33580 ||||MSMC, DMA,    1c0(   448),    180(   384),   20(   32),   3900(  14592),   0,    42800 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  23(TIDL_EltWiseLayer) [23, 23] --[64 x 24 x  24] => [32 x 24 x  24] *** [64] ***[ COL] ***[0, 0, 0, 1152, 1152]**** [2], [0],[2] -[19 22 ]---
  IN:MSMC, DMA,    4c0(  1216),    480(  1152),   20(   32),   9800(  38912),   0,        0 ||||  L2, DMA,    4c8(  1224),    4c8(  1224),   20(   32),  13200(  78336),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    4c0(  1216),    480(  1152),   20(   32),   9800(  38912),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  24(TIDL_ConvolutionLayer) [24, 24] --[32 x 24 x  24] => [192 x 24 x  24] *** [32] ***[ROW_L] ***[0, 0, 0, 1152, 1152]**** [1], [1],[1] -[23 ]---
  IN:MSMC, DMA,    4c0(  1216),    480(  1152),   20(   32),   9800(  38912),   0,        0 ||||  L2, DMA,    4c0(  1216),    4c0(  1216),   20(   32),   9880(  39040),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    4c0(  1216),    480(  1152),   c0(  192),  39000( 233472),   0,        0 
  WT:DDR_PERSIST, DMA,     40(    64),     40(    64),   c0(  192),   3600(  13824),   0,    36680 ||||MSMC, DMA,     40(    64),     40(    64),   c0(  192),   3600(  13824),   0,    39000 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  25(TIDL_ConvolutionLayer) [25, 25] --[192 x 24 x  24] => [192 x 12 x  12] *** [1] ***[ COL] ***[0, 0, 0, 1152, 1152]**** [1], [1],[1] -[24 ]---
  IN:MSMC, DMA,    4c0(  1216),    480(  1152),   c0(  192),  39000( 233472),   0,        0 ||||  L2, DMA,    480(  1152),    480(  1152),   c0(  192),  36080( 221312),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),   c0(  192),   f000(  61440),   0,        0 
  WT:DDR_PERSIST, DMA,     14(    20),     14(    20),  480( 1152),   5a00(  23040),   0,    39c80 ||||MSMC, DMA,     14(    20),     14(    20),  480( 1152),   5a00(  23040),   0,    39000 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  26(TIDL_PoolingLayer) [26, 26] --[192 x 12 x  12] => [192 x 6 x  6] *** [192] ***[ COL] ***[0, 0, 0, 288, 288]**** [1], [0],[1] -[25 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),   c0(  192),   f000(  61440),   0,        0 ||||  L2, DMA,    144(   324),    144(   324),   c0(  192),   f380(  62336),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     c0(   192),     48(    72),   c0(  192),   9000(  36864),   0,     f000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  27(TIDL_PoolingLayer) [27, 27] --[192 x 6 x  6] => [192 x 3 x  3] *** [192] ***[ COL] ***[0, 0, 0, 72, 72]**** [1], [0],[1] -[26 ]---
  IN:MSMC, DMA,     c0(   192),     48(    72),   c0(  192),   9000(  36864),   0,     f000 ||||  L2, DMA,     c0(   192),     c0(   192),   c0(  192),   9080(  36992),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     12(    18),     12(    18),   c0(  192),    d80(   3456),   0,     f000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  28(TIDL_PoolingLayer) [28, 28] --[192 x 3 x  3] => [192 x 1 x  1] *** [192] ***[ COL] ***[0, 0, 0, 18, 18]**** [1], [0],[1] -[27 ]---
  IN:MSMC, DMA,     12(    18),     12(    18),   c0(  192),    d80(   3456),   0,     f000 ||||  L2, DMA,     12(    18),     12(    18),   c0(  192),    e80(   3712),   0,       80 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,      2(     2),      2(     2),   c0(  192),    180(    384),   0,     f000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  29(TIDL_ConvolutionLayer) [29, 29] --[192 x 1 x  1] => [12 x 1 x  1] *** [192] ***[ROW_L] ***[0, 0, 0, 2, 2]**** [1], [1],[1] -[28 ]---
  IN:MSMC, DMA,      2(     2),      2(     2),   c0(  192),    180(    384),   0,     f000 ||||  L2, DMA,      2(     2),      2(     2),   c0(  192),    200(    512),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,      2(     2),      2(     2),    c(   12),     80(    128),   0,    10800 
  WT:DDR_PERSIST, DMA,    180(   384),    180(   384),    c(   12),   1280(   4736),   0,    3f680 ||||MSMC, DMA,    1c0(   448),    180(   384),    c(   12),   1580(   5504),   0,     f180 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  30(TIDL_ConvolutionLayer) [30, 30] --[12 x 1 x  1] => [192 x 1 x  1] *** [12] ***[ROW_L] ***[0, 0, 0, 2, 2]**** [1], [1],[1] -[29 ]---
  IN:MSMC, DMA,      2(     2),      2(     2),    c(   12),     80(    128),   0,    10800 ||||  L2, DMA,      2(     2),      2(     2),    c(   12),    100(    256),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,      2(     2),      2(     2),   c0(  192),    180(    384),   0,    10800 
  WT:DDR_PERSIST, DMA,     18(    24),     18(    24),   c0(  192),   1800(   6144),   0,    40900 ||||MSMC, DMA,     18(    24),     18(    24),   c0(  192),   1800(   6144),   0,     f000 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  31(TIDL_BatchNormLayer) [31, 31] --[192 x 1 x  1] => [192 x 1 x  1] *** [192] ***[ COL] ***[0, 0, 0, 2, 2]**** [1], [0],[1] -[30 ]---
  IN:MSMC, DMA,      2(     2),      2(     2),   c0(  192),    180(    384),   0,    10800 ||||  L2, DMA,      2(     2),      2(     2),   c0(  192),    180(    384),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,      2(     2),      2(     2),   c0(  192),    180(    384),   0,     f000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  32(TIDL_EltWiseLayer) [32, 32] --[384 x 12 x  12] => [192 x 12 x  12] *** [384] ***[ COL] ***[0, 0, 0, 288, 288]**** [2], [0],[2] -[25 31 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),   c0(  192),   f000(  61440),   0,        0 ||||  L2, DMA,    144(   324),    144(   324),   c0(  192),  1e600( 124416),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),   c0(  192),   f000(  61440),   0,     f180 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  33(TIDL_ConvolutionLayer) [33, 33] --[192 x 12 x  12] => [64 x 12 x  12] *** [192] ***[ROW_L] ***[0, 0, 0, 288, 288]**** [1], [1],[1] -[32 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),   c0(  192),   f000(  61440),   0,     f180 ||||  L2, DMA,    140(   320),    140(   320),   c0(  192),   f080(  61568),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),   40(   64),   5000(  20480),   0,        0 
  WT:DDR_PERSIST, DMA,    180(   384),    180(   384),   40(   64),   6200(  25088),   0,    42100 ||||MSMC, DMA,    1c0(   448),    180(   384),   40(   64),   7200(  29184),   0,     5000 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  34(TIDL_ConvolutionLayer) [34, 34] --[64 x 12 x  12] => [384 x 12 x  12] *** [64] ***[ROW_L] ***[0, 0, 0, 288, 288]**** [1], [1],[1] -[33 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),   40(   64),   5000(  20480),   0,        0 ||||  L2, DMA,    140(   320),    140(   320),   40(   64),   5080(  20608),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),  180(  384),  1e000( 122880),   0,    17c00 
  WT:DDR_PERSIST, DMA,     80(   128),     80(   128),  180(  384),   cc00(  52224),   0,    48300 ||||MSMC, DMA,     c0(   192),     80(   128),  180(  384),  12c00(  76800),   0,     5000 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  35(TIDL_ConvolutionLayer) [35, 35] --[384 x 12 x  12] => [384 x 12 x  12] *** [1] ***[ COL] ***[0, 0, 0, 288, 288]**** [1], [1],[1] -[34 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),  180(  384),  1e000( 122880),   0,    17c00 ||||  L2, DMA,    120(   288),    120(   288),  180(  384),  1b080( 110720),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),  180(  384),  1e000( 122880),   0,     5000 
  WT:DDR_PERSIST, DMA,     14(    20),     14(    20),  900( 2304),   b400(  46080),   0,    54f00 ||||MSMC, DMA,     14(    20),     14(    20),  900( 2304),   b400(  46080),   0,    35c00 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  36(TIDL_PoolingLayer) [36, 36] --[384 x 12 x  12] => [384 x 6 x  6] *** [384] ***[ COL] ***[0, 0, 0, 288, 288]**** [1], [0],[1] -[35 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),  180(  384),  1e000( 122880),   0,     5000 ||||  L2, DMA,    144(   324),    144(   324),  180(  384),  1e680( 124544),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     c0(   192),     48(    72),  180(  384),  12000(  73728),   0,    23000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  37(TIDL_PoolingLayer) [37, 37] --[384 x 6 x  6] => [384 x 3 x  3] *** [384] ***[ COL] ***[0, 0, 0, 72, 72]**** [1], [0],[1] -[36 ]---
  IN:MSMC, DMA,     c0(   192),     48(    72),  180(  384),  12000(  73728),   0,    23000 ||||  L2, DMA,     c0(   192),     c0(   192),  180(  384),  12080(  73856),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     12(    18),     12(    18),  180(  384),   1b00(   6912),   0,    23000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  38(TIDL_PoolingLayer) [38, 38] --[384 x 3 x  3] => [384 x 1 x  1] *** [384] ***[ COL] ***[0, 0, 0, 18, 18]**** [1], [0],[1] -[37 ]---
  IN:MSMC, DMA,     12(    18),     12(    18),  180(  384),   1b00(   6912),   0,    23000 ||||  L2, DMA,     12(    18),     12(    18),  180(  384),   1c00(   7168),   0,       80 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,      2(     2),      2(     2),  180(  384),    300(    768),   0,    23000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  39(TIDL_ConvolutionLayer) [39, 39] --[384 x 1 x  1] => [12 x 1 x  1] *** [384] ***[ROW_L] ***[0, 0, 0, 2, 2]**** [1], [1],[1] -[38 ]---
  IN:MSMC, DMA,      2(     2),      2(     2),  180(  384),    300(    768),   0,    23000 ||||  L2, DMA,      2(     2),      2(     2),  180(  384),    380(    896),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,      2(     2),      2(     2),    c(   12),     80(    128),   0,    26000 
  WT:DDR_PERSIST, DMA,    300(   768),    300(   768),    c(   12),   2480(   9344),   0,    60300 ||||MSMC, DMA,    340(   832),    300(   768),    c(   12),   2780(  10112),   0,    23300 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  40(TIDL_ConvolutionLayer) [40, 40] --[12 x 1 x  1] => [384 x 1 x  1] *** [12] ***[ROW_L] ***[0, 0, 0, 2, 2]**** [1], [1],[1] -[39 ]---
  IN:MSMC, DMA,      2(     2),      2(     2),    c(   12),     80(    128),   0,    26000 ||||  L2, DMA,      2(     2),      2(     2),    c(   12),    100(    256),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,      2(     2),      2(     2),  180(  384),    300(    768),   0,    26000 
  WT:DDR_PERSIST, DMA,     18(    24),     18(    24),  180(  384),   3000(  12288),   0,    62780 ||||MSMC, DMA,     18(    24),     18(    24),  180(  384),   3000(  12288),   0,    23000 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  41(TIDL_BatchNormLayer) [41, 41] --[384 x 1 x  1] => [384 x 1 x  1] *** [384] ***[ COL] ***[0, 0, 0, 2, 2]**** [1], [0],[1] -[40 ]---
  IN:MSMC, DMA,      2(     2),      2(     2),  180(  384),    300(    768),   0,    26000 ||||  L2, DMA,      2(     2),      2(     2),  180(  384),    300(    768),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,      2(     2),      2(     2),  180(  384),    300(    768),   0,    23000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  42(TIDL_EltWiseLayer) [42, 42] --[768 x 12 x  12] => [384 x 12 x  12] *** [768] ***[ COL] ***[0, 0, 0, 288, 288]**** [4], [0],[4] -[35 41 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),  180(  384),  1e000( 122880),   0,     5000 ||||  L2, DMA,    144(   324),    144(   324),   c0(  192),  1e600( 124416),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),  180(  384),  1e000( 122880),   0,    23300 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  43(TIDL_ConvolutionLayer) [43, 43] --[384 x 12 x  12] => [64 x 12 x  12] *** [384] ***[ROW_L] ***[0, 0, 0, 288, 288]**** [1], [1],[1] -[42 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),  180(  384),  1e000( 122880),   0,    23300 ||||  L2, DMA,    140(   320),    140(   320),  180(  384),  1e080( 123008),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),   40(   64),   5000(  20480),   0,    12200 
  WT:DDR_PERSIST, DMA,    300(   768),    300(   768),   40(   64),   c200(  49664),   0,    65780 ||||MSMC, DMA,    340(   832),    300(   768),   40(   64),   d200(  53760),   0,     5000 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  44(TIDL_EltWiseLayer) [44, 44] --[128 x 12 x  12] => [64 x 12 x  12] *** [128] ***[ COL] ***[0, 0, 0, 288, 288]**** [2], [0],[2] -[33 43 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),   40(   64),   5000(  20480),   0,        0 ||||  L2, DMA,    144(   324),    144(   324),   40(   64),   a200(  41472),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),   40(   64),   5000(  20480),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  45(TIDL_ConvolutionLayer) [45, 45] --[64 x 12 x  12] => [384 x 12 x  12] *** [64] ***[ROW_L] ***[0, 0, 0, 288, 288]**** [1], [1],[1] -[44 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),   40(   64),   5000(  20480),   0,        0 ||||  L2, DMA,    140(   320),    140(   320),   40(   64),   5080(  20608),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),  180(  384),  1e000( 122880),   0,    17c00 
  WT:DDR_PERSIST, DMA,     80(   128),     80(   128),  180(  384),   cc00(  52224),   0,    71980 ||||MSMC, DMA,     c0(   192),     80(   128),  180(  384),  12c00(  76800),   0,     5000 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  46(TIDL_ConvolutionLayer) [46, 46] --[384 x 12 x  12] => [384 x 12 x  12] *** [1] ***[ COL] ***[0, 0, 0, 288, 288]**** [1], [1],[1] -[45 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),  180(  384),  1e000( 122880),   0,    17c00 ||||  L2, DMA,    120(   288),    120(   288),  180(  384),  1b080( 110720),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),  180(  384),  1e000( 122880),   0,     5000 
  WT:DDR_PERSIST, DMA,     14(    20),     14(    20),  900( 2304),   b400(  46080),   0,    7e580 ||||MSMC, DMA,     14(    20),     14(    20),  900( 2304),   b400(  46080),   0,    35c00 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  47(TIDL_PoolingLayer) [47, 47] --[384 x 12 x  12] => [384 x 6 x  6] *** [384] ***[ COL] ***[0, 0, 0, 288, 288]**** [1], [0],[1] -[46 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),  180(  384),  1e000( 122880),   0,     5000 ||||  L2, DMA,    144(   324),    144(   324),  180(  384),  1e680( 124544),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     c0(   192),     48(    72),  180(  384),  12000(  73728),   0,    23000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  48(TIDL_PoolingLayer) [48, 48] --[384 x 6 x  6] => [384 x 3 x  3] *** [384] ***[ COL] ***[0, 0, 0, 72, 72]**** [1], [0],[1] -[47 ]---
  IN:MSMC, DMA,     c0(   192),     48(    72),  180(  384),  12000(  73728),   0,    23000 ||||  L2, DMA,     c0(   192),     c0(   192),  180(  384),  12080(  73856),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     12(    18),     12(    18),  180(  384),   1b00(   6912),   0,    23000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  49(TIDL_PoolingLayer) [49, 49] --[384 x 3 x  3] => [384 x 1 x  1] *** [384] ***[ COL] ***[0, 0, 0, 18, 18]**** [1], [0],[1] -[48 ]---
  IN:MSMC, DMA,     12(    18),     12(    18),  180(  384),   1b00(   6912),   0,    23000 ||||  L2, DMA,     12(    18),     12(    18),  180(  384),   1c00(   7168),   0,       80 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,      2(     2),      2(     2),  180(  384),    300(    768),   0,    23000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  50(TIDL_ConvolutionLayer) [50, 50] --[384 x 1 x  1] => [12 x 1 x  1] *** [384] ***[ROW_L] ***[0, 0, 0, 2, 2]**** [1], [1],[1] -[49 ]---
  IN:MSMC, DMA,      2(     2),      2(     2),  180(  384),    300(    768),   0,    23000 ||||  L2, DMA,      2(     2),      2(     2),  180(  384),    380(    896),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,      2(     2),      2(     2),    c(   12),     80(    128),   0,    26000 
  WT:DDR_PERSIST, DMA,    300(   768),    300(   768),    c(   12),   2480(   9344),   0,    89980 ||||MSMC, DMA,    340(   832),    300(   768),    c(   12),   2780(  10112),   0,    23300 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  51(TIDL_ConvolutionLayer) [51, 51] --[12 x 1 x  1] => [384 x 1 x  1] *** [12] ***[ROW_L] ***[0, 0, 0, 2, 2]**** [1], [1],[1] -[50 ]---
  IN:MSMC, DMA,      2(     2),      2(     2),    c(   12),     80(    128),   0,    26000 ||||  L2, DMA,      2(     2),      2(     2),    c(   12),    100(    256),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,      2(     2),      2(     2),  180(  384),    300(    768),   0,    26000 
  WT:DDR_PERSIST, DMA,     18(    24),     18(    24),  180(  384),   3000(  12288),   0,    8be00 ||||MSMC, DMA,     18(    24),     18(    24),  180(  384),   3000(  12288),   0,    23000 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  52(TIDL_BatchNormLayer) [52, 52] --[384 x 1 x  1] => [384 x 1 x  1] *** [384] ***[ COL] ***[0, 0, 0, 2, 2]**** [1], [0],[1] -[51 ]---
  IN:MSMC, DMA,      2(     2),      2(     2),  180(  384),    300(    768),   0,    26000 ||||  L2, DMA,      2(     2),      2(     2),  180(  384),    300(    768),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,      2(     2),      2(     2),  180(  384),    300(    768),   0,    23000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  53(TIDL_EltWiseLayer) [53, 53] --[768 x 12 x  12] => [384 x 12 x  12] *** [768] ***[ COL] ***[0, 0, 0, 288, 288]**** [4], [0],[4] -[46 52 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),  180(  384),  1e000( 122880),   0,     5000 ||||  L2, DMA,    144(   324),    144(   324),   c0(  192),  1e600( 124416),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),  180(  384),  1e000( 122880),   0,    23300 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  54(TIDL_ConvolutionLayer) [54, 54] --[384 x 12 x  12] => [64 x 12 x  12] *** [384] ***[ROW_L] ***[0, 0, 0, 288, 288]**** [1], [1],[1] -[53 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),  180(  384),  1e000( 122880),   0,    23300 ||||  L2, DMA,    140(   320),    140(   320),  180(  384),  1e080( 123008),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),   40(   64),   5000(  20480),   0,    12200 
  WT:DDR_PERSIST, DMA,    300(   768),    300(   768),   40(   64),   c200(  49664),   0,    8ee00 ||||MSMC, DMA,    340(   832),    300(   768),   40(   64),   d200(  53760),   0,     5000 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  55(TIDL_EltWiseLayer) [55, 55] --[128 x 12 x  12] => [64 x 12 x  12] *** [128] ***[ COL] ***[0, 0, 0, 288, 288]**** [2], [0],[2] -[44 54 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),   40(   64),   5000(  20480),   0,        0 ||||  L2, DMA,    144(   324),    144(   324),   40(   64),   a200(  41472),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),   40(   64),   5000(  20480),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  56(TIDL_ConvolutionLayer) [56, 56] --[64 x 12 x  12] => [384 x 12 x  12] *** [64] ***[ROW_L] ***[0, 0, 0, 288, 288]**** [1], [1],[1] -[55 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),   40(   64),   5000(  20480),   0,        0 ||||  L2, DMA,    140(   320),    140(   320),   40(   64),   5080(  20608),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),  180(  384),  1e000( 122880),   0,    17c00 
  WT:DDR_PERSIST, DMA,     80(   128),     80(   128),  180(  384),   cc00(  52224),   0,    9b000 ||||MSMC, DMA,     c0(   192),     80(   128),  180(  384),  12c00(  76800),   0,     5000 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  57(TIDL_ConvolutionLayer) [57, 57] --[384 x 12 x  12] => [384 x 12 x  12] *** [1] ***[ COL] ***[0, 0, 0, 288, 288]**** [1], [1],[1] -[56 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),  180(  384),  1e000( 122880),   0,    17c00 ||||  L2, DMA,    120(   288),    120(   288),  180(  384),  1b080( 110720),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),  180(  384),  1e000( 122880),   0,     5000 
  WT:DDR_PERSIST, DMA,     14(    20),     14(    20),  900( 2304),   b400(  46080),   0,    a7c00 ||||MSMC, DMA,     14(    20),     14(    20),  900( 2304),   b400(  46080),   0,    35c00 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  58(TIDL_PoolingLayer) [58, 58] --[384 x 12 x  12] => [384 x 6 x  6] *** [384] ***[ COL] ***[0, 0, 0, 288, 288]**** [1], [0],[1] -[57 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),  180(  384),  1e000( 122880),   0,     5000 ||||  L2, DMA,    144(   324),    144(   324),  180(  384),  1e680( 124544),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     c0(   192),     48(    72),  180(  384),  12000(  73728),   0,    23000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  59(TIDL_PoolingLayer) [59, 59] --[384 x 6 x  6] => [384 x 3 x  3] *** [384] ***[ COL] ***[0, 0, 0, 72, 72]**** [1], [0],[1] -[58 ]---
  IN:MSMC, DMA,     c0(   192),     48(    72),  180(  384),  12000(  73728),   0,    23000 ||||  L2, DMA,     c0(   192),     c0(   192),  180(  384),  12080(  73856),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     12(    18),     12(    18),  180(  384),   1b00(   6912),   0,    23000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  60(TIDL_PoolingLayer) [60, 60] --[384 x 3 x  3] => [384 x 1 x  1] *** [384] ***[ COL] ***[0, 0, 0, 18, 18]**** [1], [0],[1] -[59 ]---
  IN:MSMC, DMA,     12(    18),     12(    18),  180(  384),   1b00(   6912),   0,    23000 ||||  L2, DMA,     12(    18),     12(    18),  180(  384),   1c00(   7168),   0,       80 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,      2(     2),      2(     2),  180(  384),    300(    768),   0,    23000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  61(TIDL_ConvolutionLayer) [61, 61] --[384 x 1 x  1] => [12 x 1 x  1] *** [384] ***[ROW_L] ***[0, 0, 0, 2, 2]**** [1], [1],[1] -[60 ]---
  IN:MSMC, DMA,      2(     2),      2(     2),  180(  384),    300(    768),   0,    23000 ||||  L2, DMA,      2(     2),      2(     2),  180(  384),    380(    896),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,      2(     2),      2(     2),    c(   12),     80(    128),   0,    26000 
  WT:DDR_PERSIST, DMA,    300(   768),    300(   768),    c(   12),   2480(   9344),   0,    b3000 ||||MSMC, DMA,    340(   832),    300(   768),    c(   12),   2780(  10112),   0,    23300 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  62(TIDL_ConvolutionLayer) [62, 62] --[12 x 1 x  1] => [384 x 1 x  1] *** [12] ***[ROW_L] ***[0, 0, 0, 2, 2]**** [1], [1],[1] -[61 ]---
  IN:MSMC, DMA,      2(     2),      2(     2),    c(   12),     80(    128),   0,    26000 ||||  L2, DMA,      2(     2),      2(     2),    c(   12),    100(    256),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,      2(     2),      2(     2),  180(  384),    300(    768),   0,    26000 
  WT:DDR_PERSIST, DMA,     18(    24),     18(    24),  180(  384),   3000(  12288),   0,    b5480 ||||MSMC, DMA,     18(    24),     18(    24),  180(  384),   3000(  12288),   0,    23000 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  63(TIDL_BatchNormLayer) [63, 63] --[384 x 1 x  1] => [384 x 1 x  1] *** [384] ***[ COL] ***[0, 0, 0, 2, 2]**** [1], [0],[1] -[62 ]---
  IN:MSMC, DMA,      2(     2),      2(     2),  180(  384),    300(    768),   0,    26000 ||||  L2, DMA,      2(     2),      2(     2),  180(  384),    300(    768),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,      2(     2),      2(     2),  180(  384),    300(    768),   0,    23000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  64(TIDL_EltWiseLayer) [64, 64] --[768 x 12 x  12] => [384 x 12 x  12] *** [768] ***[ COL] ***[0, 0, 0, 288, 288]**** [4], [0],[4] -[57 63 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),  180(  384),  1e000( 122880),   0,     5000 ||||  L2, DMA,    144(   324),    144(   324),   c0(  192),  1e600( 124416),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),  180(  384),  1e000( 122880),   0,    23300 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  65(TIDL_ConvolutionLayer) [65, 65] --[384 x 12 x  12] => [64 x 12 x  12] *** [384] ***[ROW_L] ***[0, 0, 0, 288, 288]**** [1], [1],[1] -[64 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),  180(  384),  1e000( 122880),   0,    23300 ||||  L2, DMA,    140(   320),    140(   320),  180(  384),  1e080( 123008),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),   40(   64),   5000(  20480),   0,    12200 
  WT:DDR_PERSIST, DMA,    300(   768),    300(   768),   40(   64),   c200(  49664),   0,    b8480 ||||MSMC, DMA,    340(   832),    300(   768),   40(   64),   d200(  53760),   0,     5000 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  66(TIDL_EltWiseLayer) [66, 66] --[128 x 12 x  12] => [64 x 12 x  12] *** [128] ***[ COL] ***[0, 0, 0, 288, 288]**** [2], [0],[2] -[55 65 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),   40(   64),   5000(  20480),   0,        0 ||||  L2, DMA,    144(   324),    144(   324),   40(   64),   a200(  41472),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),   40(   64),   5000(  20480),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  67(TIDL_ConvolutionLayer) [67, 67] --[64 x 12 x  12] => [384 x 12 x  12] *** [64] ***[ROW_L] ***[0, 0, 0, 288, 288]**** [1], [1],[1] -[66 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),   40(   64),   5000(  20480),   0,        0 ||||  L2, DMA,    140(   320),    140(   320),   40(   64),   5080(  20608),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),  180(  384),  1e000( 122880),   0,    17c00 
  WT:DDR_PERSIST, DMA,     80(   128),     80(   128),  180(  384),   cc00(  52224),   0,    c4680 ||||MSMC, DMA,     c0(   192),     80(   128),  180(  384),  12c00(  76800),   0,     5000 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  69(TIDL_ConvolutionLayer) [68, 69] --[384 x 12 x  12] => [384 x 12 x  12] *** [1] ***[ COL] ***[0, 0, 0, 288, 288]**** [1], [1],[1] -[67 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),  180(  384),  1e000( 122880),   0,    17c00 ||||  L2, DMA,    120(   288),    120(   288),  180(  384),  1b080( 110720),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),  180(  384),  1e000( 122880),   0,     5000 
  WT:DDR_PERSIST, DMA,     14(    20),     14(    20),  900( 2304),   b400(  46080),   0,    d1280 ||||MSMC, DMA,     14(    20),     14(    20),  900( 2304),   b400(  46080),   0,    35c00 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  71(TIDL_PoolingLayer) [69, 71] --[384 x 12 x  12] => [384 x 6 x  6] *** [384] ***[ COL] ***[0, 0, 0, 288, 288]**** [1], [0],[1] -[69 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),  180(  384),  1e000( 122880),   0,     5000 ||||  L2, DMA,    144(   324),    144(   324),  180(  384),  1e680( 124544),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     c0(   192),     48(    72),  180(  384),  12000(  73728),   0,    23000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  73(TIDL_PoolingLayer) [70, 73] --[384 x 6 x  6] => [384 x 3 x  3] *** [384] ***[ COL] ***[0, 0, 0, 72, 72]**** [1], [0],[1] -[71 ]---
  IN:MSMC, DMA,     c0(   192),     48(    72),  180(  384),  12000(  73728),   0,    23000 ||||  L2, DMA,     c0(   192),     c0(   192),  180(  384),  12080(  73856),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     12(    18),     12(    18),  180(  384),   1b00(   6912),   0,    23000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  75(TIDL_PoolingLayer) [71, 75] --[384 x 3 x  3] => [384 x 1 x  1] *** [384] ***[ COL] ***[0, 0, 0, 18, 18]**** [1], [0],[1] -[73 ]---
  IN:MSMC, DMA,     12(    18),     12(    18),  180(  384),   1b00(   6912),   0,    23000 ||||  L2, DMA,     12(    18),     12(    18),  180(  384),   1c00(   7168),   0,       80 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,      2(     2),      2(     2),  180(  384),    300(    768),   0,    23000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  77(TIDL_ConvolutionLayer) [72, 77] --[384 x 1 x  1] => [24 x 1 x  1] *** [384] ***[ROW_L] ***[0, 0, 0, 2, 2]**** [1], [1],[1] -[75 ]---
  IN:MSMC, DMA,      2(     2),      2(     2),  180(  384),    300(    768),   0,    23000 ||||  L2, DMA,      2(     2),      2(     2),  180(  384),    380(    896),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,      2(     2),      2(     2),   18(   24),     80(    128),   0,    28400 
  WT:DDR_PERSIST, DMA,    300(   768),    300(   768),   18(   24),   4900(  18688),   0,    dc680 ||||MSMC, DMA,    340(   832),    300(   768),   18(   24),   4f00(  20224),   0,    23300 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  79(TIDL_ConvolutionLayer) [73, 79] --[24 x 1 x  1] => [384 x 1 x  1] *** [24] ***[ROW_L] ***[0, 0, 0, 2, 2]**** [1], [1],[1] -[77 ]---
  IN:MSMC, DMA,      2(     2),      2(     2),   18(   24),     80(    128),   0,    28400 ||||  L2, DMA,      2(     2),      2(     2),   18(   24),    100(    256),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,      2(     2),      2(     2),  180(  384),    300(    768),   0,    28400 
  WT:DDR_PERSIST, DMA,     30(    48),     30(    48),  180(  384),   5400(  21504),   0,    e0f80 ||||MSMC, DMA,     30(    48),     30(    48),  180(  384),   5400(  21504),   0,    23000 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  81(TIDL_BatchNormLayer) [74, 81] --[384 x 1 x  1] => [384 x 1 x  1] *** [384] ***[ COL] ***[0, 0, 0, 2, 2]**** [1], [0],[1] -[79 ]---
  IN:MSMC, DMA,      2(     2),      2(     2),  180(  384),    300(    768),   0,    28400 ||||  L2, DMA,      2(     2),      2(     2),  180(  384),    300(    768),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,      2(     2),      2(     2),  180(  384),    300(    768),   0,    23000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  83(TIDL_EltWiseLayer) [75, 83] --[768 x 12 x  12] => [384 x 12 x  12] *** [768] ***[ COL] ***[0, 0, 0, 288, 288]**** [4], [0],[4] -[69 81 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),  180(  384),  1e000( 122880),   0,     5000 ||||  L2, DMA,    144(   324),    144(   324),   c0(  192),  1e600( 124416),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),  180(  384),  1e000( 122880),   0,    23300 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  85(TIDL_ConvolutionLayer) [76, 85] --[384 x 12 x  12] => [64 x 12 x  12] *** [384] ***[ROW_L] ***[0, 0, 0, 288, 288]**** [1], [1],[1] -[83 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),  180(  384),  1e000( 122880),   0,    23300 ||||  L2, DMA,    140(   320),    140(   320),  180(  384),  1e080( 123008),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),   40(   64),   5000(  20480),   0,    12200 
  WT:DDR_PERSIST, DMA,    300(   768),    300(   768),   40(   64),   c200(  49664),   0,    e6380 ||||MSMC, DMA,    340(   832),    300(   768),   40(   64),   d200(  53760),   0,     5000 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  87(TIDL_EltWiseLayer) [77, 87] --[128 x 12 x  12] => [64 x 12 x  12] *** [128] ***[ COL] ***[0, 0, 0, 288, 288]**** [2], [0],[2] -[66 85 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),   40(   64),   5000(  20480),   0,        0 ||||  L2, DMA,    144(   324),    144(   324),   40(   64),   a200(  41472),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),   40(   64),   5000(  20480),   0,     5000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  89(TIDL_ConvolutionLayer) [78, 89] --[64 x 12 x  12] => [384 x 12 x  12] *** [64] ***[ROW_L] ***[0, 0, 0, 288, 288]**** [1], [1],[1] -[87 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),   40(   64),   5000(  20480),   0,     5000 ||||  L2, DMA,    140(   320),    140(   320),   40(   64),   5080(  20608),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),  180(  384),  1e000( 122880),   0,    1cc00 
  WT:DDR_PERSIST, DMA,     80(   128),     80(   128),  180(  384),   cc00(  52224),   0,    f2580 ||||MSMC, DMA,     c0(   192),     80(   128),  180(  384),  12c00(  76800),   0,     a000 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  91(TIDL_ConvolutionLayer) [79, 91] --[384 x 12 x  12] => [384 x 12 x  12] *** [1] ***[ COL] ***[0, 0, 0, 288, 288]**** [1], [1],[1] -[89 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),  180(  384),  1e000( 122880),   0,    1cc00 ||||  L2, DMA,    120(   288),    120(   288),  180(  384),  1b080( 110720),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),  180(  384),  1e000( 122880),   0,     a000 
  WT:DDR_PERSIST, DMA,     14(    20),     14(    20),  900( 2304),   b400(  46080),   0,    ff180 ||||MSMC, DMA,     14(    20),     14(    20),  900( 2304),   b400(  46080),   0,    3ac00 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  92(TIDL_PoolingLayer) [80, 92] --[384 x 12 x  12] => [384 x 6 x  6] *** [384] ***[ COL] ***[0, 0, 0, 288, 288]**** [1], [0],[1] -[91 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),  180(  384),  1e000( 122880),   0,     a000 ||||  L2, DMA,    144(   324),    144(   324),  180(  384),  1e680( 124544),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     c0(   192),     48(    72),  180(  384),  12000(  73728),   0,    28000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  93(TIDL_PoolingLayer) [81, 93] --[384 x 6 x  6] => [384 x 3 x  3] *** [384] ***[ COL] ***[0, 0, 0, 72, 72]**** [1], [0],[1] -[92 ]---
  IN:MSMC, DMA,     c0(   192),     48(    72),  180(  384),  12000(  73728),   0,    28000 ||||  L2, DMA,     c0(   192),     c0(   192),  180(  384),  12080(  73856),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     12(    18),     12(    18),  180(  384),   1b00(   6912),   0,    28000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  94(TIDL_PoolingLayer) [82, 94] --[384 x 3 x  3] => [384 x 1 x  1] *** [384] ***[ COL] ***[0, 0, 0, 18, 18]**** [1], [0],[1] -[93 ]---
  IN:MSMC, DMA,     12(    18),     12(    18),  180(  384),   1b00(   6912),   0,    28000 ||||  L2, DMA,     12(    18),     12(    18),  180(  384),   1c00(   7168),   0,       80 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,      2(     2),      2(     2),  180(  384),    300(    768),   0,    28000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  95(TIDL_ConvolutionLayer) [83, 95] --[384 x 1 x  1] => [24 x 1 x  1] *** [384] ***[ROW_L] ***[0, 0, 0, 2, 2]**** [1], [1],[1] -[94 ]---
  IN:MSMC, DMA,      2(     2),      2(     2),  180(  384),    300(    768),   0,    28000 ||||  L2, DMA,      2(     2),      2(     2),  180(  384),    380(    896),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,      2(     2),      2(     2),   18(   24),     80(    128),   0,    2d400 
  WT:DDR_PERSIST, DMA,    300(   768),    300(   768),   18(   24),   4900(  18688),   0,   10a580 ||||MSMC, DMA,    340(   832),    300(   768),   18(   24),   4f00(  20224),   0,    28300 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  96(TIDL_ConvolutionLayer) [84, 96] --[24 x 1 x  1] => [384 x 1 x  1] *** [24] ***[ROW_L] ***[0, 0, 0, 2, 2]**** [1], [1],[1] -[95 ]---
  IN:MSMC, DMA,      2(     2),      2(     2),   18(   24),     80(    128),   0,    2d400 ||||  L2, DMA,      2(     2),      2(     2),   18(   24),    100(    256),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,      2(     2),      2(     2),  180(  384),    300(    768),   0,    2d400 
  WT:DDR_PERSIST, DMA,     30(    48),     30(    48),  180(  384),   5400(  21504),   0,   10ee80 ||||MSMC, DMA,     30(    48),     30(    48),  180(  384),   5400(  21504),   0,    28000 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  97(TIDL_BatchNormLayer) [85, 97] --[384 x 1 x  1] => [384 x 1 x  1] *** [384] ***[ COL] ***[0, 0, 0, 2, 2]**** [1], [0],[1] -[96 ]---
  IN:MSMC, DMA,      2(     2),      2(     2),  180(  384),    300(    768),   0,    2d400 ||||  L2, DMA,      2(     2),      2(     2),  180(  384),    300(    768),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,      2(     2),      2(     2),  180(  384),    300(    768),   0,    28000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  98(TIDL_EltWiseLayer) [86, 98] --[768 x 12 x  12] => [384 x 12 x  12] *** [768] ***[ COL] ***[0, 0, 0, 288, 288]**** [4], [0],[4] -[91 97 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),  180(  384),  1e000( 122880),   0,     a000 ||||  L2, DMA,    144(   324),    144(   324),   c0(  192),  1e600( 124416),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),  180(  384),  1e000( 122880),   0,    28300 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  99(TIDL_ConvolutionLayer) [87, 99] --[384 x 12 x  12] => [64 x 12 x  12] *** [384] ***[ROW_L] ***[0, 0, 0, 288, 288]**** [1], [1],[1] -[98 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),  180(  384),  1e000( 122880),   0,    28300 ||||  L2, DMA,    140(   320),    140(   320),  180(  384),  1e080( 123008),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),   40(   64),   5000(  20480),   0,    17200 
  WT:DDR_PERSIST, DMA,    300(   768),    300(   768),   40(   64),   c200(  49664),   0,   114280 ||||MSMC, DMA,    340(   832),    300(   768),   40(   64),   d200(  53760),   0,     a000 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  100(TIDL_EltWiseLayer) [88, 100] --[128 x 12 x  12] => [64 x 12 x  12] *** [128] ***[ COL] ***[0, 0, 0, 288, 288]**** [2], [0],[2] -[87 99 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),   40(   64),   5000(  20480),   0,     5000 ||||  L2, DMA,    144(   324),    144(   324),   40(   64),   a200(  41472),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),   40(   64),   5000(  20480),   0,     5000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  101(TIDL_ConvolutionLayer) [89, 101] --[64 x 12 x  12] => [384 x 12 x  12] *** [64] ***[ROW_L] ***[0, 0, 0, 288, 288]**** [1], [1],[1] -[100 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),   40(   64),   5000(  20480),   0,     5000 ||||  L2, DMA,    140(   320),    140(   320),   40(   64),   5080(  20608),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),  180(  384),  1e000( 122880),   0,    1cc00 
  WT:DDR_PERSIST, DMA,     80(   128),     80(   128),  180(  384),   cc00(  52224),   0,   120480 ||||MSMC, DMA,     c0(   192),     80(   128),  180(  384),  12c00(  76800),   0,     a000 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  102(TIDL_ConvolutionLayer) [90, 102] --[384 x 12 x  12] => [384 x 12 x  12] *** [1] ***[ COL] ***[0, 0, 0, 288, 288]**** [1], [1],[1] -[101 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),  180(  384),  1e000( 122880),   0,    1cc00 ||||  L2, DMA,    120(   288),    120(   288),  180(  384),  1b080( 110720),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),  180(  384),  1e000( 122880),   0,     a000 
  WT:DDR_PERSIST, DMA,     14(    20),     14(    20),  900( 2304),   b400(  46080),   0,   12d080 ||||MSMC, DMA,     14(    20),     14(    20),  900( 2304),   b400(  46080),   0,    3ac00 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  103(TIDL_PoolingLayer) [91, 103] --[384 x 12 x  12] => [384 x 6 x  6] *** [384] ***[ COL] ***[0, 0, 0, 288, 288]**** [1], [0],[1] -[102 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),  180(  384),  1e000( 122880),   0,     a000 ||||  L2, DMA,    144(   324),    144(   324),  180(  384),  1e680( 124544),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     c0(   192),     48(    72),  180(  384),  12000(  73728),   0,    28000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  104(TIDL_PoolingLayer) [92, 104] --[384 x 6 x  6] => [384 x 3 x  3] *** [384] ***[ COL] ***[0, 0, 0, 72, 72]**** [1], [0],[1] -[103 ]---
  IN:MSMC, DMA,     c0(   192),     48(    72),  180(  384),  12000(  73728),   0,    28000 ||||  L2, DMA,     c0(   192),     c0(   192),  180(  384),  12080(  73856),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     12(    18),     12(    18),  180(  384),   1b00(   6912),   0,    28000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  105(TIDL_PoolingLayer) [93, 105] --[384 x 3 x  3] => [384 x 1 x  1] *** [384] ***[ COL] ***[0, 0, 0, 18, 18]**** [1], [0],[1] -[104 ]---
  IN:MSMC, DMA,     12(    18),     12(    18),  180(  384),   1b00(   6912),   0,    28000 ||||  L2, DMA,     12(    18),     12(    18),  180(  384),   1c00(   7168),   0,       80 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,      2(     2),      2(     2),  180(  384),    300(    768),   0,    28000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  106(TIDL_ConvolutionLayer) [94, 106] --[384 x 1 x  1] => [24 x 1 x  1] *** [384] ***[ROW_L] ***[0, 0, 0, 2, 2]**** [1], [1],[1] -[105 ]---
  IN:MSMC, DMA,      2(     2),      2(     2),  180(  384),    300(    768),   0,    28000 ||||  L2, DMA,      2(     2),      2(     2),  180(  384),    380(    896),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,      2(     2),      2(     2),   18(   24),     80(    128),   0,    2d400 
  WT:DDR_PERSIST, DMA,    300(   768),    300(   768),   18(   24),   4900(  18688),   0,   138480 ||||MSMC, DMA,    340(   832),    300(   768),   18(   24),   4f00(  20224),   0,    28300 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  107(TIDL_ConvolutionLayer) [95, 107] --[24 x 1 x  1] => [384 x 1 x  1] *** [24] ***[ROW_L] ***[0, 0, 0, 2, 2]**** [1], [1],[1] -[106 ]---
  IN:MSMC, DMA,      2(     2),      2(     2),   18(   24),     80(    128),   0,    2d400 ||||  L2, DMA,      2(     2),      2(     2),   18(   24),    100(    256),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,      2(     2),      2(     2),  180(  384),    300(    768),   0,    2d400 
  WT:DDR_PERSIST, DMA,     30(    48),     30(    48),  180(  384),   5400(  21504),   0,   13cd80 ||||MSMC, DMA,     30(    48),     30(    48),  180(  384),   5400(  21504),   0,    28000 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  108(TIDL_BatchNormLayer) [96, 108] --[384 x 1 x  1] => [384 x 1 x  1] *** [384] ***[ COL] ***[0, 0, 0, 2, 2]**** [1], [0],[1] -[107 ]---
  IN:MSMC, DMA,      2(     2),      2(     2),  180(  384),    300(    768),   0,    2d400 ||||  L2, DMA,      2(     2),      2(     2),  180(  384),    300(    768),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,      2(     2),      2(     2),  180(  384),    300(    768),   0,    28000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  109(TIDL_EltWiseLayer) [97, 109] --[768 x 12 x  12] => [384 x 12 x  12] *** [768] ***[ COL] ***[0, 0, 0, 288, 288]**** [4], [0],[4] -[102 108 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),  180(  384),  1e000( 122880),   0,     a000 ||||  L2, DMA,    144(   324),    144(   324),   c0(  192),  1e600( 124416),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),  180(  384),  1e000( 122880),   0,    28300 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  110(TIDL_ConvolutionLayer) [98, 110] --[384 x 12 x  12] => [64 x 12 x  12] *** [384] ***[ROW_L] ***[0, 0, 0, 288, 288]**** [1], [1],[1] -[109 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),  180(  384),  1e000( 122880),   0,    28300 ||||  L2, DMA,    140(   320),    140(   320),  180(  384),  1e080( 123008),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),   40(   64),   5000(  20480),   0,    17c00 
  WT:DDR_PERSIST, DMA,    300(   768),    300(   768),   40(   64),   c200(  49664),   0,   142180 ||||MSMC, DMA,    340(   832),    300(   768),   40(   64),   d200(  53760),   0,     a000 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  111(TIDL_EltWiseLayer) [99, 111] --[128 x 12 x  12] => [64 x 12 x  12] *** [128] ***[ COL] ***[0, 0, 0, 288, 288]**** [2], [0],[2] -[100 110 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),   40(   64),   5000(  20480),   0,     5000 ||||  L2, DMA,    144(   324),    144(   324),   40(   64),   a200(  41472),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),   40(   64),   5000(  20480),   0,    17c00 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  112(TIDL_ConvolutionLayer) [100, 112] --[64 x 12 x  12] => [384 x 12 x  12] *** [64] ***[ROW_L] ***[0, 0, 0, 288, 288]**** [1], [1],[1] -[111 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),   40(   64),   5000(  20480),   0,    17c00 ||||  L2, DMA,    140(   320),    140(   320),   40(   64),   5080(  20608),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),  180(  384),  1e000( 122880),   0,    17c00 
  WT:DDR_PERSIST, DMA,     80(   128),     80(   128),  180(  384),   cc00(  52224),   0,   14e380 ||||MSMC, DMA,     c0(   192),     80(   128),  180(  384),  12c00(  76800),   0,     5000 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  113(TIDL_ConvolutionLayer) [101, 113] --[384 x 12 x  12] => [384 x 6 x  6] *** [1] ***[ COL] ***[0, 0, 0, 288, 288]**** [1], [1],[1] -[112 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),  180(  384),  1e000( 122880),   0,    17c00 ||||  L2, DMA,    120(   288),    120(   288),  180(  384),  1b080( 110720),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     c0(   192),     60(    96),  180(  384),  1200c(  73740),   c,    10474 
  WT:DDR_PERSIST, DMA,     14(    20),     14(    20),  900( 2304),   b400(  46080),   0,   15af80 ||||MSMC, DMA,     14(    20),     14(    20),  900( 2304),   b400(  46080),   0,     5000 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  114(TIDL_PoolingLayer) [102, 114] --[384 x 6 x  6] => [384 x 3 x  3] *** [384] ***[ COL] ***[0, 0, 0, 72, 72]**** [1], [0],[1] -[113 ]---
  IN:MSMC, DMA,     c0(   192),     60(    96),  180(  384),  1200c(  73740),   c,    10474 ||||  L2, DMA,     c0(   192),     c0(   192),  180(  384),  12080(  73856),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     12(    18),     12(    18),  180(  384),   1b00(   6912),   0,     5080 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  115(TIDL_PoolingLayer) [103, 115] --[384 x 3 x  3] => [384 x 1 x  1] *** [384] ***[ COL] ***[0, 0, 0, 18, 18]**** [1], [0],[1] -[114 ]---
  IN:MSMC, DMA,     12(    18),     12(    18),  180(  384),   1b00(   6912),   0,     5080 ||||  L2, DMA,     12(    18),     12(    18),  180(  384),   1c00(   7168),   0,       80 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,      6(     6),      6(     6),  180(  384),    902(   2306),   2,     507e 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  116(TIDL_ConvolutionLayer) [104, 116] --[384 x 1 x  1] => [36 x 1 x  1] *** [384] ***[ROW_L] ***[0, 0, 0, 2, 2]**** [1], [1],[1] -[115 ]---
  IN:MSMC, DMA,      6(     6),      6(     6),  180(  384),    902(   2306),   2,     507e ||||  L2, DMA,      2(     2),      2(     2),  180(  384),    380(    896),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,      6(     6),      6(     6),   24(   36),    102(    258),   2,     507e 
  WT:DDR_PERSIST, DMA,    300(   768),    300(   768),   24(   36),   6d80(  28032),   0,   166380 ||||MSMC, DMA,    340(   832),    300(   768),   24(   36),   7680(  30336),   0,     5980 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  117(TIDL_ConvolutionLayer) [105, 117] --[36 x 1 x  1] => [384 x 1 x  1] *** [36] ***[ROW_L] ***[0, 0, 0, 2, 2]**** [1], [1],[1] -[116 ]---
  IN:MSMC, DMA,      6(     6),      6(     6),   24(   36),    102(    258),   2,     507e ||||  L2, DMA,      2(     2),      2(     2),   24(   36),    100(    256),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,      6(     6),      6(     6),  180(  384),    902(   2306),   2,     507e 
  WT:DDR_PERSIST, DMA,     48(    72),     48(    72),  180(  384),   7800(  30720),   0,   16d100 ||||MSMC, DMA,     c0(   192),     48(    72),  180(  384),  12c00(  76800),   0,    22480 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  118(TIDL_BatchNormLayer) [106, 118] --[384 x 1 x  1] => [384 x 1 x  1] *** [384] ***[ COL] ***[0, 0, 0, 2, 2]**** [1], [0],[1] -[117 ]---
  IN:MSMC, DMA,      6(     6),      6(     6),  180(  384),    902(   2306),   2,     507e ||||  L2, DMA,      6(     6),      6(     6),  180(  384),    900(   2304),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,      6(     6),      6(     6),  180(  384),    902(   2306),   2,     507e 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  119(TIDL_EltWiseLayer) [107, 119] --[768 x 6 x  6] => [384 x 6 x  6] *** [768] ***[ COL] ***[0, 0, 0, 72, 72]**** [2], [0],[2] -[113 118 ]---
  IN:MSMC, DMA,     c0(   192),     60(    96),  180(  384),  1200c(  73740),   c,    10474 ||||  L2, DMA,     c0(   192),     c0(   192),  180(  384),  24000( 147456),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     c0(   192),     60(    96),  180(  384),  1200c(  73740),   c,    224f4 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  120(TIDL_ConvolutionLayer) [108, 120] --[384 x 6 x  6] => [64 x 6 x  6] *** [384] ***[ROW_L] ***[0, 0, 0, 72, 72]**** [1], [1],[1] -[119 ]---
  IN:MSMC, DMA,     c0(   192),     60(    96),  180(  384),  1200c(  73740),   c,    224f4 ||||  L2, DMA,     c0(   192),     c0(   192),  180(  384),  12080(  73856),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     c0(   192),     60(    96),   40(   64),   300c(  12300),   c,     5074 
  WT:DDR_PERSIST, DMA,    300(   768),    300(   768),   40(   64),   c200(  49664),   0,   174900 ||||MSMC, DMA,    340(   832),    300(   768),   40(   64),   d200(  53760),   0,     8080 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  121(TIDL_ConvolutionLayer) [109, 121] --[64 x 6 x  6] => [384 x 6 x  6] *** [64] ***[ROW_L] ***[0, 0, 0, 72, 72]**** [1], [1],[1] -[120 ]---
  IN:MSMC, DMA,     c0(   192),     60(    96),   40(   64),   300c(  12300),   c,     5074 ||||  L2, DMA,     c0(   192),     c0(   192),   40(   64),   3080(  12416),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     c0(   192),     60(    96),  180(  384),  1200c(  73740),   c,    1acf4 
  WT:DDR_PERSIST, DMA,     80(   128),     80(   128),  180(  384),   cc00(  52224),   0,   180b00 ||||MSMC, DMA,     c0(   192),     80(   128),  180(  384),  12c00(  76800),   0,     8080 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  122(TIDL_ConvolutionLayer) [110, 122] --[384 x 6 x  6] => [384 x 6 x  6] *** [1] ***[ COL] ***[0, 0, 0, 72, 72]**** [1], [1],[1] -[121 ]---
  IN:MSMC, DMA,     c0(   192),     60(    96),  180(  384),  1200c(  73740),   c,    1acf4 ||||  L2, DMA,     48(    72),     48(    72),  180(  384),   6c80(  27776),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     c0(   192),     60(    96),  180(  384),  1200c(  73740),   c,     80f4 
  WT:DDR_PERSIST, DMA,     14(    20),     14(    20),  900( 2304),   b400(  46080),   0,   18d700 ||||MSMC, DMA,     14(    20),     14(    20),  900( 2304),   b400(  46080),   0,    2cd00 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  123(TIDL_PoolingLayer) [111, 123] --[384 x 6 x  6] => [384 x 3 x  3] *** [384] ***[ COL] ***[0, 0, 0, 72, 72]**** [1], [0],[1] -[122 ]---
  IN:MSMC, DMA,     c0(   192),     60(    96),  180(  384),  1200c(  73740),   c,     80f4 ||||  L2, DMA,     c0(   192),     c0(   192),  180(  384),  12080(  73856),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     12(    18),     12(    18),  180(  384),   1b00(   6912),   0,    1a180 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  124(TIDL_PoolingLayer) [112, 124] --[384 x 3 x  3] => [384 x 1 x  1] *** [384] ***[ COL] ***[0, 0, 0, 18, 18]**** [1], [0],[1] -[123 ]---
  IN:MSMC, DMA,     12(    18),     12(    18),  180(  384),   1b00(   6912),   0,    1a180 ||||  L2, DMA,     12(    18),     12(    18),  180(  384),   1c00(   7168),   0,       80 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,      6(     6),      6(     6),  180(  384),    902(   2306),   2,    1a17e 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  125(TIDL_ConvolutionLayer) [113, 125] --[384 x 1 x  1] => [36 x 1 x  1] *** [384] ***[ROW_L] ***[0, 0, 0, 2, 2]**** [1], [1],[1] -[124 ]---
  IN:MSMC, DMA,      6(     6),      6(     6),  180(  384),    902(   2306),   2,    1a17e ||||  L2, DMA,      2(     2),      2(     2),  180(  384),    380(    896),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,      6(     6),      6(     6),   24(   36),    102(    258),   2,    2cd7e 
  WT:DDR_PERSIST, DMA,    300(   768),    300(   768),   24(   36),   6d80(  28032),   0,   198b00 ||||MSMC, DMA,    340(   832),    300(   768),   24(   36),   7680(  30336),   0,    1aa80 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  126(TIDL_ConvolutionLayer) [114, 126] --[36 x 1 x  1] => [384 x 1 x  1] *** [36] ***[ROW_L] ***[0, 0, 0, 2, 2]**** [1], [1],[1] -[125 ]---
  IN:MSMC, DMA,      6(     6),      6(     6),   24(   36),    102(    258),   2,    2cd7e ||||  L2, DMA,      2(     2),      2(     2),   24(   36),    100(    256),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,      6(     6),      6(     6),  180(  384),    902(   2306),   2,    2cd7e 
  WT:DDR_PERSIST, DMA,     48(    72),     48(    72),  180(  384),   7800(  30720),   0,   19f880 ||||MSMC, DMA,     c0(   192),     48(    72),  180(  384),  12c00(  76800),   0,    1a100 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  127(TIDL_BatchNormLayer) [115, 127] --[384 x 1 x  1] => [384 x 1 x  1] *** [384] ***[ COL] ***[0, 0, 0, 2, 2]**** [1], [0],[1] -[126 ]---
  IN:MSMC, DMA,      6(     6),      6(     6),  180(  384),    902(   2306),   2,    2cd7e ||||  L2, DMA,      6(     6),      6(     6),  180(  384),    900(   2304),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,      6(     6),      6(     6),  180(  384),    902(   2306),   2,    1a17e 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  128(TIDL_EltWiseLayer) [116, 128] --[768 x 6 x  6] => [384 x 6 x  6] *** [768] ***[ COL] ***[0, 0, 0, 72, 72]**** [2], [0],[2] -[122 127 ]---
  IN:MSMC, DMA,     c0(   192),     60(    96),  180(  384),  1200c(  73740),   c,     80f4 ||||  L2, DMA,     c0(   192),     c0(   192),  180(  384),  24000( 147456),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     c0(   192),     60(    96),  180(  384),  1200c(  73740),   c,    1aaf4 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  129(TIDL_ConvolutionLayer) [117, 129] --[384 x 6 x  6] => [64 x 6 x  6] *** [384] ***[ROW_L] ***[0, 0, 0, 72, 72]**** [1], [1],[1] -[128 ]---
  IN:MSMC, DMA,     c0(   192),     60(    96),  180(  384),  1200c(  73740),   c,    1aaf4 ||||  L2, DMA,     c0(   192),     c0(   192),  180(  384),  12080(  73856),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     c0(   192),     60(    96),   40(   64),   300c(  12300),   c,    152f4 
  WT:DDR_PERSIST, DMA,    300(   768),    300(   768),   40(   64),   c200(  49664),   0,   1a7080 ||||MSMC, DMA,    340(   832),    300(   768),   40(   64),   d200(  53760),   0,     8080 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  130(TIDL_EltWiseLayer) [118, 130] --[128 x 6 x  6] => [64 x 6 x  6] *** [128] ***[ COL] ***[0, 0, 0, 72, 72]**** [2], [0],[2] -[120 129 ]---
  IN:MSMC, DMA,     c0(   192),     60(    96),   40(   64),   300c(  12300),   c,     5074 ||||  L2, DMA,     c0(   192),     c0(   192),   40(   64),   6000(  24576),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     c0(   192),     60(    96),   40(   64),   300c(  12300),   c,     5074 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  131(TIDL_ConvolutionLayer) [119, 131] --[64 x 6 x  6] => [384 x 6 x  6] *** [64] ***[ROW_L] ***[0, 0, 0, 72, 72]**** [1], [1],[1] -[130 ]---
  IN:MSMC, DMA,     c0(   192),     60(    96),   40(   64),   300c(  12300),   c,     5074 ||||  L2, DMA,     c0(   192),     c0(   192),   40(   64),   3080(  12416),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     c0(   192),     60(    96),  180(  384),  1200c(  73740),   c,    1acf4 
  WT:DDR_PERSIST, DMA,     80(   128),     80(   128),  180(  384),   cc00(  52224),   0,   1b3280 ||||MSMC, DMA,     c0(   192),     80(   128),  180(  384),  12c00(  76800),   0,     8080 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  132(TIDL_ConvolutionLayer) [120, 132] --[384 x 6 x  6] => [384 x 6 x  6] *** [1] ***[ COL] ***[0, 0, 0, 72, 72]**** [1], [1],[1] -[131 ]---
  IN:MSMC, DMA,     c0(   192),     60(    96),  180(  384),  1200c(  73740),   c,    1acf4 ||||  L2, DMA,     48(    72),     48(    72),  180(  384),   6c80(  27776),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     c0(   192),     60(    96),  180(  384),  1200c(  73740),   c,     80f4 
  WT:DDR_PERSIST, DMA,     14(    20),     14(    20),  900( 2304),   b400(  46080),   0,   1bfe80 ||||MSMC, DMA,     14(    20),     14(    20),  900( 2304),   b400(  46080),   0,    2cd00 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  133(TIDL_PoolingLayer) [121, 133] --[384 x 6 x  6] => [384 x 3 x  3] *** [384] ***[ COL] ***[0, 0, 0, 72, 72]**** [1], [0],[1] -[132 ]---
  IN:MSMC, DMA,     c0(   192),     60(    96),  180(  384),  1200c(  73740),   c,     80f4 ||||  L2, DMA,     c0(   192),     c0(   192),  180(  384),  12080(  73856),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     12(    18),     12(    18),  180(  384),   1b00(   6912),   0,    1a180 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  134(TIDL_PoolingLayer) [122, 134] --[384 x 3 x  3] => [384 x 1 x  1] *** [384] ***[ COL] ***[0, 0, 0, 18, 18]**** [1], [0],[1] -[133 ]---
  IN:MSMC, DMA,     12(    18),     12(    18),  180(  384),   1b00(   6912),   0,    1a180 ||||  L2, DMA,     12(    18),     12(    18),  180(  384),   1c00(   7168),   0,       80 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,      6(     6),      6(     6),  180(  384),    902(   2306),   2,    1a17e 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  135(TIDL_ConvolutionLayer) [123, 135] --[384 x 1 x  1] => [36 x 1 x  1] *** [384] ***[ROW_L] ***[0, 0, 0, 2, 2]**** [1], [1],[1] -[134 ]---
  IN:MSMC, DMA,      6(     6),      6(     6),  180(  384),    902(   2306),   2,    1a17e ||||  L2, DMA,      2(     2),      2(     2),  180(  384),    380(    896),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,      6(     6),      6(     6),   24(   36),    102(    258),   2,    2cd7e 
  WT:DDR_PERSIST, DMA,    300(   768),    300(   768),   24(   36),   6d80(  28032),   0,   1cb280 ||||MSMC, DMA,    340(   832),    300(   768),   24(   36),   7680(  30336),   0,    1aa80 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  136(TIDL_ConvolutionLayer) [124, 136] --[36 x 1 x  1] => [384 x 1 x  1] *** [36] ***[ROW_L] ***[0, 0, 0, 2, 2]**** [1], [1],[1] -[135 ]---
  IN:MSMC, DMA,      6(     6),      6(     6),   24(   36),    102(    258),   2,    2cd7e ||||  L2, DMA,      2(     2),      2(     2),   24(   36),    100(    256),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,      6(     6),      6(     6),  180(  384),    902(   2306),   2,    2cd7e 
  WT:DDR_PERSIST, DMA,     48(    72),     48(    72),  180(  384),   7800(  30720),   0,   1d2000 ||||MSMC, DMA,     c0(   192),     48(    72),  180(  384),  12c00(  76800),   0,    1a100 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  137(TIDL_BatchNormLayer) [125, 137] --[384 x 1 x  1] => [384 x 1 x  1] *** [384] ***[ COL] ***[0, 0, 0, 2, 2]**** [1], [0],[1] -[136 ]---
  IN:MSMC, DMA,      6(     6),      6(     6),  180(  384),    902(   2306),   2,    2cd7e ||||  L2, DMA,      6(     6),      6(     6),  180(  384),    900(   2304),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,      6(     6),      6(     6),  180(  384),    902(   2306),   2,    1a17e 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  138(TIDL_EltWiseLayer) [126, 138] --[768 x 6 x  6] => [384 x 6 x  6] *** [768] ***[ COL] ***[0, 0, 0, 72, 72]**** [2], [0],[2] -[132 137 ]---
  IN:MSMC, DMA,     c0(   192),     60(    96),  180(  384),  1200c(  73740),   c,     80f4 ||||  L2, DMA,     c0(   192),     c0(   192),  180(  384),  24000( 147456),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     c0(   192),     60(    96),  180(  384),  1200c(  73740),   c,    1aaf4 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  139(TIDL_ConvolutionLayer) [127, 139] --[384 x 6 x  6] => [64 x 6 x  6] *** [384] ***[ROW_L] ***[0, 0, 0, 72, 72]**** [1], [1],[1] -[138 ]---
  IN:MSMC, DMA,     c0(   192),     60(    96),  180(  384),  1200c(  73740),   c,    1aaf4 ||||  L2, DMA,     c0(   192),     c0(   192),  180(  384),  12080(  73856),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     c0(   192),     60(    96),   40(   64),   300c(  12300),   c,    152f4 
  WT:DDR_PERSIST, DMA,    300(   768),    300(   768),   40(   64),   c200(  49664),   0,   1d9800 ||||MSMC, DMA,    340(   832),    300(   768),   40(   64),   d200(  53760),   0,     8080 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  140(TIDL_EltWiseLayer) [128, 140] --[128 x 6 x  6] => [64 x 6 x  6] *** [128] ***[ COL] ***[0, 0, 0, 72, 72]**** [2], [0],[2] -[130 139 ]---
  IN:MSMC, DMA,     c0(   192),     60(    96),   40(   64),   300c(  12300),   c,     5074 ||||  L2, DMA,     c0(   192),     c0(   192),   40(   64),   6000(  24576),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     c0(   192),     60(    96),   40(   64),   300c(  12300),   c,     5074 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  141(TIDL_ConvolutionLayer) [129, 141] --[64 x 6 x  6] => [384 x 6 x  6] *** [64] ***[ROW_L] ***[0, 0, 0, 72, 72]**** [1], [1],[1] -[140 ]---
  IN:MSMC, DMA,     c0(   192),     60(    96),   40(   64),   300c(  12300),   c,     5074 ||||  L2, DMA,     c0(   192),     c0(   192),   40(   64),   3080(  12416),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     c0(   192),     60(    96),  180(  384),  1200c(  73740),   c,    1acf4 
  WT:DDR_PERSIST, DMA,     80(   128),     80(   128),  180(  384),   cc00(  52224),   0,   1e5a00 ||||MSMC, DMA,     c0(   192),     80(   128),  180(  384),  12c00(  76800),   0,     8080 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  142(TIDL_ConvolutionLayer) [130, 142] --[384 x 6 x  6] => [384 x 6 x  6] *** [1] ***[ COL] ***[0, 0, 0, 72, 72]**** [1], [1],[1] -[141 ]---
  IN:MSMC, DMA,     c0(   192),     60(    96),  180(  384),  1200c(  73740),   c,    1acf4 ||||  L2, DMA,     48(    72),     48(    72),  180(  384),   6c80(  27776),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     c0(   192),     60(    96),  180(  384),  1200c(  73740),   c,     80f4 
  WT:DDR_PERSIST, DMA,     14(    20),     14(    20),  900( 2304),   b400(  46080),   0,   1f2600 ||||MSMC, DMA,     14(    20),     14(    20),  900( 2304),   b400(  46080),   0,    2cd00 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  143(TIDL_PoolingLayer) [131, 143] --[384 x 6 x  6] => [384 x 3 x  3] *** [384] ***[ COL] ***[0, 0, 0, 72, 72]**** [1], [0],[1] -[142 ]---
  IN:MSMC, DMA,     c0(   192),     60(    96),  180(  384),  1200c(  73740),   c,     80f4 ||||  L2, DMA,     c0(   192),     c0(   192),  180(  384),  12080(  73856),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     12(    18),     12(    18),  180(  384),   1b00(   6912),   0,    1a180 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  144(TIDL_PoolingLayer) [132, 144] --[384 x 3 x  3] => [384 x 1 x  1] *** [384] ***[ COL] ***[0, 0, 0, 18, 18]**** [1], [0],[1] -[143 ]---
  IN:MSMC, DMA,     12(    18),     12(    18),  180(  384),   1b00(   6912),   0,    1a180 ||||  L2, DMA,     12(    18),     12(    18),  180(  384),   1c00(   7168),   0,       80 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,      6(     6),      6(     6),  180(  384),    902(   2306),   2,    1a17e 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  145(TIDL_ConvolutionLayer) [133, 145] --[384 x 1 x  1] => [60 x 1 x  1] *** [384] ***[ROW_L] ***[0, 0, 0, 2, 2]**** [1], [1],[1] -[144 ]---
  IN:MSMC, DMA,      6(     6),      6(     6),  180(  384),    902(   2306),   2,    1a17e ||||  L2, DMA,      2(     2),      2(     2),  180(  384),    380(    896),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,      6(     6),      6(     6),   3c(   60),    182(    386),   2,    2cd7e 
  WT:DDR_PERSIST, DMA,    300(   768),    300(   768),   3c(   60),   b600(  46592),   0,   1fda00 ||||MSMC, DMA,    340(   832),    300(   768),   3c(   60),   c500(  50432),   0,    1aa80 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  146(TIDL_ConvolutionLayer) [134, 146] --[60 x 1 x  1] => [384 x 1 x  1] *** [60] ***[ROW_L] ***[0, 0, 0, 2, 2]**** [1], [1],[1] -[145 ]---
  IN:MSMC, DMA,      6(     6),      6(     6),   3c(   60),    182(    386),   2,    2cd7e ||||  L2, DMA,      2(     2),      2(     2),   3c(   60),    100(    256),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,      6(     6),      6(     6),  180(  384),    902(   2306),   2,    2cd7e 
  WT:DDR_PERSIST, DMA,     78(   120),     78(   120),  180(  384),   c000(  49152),   0,   209000 ||||MSMC, DMA,     c0(   192),     78(   120),  180(  384),  12c00(  76800),   0,    1a100 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  147(TIDL_BatchNormLayer) [135, 147] --[384 x 1 x  1] => [384 x 1 x  1] *** [384] ***[ COL] ***[0, 0, 0, 2, 2]**** [1], [0],[1] -[146 ]---
  IN:MSMC, DMA,      6(     6),      6(     6),  180(  384),    902(   2306),   2,    2cd7e ||||  L2, DMA,      6(     6),      6(     6),  180(  384),    900(   2304),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,      6(     6),      6(     6),  180(  384),    902(   2306),   2,    1a17e 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  148(TIDL_EltWiseLayer) [136, 148] --[768 x 6 x  6] => [384 x 6 x  6] *** [768] ***[ COL] ***[0, 0, 0, 72, 72]**** [2], [0],[2] -[142 147 ]---
  IN:MSMC, DMA,     c0(   192),     60(    96),  180(  384),  1200c(  73740),   c,     80f4 ||||  L2, DMA,     c0(   192),     c0(   192),  180(  384),  24000( 147456),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     c0(   192),     60(    96),  180(  384),  1200c(  73740),   c,    1aaf4 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  149(TIDL_ConvolutionLayer) [137, 149] --[384 x 6 x  6] => [64 x 6 x  6] *** [384] ***[ROW_L] ***[0, 0, 0, 72, 72]**** [1], [1],[1] -[148 ]---
  IN:MSMC, DMA,     c0(   192),     60(    96),  180(  384),  1200c(  73740),   c,    1aaf4 ||||  L2, DMA,     c0(   192),     c0(   192),  180(  384),  12080(  73856),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     c0(   192),     60(    96),   40(   64),   300c(  12300),   c,    152f4 
  WT:DDR_PERSIST, DMA,    300(   768),    300(   768),   40(   64),   c200(  49664),   0,   215000 ||||MSMC, DMA,    340(   832),    300(   768),   40(   64),   d200(  53760),   0,     8080 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  150(TIDL_EltWiseLayer) [138, 150] --[128 x 6 x  6] => [64 x 6 x  6] *** [128] ***[ COL] ***[0, 0, 0, 72, 72]**** [2], [0],[2] -[140 149 ]---
  IN:MSMC, DMA,     c0(   192),     60(    96),   40(   64),   300c(  12300),   c,     5074 ||||  L2, DMA,     c0(   192),     c0(   192),   40(   64),   6000(  24576),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     c0(   192),     60(    96),   40(   64),   300c(  12300),   c,     5074 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  151(TIDL_ConvolutionLayer) [139, 151] --[64 x 6 x  6] => [1 x 6 x  6] *** [64] ***[ROW_L] ***[0, 0, 0, 72, 72]**** [1], [1],[1] -[150 ]---
  IN:MSMC, DMA,     c0(   192),     60(    96),   40(   64),   300c(  12300),   c,     5074 ||||  L2, DMA,     c0(   192),     c0(   192),   40(   64),   3080(  12416),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     c0(   192),     60(    96),    1(    1),    10c(    268),   c,     80f4 
  WT:DDR_PERSIST, DMA,     80(   128),     80(   128),    1(    1),    100(    256),   0,   221200 ||||MSMC, DMA,     c0(   192),     80(   128),    1(    1),    100(    256),   0,     8200 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  152(TIDL_ConvolutionLayer) [140, 152] --[1 x 6 x  6] => [64 x 6 x  6] *** [1] ***[ROW_L] ***[0, 0, 0, 72, 72]**** [1], [1],[1] -[151 ]---
  IN:MSMC, DMA,     c0(   192),     60(    96),    1(    1),    10c(    268),   c,     80f4 ||||  L2, DMA,     c0(   192),     c0(   192),    1(    1),    180(    384),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     c0(   192),     60(    96),   40(   64),   300c(  12300),   c,     8274 
  WT:DDR_PERSIST, DMA,      2(     2),      2(     2),   40(   64),    280(    640),   0,   221300 ||||MSMC, DMA,      2(     2),      2(     2),   40(   64),    280(    640),   0,     b280 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  153(TIDL_EltWiseLayer) [141, 153] --[128 x 6 x  6] => [64 x 6 x  6] *** [128] ***[ COL] ***[0, 0, 0, 72, 72]**** [2], [0],[2] -[150 152 ]---
  IN:MSMC, DMA,     c0(   192),     60(    96),   40(   64),   300c(  12300),   c,     5074 ||||  L2, DMA,     c0(   192),     c0(   192),   40(   64),   6000(  24576),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     c0(   192),     60(    96),   40(   64),   300c(  12300),   c,     b2f4 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  154(TIDL_BatchNormLayer) [142, 154] --[64 x 6 x  6] => [64 x 6 x  6] *** [64] ***[ COL] ***[0, 0, 0, 72, 72]**** [1], [0],[1] -[153 ]---
  IN:MSMC, DMA,     c0(   192),     60(    96),   40(   64),   300c(  12300),   c,     b2f4 ||||  L2, DMA,     c0(   192),     c0(   192),   40(   64),   3000(  12288),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     c0(   192),     60(    96),   40(   64),   300c(  12300),   c,     8274 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  155(TIDL_ConvolutionLayer) [143, 155] --[64 x 6 x  6] => [1 x 6 x  6] *** [64] ***[ROW_L] ***[0, 0, 0, 72, 72]**** [1], [1],[1] -[154 ]---
  IN:MSMC, DMA,     c0(   192),     60(    96),   40(   64),   300c(  12300),   c,     8274 ||||  L2, DMA,     c0(   192),     c0(   192),   40(   64),   3080(  12416),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     c0(   192),     60(    96),    1(    1),    10c(    268),   c,     8574 
  WT:DDR_PERSIST, DMA,     80(   128),     80(   128),    1(    1),    100(    256),   0,   221580 ||||MSMC, DMA,     c0(   192),     80(   128),    1(    1),    100(    256),   0,     b280 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  156(TIDL_ConcatLayer) [144, 156] --[2 x 6 x  6] => [2 x 6 x  6] *** [2] ***[ COL] ***[0, 0, 0, 72, 72]**** [2], [0],[2] -[151 155 ]---
  IN:MSMC, DMA,     c0(   192),     60(    96),    1(    1),    10c(    268),   c,     80f4 ||||  L2, DMA,     c0(   192),     c0(   192),    2(    2),    180(    384),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     c0(   192),     60(    96),    2(    2),    18c(    396),   c,     8274 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  157(TIDL_ConvolutionLayer) [145, 157] --[2 x 6 x  6] => [32 x 6 x  6] *** [2] ***[ROW_L] ***[28, 32, 14, 40, 72]**** [1], [1],[1] -[156 ]---
  IN:MSMC, DMA,     c0(   192),     60(    96),    2(    2),    18c(    396),   c,     8274 ||||  L2, DMA,     c0(   192),     c0(   192),    2(    2),    200(    512),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     c0(   192),     60(    96),   20(   32),   180c(   6156),   c,     80f4 
  WT:DDR_PERSIST, DMA,     24(    36),     24(    36),   20(   32),    580(   1408),   0,   221680 ||||MSMC, DMA,     24(    36),     24(    36),   20(   32),    580(   1408),   0,     9900 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  158(TIDL_ConvolutionLayer) [146, 158] --[32 x 6 x  6] => [32 x 6 x  6] *** [32] ***[ROW_L] ***[28, 32, 14, 40, 72]**** [1], [1],[1] -[157 ]---
  IN:MSMC, DMA,     c0(   192),     60(    96),   20(   32),   180c(   6156),   c,     80f4 ||||  L2, DMA,     c0(   192),     c0(   192),   20(   32),   1880(   6272),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     c0(   192),     60(    96),   20(   32),   180c(   6156),   c,     80f4 
  WT:DDR_PERSIST, DMA,    240(   576),    240(   576),   20(   32),   4900(  18688),   0,   221c00 ||||MSMC, DMA,    240(   576),    240(   576),   20(   32),   4900(  18688),   0,     9900 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  159(TIDL_ConvolutionLayer) [147, 159] --[32 x 6 x  6] => [1 x 6 x  6] *** [32] ***[ROW_L] ***[0, 0, 0, 72, 72]**** [1], [1],[1] -[158 ]---
  IN:MSMC, DMA,     c0(   192),     60(    96),   20(   32),   180c(   6156),   c,     80f4 ||||  L2, DMA,     c0(   192),     c0(   192),   20(   32),   1880(   6272),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     c0(   192),     60(    96),    1(    1),    10c(    268),   c,     80f4 
  WT:DDR_PERSIST, DMA,     40(    64),     40(    64),    1(    1),     80(    128),   0,   226500 ||||MSMC, DMA,     40(    64),     40(    64),    1(    1),     80(    128),   0,     9900 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  160(TIDL_BatchNormLayer) [148, 160] --[1 x 6 x  6] => [1 x 6 x  6] *** [1] ***[ COL] ***[0, 0, 0, 72, 72]**** [1], [0],[1] -[159 ]---
  IN:MSMC, DMA,     c0(   192),     60(    96),    1(    1),    10c(    268),   c,     80f4 ||||  L2, DMA,     c0(   192),     c0(   192),    1(    1),    100(    256),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     c0(   192),     60(    96),    1(    1),    10c(    268),   c,     8374 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  161(TIDL_ConvolutionLayer) [149, 161] --[1 x 6 x  6] => [64 x 6 x  6] *** [1] ***[ROW_L] ***[0, 0, 0, 72, 72]**** [1], [1],[1] -[160 ]---
  IN:MSMC, DMA,     c0(   192),     60(    96),    1(    1),    10c(    268),   c,     8374 ||||  L2, DMA,     c0(   192),     c0(   192),    1(    1),    180(    384),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     c0(   192),     60(    96),   40(   64),   300c(  12300),   c,     8374 
  WT:DDR_PERSIST, DMA,      2(     2),      2(     2),   40(   64),    280(    640),   0,   226580 ||||MSMC, DMA,      2(     2),      2(     2),   40(   64),    280(    640),   0,     8080 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  162(TIDL_EltWiseLayer) [150, 162] --[128 x 6 x  6] => [64 x 6 x  6] *** [128] ***[ COL] ***[0, 0, 0, 72, 72]**** [2], [0],[2] -[161 150 ]---
  IN:MSMC, DMA,     c0(   192),     60(    96),   40(   64),   300c(  12300),   c,     8374 ||||  L2, DMA,     c0(   192),     c0(   192),   40(   64),   6000(  24576),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     c0(   192),     60(    96),   40(   64),   300c(  12300),   c,     5074 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 1,  0]
------  164(TIDL_ConvolutionLayer) [151, 164] --[64 x 6 x  6] => [96 x 6 x  6] *** [64] ***[ROW_L] ***[28, 32, 14, 40, 72]**** [1], [1],[1] -[162 ]---
  IN:MSMC, DMA,     c0(   192),     60(    96),   40(   64),   300c(  12300),   c,     5074 ||||  L2, DMA,     c0(   192),     c0(   192),   40(   64),   3080(  12416),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     c0(   192),     60(    96),   60(   96),   480c(  18444),   c,     80f4 
  WT:DDR_PERSIST, DMA,    480(  1152),    480(  1152),   60(   96),  1b300( 111360),   0,   226800 ||||MSMC, DMA,    4c0(  1216),    480(  1152),   60(   96),  1cb00( 117504),   0,     c900 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  166(TIDL_ConvolutionLayer) [152, 166] --[96 x 6 x  6] => [96 x 6 x  6] *** [96] ***[ROW_L] ***[28, 32, 14, 40, 72]**** [1], [1],[1] -[164 ]---
  IN:MSMC, DMA,     c0(   192),     60(    96),   60(   96),   480c(  18444),   c,     80f4 ||||  L2, DMA,     c0(   192),     c0(   192),   60(   96),   4880(  18560),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     c0(   192),     60(    96),   60(   96),   480c(  18444),   c,    35474 
  WT:DDR_PERSIST, DMA,    6c0(  1728),    6c0(  1728),   60(   96),  28b00( 166656),   0,   241b00 ||||MSMC, DMA,    6c0(  1728),    6c0(  1728),   60(   96),  28b00( 166656),   0,     c900 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  168(TIDL_ConvolutionLayer) [153, 168] --[96 x 6 x  6] => [96 x 6 x  6] *** [96] ***[ROW_L] ***[28, 32, 14, 40, 72]**** [1], [1],[1] -[166 ]---
  IN:MSMC, DMA,     c0(   192),     60(    96),   60(   96),   480c(  18444),   c,    35474 ||||  L2, DMA,     c0(   192),     c0(   192),   60(   96),   4880(  18560),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     c0(   192),     60(    96),   60(   96),   480c(  18444),   c,    35474 
  WT:DDR_PERSIST, DMA,    6c0(  1728),    6c0(  1728),   60(   96),  28b00( 166656),   0,   26a600 ||||MSMC, DMA,    6c0(  1728),    6c0(  1728),   60(   96),  28b00( 166656),   0,     c900 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  170(TIDL_ConvolutionLayer) [154, 170] --[96 x 6 x  6] => [96 x 6 x  6] *** [96] ***[ROW_L] ***[28, 32, 14, 40, 72]**** [1], [1],[1] -[168 ]---
  IN:MSMC, DMA,     c0(   192),     60(    96),   60(   96),   480c(  18444),   c,    35474 ||||  L2, DMA,     c0(   192),     c0(   192),   60(   96),   4880(  18560),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     c0(   192),     60(    96),   60(   96),   480c(  18444),   c,    35474 
  WT:DDR_PERSIST, DMA_ONCE,    6c0(  1728),    6c0(  1728),   60(   96),  28b00( 166656),   0,   293100 ||||MSMC, DMA_ONCE,    6c0(  1728),    6c0(  1728),   60(   96),  28b00( 166656),   0,    c8100 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  172(TIDL_EltWiseLayer) [155, 172] --[192 x 6 x  6] => [96 x 6 x  6] *** [192] ***[ COL] ***[0, 0, 0, 72, 72]**** [2], [0],[2] -[170 164 ]---
  IN:MSMC, DMA,     c0(   192),     60(    96),   60(   96),   480c(  18444),   c,    35474 ||||  L2, DMA,     c0(   192),     c0(   192),   60(   96),   9000(  36864),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     c0(   192),     60(    96),   60(   96),   480c(  18444),   c,     80f4 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  174(TIDL_ConvolutionLayer) [156, 174] --[96 x 6 x  6] => [96 x 6 x  6] *** [96] ***[ROW_L] ***[28, 32, 14, 40, 72]**** [1], [1],[1] -[172 ]---
  IN:MSMC, DMA,     c0(   192),     60(    96),   60(   96),   480c(  18444),   c,     80f4 ||||  L2, DMA,     c0(   192),     c0(   192),   60(   96),   4880(  18560),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     c0(   192),     60(    96),   60(   96),   480c(  18444),   c,     80f4 
  WT:DDR_PERSIST, DMA,    6c0(  1728),    6c0(  1728),   60(   96),  28b00( 166656),   0,   2bbc00 ||||MSMC, DMA,    6c0(  1728),    6c0(  1728),   60(   96),  28b00( 166656),   0,     c900 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  176(TIDL_PoolingLayer) [157, 176] --[96 x 6 x  6] => [96 x 1 x  1] *** [96] ***[ COL] ***[0, 0, 0, 72, 72]**** [1], [0],[1] -[174 ]---
  IN:MSMC, DMA,     c0(   192),     60(    96),   60(   96),   480c(  18444),   c,     80f4 ||||  L2, DMA,     c0(   192),     c0(   192),   60(   96),   4900(  18688),   0,       80 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,      2(     2),      2(     2),   60(   96),    100(    256),   0,     8080 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  178(TIDL_ConvolutionLayer) [158, 178] --[96 x 1 x  1] => [7 x 1 x  1] *** [96] ***[ROW_L] ***[0, 0, 0, 2, 2]**** [1], [1],[1] -[176 ]---
  IN:MSMC, DMA,      2(     2),      2(     2),   60(   96),    100(    256),   0,     8080 ||||  L2, DMA,      2(     2),      2(     2),   60(   96),    180(    384),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,      2(     2),      2(     2),    7(    7),     80(    128),   0,     8080 
  WT:DDR_PERSIST, DMA,     c0(   192),     c0(   192),    7(    7),    580(   1408),   0,   2e4700 ||||MSMC, DMA,     c0(   192),     c0(   192),    7(    7),    580(   1408),   0,     8180 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  180(TIDL_BatchNormLayer) [159, 180] --[7 x 1 x  1] => [7 x 1 x  1] *** [7] ***[ COL] ***[0, 0, 0, 2, 2]**** [7], [0],[7] -[178 ]---
  IN:MSMC, DMA,      2(     2),      2(     2),    7(    7),     80(    128),   0,     8080 ||||  L2, DMA,      2(     2),      2(     2),    2(    2),     80(    128),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,      2(     2),      2(     2),    7(    7),     80(    128),   0,     8080 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  182(TIDL_DataConvertLayer) [160, 182] --[7 x 1 x  1] => [7 x 1 x  1] *** [7] ***[ COL] ***[0, 0, 0, 2, 2]**** [7], [0],[7] -[180 ]---
  IN:MSMC, DMA,      2(     2),      2(     2),    7(    7),     80(    128),   0,     8080 ||||  L2, DMA,      2(     2),      2(     2),    2(    2),     80(    128),   0,        0 
 OUT:MSMC, CPU,      4(     4),      4(     4),    2(    2),     80(    128),   0,     8100 |||| DDR, DMA,      4(     4),      4(     4),    7(    7),    480(   1152),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  163(TIDL_ResizeLayer) [162, 163] --[64 x 6 x  6] => [64 x 12 x  12] *** [64] ***[ COL] ***[0, 0, 0, 96, 96]**** [1], [0],[1] -[162 ]---
  IN:MSMC, DMA,     c0(   192),     60(    96),   40(   64),   300c(  12300),   0,     5074 ||||  L2, DMA,     c0(   192),     c0(   192),   40(   64),   3000(  12288),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    150(   336),   40(   64),   7098(  28824),  18,     80e8 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  68(TIDL_ConvolutionLayer) [163, 68] --[64 x 12 x  12] => [1 x 12 x  12] *** [64] ***[ROW_L] ***[0, 0, 0, 288, 288]**** [1], [1],[1] -[66 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),   40(   64),   5000(  20480),   0,        0 ||||  L2, DMA,    140(   320),    140(   320),   40(   64),   5080(  20608),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),    1(    1),    180(    384),   0,     5000 
  WT:DDR_PERSIST, DMA_ONCE,     80(   128),     80(   128),    1(    1),    100(    256),   0,   2e4c80 ||||MSMC, DMA_ONCE,     c0(   192),     80(   128),    1(    1),    100(    256),   0,    f1f00 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  70(TIDL_ConvolutionLayer) [164, 70] --[1 x 12 x  12] => [64 x 12 x  12] *** [1] ***[ROW_L] ***[0, 0, 0, 288, 288]**** [1], [1],[1] -[68 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),    1(    1),    180(    384),   0,     5000 ||||  L2, DMA,    140(   320),    140(   320),    1(    1),    200(    512),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),   40(   64),   5000(  20480),   0,     f180 
  WT:DDR_PERSIST, DMA,      2(     2),      2(     2),   40(   64),    280(    640),   0,   2e4d80 ||||MSMC, DMA,      2(     2),      2(     2),   40(   64),    280(    640),   0,     5180 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  72(TIDL_EltWiseLayer) [165, 72] --[128 x 12 x  12] => [64 x 12 x  12] *** [128] ***[ COL] ***[0, 0, 0, 288, 288]**** [2], [0],[2] -[66 70 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),   40(   64),   5000(  20480),   0,        0 ||||  L2, DMA,    144(   324),    144(   324),   40(   64),   a200(  41472),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),   40(   64),   5000(  20480),   0,    14180 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  74(TIDL_BatchNormLayer) [166, 74] --[64 x 12 x  12] => [64 x 12 x  12] *** [64] ***[ COL] ***[0, 0, 0, 288, 288]**** [1], [0],[1] -[72 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),   40(   64),   5000(  20480),   0,    14180 ||||  L2, DMA,    144(   324),    144(   324),   40(   64),   5100(  20736),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),   40(   64),   5000(  20480),   0,     f180 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  76(TIDL_ConvolutionLayer) [167, 76] --[64 x 12 x  12] => [1 x 12 x  12] *** [64] ***[ROW_L] ***[0, 0, 0, 288, 288]**** [1], [1],[1] -[74 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),   40(   64),   5000(  20480),   0,     f180 ||||  L2, DMA,    140(   320),    140(   320),   40(   64),   5080(  20608),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),    1(    1),    180(    384),   0,     5500 
  WT:DDR_PERSIST, DMA,     80(   128),     80(   128),    1(    1),    100(    256),   0,   2e5000 ||||MSMC, DMA,     c0(   192),     80(   128),    1(    1),    100(    256),   0,     5180 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  78(TIDL_ConcatLayer) [168, 78] --[2 x 12 x  12] => [2 x 12 x  12] *** [2] ***[ COL] ***[0, 0, 0, 288, 288]**** [2], [0],[2] -[68 76 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),    1(    1),    180(    384),   0,     5000 ||||  L2, DMA,    144(   324),    144(   324),    2(    2),    300(    768),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),    2(    2),    280(    640),   0,     5280 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  80(TIDL_ConvolutionLayer) [169, 80] --[2 x 12 x  12] => [32 x 12 x  12] *** [2] ***[ROW_L] ***[52, 64, 26, 224, 288]**** [1], [1],[1] -[78 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),    2(    2),    280(    640),   0,     5280 ||||  L2, DMA,    140(   320),    140(   320),    2(    2),    400(   1024),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),   20(   32),   2800(  10240),   0,     5000 
  WT:DDR_PERSIST, DMA,     24(    36),     24(    36),   20(   32),    580(   1408),   0,   2e5100 ||||MSMC, DMA,     24(    36),     24(    36),   20(   32),    580(   1408),   0,     7800 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  82(TIDL_ConvolutionLayer) [170, 82] --[32 x 12 x  12] => [32 x 12 x  12] *** [32] ***[ROW_L] ***[52, 64, 26, 224, 288]**** [1], [1],[1] -[80 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),   20(   32),   2800(  10240),   0,     5000 ||||  L2, DMA,    140(   320),    140(   320),   20(   32),   2980(  10624),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),   20(   32),   2800(  10240),   0,     5000 
  WT:DDR_PERSIST, DMA,    240(   576),    240(   576),   20(   32),   4900(  18688),   0,   2e5680 ||||MSMC, DMA,    240(   576),    240(   576),   20(   32),   4900(  18688),   0,     f180 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  84(TIDL_ConvolutionLayer) [171, 84] --[32 x 12 x  12] => [1 x 12 x  12] *** [32] ***[ROW_L] ***[0, 0, 0, 288, 288]**** [1], [1],[1] -[82 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),   20(   32),   2800(  10240),   0,     5000 ||||  L2, DMA,    140(   320),    140(   320),   20(   32),   2880(  10368),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),    1(    1),    180(    384),   0,     5000 
  WT:DDR_PERSIST, DMA,     40(    64),     40(    64),    1(    1),     80(    128),   0,   2e9f80 ||||MSMC, DMA,     40(    64),     40(    64),    1(    1),     80(    128),   0,     7800 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  86(TIDL_BatchNormLayer) [172, 86] --[1 x 12 x  12] => [1 x 12 x  12] *** [1] ***[ COL] ***[0, 0, 0, 288, 288]**** [1], [0],[1] -[84 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),    1(    1),    180(    384),   0,     5000 ||||  L2, DMA,    144(   324),    144(   324),    1(    1),    180(    384),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),    1(    1),    180(    384),   0,     5280 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  88(TIDL_ConvolutionLayer) [173, 88] --[1 x 12 x  12] => [64 x 12 x  12] *** [1] ***[ROW_L] ***[0, 0, 0, 288, 288]**** [1], [1],[1] -[86 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),    1(    1),    180(    384),   0,     5280 ||||  L2, DMA,    140(   320),    140(   320),    1(    1),    200(    512),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),   40(   64),   5000(  20480),   0,     f180 
  WT:DDR_PERSIST, DMA,      2(     2),      2(     2),   40(   64),    280(    640),   0,   2ea000 ||||MSMC, DMA,      2(     2),      2(     2),   40(   64),    280(    640),   0,     5000 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  90(TIDL_EltWiseLayer) [174, 90] --[128 x 12 x  12] => [64 x 12 x  12] *** [128] ***[ COL] ***[0, 0, 0, 288, 288]**** [2], [0],[2] -[88 66 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),   40(   64),   5000(  20480),   0,     f180 ||||  L2, DMA,    144(   324),    144(   324),   40(   64),   a200(  41472),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),   40(   64),   5000(  20480),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  165(TIDL_ConcatLayer) [175, 165] --[128 x 12 x  12] => [128 x 12 x  12] *** [128] ***[ COL] ***[0, 0, 0, 288, 288]**** [2], [0],[2] -[90 163 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),   40(   64),   5000(  20480),  18,        0 ||||  L2, DMA,    1c8(   456),    1c8(   456),   80(  128),   e400(  58368),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),   80(  128),   a000(  40960),   0,     f180 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  167(TIDL_ConvolutionLayer) [176, 167] --[128 x 12 x  12] => [128 x 12 x  12] *** [128] ***[ROW_L] ***[0, 0, 0, 288, 288]**** [1], [1],[1] -[165 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),   80(  128),   a000(  40960),   0,     f180 ||||  L2, DMA,    140(   320),    140(   320),   80(  128),   a080(  41088),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),   80(  128),   a000(  40960),   0,        0 
  WT:DDR_PERSIST, DMA,    100(   256),    100(   256),   80(  128),   8400(  33792),   0,   2ea280 ||||MSMC, DMA,    140(   320),    100(   256),   80(  128),   a400(  41984),   0,    19180 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  169(TIDL_ConvolutionLayer) [177, 169] --[128 x 12 x  12] => [1 x 12 x  12] *** [128] ***[ROW_L] ***[0, 0, 0, 288, 288]**** [1], [1],[1] -[167 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),   80(  128),   a000(  40960),   0,        0 ||||  L2, DMA,    140(   320),    140(   320),   80(  128),   a080(  41088),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),    1(    1),    180(    384),   0,     a000 
  WT:DDR_PERSIST, DMA,    100(   256),    100(   256),    1(    1),    180(    384),   0,   2f2680 ||||MSMC, DMA,    140(   320),    100(   256),    1(    1),    180(    384),   0,     a180 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  171(TIDL_ConvolutionLayer) [178, 171] --[1 x 12 x  12] => [128 x 12 x  12] *** [1] ***[ROW_L] ***[0, 0, 0, 288, 288]**** [1], [1],[1] -[169 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),    1(    1),    180(    384),   0,     a000 ||||  L2, DMA,    140(   320),    140(   320),    1(    1),    200(    512),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),   80(  128),   a000(  40960),   0,     a180 
  WT:DDR_PERSIST, DMA,      2(     2),      2(     2),   80(  128),    500(   1280),   0,   2f2800 ||||MSMC, DMA,      2(     2),      2(     2),   80(  128),    500(   1280),   0,    14180 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  173(TIDL_EltWiseLayer) [179, 173] --[256 x 12 x  12] => [128 x 12 x  12] *** [256] ***[ COL] ***[0, 0, 0, 288, 288]**** [2], [0],[2] -[167 171 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),   80(  128),   a000(  40960),   0,        0 ||||  L2, DMA,    144(   324),    144(   324),   80(  128),  14400(  82944),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),   80(  128),   a000(  40960),   0,    14180 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  175(TIDL_BatchNormLayer) [180, 175] --[128 x 12 x  12] => [128 x 12 x  12] *** [128] ***[ COL] ***[0, 0, 0, 288, 288]**** [1], [0],[1] -[173 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),   80(  128),   a000(  40960),   0,    14180 ||||  L2, DMA,    144(   324),    144(   324),   80(  128),   a200(  41472),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),   80(  128),   a000(  40960),   0,     a180 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  177(TIDL_ConvolutionLayer) [181, 177] --[128 x 12 x  12] => [1 x 12 x  12] *** [128] ***[ROW_L] ***[0, 0, 0, 288, 288]**** [1], [1],[1] -[175 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),   80(  128),   a000(  40960),   0,     a180 ||||  L2, DMA,    140(   320),    140(   320),   80(  128),   a080(  41088),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),    1(    1),    180(    384),   0,     a680 
  WT:DDR_PERSIST, DMA,    100(   256),    100(   256),    1(    1),    180(    384),   0,   2f2d00 ||||MSMC, DMA,    140(   320),    100(   256),    1(    1),    180(    384),   0,    14180 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  179(TIDL_ConcatLayer) [182, 179] --[2 x 12 x  12] => [2 x 12 x  12] *** [2] ***[ COL] ***[0, 0, 0, 288, 288]**** [2], [0],[2] -[169 177 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),    1(    1),    180(    384),   0,     a000 ||||  L2, DMA,    144(   324),    144(   324),    2(    2),    300(    768),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),    2(    2),    280(    640),   0,     a280 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  181(TIDL_ConvolutionLayer) [183, 181] --[2 x 12 x  12] => [32 x 12 x  12] *** [2] ***[ROW_L] ***[52, 64, 26, 224, 288]**** [1], [1],[1] -[179 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),    2(    2),    280(    640),   0,     a280 ||||  L2, DMA,    140(   320),    140(   320),    2(    2),    400(   1024),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),   20(   32),   2800(  10240),   0,     a000 
  WT:DDR_PERSIST, DMA,     24(    36),     24(    36),   20(   32),    580(   1408),   0,   2f2e80 ||||MSMC, DMA,     24(    36),     24(    36),   20(   32),    580(   1408),   0,     c800 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  183(TIDL_ConvolutionLayer) [184, 183] --[32 x 12 x  12] => [32 x 12 x  12] *** [32] ***[ROW_L] ***[52, 64, 26, 224, 288]**** [1], [1],[1] -[181 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),   20(   32),   2800(  10240),   0,     a000 ||||  L2, DMA,    140(   320),    140(   320),   20(   32),   2980(  10624),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),   20(   32),   2800(  10240),   0,     a000 
  WT:DDR_PERSIST, DMA,    240(   576),    240(   576),   20(   32),   4900(  18688),   0,   2f3400 ||||MSMC, DMA,    240(   576),    240(   576),   20(   32),   4900(  18688),   0,     c800 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  185(TIDL_ConvolutionLayer) [185, 185] --[32 x 12 x  12] => [1 x 12 x  12] *** [32] ***[ROW_L] ***[0, 0, 0, 288, 288]**** [1], [1],[1] -[183 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),   20(   32),   2800(  10240),   0,     a000 ||||  L2, DMA,    140(   320),    140(   320),   20(   32),   2880(  10368),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),    1(    1),    180(    384),   0,     a000 
  WT:DDR_PERSIST, DMA,     40(    64),     40(    64),    1(    1),     80(    128),   0,   2f7d00 ||||MSMC, DMA,     40(    64),     40(    64),    1(    1),     80(    128),   0,     c800 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  186(TIDL_BatchNormLayer) [186, 186] --[1 x 12 x  12] => [1 x 12 x  12] *** [1] ***[ COL] ***[0, 0, 0, 288, 288]**** [1], [0],[1] -[185 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),    1(    1),    180(    384),   0,     a000 ||||  L2, DMA,    144(   324),    144(   324),    1(    1),    180(    384),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),    1(    1),    180(    384),   0,     a500 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  187(TIDL_ConvolutionLayer) [187, 187] --[1 x 12 x  12] => [128 x 12 x  12] *** [1] ***[ROW_L] ***[0, 0, 0, 288, 288]**** [1], [1],[1] -[186 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),    1(    1),    180(    384),   0,     a500 ||||  L2, DMA,    140(   320),    140(   320),    1(    1),    200(    512),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),   80(  128),   a000(  40960),   0,     a500 
  WT:DDR_PERSIST, DMA,      2(     2),      2(     2),   80(  128),    500(   1280),   0,   2f7d80 ||||MSMC, DMA,      2(     2),      2(     2),   80(  128),    500(   1280),   0,     a000 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  188(TIDL_EltWiseLayer) [188, 188] --[256 x 12 x  12] => [128 x 12 x  12] *** [256] ***[ COL] ***[0, 0, 0, 288, 288]**** [2], [0],[2] -[167 187 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),   80(  128),   a000(  40960),   0,        0 ||||  L2, DMA,    144(   324),    144(   324),   80(  128),  14400(  82944),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),   80(  128),   a000(  40960),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  189(TIDL_ConvolutionLayer) [189, 189] --[128 x 12 x  12] => [96 x 12 x  12] *** [128] ***[ROW_L] ***[52, 64, 26, 224, 288]**** [1], [1],[1] -[188 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),   80(  128),   a000(  40960),   0,        0 ||||  L2, DMA,    140(   320),    140(   320),   80(  128),   a180(  41344),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),   60(   96),   7800(  30720),   0,        0 
  WT:DDR_PERSIST, DMA,    900(  2304),    900(  2304),   60(   96),  36300( 221952),   0,   2f8280 ||||MSMC, DMA,    940(  2368),    900(  2304),   60(   96),  37b00( 228096),   0,     a000 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  190(TIDL_ConvolutionLayer) [190, 190] --[96 x 12 x  12] => [12 x 12 x  12] *** [96] ***[ROW_L] ***[52, 64, 26, 224, 288]**** [1], [1],[1] -[189 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),   60(   96),   7800(  30720),   0,        0 ||||  L2, DMA,    140(   320),    140(   320),   60(   96),   7980(  31104),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),    c(   12),    f00(   3840),   0,     c980 
  WT:DDR_PERSIST, DMA,    6c0(  1728),    6c0(  1728),    c(   12),   5180(  20864),   0,   32e580 ||||MSMC, DMA,    6c0(  1728),    6c0(  1728),    c(   12),   5180(  20864),   0,     7800 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  191(TIDL_ConvolutionLayer) [191, 191] --[12 x 12 x  12] => [12 x 12 x  12] *** [12] ***[ROW_L] ***[52, 64, 26, 224, 288]**** [1], [1],[1] -[190 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),    c(   12),    f00(   3840),   0,     c980 ||||  L2, DMA,    140(   320),    140(   320),    c(   12),   1080(   4224),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),    c(   12),    f00(   3840),   0,     f300 
  WT:DDR_PERSIST, DMA,     d8(   216),     d8(   216),    c(   12),    a80(   2688),   0,   333700 ||||MSMC, DMA,    140(   320),     d8(   216),    c(   12),    f80(   3968),   0,     7800 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  192(TIDL_ConvolutionLayer) [192, 192] --[12 x 12 x  12] => [96 x 12 x  12] *** [12] ***[ROW_L] ***[52, 64, 26, 224, 288]**** [1], [1],[1] -[191 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),    c(   12),    f00(   3840),   0,     f300 ||||  L2, DMA,    140(   320),    140(   320),    c(   12),   1080(   4224),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),   60(   96),   7800(  30720),   0,     f300 
  WT:DDR_PERSIST, DMA,     d8(   216),     d8(   216),   60(   96),   5400(  21504),   0,   334180 ||||MSMC, DMA,    140(   320),     d8(   216),   60(   96),   7b00(  31488),   0,     7800 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  193(TIDL_EltWiseLayer) [193, 193] --[192 x 12 x  12] => [96 x 12 x  12] *** [192] ***[ COL] ***[0, 0, 0, 288, 288]**** [2], [0],[2] -[192 189 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),   60(   96),   7800(  30720),   0,     f300 ||||  L2, DMA,    144(   324),    144(   324),   60(   96),   f300(  62208),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),   60(   96),   7800(  30720),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  194(TIDL_ConvolutionLayer) [194, 194] --[96 x 12 x  12] => [96 x 12 x  12] *** [96] ***[ROW_L] ***[0, 0, 0, 288, 288]**** [1], [1],[1] -[193 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),   60(   96),   7800(  30720),   0,        0 ||||  L2, DMA,    140(   320),    140(   320),   60(   96),   7880(  30848),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),   60(   96),   7800(  30720),   0,        0 
  WT:DDR_PERSIST, DMA,     c0(   192),     c0(   192),   60(   96),   4b00(  19200),   0,   339580 ||||MSMC, DMA,     c0(   192),     c0(   192),   60(   96),   4b00(  19200),   0,     7800 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  195(TIDL_ConvolutionLayer) [195, 195] --[96 x 12 x  12] => [12 x 12 x  12] *** [96] ***[ROW_L] ***[52, 64, 26, 224, 288]**** [1], [1],[1] -[194 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),   60(   96),   7800(  30720),   0,        0 ||||  L2, DMA,    140(   320),    140(   320),   60(   96),   7980(  31104),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),    c(   12),    f00(   3840),   0,     c980 
  WT:DDR_PERSIST, DMA,    6c0(  1728),    6c0(  1728),    c(   12),   5180(  20864),   0,   33e080 ||||MSMC, DMA,    6c0(  1728),    6c0(  1728),    c(   12),   5180(  20864),   0,     7800 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  196(TIDL_ConvolutionLayer) [196, 196] --[12 x 12 x  12] => [12 x 12 x  12] *** [12] ***[ROW_L] ***[52, 64, 26, 224, 288]**** [1], [1],[1] -[195 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),    c(   12),    f00(   3840),   0,     c980 ||||  L2, DMA,    140(   320),    140(   320),    c(   12),   1080(   4224),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),    c(   12),    f00(   3840),   0,     f300 
  WT:DDR_PERSIST, DMA,     d8(   216),     d8(   216),    c(   12),    a80(   2688),   0,   343200 ||||MSMC, DMA,    140(   320),     d8(   216),    c(   12),    f80(   3968),   0,     7800 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  197(TIDL_ConvolutionLayer) [197, 197] --[12 x 12 x  12] => [96 x 12 x  12] *** [12] ***[ROW_L] ***[52, 64, 26, 224, 288]**** [1], [1],[1] -[196 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),    c(   12),    f00(   3840),   0,     f300 ||||  L2, DMA,    140(   320),    140(   320),    c(   12),   1080(   4224),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),   60(   96),   7800(  30720),   0,     f300 
  WT:DDR_PERSIST, DMA,     d8(   216),     d8(   216),   60(   96),   5400(  21504),   0,   343c80 ||||MSMC, DMA,    140(   320),     d8(   216),   60(   96),   7b00(  31488),   0,     7800 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  198(TIDL_EltWiseLayer) [198, 198] --[192 x 12 x  12] => [96 x 12 x  12] *** [192] ***[ COL] ***[0, 0, 0, 288, 288]**** [2], [0],[2] -[197 194 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),   60(   96),   7800(  30720),   0,     f300 ||||  L2, DMA,    144(   324),    144(   324),   60(   96),   f300(  62208),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),   60(   96),   7800(  30720),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  199(TIDL_ConvolutionLayer) [199, 199] --[96 x 12 x  12] => [96 x 12 x  12] *** [96] ***[ROW_L] ***[0, 0, 0, 288, 288]**** [1], [1],[1] -[198 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),   60(   96),   7800(  30720),   0,        0 ||||  L2, DMA,    140(   320),    140(   320),   60(   96),   7880(  30848),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),   60(   96),   7800(  30720),   0,        0 
  WT:DDR_PERSIST, DMA,     c0(   192),     c0(   192),   60(   96),   4b00(  19200),   0,   349080 ||||MSMC, DMA,     c0(   192),     c0(   192),   60(   96),   4b00(  19200),   0,     7800 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  200(TIDL_ConvolutionLayer) [200, 200] --[96 x 12 x  12] => [12 x 12 x  12] *** [96] ***[ROW_L] ***[52, 64, 26, 224, 288]**** [1], [1],[1] -[199 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),   60(   96),   7800(  30720),   0,        0 ||||  L2, DMA,    140(   320),    140(   320),   60(   96),   7980(  31104),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),    c(   12),    f00(   3840),   0,     c980 
  WT:DDR_PERSIST, DMA,    6c0(  1728),    6c0(  1728),    c(   12),   5180(  20864),   0,   34db80 ||||MSMC, DMA,    6c0(  1728),    6c0(  1728),    c(   12),   5180(  20864),   0,     7800 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  201(TIDL_ConvolutionLayer) [201, 201] --[12 x 12 x  12] => [12 x 12 x  12] *** [12] ***[ROW_L] ***[52, 64, 26, 224, 288]**** [1], [1],[1] -[200 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),    c(   12),    f00(   3840),   0,     c980 ||||  L2, DMA,    140(   320),    140(   320),    c(   12),   1080(   4224),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),    c(   12),    f00(   3840),   0,     f300 
  WT:DDR_PERSIST, DMA,     d8(   216),     d8(   216),    c(   12),    a80(   2688),   0,   352d00 ||||MSMC, DMA,    140(   320),     d8(   216),    c(   12),    f80(   3968),   0,     7800 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  202(TIDL_ConvolutionLayer) [202, 202] --[12 x 12 x  12] => [96 x 12 x  12] *** [12] ***[ROW_L] ***[52, 64, 26, 224, 288]**** [1], [1],[1] -[201 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),    c(   12),    f00(   3840),   0,     f300 ||||  L2, DMA,    140(   320),    140(   320),    c(   12),   1080(   4224),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),   60(   96),   7800(  30720),   0,     f300 
  WT:DDR_PERSIST, DMA,     d8(   216),     d8(   216),   60(   96),   5400(  21504),   0,   353780 ||||MSMC, DMA,    140(   320),     d8(   216),   60(   96),   7b00(  31488),   0,     7800 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  203(TIDL_EltWiseLayer) [203, 203] --[192 x 12 x  12] => [96 x 12 x  12] *** [192] ***[ COL] ***[0, 0, 0, 288, 288]**** [2], [0],[2] -[202 199 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),   60(   96),   7800(  30720),   0,     f300 ||||  L2, DMA,    144(   324),    144(   324),   60(   96),   f300(  62208),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),   60(   96),   7800(  30720),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  204(TIDL_ConvolutionLayer) [204, 204] --[96 x 12 x  12] => [96 x 12 x  12] *** [96] ***[ROW_L] ***[0, 0, 0, 288, 288]**** [1], [1],[1] -[203 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),   60(   96),   7800(  30720),   0,        0 ||||  L2, DMA,    140(   320),    140(   320),   60(   96),   7880(  30848),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),   60(   96),   7800(  30720),   0,        0 
  WT:DDR_PERSIST, DMA,     c0(   192),     c0(   192),   60(   96),   4b00(  19200),   0,   358b80 ||||MSMC, DMA,     c0(   192),     c0(   192),   60(   96),   4b00(  19200),   0,     7800 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  205(TIDL_ConvolutionLayer) [205, 205] --[96 x 12 x  12] => [12 x 12 x  12] *** [96] ***[ROW_L] ***[52, 64, 26, 224, 288]**** [1], [1],[1] -[204 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),   60(   96),   7800(  30720),   0,        0 ||||  L2, DMA,    140(   320),    140(   320),   60(   96),   7980(  31104),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),    c(   12),    f00(   3840),   0,     c980 
  WT:DDR_PERSIST, DMA,    6c0(  1728),    6c0(  1728),    c(   12),   5180(  20864),   0,   35d680 ||||MSMC, DMA,    6c0(  1728),    6c0(  1728),    c(   12),   5180(  20864),   0,     7800 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  206(TIDL_ConvolutionLayer) [206, 206] --[12 x 12 x  12] => [12 x 12 x  12] *** [12] ***[ROW_L] ***[52, 64, 26, 224, 288]**** [1], [1],[1] -[205 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),    c(   12),    f00(   3840),   0,     c980 ||||  L2, DMA,    140(   320),    140(   320),    c(   12),   1080(   4224),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),    c(   12),    f00(   3840),   0,     f300 
  WT:DDR_PERSIST, DMA,     d8(   216),     d8(   216),    c(   12),    a80(   2688),   0,   362800 ||||MSMC, DMA,    140(   320),     d8(   216),    c(   12),    f80(   3968),   0,     7800 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  207(TIDL_ConvolutionLayer) [207, 207] --[12 x 12 x  12] => [96 x 12 x  12] *** [12] ***[ROW_L] ***[52, 64, 26, 224, 288]**** [1], [1],[1] -[206 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),    c(   12),    f00(   3840),   0,     f300 ||||  L2, DMA,    140(   320),    140(   320),    c(   12),   1080(   4224),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),   60(   96),   7800(  30720),   0,     f300 
  WT:DDR_PERSIST, DMA,     d8(   216),     d8(   216),   60(   96),   5400(  21504),   0,   363280 ||||MSMC, DMA,    140(   320),     d8(   216),   60(   96),   7b00(  31488),   0,     7800 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  208(TIDL_EltWiseLayer) [208, 208] --[192 x 12 x  12] => [96 x 12 x  12] *** [192] ***[ COL] ***[0, 0, 0, 288, 288]**** [2], [0],[2] -[207 204 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),   60(   96),   7800(  30720),   0,     f300 ||||  L2, DMA,    144(   324),    144(   324),   60(   96),   f300(  62208),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),   60(   96),   7800(  30720),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  209(TIDL_ConvolutionLayer) [209, 209] --[96 x 12 x  12] => [96 x 12 x  12] *** [96] ***[ROW_L] ***[0, 0, 0, 288, 288]**** [1], [1],[1] -[208 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),   60(   96),   7800(  30720),   0,        0 ||||  L2, DMA,    140(   320),    140(   320),   60(   96),   7880(  30848),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),   60(   96),   7800(  30720),   0,        0 
  WT:DDR_PERSIST, DMA,     c0(   192),     c0(   192),   60(   96),   4b00(  19200),   0,   368680 ||||MSMC, DMA,     c0(   192),     c0(   192),   60(   96),   4b00(  19200),   0,     7800 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  210(TIDL_ConvolutionLayer) [210, 210] --[96 x 12 x  12] => [12 x 12 x  12] *** [96] ***[ROW_L] ***[52, 64, 26, 224, 288]**** [1], [1],[1] -[209 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),   60(   96),   7800(  30720),   0,        0 ||||  L2, DMA,    140(   320),    140(   320),   60(   96),   7980(  31104),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),    c(   12),    f00(   3840),   0,     c980 
  WT:DDR_PERSIST, DMA,    6c0(  1728),    6c0(  1728),    c(   12),   5180(  20864),   0,   36d180 ||||MSMC, DMA,    6c0(  1728),    6c0(  1728),    c(   12),   5180(  20864),   0,     7800 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  211(TIDL_ConvolutionLayer) [211, 211] --[12 x 12 x  12] => [12 x 12 x  12] *** [12] ***[ROW_L] ***[52, 64, 26, 224, 288]**** [1], [1],[1] -[210 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),    c(   12),    f00(   3840),   0,     c980 ||||  L2, DMA,    140(   320),    140(   320),    c(   12),   1080(   4224),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),    c(   12),    f00(   3840),   0,     f300 
  WT:DDR_PERSIST, DMA,     d8(   216),     d8(   216),    c(   12),    a80(   2688),   0,   372300 ||||MSMC, DMA,    140(   320),     d8(   216),    c(   12),    f80(   3968),   0,     7800 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  212(TIDL_ConvolutionLayer) [212, 212] --[12 x 12 x  12] => [96 x 12 x  12] *** [12] ***[ROW_L] ***[52, 64, 26, 224, 288]**** [1], [1],[1] -[211 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),    c(   12),    f00(   3840),   0,     f300 ||||  L2, DMA,    140(   320),    140(   320),    c(   12),   1080(   4224),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),   60(   96),   7800(  30720),   0,     f300 
  WT:DDR_PERSIST, DMA,     d8(   216),     d8(   216),   60(   96),   5400(  21504),   0,   372d80 ||||MSMC, DMA,    140(   320),     d8(   216),   60(   96),   7b00(  31488),   0,     7800 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  213(TIDL_EltWiseLayer) [213, 213] --[192 x 12 x  12] => [96 x 12 x  12] *** [192] ***[ COL] ***[0, 0, 0, 288, 288]**** [2], [0],[2] -[212 209 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),   60(   96),   7800(  30720),   0,     f300 ||||  L2, DMA,    144(   324),    144(   324),   60(   96),   f300(  62208),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),   60(   96),   7800(  30720),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  214(TIDL_ConvolutionLayer) [214, 214] --[96 x 12 x  12] => [96 x 12 x  12] *** [96] ***[ROW_L] ***[0, 0, 0, 288, 288]**** [1], [1],[1] -[213 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),   60(   96),   7800(  30720),   0,        0 ||||  L2, DMA,    140(   320),    140(   320),   60(   96),   7880(  30848),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),   60(   96),   7800(  30720),   0,        0 
  WT:DDR_PERSIST, DMA,     c0(   192),     c0(   192),   60(   96),   4b00(  19200),   0,   378180 ||||MSMC, DMA,     c0(   192),     c0(   192),   60(   96),   4b00(  19200),   0,     7800 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  215(TIDL_ConvolutionLayer) [215, 215] --[96 x 12 x  12] => [12 x 12 x  12] *** [96] ***[ROW_L] ***[52, 64, 26, 224, 288]**** [1], [1],[1] -[214 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),   60(   96),   7800(  30720),   0,        0 ||||  L2, DMA,    140(   320),    140(   320),   60(   96),   7980(  31104),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),    c(   12),    f00(   3840),   0,     c980 
  WT:DDR_PERSIST, DMA,    6c0(  1728),    6c0(  1728),    c(   12),   5180(  20864),   0,   37cc80 ||||MSMC, DMA,    6c0(  1728),    6c0(  1728),    c(   12),   5180(  20864),   0,     7800 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  216(TIDL_ConvolutionLayer) [216, 216] --[12 x 12 x  12] => [12 x 12 x  12] *** [12] ***[ROW_L] ***[52, 64, 26, 224, 288]**** [1], [1],[1] -[215 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),    c(   12),    f00(   3840),   0,     c980 ||||  L2, DMA,    140(   320),    140(   320),    c(   12),   1080(   4224),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),    c(   12),    f00(   3840),   0,     f300 
  WT:DDR_PERSIST, DMA,     d8(   216),     d8(   216),    c(   12),    a80(   2688),   0,   381e00 ||||MSMC, DMA,    140(   320),     d8(   216),    c(   12),    f80(   3968),   0,     7800 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  217(TIDL_ConvolutionLayer) [217, 217] --[12 x 12 x  12] => [96 x 12 x  12] *** [12] ***[ROW_L] ***[52, 64, 26, 224, 288]**** [1], [1],[1] -[216 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),    c(   12),    f00(   3840),   0,     f300 ||||  L2, DMA,    140(   320),    140(   320),    c(   12),   1080(   4224),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),   60(   96),   7800(  30720),   0,     f300 
  WT:DDR_PERSIST, DMA,     d8(   216),     d8(   216),   60(   96),   5400(  21504),   0,   382880 ||||MSMC, DMA,    140(   320),     d8(   216),   60(   96),   7b00(  31488),   0,     7800 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  218(TIDL_EltWiseLayer) [218, 218] --[192 x 12 x  12] => [96 x 12 x  12] *** [192] ***[ COL] ***[0, 0, 0, 288, 288]**** [2], [0],[2] -[217 214 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),   60(   96),   7800(  30720),   0,     f300 ||||  L2, DMA,    144(   324),    144(   324),   60(   96),   f300(  62208),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),   60(   96),   7800(  30720),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  219(TIDL_ConvolutionLayer) [219, 219] --[96 x 12 x  12] => [96 x 12 x  12] *** [96] ***[ROW_L] ***[0, 0, 0, 288, 288]**** [1], [1],[1] -[218 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),   60(   96),   7800(  30720),   0,        0 ||||  L2, DMA,    140(   320),    140(   320),   60(   96),   7880(  30848),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),   60(   96),   7800(  30720),   0,    35b80 
  WT:DDR_PERSIST, DMA,     c0(   192),     c0(   192),   60(   96),   4b00(  19200),   0,   387c80 ||||MSMC, DMA,     c0(   192),     c0(   192),   60(   96),   4b00(  19200),   0,     7800 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  220(TIDL_ConvolutionLayer) [220, 220] --[96 x 12 x  12] => [58 x 12 x  12] *** [96] ***[ROW_L] ***[52, 64, 26, 224, 288]**** [1], [1],[1] -[219 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),   60(   96),   7800(  30720),   0,    35b80 ||||  L2, DMA,    140(   320),    140(   320),   60(   96),   7980(  31104),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),   3a(   58),   4880(  18560),   0,        0 
  WT:DDR_PERSIST, DMA,    6c0(  1728),    6c0(  1728),   3a(   58),  18980( 100736),   0,   38c780 ||||MSMC, DMA,    6c0(  1728),    6c0(  1728),   3a(   58),  18980( 100736),   0,     4880 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  221(TIDL_ConvolutionLayer) [221, 221] --[96 x 12 x  12] => [116 x 12 x  12] *** [96] ***[ROW_L] ***[52, 64, 26, 224, 288]**** [1], [1],[1] -[219 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),   60(   96),   7800(  30720),   0,    35b80 ||||  L2, DMA,    140(   320),    140(   320),   60(   96),   7980(  31104),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),   74(  116),   9100(  37120),   0,    35b80 
  WT:DDR_PERSIST, DMA,    6c0(  1728),    6c0(  1728),   74(  116),  31300( 201472),   0,   3a5100 ||||MSMC, DMA,    6c0(  1728),    6c0(  1728),   74(  116),  31300( 201472),   0,     4880 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  222(TIDL_ConcatLayer) [222, 222] --[174 x 12 x  12] => [174 x 12 x  12] *** [174] ***[ COL] ***[0, 0, 0, 288, 288]**** [3], [0],[3] -[220 221 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),   3a(   58),   4880(  18560),   0,        0 ||||  L2, DMA,    144(   324),    144(   324),   74(  116),   9300(  37632),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    120(   288),   ae(  174),   d980(  55680),   0,     4880 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  223(TIDL_DataConvertLayer) [223, 223] --[174 x 12 x  12] => [174 x 12 x  12] *** [174] ***[ COL] ***[0, 0, 0, 288, 288]**** [1], [0],[1] -[222 ]---
  IN:MSMC, DMA,    140(   320),    120(   288),   ae(  174),   d980(  55680),   0,     4880 ||||  L2, DMA,    120(   288),    120(   288),   ae(  174),   c400(  50176),   0,        0 
 OUT:MSMC, CPU,    240(   576),    240(   576),   ae(  174),  18780( 100224),   0,    12200 |||| DDR, DMA,    240(   576),    240(   576),   ae(  174),  18b80( 101248),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
