diff --git a/packages/ti/kernel/freertos/config/j721s2/r5f/FreeRTOSConfig_mcu1_0.h b/packages/ti/kernel/freertos/config/j721s2/r5f/FreeRTOSConfig_mcu1_0.h
old mode 100644
new mode 100755
index cad6723..057b1a4
--- a/packages/ti/kernel/freertos/config/j721s2/r5f/FreeRTOSConfig_mcu1_0.h
+++ b/packages/ti/kernel/freertos/config/j721s2/r5f/FreeRTOSConfig_mcu1_0.h
@@ -48,14 +48,14 @@
 
 /* -- Default DMTimer allocations for various cores in j721s2 ---*/
 /* c7x_1  - DMTimer 0
- * c7x_2  - DMTimer 1 
+ * c7x_2  - DMTimer 1
  * mcu2_0 - DMTimer 2
  * mcu2_1 - DMTimer 3
  * mcu3_0 - DMTimer 4
  * mcu3_1 - DMTimer 5
- * mcu1_0 - MCU DMTimer 1
+ * mcu1_0 - MCU DMTimer 19
  * mcu1_1 - MCU DMTimer 2
- */  
+ */
 
-#define configTIMER_ID                                                    (1)
+#define configTIMER_ID                                                    (19)
 #endif /* TI_FREERTOS_MCU1_0_CONFIG_H */
diff --git a/packages/ti/osal/soc/j721s2/TimerP_default.c b/packages/ti/osal/soc/j721s2/TimerP_default.c
old mode 100644
new mode 100755
index d7eb66a..2fd0626
--- a/packages/ti/osal/soc/j721s2/TimerP_default.c
+++ b/packages/ti/osal/soc/j721s2/TimerP_default.c
@@ -364,14 +364,14 @@ TimerP_dmTimerDefault gDmTimerPInfoTbl[TimerP_numTimerDevices] = {
   {
     "DMTimer19",
 #if defined (BUILD_MCU)
-     0U,
-     0,
-     TIMERP_EVENT_NOT_AVAILABLE
+    (uint32_t)CSL_TIMER19_CFG_BASE,
+    191u,
+    TIMERP_EVENT_NOT_AVAILABLE
 #endif
 #if defined (BUILD_MPU)
-     (uint32_t)CSL_TIMER19_CFG_BASE,
-     (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER19_INTR_PEND_0,
-     TIMERP_EVENT_NOT_AVAILABLE
+    (uint32_t)CSL_TIMER19_CFG_BASE,
+    (int32_t)CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_TIMER19_INTR_PEND_0,
+    TIMERP_EVENT_NOT_AVAILABLE
 #endif
   }
 };
@@ -432,7 +432,7 @@ void TimerP_updateDefaultInfoTbl(void)
             gDmTimerPInfoTbl[i].baseAddr = CSL_TIMER0_CFG_BASE + (i * 0x10000U);
             if(i == 12U)
             {
-                /* Interrupt number from Timer12 is a separate group */ 
+                /* Interrupt number from Timer12 is a separate group */
                 intIdx = CSLR_R5FSS0_CORE0_INTR_TIMER12_INTR_PEND_0;
             }
             gDmTimerPInfoTbl[i].intNum = intIdx++;
diff --git a/packages/ti/osal/soc/j721s2/osal_soc.h b/packages/ti/osal/soc/j721s2/osal_soc.h
index 65877c5..7e78970 100755
--- a/packages/ti/osal/soc/j721s2/osal_soc.h
+++ b/packages/ti/osal/soc/j721s2/osal_soc.h
@@ -70,8 +70,8 @@ extern "C" {
 
 #define TimerP_numTimerDevices          ((uint32_t) 20U )
 #if defined (BUILD_MCU)
-  #define TIMERP_ANY_MASK               ((uint32_t) 0x03FF)
-  #define TIMERP_AVAILABLE_MASK       ((uint32_t)(0x03FF))
+  #define TIMERP_ANY_MASK               ((uint32_t) 0x803FF)
+  #define TIMERP_AVAILABLE_MASK       ((uint32_t)(0x803FF))
 #endif
 #if defined (BUILD_MPU)
   #define TIMERP_ANY_MASK               ((uint32_t) 0x0FFF)
diff --git a/packages/ti/osal/src/freertos/TaskP_freertos.c b/packages/ti/osal/src/freertos/TaskP_freertos.c
old mode 100644
new mode 100755
index 18d1076..12a2348
--- a/packages/ti/osal/src/freertos/TaskP_freertos.c
+++ b/packages/ti/osal/src/freertos/TaskP_freertos.c
@@ -61,12 +61,12 @@ static int32_t prvC66xTickInterruptConfig( void );
 static int32_t prvSetupTimerPSC( void );
 
 /**
- * \brief Value to be used for lowest priority task 
+ * \brief Value to be used for lowest priority task
  */
 #define TaskP_PRIORITY_LOWEST       (0u)
 
 /**
- * \brief Value to be used for highest priority task 
+ * \brief Value to be used for highest priority task
  */
 #define TaskP_PRIORITY_HIGHEST      (configMAX_PRIORITIES - 1)
 
@@ -122,7 +122,7 @@ void TaskP_Function (void *arg)
 
     /* Call the application function. */
     (*handle->taskfxn)(handle->arg0, handle->arg1);
-    
+
     /* Task Fxn completed execution. */
     handle->terminated = TRUE;
     /* Put vTaskSuspend in a loop just in case some calls vTaskResume, it will go back to suspend. */
@@ -130,7 +130,7 @@ void TaskP_Function (void *arg)
     {
         vTaskSuspend(NULL);
     }
-    
+
 }
 
 /*
@@ -153,8 +153,8 @@ TaskP_Handle TaskP_create(TaskP_Fxn taskfxn, const TaskP_Params *params)
     /* Pick up the internal static memory block */
     taskPool        = (TaskP_freertos *) &gOsalTaskPfreertosPool[0];
     maxTasks        = OSAL_FREERTOS_CONFIGNUM_TASK;
-    
-    if(gOsalTaskAllocCnt==0U) 
+
+    if(gOsalTaskAllocCnt==0U)
     {
         (void)memset( (void *)gOsalTaskPfreertosPool,0,sizeof(gOsalTaskPfreertosPool));
         (void)memset( (void *)gOsalFreertosTaskObjPool,0,sizeof(gOsalFreertosTaskObjPool));
@@ -285,7 +285,7 @@ TaskP_Status TaskP_delete(TaskP_Handle *hTaskPtr)
     else
     {
        ret = TaskP_FAILURE;
-    }  
+    }
     return (ret);
 }
 
@@ -425,14 +425,14 @@ static int32_t prvSetupTimerPSC( void )
     if (info.grpId != (uint32_t)CSL_ARM_R5_CLUSTER_GROUP_ID_0)
     {
         Sciclient_ConfigPrms_t config;
- 
+
         Sciclient_configPrmsInit(&config);
- 
+
         xStatus = Sciclient_init(&config);
         if(  xStatus == CSL_PASS )
         {
             uint32_t currState, resetState, contextLossState, timerModuleId;
-            /* on J7AHP, Main domain timers 8-19 are connected to LPSC_PER_SPARE_0 which is not powered ON by default. 
+            /* on J7AHP, Main domain timers 8-19 are connected to LPSC_PER_SPARE_0 which is not powered ON by default.
              * All other timers are connected to LPSC which is ALWAYS_ON */
             xStatus = Sciclient_pmGetModuleState(TISCI_DEV_TIMER8, &currState, &resetState,
                                                 &contextLossState, SCICLIENT_SERVICE_WAIT_FOREVER);
@@ -516,6 +516,40 @@ static int32_t prvC66xTickInterruptConfig( void )
     }
 #endif
 
+#if defined (BUILD_MCU1_0) && defined (SOC_J721S2)
+    Sciclient_ConfigPrms_t config;
+
+    Sciclient_configPrmsInit(&config);
+
+    xStatus = Sciclient_init(&config);
+    if( xStatus != CSL_PASS )
+    {
+        return xStatus;
+    }
+    else
+    {
+        struct tisci_msg_rm_irq_set_req rmIrqReq;
+        struct tisci_msg_rm_irq_set_resp rmIrqResp;
+
+        rmIrqReq.valid_params = TISCI_MSG_VALUE_RM_DST_ID_VALID |
+        TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID;
+
+        rmIrqReq.src_index = 0U;
+        rmIrqReq.src_id = TISCI_DEV_TIMER19;
+        rmIrqReq.dst_id = TISCI_DEV_MCU_R5FSS0_CORE0;
+        rmIrqReq.dst_host_irq = 191U;
+
+        /* Unused params */
+        rmIrqReq.global_event = 0U;
+        rmIrqReq.ia_id = 0U;
+        rmIrqReq.vint = 0U;
+        rmIrqReq.vint_status_bit_index = 0U;
+        rmIrqReq.secondary_host = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;
+
+        xStatus = Sciclient_rmIrqSet(&rmIrqReq, &rmIrqResp, SCICLIENT_SERVICE_WAIT_FOREVER);
+    }
+#endif
+
     return xStatus;
 }
 /* Nothing past this point */
