ISSI initialization 533MHz ----------------------------- AM65x_DRA80xM_EMIF_Tool_2.02_ISSI_od_533.xlsm But with: Write_MMR( DDRSS_DDRCTL_INIT4 , 0x00100000 ); /* SDRAM Initialization Register 4 */ Write_MMR( DDRSS_DDRPHY_MR3 , 0x00000029 ); /* DDR Mode Register */ DDR not initialized with R5 connect. Go to menu Scripts --> DDR_Initialization to initialize DDR. ==== MCU_PULSAR_Cortex_R5_0: GEL Output: base = 0x43000000 MCU_PULSAR_Cortex_R5_0: GEL Output: offset = 0x0001C040 MCU_PULSAR_Cortex_R5_0: GEL Output: partition = 0x00000007 MCU_PULSAR_Cortex_R5_0: GEL Output: Partition successfully unlocked! MCU_PULSAR_Cortex_R5_0: GEL Output: Partition successfully locked! MCU_PULSAR_Cortex_R5_0: GEL Output: VTT Regulator Enabled MCU_PULSAR_Cortex_R5_0: GEL Output: PHY Init complete MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000000F MCU_PULSAR_Cortex_R5_0: GEL Output: Waiting for DRAM Init to complete... MCU_PULSAR_Cortex_R5_0: GEL Output: DRAM Init complete MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000001F MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000001F MCU_PULSAR_Cortex_R5_0: GEL Output: Waiting for DRAM Init to complete... MCU_PULSAR_Cortex_R5_0: GEL Output: DRAM Init complete MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000001F MCU_PULSAR_Cortex_R5_0: GEL Output: Waiting for write leveling to complete MCU_PULSAR_Cortex_R5_0: GEL Output: Write leveling done MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8020003F MCU_PULSAR_Cortex_R5_0: GEL Output: ****ERROR in Write Leveling**** MCU_PULSAR_Cortex_R5_0: GEL Output: checking Write Leveling status per byte... MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_DX0GSR0 = 0x010941E0 MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_DX1GSR0 = 0x010641E0 MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_DX2GSR0 = 0x01074160 MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_DX3GSR0 = 0x010E42E0 MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_DX4GSR0 = 0x00010000 MCU_PULSAR_Cortex_R5_0: GEL Output: CTRLMMR_WKUP_PID = 0x61800211 MCU_PULSAR_Cortex_R5_0: GEL Output: ==== LPDDR4 Initialization has FAILED!!!! DDR is configured for 532MHz operation ==== MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8020003F ISSI initialization 533MHz ----------------------------- Micron_AM65x_DRA80xM_EMIF_Tool_2.02_mod_od1_533.xlsm But with: Write_MMR( DDRSS_DDRCTL_INIT4 , 0x00100000 ); /* SDRAM Initialization Register 4 */ Write_MMR( DDRSS_DDRPHY_MR3 , 0x00000029 ); /* DDR Mode Register */ DDR not initialized with R5 connect. Go to menu Scripts --> DDR_Initialization to initialize DDR. ==== MCU_PULSAR_Cortex_R5_0: GEL Output: base = 0x43000000 MCU_PULSAR_Cortex_R5_0: GEL Output: offset = 0x0001C040 MCU_PULSAR_Cortex_R5_0: GEL Output: partition = 0x00000007 MCU_PULSAR_Cortex_R5_0: GEL Output: Partition successfully unlocked! MCU_PULSAR_Cortex_R5_0: GEL Output: Partition successfully locked! MCU_PULSAR_Cortex_R5_0: GEL Output: VTT Regulator Enabled MCU_PULSAR_Cortex_R5_0: GEL Output: PHY Init complete MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000000F MCU_PULSAR_Cortex_R5_0: GEL Output: Waiting for DRAM Init to complete... MCU_PULSAR_Cortex_R5_0: GEL Output: DRAM Init complete MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000001F MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000001F MCU_PULSAR_Cortex_R5_0: GEL Output: Waiting for DRAM Init to complete... MCU_PULSAR_Cortex_R5_0: GEL Output: DRAM Init complete MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000001F MCU_PULSAR_Cortex_R5_0: GEL Output: Waiting for write leveling to complete MCU_PULSAR_Cortex_R5_0: GEL Output: Write leveling done MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8020003F MCU_PULSAR_Cortex_R5_0: GEL Output: ****ERROR in Write Leveling**** MCU_PULSAR_Cortex_R5_0: GEL Output: checking Write Leveling status per byte... MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_DX0GSR0 = 0x010B41E0 MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_DX1GSR0 = 0x010641E0 MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_DX2GSR0 = 0x01074160 MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_DX3GSR0 = 0x010E42E0 MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_DX4GSR0 = 0x00010000 MCU_PULSAR_Cortex_R5_0: GEL Output: CTRLMMR_WKUP_PID = 0x61800211 MCU_PULSAR_Cortex_R5_0: GEL Output: ==== LPDDR4 Initialization has FAILED!!!! DDR is configured for 532MHz operation ==== MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8020003F Micron initialization 533MHz ----------------------------- Micron_AM65x_DRA80xM_EMIF_Tool_2.02_mod_od1_533.xlsm But with: Write_MMR( DDRSS_DDRCTL_INIT4 , 0x00100000 ); /* SDRAM Initialization Register 4 */ Write_MMR( DDRSS_DDRPHY_MR3 , 0x00000029 ); /* DDR Mode Register */ DDR not initialized with R5 connect. Go to menu Scripts --> DDR_Initialization to initialize DDR. ==== MCU_PULSAR_Cortex_R5_0: GEL Output: base = 0x43000000 MCU_PULSAR_Cortex_R5_0: GEL Output: offset = 0x0001C040 MCU_PULSAR_Cortex_R5_0: GEL Output: partition = 0x00000007 MCU_PULSAR_Cortex_R5_0: GEL Output: Partition successfully unlocked! MCU_PULSAR_Cortex_R5_0: GEL Output: Partition successfully locked! MCU_PULSAR_Cortex_R5_0: GEL Output: VTT Regulator Enabled MCU_PULSAR_Cortex_R5_0: GEL Output: PHY Init complete MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000000F MCU_PULSAR_Cortex_R5_0: GEL Output: Waiting for DRAM Init to complete... MCU_PULSAR_Cortex_R5_0: GEL Output: DRAM Init complete MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000001F MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000001F MCU_PULSAR_Cortex_R5_0: GEL Output: Waiting for DRAM Init to complete... MCU_PULSAR_Cortex_R5_0: GEL Output: DRAM Init complete MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000001F MCU_PULSAR_Cortex_R5_0: GEL Output: Waiting for write leveling to complete MCU_PULSAR_Cortex_R5_0: GEL Output: Write leveling done MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000003F MCU_PULSAR_Cortex_R5_0: GEL Output: Write Leveling completed successfully MCU_PULSAR_Cortex_R5_0: GEL Output: Waiting for Read DQS training to complete MCU_PULSAR_Cortex_R5_0: GEL Output: Read DQS training done MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000007F MCU_PULSAR_Cortex_R5_0: GEL Output: Read DQS training completed successfully MCU_PULSAR_Cortex_R5_0: GEL Output: --->>> Starting the DQS2DQ Training Process <<<--- MCU_PULSAR_Cortex_R5_0: GEL Output: DQS2DQ Training done MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000807F MCU_PULSAR_Cortex_R5_0: GEL Output: DQS2DQ completed successfully MCU_PULSAR_Cortex_R5_0: GEL Output: Waiting for Write leveling adjustment to complete MCU_PULSAR_Cortex_R5_0: GEL Output: Write leveling adjustment done MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x800080FF MCU_PULSAR_Cortex_R5_0: GEL Output: Write Leveling Adjustment completed successfully MCU_PULSAR_Cortex_R5_0: GEL Output: Waiting for Read deskew to complete MCU_PULSAR_Cortex_R5_0: GEL Output: Read deskew complete MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x800081FF MCU_PULSAR_Cortex_R5_0: GEL Output: Read Deskew completed successfully MCU_PULSAR_Cortex_R5_0: GEL Output: Waiting for Write deskew to complete MCU_PULSAR_Cortex_R5_0: GEL Output: Write deskew complete MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x800083FF MCU_PULSAR_Cortex_R5_0: GEL Output: Write Deskew completed successfully MCU_PULSAR_Cortex_R5_0: GEL Output: Waiting for Read Eye training to complete MCU_PULSAR_Cortex_R5_0: GEL Output: Read Eye training complete MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x800087FF MCU_PULSAR_Cortex_R5_0: GEL Output: Read Eye Training completed successfully MCU_PULSAR_Cortex_R5_0: GEL Output: Waiting for Write Eye training to complete MCU_PULSAR_Cortex_R5_0: GEL Output: Write Eye training complete MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x80008FFF MCU_PULSAR_Cortex_R5_0: GEL Output: Write Eye Training completed successfully MCU_PULSAR_Cortex_R5_0: GEL Output: Waiting for VREF training to complete MCU_PULSAR_Cortex_R5_0: GEL Output: VREF training complete MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000CFFF MCU_PULSAR_Cortex_R5_0: GEL Output: VREF Training completed successfully MCU_PULSAR_Cortex_R5_0: GEL Output: CTRLMMR_WKUP_PID = 0x61800211 MCU_PULSAR_Cortex_R5_0: GEL Output: ==== LPDDR4 Initialization has PASSED!!!! DDR is configured for 532MHz operation ==== ISSI initialization 600MHz ----------------------------- AM65x_DRA80xM_EMIF_Tool_2.02_ISSI_od_600.xlsm But with: Write_MMR( DDRSS_DDRCTL_INIT4 , 0x00100000 ); /* SDRAM Initialization Register 4 */ Write_MMR( DDRSS_DDRPHY_MR3 , 0x00000029 ); /* DDR Mode Register */ DDR not initialized with R5 connect. Go to menu Scripts --> DDR_Initialization to initialize DDR. ==== MCU_PULSAR_Cortex_R5_0: GEL Output: base = 0x43000000 MCU_PULSAR_Cortex_R5_0: GEL Output: offset = 0x0001C040 MCU_PULSAR_Cortex_R5_0: GEL Output: partition = 0x00000007 MCU_PULSAR_Cortex_R5_0: GEL Output: Partition successfully unlocked! MCU_PULSAR_Cortex_R5_0: GEL Output: Partition successfully locked! MCU_PULSAR_Cortex_R5_0: GEL Output: VTT Regulator Enabled MCU_PULSAR_Cortex_R5_0: GEL Output: PHY Init complete MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000000F MCU_PULSAR_Cortex_R5_0: GEL Output: Waiting for DRAM Init to complete... MCU_PULSAR_Cortex_R5_0: GEL Output: DRAM Init complete MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000001F MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000001F MCU_PULSAR_Cortex_R5_0: GEL Output: Waiting for DRAM Init to complete... MCU_PULSAR_Cortex_R5_0: GEL Output: DRAM Init complete MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000001F MCU_PULSAR_Cortex_R5_0: GEL Output: Waiting for write leveling to complete MCU_PULSAR_Cortex_R5_0: GEL Output: Write leveling done MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8020003F MCU_PULSAR_Cortex_R5_0: GEL Output: ****ERROR in Write Leveling**** MCU_PULSAR_Cortex_R5_0: GEL Output: checking Write Leveling status per byte... MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_DX0GSR0 = 0x00ED3A60 MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_DX1GSR0 = 0x00EA3A60 MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_DX2GSR0 = 0x00ED39E0 MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_DX3GSR0 = 0x00F03B60 MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_DX4GSR0 = 0x00010000 MCU_PULSAR_Cortex_R5_0: GEL Output: CTRLMMR_WKUP_PID = 0x61800211 MCU_PULSAR_Cortex_R5_0: GEL Output: ==== LPDDR4 Initialization has FAILED!!!! DDR is configured for 600MHz operation ==== MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8020003F ISSI initialization 600MHz ----------------------------- Micron_AM65x_DRA80xM_EMIF_Tool_2.02_mod_od1_600.xlsm But with: Write_MMR( DDRSS_DDRCTL_INIT4 , 0x00100000 ); /* SDRAM Initialization Register 4 */ Write_MMR( DDRSS_DDRPHY_MR3 , 0x00000029 ); /* DDR Mode Register */ DDR not initialized with R5 connect. Go to menu Scripts --> DDR_Initialization to initialize DDR. ==== MCU_PULSAR_Cortex_R5_0: GEL Output: base = 0x43000000 MCU_PULSAR_Cortex_R5_0: GEL Output: offset = 0x0001C040 MCU_PULSAR_Cortex_R5_0: GEL Output: partition = 0x00000007 MCU_PULSAR_Cortex_R5_0: GEL Output: Partition successfully unlocked! MCU_PULSAR_Cortex_R5_0: GEL Output: Partition successfully locked! MCU_PULSAR_Cortex_R5_0: GEL Output: VTT Regulator Enabled MCU_PULSAR_Cortex_R5_0: GEL Output: PHY Init complete MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000000F MCU_PULSAR_Cortex_R5_0: GEL Output: Waiting for DRAM Init to complete... MCU_PULSAR_Cortex_R5_0: GEL Output: DRAM Init complete MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000001F MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000001F MCU_PULSAR_Cortex_R5_0: GEL Output: Waiting for DRAM Init to complete... MCU_PULSAR_Cortex_R5_0: GEL Output: DRAM Init complete MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000001F MCU_PULSAR_Cortex_R5_0: GEL Output: Waiting for write leveling to complete MCU_PULSAR_Cortex_R5_0: GEL Output: Write leveling done MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8020003F MCU_PULSAR_Cortex_R5_0: GEL Output: ****ERROR in Write Leveling**** MCU_PULSAR_Cortex_R5_0: GEL Output: checking Write Leveling status per byte... MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_DX0GSR0 = 0x00EB3A60 MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_DX1GSR0 = 0x00E83A60 MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_DX2GSR0 = 0x00ED39E0 MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_DX3GSR0 = 0x00F03B60 MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_DX4GSR0 = 0x00010000 MCU_PULSAR_Cortex_R5_0: GEL Output: CTRLMMR_WKUP_PID = 0x61800211 MCU_PULSAR_Cortex_R5_0: GEL Output: ==== LPDDR4 Initialization has FAILED!!!! DDR is configured for 600MHz operation ==== MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8020003F Micron initialization 600MHz ----------------------------- Micron_AM65x_DRA80xM_EMIF_Tool_2.02_mod_od1_600.xlsm But with: Write_MMR( DDRSS_DDRCTL_INIT4 , 0x00100000 ); /* SDRAM Initialization Register 4 */ Write_MMR( DDRSS_DDRPHY_MR3 , 0x00000029 ); /* DDR Mode Register */ DDR not initialized with R5 connect. Go to menu Scripts --> DDR_Initialization to initialize DDR. ==== MCU_PULSAR_Cortex_R5_0: GEL Output: base = 0x43000000 MCU_PULSAR_Cortex_R5_0: GEL Output: offset = 0x0001C040 MCU_PULSAR_Cortex_R5_0: GEL Output: partition = 0x00000007 MCU_PULSAR_Cortex_R5_0: GEL Output: Partition successfully unlocked! MCU_PULSAR_Cortex_R5_0: GEL Output: Partition successfully locked! MCU_PULSAR_Cortex_R5_0: GEL Output: VTT Regulator Enabled MCU_PULSAR_Cortex_R5_0: GEL Output: PHY Init complete MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000000F MCU_PULSAR_Cortex_R5_0: GEL Output: Waiting for DRAM Init to complete... MCU_PULSAR_Cortex_R5_0: GEL Output: DRAM Init complete MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000001F MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000001F MCU_PULSAR_Cortex_R5_0: GEL Output: Waiting for DRAM Init to complete... MCU_PULSAR_Cortex_R5_0: GEL Output: DRAM Init complete MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000001F MCU_PULSAR_Cortex_R5_0: GEL Output: Waiting for write leveling to complete MCU_PULSAR_Cortex_R5_0: GEL Output: Write leveling done MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000003F MCU_PULSAR_Cortex_R5_0: GEL Output: Write Leveling completed successfully MCU_PULSAR_Cortex_R5_0: GEL Output: Waiting for Read DQS training to complete MCU_PULSAR_Cortex_R5_0: GEL Output: Read DQS training done MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000007F MCU_PULSAR_Cortex_R5_0: GEL Output: Read DQS training completed successfully MCU_PULSAR_Cortex_R5_0: GEL Output: --->>> Starting the DQS2DQ Training Process <<<--- MCU_PULSAR_Cortex_R5_0: GEL Output: DQS2DQ Training done MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000807F MCU_PULSAR_Cortex_R5_0: GEL Output: DQS2DQ completed successfully MCU_PULSAR_Cortex_R5_0: GEL Output: Waiting for Write leveling adjustment to complete MCU_PULSAR_Cortex_R5_0: GEL Output: Write leveling adjustment done MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x800080FF MCU_PULSAR_Cortex_R5_0: GEL Output: Write Leveling Adjustment completed successfully MCU_PULSAR_Cortex_R5_0: GEL Output: Waiting for Read deskew to complete MCU_PULSAR_Cortex_R5_0: GEL Output: Read deskew complete MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x800081FF MCU_PULSAR_Cortex_R5_0: GEL Output: Read Deskew completed successfully MCU_PULSAR_Cortex_R5_0: GEL Output: Waiting for Write deskew to complete MCU_PULSAR_Cortex_R5_0: GEL Output: Write deskew complete MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x800083FF MCU_PULSAR_Cortex_R5_0: GEL Output: Write Deskew completed successfully MCU_PULSAR_Cortex_R5_0: GEL Output: Waiting for Read Eye training to complete MCU_PULSAR_Cortex_R5_0: GEL Output: Read Eye training complete MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x800087FF MCU_PULSAR_Cortex_R5_0: GEL Output: Read Eye Training completed successfully MCU_PULSAR_Cortex_R5_0: GEL Output: Waiting for Write Eye training to complete MCU_PULSAR_Cortex_R5_0: GEL Output: Write Eye training complete MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x80008FFF MCU_PULSAR_Cortex_R5_0: GEL Output: Write Eye Training completed successfully MCU_PULSAR_Cortex_R5_0: GEL Output: Waiting for VREF training to complete MCU_PULSAR_Cortex_R5_0: GEL Output: VREF training complete MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRPHY_PGSR0 = 0x8000CFFF MCU_PULSAR_Cortex_R5_0: GEL Output: VREF Training completed successfully MCU_PULSAR_Cortex_R5_0: GEL Output: CTRLMMR_WKUP_PID = 0x61800211 MCU_PULSAR_Cortex_R5_0: GEL Output: ==== LPDDR4 Initialization has PASSED!!!! DDR is configured for 600MHz operation ====