Updated MCU CPSW2G Interrupt mapping to Main Domain R5F Cores

diff --git a/soc/j7x/j742s2/enet_soc.c b/soc/j7x/j742s2/enet_soc.c
index cd21e7f4..1ff52dab 100644
--- a/soc/j7x/j742s2/enet_soc.c
+++ b/soc/j7x/j742s2/enet_soc.c
@@ -1,4 +1,4 @@
-/*
+    /*
  *  Copyright (c) Texas Instruments Incorporated 2021-2024
  *
  *  Redistribution and use in source and binary forms, with or without
@@ -137,98 +137,98 @@ CpswSoc_Cfg gEnetSoc_cpsw2gSocCfg =
 #elif defined(BUILD_MCU2_0)
         {   /* EVNT_PEND - Event pending interrupt (CPTS) */
             .intrId     = CPSW_INTR_EVNT_PEND,
-            .coreIntNum = CSLR_R5FSS0_CORE1_INTR_CPSW_9XUSSM0_EVNT_PEND_0,
-            .srcIdx     = CPSW_INTR_EVENT_PEND_SRCIDX,
+            .coreIntNum = CSLR_R5FSS0_CORE0_INTR_MCU_CPSW0_EVNT_PEND_0,
+            .srcIdx     = ENET_SOC_DIRECT_INTR_SRCIDX_INVALID,
         },
         {   /* STATS_PEND - Statistics pending interrupt */
             .intrId     = CPSW_INTR_STATS_PEND0,
-            .coreIntNum = CSLR_R5FSS0_CORE1_INTR_CPSW_9XUSSM0_STAT_PEND_0,
-            .srcIdx     = CPSW_INTR_STAT_PEND0_SRCIDX,
+            .coreIntNum = CSLR_R5FSS0_CORE0_INTR_MCU_CPSW0_STAT_PEND_0,
+            .srcIdx     = ENET_SOC_DIRECT_INTR_SRCIDX_INVALID,
         },
         {   /* MDIO_PEND - MDIO interrupt */
             .intrId     = CPSW_INTR_MDIO_PEND,
-            .coreIntNum = CSLR_R5FSS0_CORE1_INTR_CPSW_9XUSSM0_MDIO_PEND_0,
-            .srcIdx     = CPSW_INTR_MDIO_INTR_SRCIDX,
+            .coreIntNum = CSLR_R5FSS0_CORE0_INTR_MCU_CPSW0_MDIO_PEND_0,
+            .srcIdx     = ENET_SOC_DIRECT_INTR_SRCIDX_INVALID,
         },
 #elif defined(BUILD_MCU2_1)
         {   /* EVNT_PEND - Event pending interrupt (CPTS) */
             .intrId     = CPSW_INTR_EVNT_PEND,
-            .coreIntNum = CSLR_R5FSS0_CORE1_INTR_CPSW1_EVNT_PEND_0,
-            .srcIdx     = CPSW_INTR_EVENT_PEND_SRCIDX,
+            .coreIntNum = CSLR_R5FSS0_CORE1_INTR_MCU_CPSW0_EVNT_PEND_0,
+            .srcIdx     = ENET_SOC_DIRECT_INTR_SRCIDX_INVALID,
         },
         {   /* STATS_PEND - Statistics pending interrupt */
             .intrId     = CPSW_INTR_STATS_PEND0,
-            .coreIntNum = CSLR_R5FSS0_CORE1_INTR_CPSW1_STAT_PEND_0,
-            .srcIdx     = CPSW_INTR_STAT_PEND0_SRCIDX,
+            .coreIntNum = CSLR_R5FSS0_CORE1_INTR_MCU_CPSW0_STAT_PEND_0,
+            .srcIdx     = ENET_SOC_DIRECT_INTR_SRCIDX_INVALID,
         },
         {   /* MDIO_PEND - MDIO interrupt */
             .intrId     = CPSW_INTR_MDIO_PEND,
-            .coreIntNum = CSLR_R5FSS0_CORE1_INTR_CPSW1_MDIO_PEND_0,
-            .srcIdx     = CPSW_INTR_MDIO_INTR_SRCIDX,
+            .coreIntNum = CSLR_R5FSS0_CORE1_INTR_MCU_CPSW0_MDIO_PEND_0,
+            .srcIdx     = ENET_SOC_DIRECT_INTR_SRCIDX_INVALID,
         },
 #elif defined(BUILD_MCU3_0)
         {   /* EVNT_PEND - Event pending interrupt (CPTS) */
             .intrId     = CPSW_INTR_EVNT_PEND,
-            .coreIntNum = CSLR_R5FSS1_CORE0_INTR_CPSW1_EVNT_PEND_0,
-            .srcIdx     = CPSW_INTR_EVENT_PEND_SRCIDX,
+            .coreIntNum = CSLR_R5FSS1_CORE0_INTR_MCU_CPSW0_EVNT_PEND_0,
+            .srcIdx     = ENET_SOC_DIRECT_INTR_SRCIDX_INVALID,
         },
         {   /* STATS_PEND - Statistics pending interrupt */
             .intrId     = CPSW_INTR_STATS_PEND0,
-            .coreIntNum = CSLR_R5FSS1_CORE0_INTR_CPSW1_STAT_PEND_0,
-            .srcIdx     = CPSW_INTR_STAT_PEND0_SRCIDX,
+            .coreIntNum = CSLR_R5FSS1_CORE0_INTR_MCU_CPSW0_STAT_PEND_0,
+            .srcIdx     = ENET_SOC_DIRECT_INTR_SRCIDX_INVALID,
         },
         {   /* MDIO_PEND - MDIO interrupt */
             .intrId     = CPSW_INTR_MDIO_PEND,
-            .coreIntNum = CSLR_R5FSS1_CORE0_INTR_CPSW1_MDIO_PEND_0,
-            .srcIdx     = CPSW_INTR_MDIO_INTR_SRCIDX,
+            .coreIntNum = CSLR_R5FSS1_CORE0_INTR_MCU_CPSW0_MDIO_PEND_0,
+            .srcIdx     = ENET_SOC_DIRECT_INTR_SRCIDX_INVALID,
         },
 #elif defined(BUILD_MCU3_1)
         {   /* EVNT_PEND - Event pending interrupt (CPTS) */
             .intrId     = CPSW_INTR_EVNT_PEND,
-            .coreIntNum = CSLR_R5FSS1_CORE1_INTR_CPSW1_EVNT_PEND_0,
-            .srcIdx     = CPSW_INTR_EVENT_PEND_SRCIDX,
+            .coreIntNum = CSLR_R5FSS1_CORE1_INTR_MCU_CPSW0_EVNT_PEND_0,
+            .srcIdx     = ENET_SOC_DIRECT_INTR_SRCIDX_INVALID,
         },
         {   /* STATS_PEND - Statistics pending interrupt */
             .intrId     = CPSW_INTR_STATS_PEND0,
-            .coreIntNum = CSLR_R5FSS1_CORE1_INTR_CPSW1_STAT_PEND_0,
-            .srcIdx     = CPSW_INTR_STAT_PEND0_SRCIDX,
+            .coreIntNum = CSLR_R5FSS1_CORE1_INTR_MCU_CPSW0_STAT_PEND_0,
+            .srcIdx     = ENET_SOC_DIRECT_INTR_SRCIDX_INVALID,
         },
         {   /* MDIO_PEND - MDIO interrupt */
             .intrId     = CPSW_INTR_MDIO_PEND,
-            .coreIntNum = CSLR_R5FSS1_CORE1_INTR_CPSW1_MDIO_PEND_0,
-            .srcIdx     = CPSW_INTR_MDIO_INTR_SRCIDX,
+            .coreIntNum = CSLR_R5FSS1_CORE1_INTR_MCU_CPSW0_MDIO_PEND_0,
+            .srcIdx     = ENET_SOC_DIRECT_INTR_SRCIDX_INVALID,
         },
 #elif defined(BUILD_MCU4_0)
         {   /* EVNT_PEND - Event pending interrupt (CPTS) */
             .intrId     = CPSW_INTR_EVNT_PEND,
-            .coreIntNum = CSLR_R5FSS2_CORE0_INTR_CPSW1_EVNT_PEND_0,
-            .srcIdx     = CPSW_INTR_EVENT_PEND_SRCIDX,
+            .coreIntNum = CSLR_R5FSS2_CORE0_INTR_MCU_CPSW0_EVNT_PEND_0,
+            .srcIdx     = ENET_SOC_DIRECT_INTR_SRCIDX_INVALID,
         },
         {   /* STATS_PEND - Statistics pending interrupt */
             .intrId     = CPSW_INTR_STATS_PEND0,
-            .coreIntNum = CSLR_R5FSS2_CORE0_INTR_CPSW1_STAT_PEND_0,
-            .srcIdx     = CPSW_INTR_STAT_PEND0_SRCIDX,
+            .coreIntNum = CSLR_R5FSS2_CORE0_INTR_MCU_CPSW0_STAT_PEND_0,
+            .srcIdx     = ENET_SOC_DIRECT_INTR_SRCIDX_INVALID,
         },
         {   /* MDIO_PEND - MDIO interrupt */
             .intrId     = CPSW_INTR_MDIO_PEND,
-            .coreIntNum = CSLR_R5FSS2_CORE0_INTR_CPSW1_MDIO_PEND_0,
-            .srcIdx     = CPSW_INTR_MDIO_INTR_SRCIDX,
+            .coreIntNum = CSLR_R5FSS2_CORE0_INTR_MCU_CPSW0_MDIO_PEND_0,
+            .srcIdx     = ENET_SOC_DIRECT_INTR_SRCIDX_INVALID,
         },
 #elif defined(BUILD_MCU4_1)
         {   /* EVNT_PEND - Event pending interrupt (CPTS) */
             .intrId     = CPSW_INTR_EVNT_PEND,
-            .coreIntNum = CSLR_R5FSS2_CORE1_INTR_CPSW1_EVNT_PEND_0,
-            .srcIdx     = CPSW_INTR_EVENT_PEND_SRCIDX,
+            .coreIntNum = CSLR_R5FSS2_CORE1_INTR_MCU_CPSW0_EVNT_PEND_0,
+            .srcIdx     = ENET_SOC_DIRECT_INTR_SRCIDX_INVALID,
         },
         {   /* STATS_PEND - Statistics pending interrupt */
             .intrId     = CPSW_INTR_STATS_PEND0,
-            .coreIntNum = CSLR_R5FSS2_CORE1_INTR_CPSW1_STAT_PEND_0,
-            .srcIdx     = CPSW_INTR_STAT_PEND0_SRCIDX,
+            .coreIntNum = CSLR_R5FSS2_CORE1_INTR_MCU_CPSW0_STAT_PEND_0,
+            .srcIdx     = ENET_SOC_DIRECT_INTR_SRCIDX_INVALID,
         },
         {   /* MDIO_PEND - MDIO interrupt */
             .intrId     = CPSW_INTR_MDIO_PEND,
-            .coreIntNum = CSLR_R5FSS2_CORE1_INTR_CPSW1_MDIO_PEND_0,
-            .srcIdx     = CPSW_INTR_MDIO_INTR_SRCIDX,
+            .coreIntNum = CSLR_R5FSS2_CORE1_INTR_MCU_CPSW0_MDIO_PEND_0,
+            .srcIdx     = ENET_SOC_DIRECT_INTR_SRCIDX_INVALID,
         },
 #elif defined(BUILD_MPU1_0)
         {   /* EVNT_PEND - Event pending interrupt (CPTS) */
