653.53> =====================DSS clock script===================
  653.53> Dumps internal clocks and muxes of DSS
  653.55> 
  653.58> CTRL_CORE_DSS_PLL_CONTROL (0x4a002538) = 0x000002A6
  653.58> video1 PLL :  Enabled
  653.59> video2 PLL :  Disabled
  653.59> HDMI   PLL :  Disabled
  653.61> DSI1_A_CLK mux : DPLL Video1
  653.61> DSI1_B_CLK mux : DPLL video2
  653.61> DSI1_C_CLK mux : DPLL Video1
  653.61> 
  653.66> DSS_CTRL (0x58000040) = 0x00010001
  653.66>  2: LCD1 clk switch :  DSI1_A_CLK
  653.66>  3: LCD2 clk switch :  DSS clk
  653.66> 10: LCD3 clk switch :  DSS clk
  653.66>  1: func clk switch :  DSS clk
  653.66> 13: DPI1 output     :  LCD1
  653.66> 
  653.66> DSS_STATUS (0x5800005C) = 0x01408A82
  653.66> 
  653.69> DSI_CLK_CTRL (0x58004054) = 0x80004001
  653.69> 
  653.78> ========================================================
  653.80> Register dump for DPLL video1
  653.80> |----------------------------|
  653.80> | Address (hex) | Data (hex) |
  653.80> |----------------------------|
  653.80> | 0x58004300    | 0x00000018 |
  653.80> | 0x58004304    | 0x00002283 |
  653.80> | 0x58004308    | 0x00000000 |
  653.80> | 0x5800430C    | 0x00602600 |
  653.80> | 0x58004310    | 0x00616008 |
  653.80> | 0x58004314    | 0x00000000 |
  653.80> | 0x58004318    | 0x00000000 |
  653.81> | 0x5800431C    | 0x00000000 |
  653.81> | 0x58004320    | 0x00000000 |
  653.81> |----------------------------|
  653.81> Details for DPLL video1
  653.81> PLL status  :  Locked
  653.81> M4 hsdiv(1) :  Active
  653.81> M5 hsdiv(2) :  inactive
  653.81> M6 hsdiv(3) :  inactive
  653.81> M7 hsdiv(4) :  inactive
  653.81> 
  653.92> PLL_REGM   =  19
  653.94> PLL_REGN   =  0
  653.94> M4 DIV     =  3
  653.94> M6 DIV     =  0
  653.94> M7 DIV     =  0
  653.94> 
  653.94> Clock calculations (DPLL video1)
  653.94> sysclk = 20000000
  653.94> DCO clk = sysclk * 2 * REGM / (REGN + 1) = 760000000
  653.94> M4clk (clkcout1) = DCO clk / (M4 DIV + 1) = 190000000
  653.94> M6clk (clkcout3) = DCO clk / (M6 DIV + 1) = 0
  653.94> M7clk (clkcout4) = DCO clk / (M7 DIV + 1) = 0
  653.95> 
  653.95> ========================================================
  653.95> Clock O/P of MUXes
  654.05> DSI1_A_CLK :  190000000
  654.06> DSI1_B_CLK :  0
  654.06> DSI1_C_CLK :  0
  654.06> 
  654.11>  2: LCD1 clk :  190000000
  654.12>  3: LCD2 clk :  33000000
  654.12> 10: LCD3 clk :  33000000
  654.12>  1: func clk :  33000000
  654.12> 
  654.28> LCD1 logic clk(/ 1 ) :  190000000  pix clk(/ 5 ) :  38000000
  654.28> LCD2 logic clk(/ 1 ) :  33000000  pix clk(/ 1 ) :  33000000
  654.28> LCD3 logic clk(/ 4 ) :  8250000  pix clk(/ 1 ) :  8250000