Working
state	Lockup 1	Lockup 2	Lockup 3	Lockup 4	Lockup 5	Lockup 6	
Software version	Any	.206	.207	.209	.209	.212	.212	
								
ARM Boot ROM 	OK	untested	OK	OK	OK	OK	OK	
ARM AXI2VBUSM	No access	No access	No access	No access	No access	No access	No access	
ARM CorePac Cfg	OK	No access	OK	OK	OK	OK	OK	
NetCP	OK	No access	OK	OK	OK	OK	OK	
PLL controller	OK	No access	OK	OK	OK	OK	OK	
Hyperlink Serdes	OK	No access	OK	OK	OK	OK	OK	
10G SerDes	OK	No access	OK	OK	OK	OK	OK	
PCIE0 SerDes	OK	No access	OK	OK	OK	OK	OK	
SGMII 1 SerDes	OK	No access	OK	OK	OK	OK	OK	
PCIE1 SerDes	OK	No access	OK	OK	OK	OK	OK	
DDRA PHY	OK	No access	OK	OK	OK	OK	OK	
SGMII 0 SerDes	OK	No access	OK	OK	OK	OK	OK	
Power Sleep Controller	OK	No access	OK	OK	OK	OK	OK	
I2C0	OK	No access	OK	OK	OK	OK	OK	
I2C1	OK	No access	OK	OK	OK	OK	OK	
I2C2	OK	No access	OK	OK	OK	OK	OK	
UART0	OK	No access	OK	OK	OK	OK	OK	
UART1	OK	No access	OK	OK	OK	OK	OK	
Int Controller	OK	OK	OK	OK	OK	OK	OK	
CIC0	OK	OK	OK	OK	OK	OK	OK	
CIC2	OK	OK	OK	OK	OK	OK	OK	
GPIO	OK	No access	OK	OK	OK	OK	OK	
BOOTCFG	OK	No access	OK	OK	OK	OK	OK	
USB0 PHY	No access	No access	No access	HUNG the debug	HUNG the debug	No access	No access	
Semaphore system	OK	No access	OK	untested	untested	OK	OK	
USB 0 MMR	No access	No access	No access			No access	No access	
Nav CFG	OK	No access	OK			OK	OK	
Nav link	OK	No access	OK			OK	OK	
10GBE CFG	OK	No access	OK			OK	OK	
XMC	No access	No access	No access			No access	No access	
MSMC	OK	OK	OK			OK	OK	
MSM	OK	OK	OK			OK	OK	
STM	No access	No access	No access			No access	No access	
SPI0	OK	No access	OK			OK	OK	
SPI1	OK	No access	OK			OK	OK	
SPI2	OK	No access	OK			OK	OK	
EMIF	OK	No access	OK			OK	OK	
DDR EMIF	No access	No access	No access			No access	No access	
Hyperlink Cfg	No access	No access	No access			No access	No access	
USB1 MMR	No access	No access	No access			No access	No access	
USB1 PHY	No access	No access	No access			No access	No access	
Hyperlink data	No access	No access	No access			No access	No access	
PCIE1 regs	No access	No access	No access			No access	No access	
PCIE1 data	No access	No access	No access			No access	No access	
PCIE0 regs	No access	No access	No access			No access	No access	
PCIE0 data	No access	No access	No access			No access	No access	
EDMA	OK	untested	OK	untested	OK	OK	OK	
DDR RAM	OK	HUNG the debug
reading CPU3 memory	OK	untested	RAM briefly tested,
seemed OK	OK	OK