Audio Pre-processing Demo for C5517 EVM with CMB This Demo Will Continuously Get Audio Input from CMB, Process the Audio Using BF+ASNR+MSS, then Send the Processed Audio to the Left Channel of the On-Board Codec (AIC3204-2) Bypass Audio Input from Mic2 of CMB to the Right Channel of the On-Board Codec Please Connect the Headphone to the Audio Output (Headphone) Jack (P9) DMA Interrupt Enable Status: 1 I2S2 Module Instance opened successfully I2S2 Module Configured successfully I2S3 ***I2S1*** Module Instance opened successfully I2S3 Module Configured successfully I2S0 Module Instance opened successfully I2S0 Module Configured successfully bf required buffers: Buffer Size(twords) Alignment Volatile address 0 82 1 no 0x0 1 138 0 no 0x0 2 144 0 no 0x0 3 184 1 yes 0x0 4 320 1 yes 0x0 Buffers allocated by SIU for bf: Buffer Size(twords) Alignment Volatile address 0 82 1 no 0x1 1 138 0 no 0x1 2 144 0 no 0x1 3 184 1 yes 0x1 4 320 1 yes 0x1 bf required buffers: Buffer Size(twords) Alignment Volatile address 0 82 1 no 0x0 1 138 0 no 0x0 2 144 0 no 0x0 3 184 1 yes 0x0 4 320 1 yes 0x0 Buffers allocated by SIU for bf: Buffer Size(twords) Alignment Volatile address 0 82 1 no 0x1 1 138 0 no 0x1 2 144 0 no 0x1 3 184 1 yes 0x1 4 320 1 yes 0x1 bf required buffers: Buffer Size(twords) Alignment Volatile address 0 82 1 no 0x0 1 138 0 no 0x0 2 144 0 no 0x0 3 184 1 yes 0x0 4 320 1 yes 0x0 Buffers allocated by SIU for bf: Buffer Size(twords) Alignment Volatile address 0 82 1 no 0x1 1 138 0 no 0x1 2 144 0 no 0x1 3 184 1 yes 0x1 4 320 1 yes 0x1 bf required buffers: Buffer Size(twords) Alignment Volatile address 0 82 1 no 0x0 1 138 0 no 0x0 2 144 0 no 0x0 3 184 1 yes 0x0 4 320 1 yes 0x0 Buffers allocated by SIU for bf: Buffer Size(twords) Alignment Volatile address 0 82 1 no 0x1 1 138 0 no 0x1 2 144 0 no 0x1 3 184 1 yes 0x1 4 320 1 yes 0x1 bf required buffers: Buffer Size(twords) Alignment Volatile address 0 82 1 no 0x0 1 138 0 no 0x0 2 144 0 no 0x0 3 184 1 yes 0x0 4 320 1 yes 0x0 Buffers allocated by SIU for bf: Buffer Size(twords) Alignment Volatile address 0 82 1 no 0x1 1 138 0 no 0x1 2 144 0 no 0x1 3 184 1 yes 0x1 4 320 1 yes 0x1 bf required buffers: Buffer Size(twords) Alignment Volatile address 0 82 1 no 0x0 1 138 0 no 0x0 2 144 0 no 0x0 3 184 1 yes 0x0 4 320 1 yes 0x0 Buffers allocated by SIU for bf: Buffer Size(twords) Alignment Volatile address 0 82 1 no 0x1 1 138 0 no 0x1 2 144 0 no 0x1 3 184 1 yes 0x1 4 320 1 yes 0x1 Buffers requested by NR: Buffer Size(twords) Alignment Volatile 0 44 1 no 1 774 1 yes 2 516 1 yes 3 387 1 yes 4 192 1 no 5 516 1 no 6 14 1 no Buffers allocated for NR: Buffer Size(twords) Alignment Volatile address 0 88 3 no 0x1 1 1552 3 yes 0x1 2 1032 3 yes 0x1 3 776 3 yes 0x1 4 384 2 no 0x1 5 1032 2 no 0x1 6 32 3 no 0x1 Buffers requested by NR: Buffer Size(twords) Alignment Volatile 0 44 1 no 1 774 1 yes 2 516 1 yes 3 387 1 yes 4 192 1 no 5 516 1 no 6 14 1 no Buffers allocated for NR: Buffer Size(twords) Alignment Volatile address 0 88 3 no 0x1 1 1552 3 yes 0x1 2 1032 3 yes 0x1 3 776 3 yes 0x1 4 384 2 no 0x1 5 1032 2 no 0x1 6 32 3 no 0x1 Buffers requested by NR: Buffer Size(twords) Alignment Volatile 0 44 1 no 1 774 1 yes 2 516 1 yes 3 387 1 yes 4 192 1 no 5 516 1 no 6 14 1 no Buffers allocated for NR: Buffer Size(twords) Alignment Volatile address 0 88 3 no 0x1 1 1552 3 yes 0x1 2 1032 3 yes 0x1 3 776 3 yes 0x1 4 384 2 no 0x1 5 1032 2 no 0x1 6 32 3 no 0x1 Buffers requested by NR: Buffer Size(twords) Alignment Volatile 0 44 1 no 1 774 1 yes 2 516 1 yes 3 387 1 yes 4 192 1 no 5 516 1 no 6 14 1 no Buffers allocated for NR: Buffer Size(twords) Alignment Volatile address 0 88 3 no 0x1 1 1552 3 yes 0x1 2 1032 3 yes 0x1 3 776 3 yes 0x1 4 384 2 no 0x1 5 1032 2 no 0x1 6 32 3 no 0x1 Buffers requested by NR: Buffer Size(twords) Alignment Volatile 0 44 1 no 1 774 1 yes 2 516 1 yes 3 387 1 yes 4 192 1 no 5 516 1 no 6 14 1 no Buffers allocated for NR: Buffer Size(twords) Alignment Volatile address 0 88 3 no 0x1 1 1552 3 yes 0x1 2 1032 3 yes 0x1 3 776 3 yes 0x1 4 384 2 no 0x1 5 1032 2 no 0x1 6 32 3 no 0x1 Buffers requested by NR: Buffer Size(twords) Alignment Volatile 0 44 1 no 1 774 1 yes 2 516 1 yes 3 387 1 yes 4 192 1 no 5 516 1 no 6 14 1 no Buffers allocated for NR: Buffer Size(twords) Alignment Volatile address 0 88 3 no 0x1 1 1552 3 yes 0x1 2 1032 3 yes 0x1 3 776 3 yes 0x1 4 384 2 no 0x1 5 1032 2 no 0x1 6 32 3 no 0x1 MSS required buffers: Buffer Size(twords) Alignment Volatile address 0 122 1 no 0x0 Buffers allocated by SIU for MSS: Buffer Size(twords) Alignment Volatile address 0 220 1 no 0x1 ...Initializing DRC Not enough heap, exiting