diff --git a/packages/ti/drv/spi/soc/SPI_v1.h b/packages/ti/drv/spi/soc/SPI_v1.h
old mode 100644
new mode 100755
index c02128c..30d6d19
--- a/packages/ti/drv/spi/soc/SPI_v1.h
+++ b/packages/ti/drv/spi/soc/SPI_v1.h
@@ -143,6 +143,14 @@ typedef struct SPI_dmaInfo_s {
     void            *rxRingMem;
     /*! UDMA RX completion queue ring memory pointer */
     void            *cqRxRingMem;
+
+    /*! Flag to indicate using TR, instead of HPD */
+    uint32_t         useTR;
+    /*! UDMA TX TR memory pointersm, used when useTR is true */
+    void            *txTrpdMem;
+    /*! UDMA RX TR memory pointers, used when useTR is true */
+    void            *rxTrpdMem;
+
     /*! UDMA TX PD memory pointers */
     void            *txHpdMem;
     /*! UDMA RX PD memory pointers */
@@ -251,7 +259,7 @@ typedef struct SPI_v1_Object_s {
     uint32_t         txTrigLvl;           /* TX FIFO almost empty level */
     uint32_t         rxTrigLvl;           /* RX FIFO almost full level */
 
-    MCSPI_Handle     mcHandle;            /* multi-channel handle of the opened channel 
+    MCSPI_Handle     mcHandle;            /* multi-channel handle of the opened channel
                                              per instance for backward compatibility */
     uint32_t         chOpenedCnt;         /* Opened channel count */
     SPI_Mode         mode;                /* saved SPI master/slave mode for the instance opened */
diff --git a/packages/ti/drv/spi/soc/dma/v2/SPI_dma.c b/packages/ti/drv/spi/soc/dma/v2/SPI_dma.c
index ce8bc05..e133dd1 100755
--- a/packages/ti/drv/spi/soc/dma/v2/SPI_dma.c
+++ b/packages/ti/drv/spi/soc/dma/v2/SPI_dma.c
@@ -72,7 +72,7 @@ int32_t MCSPI_dmaConfig(MCSPI_Handle mcHandle)
     SPI_dmaInfo       *pDmaInfo;
     uint32_t           chNum;
     Udma_DrvHandle     drvHandle;
-    uint32_t           chType;
+    uint32_t           txChType, rxChType;
     Udma_ChPrms        chPrms;
     Udma_ChTxPrms      txPrms;
     Udma_ChRxPrms      rxPrms;
@@ -91,8 +91,8 @@ int32_t MCSPI_dmaConfig(MCSPI_Handle mcHandle)
     chNum      = mcHandle->chnNum;
 
     /* Init TX channel parameters */
-    chType = UDMA_CH_TYPE_PDMA_TX;
-    UdmaChPrms_init(&chPrms, chType);
+    txChType = UDMA_CH_TYPE_PDMA_TX;
+    UdmaChPrms_init(&chPrms, txChType);
     chPrms.peerChNum            = hwAttrs->txDmaEventNumber + chNum;
     chPrms.fqRingPrms.ringMem   = pDmaInfo->txRingMem;
     chPrms.cqRingPrms.ringMem   = pDmaInfo->cqTxRingMem;
@@ -100,13 +100,13 @@ int32_t MCSPI_dmaConfig(MCSPI_Handle mcHandle)
     chPrms.cqRingPrms.elemCnt   = 1;
 
     /* Open TX channel for transmit */
-    retVal = Udma_chOpen(drvHandle, txChHandle, chType, &chPrms);
+    retVal = Udma_chOpen(drvHandle, txChHandle, txChType, &chPrms);
 
     if(UDMA_SOK == retVal)
     {
         /* Init RX channel parameters */
-        chType = UDMA_CH_TYPE_PDMA_RX;
-        UdmaChPrms_init(&chPrms, chType);
+        rxChType = UDMA_CH_TYPE_PDMA_RX;
+        UdmaChPrms_init(&chPrms, rxChType);
         chPrms.peerChNum            = hwAttrs->rxDmaEventNumber + chNum;
         chPrms.fqRingPrms.ringMem   = pDmaInfo->rxRingMem;
         chPrms.cqRingPrms.ringMem   = pDmaInfo->cqRxRingMem;
@@ -114,18 +114,28 @@ int32_t MCSPI_dmaConfig(MCSPI_Handle mcHandle)
         chPrms.cqRingPrms.elemCnt   = 1;
 
         /* Open RX channel for transmit */
-        retVal = Udma_chOpen(drvHandle, rxChHandle, chType, &chPrms);
+        retVal = Udma_chOpen(drvHandle, rxChHandle, rxChType, &chPrms);
     }
 
     if(UDMA_SOK == retVal)
     {
-        UdmaChTxPrms_init(&txPrms, chType);
+        UdmaChTxPrms_init(&txPrms, txChType);
+        if (pDmaInfo->useTR)
+        {
+            /* Channel Type requires to be 10 for TR mode */
+            txPrms.chanType         = 10; /* TISCI_MSG_VALUE_RM_UDMAP_CH_TYPE_3P_DMA_REF */
+        }
         retVal = Udma_chConfigTx(txChHandle, &txPrms);
     }
 
     if(UDMA_SOK == retVal)
     {
-        UdmaChRxPrms_init(&rxPrms, chType);
+        UdmaChRxPrms_init(&rxPrms, rxChType);
+        if (pDmaInfo->useTR)
+        {
+            /* Channel Type requires to be 10 for TR mode */
+            txPrms.chanType         = 10; /* TISCI_MSG_VALUE_RM_UDMAP_CH_TYPE_3P_DMA_REF */
+        }
         retVal = Udma_chConfigRx(rxChHandle, &rxPrms);
     }
 
@@ -170,6 +180,97 @@ int32_t MCSPI_dmaConfig(MCSPI_Handle mcHandle)
     return(status);
 }
 
+static void MCSPI_udmaTrpdInit(Udma_ChHandle  chHandle,
+                               SPI_dmaInfo   *pDmaInfo,
+                               uint8_t       *pTrpdMem,
+                               uint64_t       bufPtr,
+                               uint32_t       elemSize,
+                               uint32_t       length)
+{
+    CSL_UdmapCppi5TRPD *pTrpd = (CSL_UdmapCppi5TRPD *) pTrpdMem;
+    uint32_t descType = (uint32_t)CSL_UDMAP_CPPI5_PD_DESCINFO_DTYPE_VAL_TR;
+    uint32_t cqRingNum = Udma_chGetCqRingNum(chHandle);
+    CSL_UdmapTR1 *pTr = (CSL_UdmapTR1 *)(pTrpdMem + sizeof(CSL_UdmapTR15));
+    uint32_t *pTrResp =
+                (uint32_t *) (pTrpdMem + (sizeof(CSL_UdmapTR15) *
+                                         (2u)));
+
+    /* Setup descriptor */
+    CSL_udmapCppi5SetDescType(pTrpd, descType);
+
+    CSL_udmapCppi5TrSetReload(pTrpd, FALSE, 0U);
+    /* Since each TRPD will always have only one TR */
+    CSL_udmapCppi5SetPktLen(pTrpd, descType, 1U);
+    /* Flow ID and Packet ID */
+    CSL_udmapCppi5SetIds(pTrpd, descType, 0U, (uint32_t)1234);
+    CSL_udmapCppi5SetSrcTag(pTrpd, 0x0044);             /* Not used */
+    CSL_udmapCppi5SetDstTag(pTrpd, 0x0416);             /* Not used */
+    CSL_udmapCppi5TrSetEntryStride(pTrpd,
+        CSL_UDMAP_CPPI5_TRPD_PKTINFO_RECSIZE_VAL_64B);
+    CSL_udmapCppi5SetReturnPolicy(pTrpd,
+        descType,
+        /* Don't care for TR */
+        CSL_UDMAP_CPPI5_PD_PKTINFO2_RETPOLICY_VAL_ENTIRE_PKT,
+        CSL_UDMAP_CPPI5_PD_PKTINFO2_EARLYRET_VAL_NO,
+        CSL_UDMAP_CPPI5_PD_PKTINFO2_RETPUSHPOLICY_VAL_TO_TAIL,
+        cqRingNum);
+
+    /* Initialize TR packet: Start */
+    /* Setup TR */
+    /* Bit fields::
+       Bit No.->Info
+       3:0->Type: 2D transfer
+       7:6->Event Size: Event is only generated with the TR is complete
+       9:8->Trigger0: No Trigger
+       10:11->Trigger0 Type:
+                    The second inner most loop (ICNT1) will be decremented by 1.
+       13:12->Trigger1: No Trigger
+       15:14->Trigger1 Type:
+                    The second inner most loop (ICNT1) will be decremented by 1.
+       23:16->Command ID: The Command ID for the TR
+       31:24->Conf Flags: Configuration Specific Flags
+       */
+    pTr->flags = 0U;
+    pTr->flags   |= CSL_FMK(UDMAP_TR_FLAGS_TYPE,
+                            CSL_UDMAP_TR_FLAGS_TYPE_2D_DATA_MOVE);
+    pTr->flags   |= CSL_FMK(UDMAP_TR_FLAGS_STATIC, FALSE);
+    pTr->flags   |= CSL_FMK(UDMAP_TR_FLAGS_EOL, (uint32_t)1u);
+    pTr->flags   |= CSL_FMK(UDMAP_TR_FLAGS_EVENT_SIZE,
+        CSL_UDMAP_TR_FLAGS_EVENT_SIZE_COMPLETION);
+
+    pTr->flags   |= CSL_FMK(UDMAP_TR_FLAGS_TRIGGER0,
+                            CSL_UDMAP_TR_FLAGS_TRIGGER_NONE);
+    pTr->flags   |= CSL_FMK(UDMAP_TR_FLAGS_TRIGGER0_TYPE,
+                            CSL_UDMAP_TR_FLAGS_TRIGGER_TYPE_ALL);
+    pTr->flags   |= CSL_FMK(UDMAP_TR_FLAGS_TRIGGER1,
+                            CSL_UDMAP_TR_FLAGS_TRIGGER_NONE);
+    pTr->flags   |= CSL_FMK(UDMAP_TR_FLAGS_TRIGGER1_TYPE,
+                                CSL_UDMAP_TR_FLAGS_TRIGGER_TYPE_ALL);
+
+    pTr->flags   |= CSL_FMK(UDMAP_TR_FLAGS_CMD_ID, 0x25);
+    pTr->flags   |= CSL_FMK(UDMAP_TR_FLAGS_SA_INDIRECT, (uint32_t)0U);
+    pTr->flags   |= CSL_FMK(UDMAP_TR_FLAGS_DA_INDIRECT, (uint32_t)0U);
+    pTr->flags   |= CSL_FMK(UDMAP_TR_FLAGS_EOP, (uint32_t)1U);
+
+    pTr->icnt0    = elemSize;
+    pTr->icnt1    = length/elemSize;
+    pTr->dim1     = pTr->icnt0;
+
+    /* Destination address does not needed to be programmed,
+       this will overwritten in Queue */
+    pTr->addr     = (uint64_t) (bufPtr);
+
+    /* Clear TR response memory */
+    *pTrResp = 0xFFFFFFFFU;
+
+    if(MCSPI_dmaIsCacheCoherent() != TRUE)
+    {
+        CacheP_wbInv((void *)pTrpdMem,
+            (int32_t)(sizeof(CSL_UdmapTR15) * 2U) + 4u);
+    }
+
+    return;
+}
 static void MCSPI_udmaHpdInit(Udma_ChHandle  chHandle,
                               uint8_t       *pHpdMem,
                               uint64_t       bufPtr,
@@ -219,8 +320,10 @@ static int32_t MCSPI_dmaTx(MCSPI_Handle   mcHandle,
     SPI_HWAttrs const *hwAttrs;
     SPI_dmaInfo       *pDmaInfo;
     uint32_t           chNum;
+    uint32_t           elemSize;
     Udma_ChPdmaPrms    pdmaPrms;
     uint8_t           *pHpdMem;
+    uint8_t           *pTrpdMem;
     Udma_ChHandle      txChHandle;
 
     /* Get the pointer to the object and hwAttrs */
@@ -262,12 +365,26 @@ static int32_t MCSPI_dmaTx(MCSPI_Handle   mcHandle,
 
     if(UDMA_SOK == retVal)
     {
-        /* Update host packet descriptor */
-        pHpdMem = (uint8_t *) pDmaInfo->txHpdMem;
-        MCSPI_udmaHpdInit(txChHandle, pHpdMem, srcBuf, length);
+        if (pDmaInfo->useTR)
+        {
+            elemSize = (1 << object->chObject[chNum].wordLenShift);
+            /* Update TR descriptor */
+            pTrpdMem = (uint8_t *) pDmaInfo->txTrpdMem;
+            MCSPI_udmaTrpdInit(txChHandle, pDmaInfo, pTrpdMem,
+                srcBuf, elemSize, length);
+
+            /* Submit TRPD to channel */
+            retVal = Udma_ringQueueRaw(Udma_chGetFqRingHandle(txChHandle), (uint64_t) pTrpdMem);
+        }
+        else
+        {
+            /* Update host packet descriptor */
+            pHpdMem = (uint8_t *) pDmaInfo->txHpdMem;
+            MCSPI_udmaHpdInit(txChHandle, pHpdMem, srcBuf, length);
 
-        /* Submit HPD to channel */
-        retVal = Udma_ringQueueRaw(Udma_chGetFqRingHandle(txChHandle), (uint64_t) pHpdMem);
+            /* Submit HPD to channel */
+            retVal = Udma_ringQueueRaw(Udma_chGetFqRingHandle(txChHandle), (uint64_t) pHpdMem);
+        }
     }
 
     return (retVal);
@@ -285,7 +402,9 @@ static int32_t MCSPI_dmaRx(MCSPI_Handle   mcHandle,
     uint32_t           chNum;
     Udma_ChPdmaPrms    pdmaPrms;
     uint8_t           *pHpdMem;
+    uint32_t           elemSize;
     Udma_ChHandle      rxChHandle;
+    uint8_t           *pTrpdMem;
 
     /* Get the pointer to the object and hwAttrs */
     handle   = mcHandle->handle;
@@ -327,12 +446,26 @@ static int32_t MCSPI_dmaRx(MCSPI_Handle   mcHandle,
 
     if(UDMA_SOK == retVal)
     {
-        /* Update host packet descriptor */
-        pHpdMem = (uint8_t *) pDmaInfo->rxHpdMem;
-        MCSPI_udmaHpdInit(rxChHandle, pHpdMem, destBuf, length);
+        if (pDmaInfo->useTR)
+        {
+            elemSize = (1 << object->chObject[chNum].wordLenShift);
+            /* Update TR descriptor */
+            pTrpdMem = (uint8_t *) pDmaInfo->rxTrpdMem;
+            MCSPI_udmaTrpdInit(rxChHandle, pDmaInfo, pTrpdMem,
+                destBuf, elemSize, length);
+
+            /* Submit TRPD to channel */
+            retVal = Udma_ringQueueRaw(Udma_chGetFqRingHandle(rxChHandle), (uint64_t) pTrpdMem);
+        }
+        else
+        {
+            /* Update host packet descriptor */
+            pHpdMem = (uint8_t *) pDmaInfo->rxHpdMem;
+            MCSPI_udmaHpdInit(rxChHandle, pHpdMem, destBuf, length);
 
-        /* Submit HPD to channel */
-        retVal = Udma_ringQueueRaw(Udma_chGetFqRingHandle(rxChHandle), (uint64_t) pHpdMem);
+            /* Submit HPD to channel */
+            retVal = Udma_ringQueueRaw(Udma_chGetFqRingHandle(rxChHandle), (uint64_t) pHpdMem);
+        }
     }
 
     return (retVal);
