# Size of L2 SRAM Memory in KB which can be used by TIDL, Recommended value is
# 448KB considering that 64KB of L2 shall be configured as cache. TIDL test bench
# configures L2 cache as 64 KB, so any value higher than 448 KB would require
# user to change the L2 cache setting in TIDL test bench
L2MEMSIZE_KB           = 448
# Size of L3 (MSMC) SRAM Memory in KB which can be used by TIDL
MSMCSIZE_KB            = 2944
#ID for a Device, TDA4VMID = 0, TIDL_TDA4AEP = 1, TIDL_TDA4AHP = 1,  TIDL_TDA4AM = 2, TIDL_TDA4AMPlus = 3
DEVICE_NAME            = 1
ENABLE_PERSIT_WT_ALLOC = 1
DDRFREQ_MHZ            = 4266
FILENAME_NET     = /home/user/data/sdk11/ti-processor-sdk-rtos-j784s4-evm-11_00_00_06/c7x-mma-tidl/ti_dl/test/testvecs/config/tidl_models/ObjectDetectionYolov3_14class/yolo_ti_full_fmt1405.bin
FILEFORMAT_NET     = -1
DEVICE_NAME     = 257
OUTPUT_DIR     = /home/user/data/sdk11/ti-processor-sdk-rtos-j784s4-evm-11_00_00_06/c7x-mma-tidl/ti_dl/test/testvecs/config/tidl_models/ObjectDetectionYolov3_14class/yolo_ti_full_fmt1405.bin
