------Layer #(Type) [Exec ID , Data ID] --[Ni x inW x inH] => [No x outW x outH] [Ni/G] [dataflowType] [preFetch, preFetchAlign, firstTransferRemainder, procSize, inPlaneSize] [dmaFreq] [dmaFreqWt] [kernelFreq] [In Data Ids] -----
------  0(TIDL_ConstDataLayer) [0, 0] --[80 x 2 x  80] => [80 x 2 x  80] *** [80] ***[FRAME] ***[0, 0, 0, 160, 160]**** [1], [0],[1] -[]---
  IN:DDR_PERSIST, DMA,     a0(   160),     a0(   160),   50(   80),   9600(  38400),   0,  3aca880 ||||  L2, DMA,     a0(   160),     a0(   160),    2(    2),    180(    384),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||DDR_PERSIST, CPU,     a0(   160),     a0(   160),   50(   80),   9600(  38400),   0,  3aca880 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  1(TIDL_ConstDataLayer) [1, 1] --[80 x 2 x  80] => [40 x 2 x  40] *** [80] ***[FRAME] ***[0, 0, 0, 160, 160]**** [1], [0],[1] -[]---
  IN:DDR_PERSIST, DMA,     a0(   160),     a0(   160),   28(   40),   2580(   9600),   0,  3ad3e80 ||||  L2, DMA,     a0(   160),     a0(   160),    2(    2),    180(    384),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||DDR_PERSIST, CPU,     50(    80),     50(    80),   28(   40),   2580(   9600),   0,  3ad3e80 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  2(TIDL_ConstDataLayer) [2, 2] --[80 x 2 x  80] => [20 x 2 x  20] *** [80] ***[FRAME] ***[0, 0, 0, 160, 160]**** [1], [0],[1] -[]---
  IN:DDR_PERSIST, DMA,     a0(   160),     a0(   160),   14(   20),    980(   2432),   0,  3ad6400 ||||  L2, DMA,     a0(   160),     a0(   160),    2(    2),    180(    384),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||DDR_PERSIST, CPU,     28(    40),     28(    40),   14(   20),    980(   2432),   0,  3ad6400 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  3(TIDL_ConstDataLayer) [3, 3] --[80 x 2 x  80] => [80 x 2 x  80] *** [80] ***[FRAME] ***[0, 0, 0, 160, 160]**** [1], [0],[1] -[]---
  IN:DDR_PERSIST, DMA,     a0(   160),     a0(   160),   50(   80),   9600(  38400),   0,  3ad6d80 ||||  L2, DMA,     a0(   160),     a0(   160),    2(    2),    180(    384),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||DDR_PERSIST, CPU,     a0(   160),     a0(   160),   50(   80),   9600(  38400),   0,  3ad6d80 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  4(TIDL_ConstDataLayer) [4, 4] --[80 x 2 x  80] => [40 x 2 x  40] *** [80] ***[FRAME] ***[0, 0, 0, 160, 160]**** [1], [0],[1] -[]---
  IN:DDR_PERSIST, DMA,     a0(   160),     a0(   160),   28(   40),   2580(   9600),   0,  3ae0380 ||||  L2, DMA,     a0(   160),     a0(   160),    2(    2),    180(    384),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||DDR_PERSIST, CPU,     50(    80),     50(    80),   28(   40),   2580(   9600),   0,  3ae0380 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  5(TIDL_ConstDataLayer) [5, 5] --[80 x 2 x  80] => [20 x 2 x  20] *** [80] ***[FRAME] ***[0, 0, 0, 160, 160]**** [1], [0],[1] -[]---
  IN:DDR_PERSIST, DMA,     a0(   160),     a0(   160),   14(   20),    980(   2432),   0,  3ae2900 ||||  L2, DMA,     a0(   160),     a0(   160),    2(    2),    180(    384),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||DDR_PERSIST, CPU,     28(    40),     28(    40),   14(   20),    980(   2432),   0,  3ae2900 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  7(TIDL_ConvolutionLayer) [7, 7] --[3 x 640 x  640] => [32 x 640 x  640] *** [3] ***[ROW_L] ***[1282, 1344, 641, 8128, 409600]**** [51], [1],[51] -[6 ]---
  IN: DDR, DMA,  64000(409600),  64000(409600),    3(    3), 12c400(1229824),   0,        0 ||||  L2, DMA,   44c0( 17600),   44c0( 17600),    3(    3),  6e280( 451200),   0,        0 
 OUT:MSMC, CPU,   1fc0(  8128),   1fc0(  8128),   20(   32),  7f000( 520192),   0,        0 |||| DDR, DMA,  67300(422656),  64000(409600),   20(   32), ce6400(13526016),   0,   12c400 
  WT:DDR_PERSIST, DMA,     1b(    27),     1b(    27),   20(   32),    400(   1024),   0,        0 ||||  L2, DMA,     1b(    27),     1b(    27),   20(   32),    400(   1024),   0,    6e280 
 STG:MSMC, DMA_ONCE,     1b(    27),     1b(    27),   20(   32),    400(   1024),   0,   2cf880 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  8(TIDL_BatchNormLayer) [8, 8] --[32 x 640 x  640] => [32 x 640 x  640] *** [32] ***[ COL] ***[0, 0, 0, 204800, 409600]**** [64], [0],[64] -[7 ]---
  IN: DDR, DMA,  67300(422656),  64000(409600),   20(   32), ce6400(13526016),   0,   12c400 ||||  L2, DMA,  64000(409600),  64000(409600),    1(    1),  64000( 409600),   0,        0 
 OUT:MSMC, CPU,  32040(204864),  32000(204800),    2(    2),  64080( 409728),   0,        0 |||| DDR, DMA,  960c0(614592),  64000(409600),   20(   32), 12c1c00(19667968),   0,   e12800 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  9(TIDL_EltWiseLayer) [9, 9] --[64 x 640 x  640] => [32 x 640 x  640] *** [64] ***[ COL] ***[0, 0, 0, 102400, 409600]**** [128], [0],[128] -[7 8 ]---
  IN: DDR, DMA,  67300(422656),  64000(409600),   20(   32), ce6400(13526016),   0,   12c400 ||||  L2, DMA,  19000(102400),  19000(102400),    2(    2),  64000( 409600),   0,        0 
 OUT:MSMC, CPU,  19040(102464),  19000(102400),    2(    2),  32080( 204928),   0,        0 |||| DDR, DMA,  7d140(512320),  64000(409600),   20(   32), fa2c00(16395264),   0,  20d4400 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  10(TIDL_ConvolutionLayer) [10, 10] --[32 x 640 x  640] => [64 x 320 x  320] *** [32] ***[ROW_C] ***[640, 640, 0, 2560, 409600]**** [160], [1],[160] -[9 ]---
  IN: DDR, DMA,  7d140(512320),  64000(409600),   20(   32), fa2c00(16395264),   0,  20d4400 ||||  L2, DMA,   2000(  8192),   2000(  8192),   20(   32),  40080( 262272),   0,        0 
 OUT:MSMC, CPU,    3c0(   960),    280(   640),   40(   64),  1e000( 122880),   0,        0 |||| DDR, DMA,  19500(103680),  19001(102401),   40(   64), 654400(6636544),   0,   76c800 
  WT:DDR_PERSIST, DMA,    120(   288),    120(   288),   40(   64),   4900(  18688),   0,      400 ||||  L2, DMA,    140(   320),    120(   288),   40(   64),   5100(  20736),   0,    40080 
 STG:MSMC, DMA_ONCE,    140(   320),    120(   288),   40(   64),   5100(  20736),   0,   2c9f00 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  11(TIDL_BatchNormLayer) [11, 11] --[64 x 320 x  320] => [64 x 320 x  320] *** [64] ***[ COL] ***[0, 0, 0, 102400, 102400]**** [32], [0],[32] -[10 ]---
  IN: DDR, DMA,  19500(103680),  19001(102401),   40(   64), 654400(6636544),   0,   76c800 ||||  L2, DMA,  19140(102720),  19140(102720),    4(    4),  64500( 410880),   0,        0 
 OUT:MSMC, CPU,  19040(102464),  19000(102400),    4(    4),  64100( 409856),   0,        0 |||| DDR, DMA,  19000(102400),  19000(102400),   40(   64), 640400(6554624),   0,   dc0c00 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  12(TIDL_EltWiseLayer) [12, 12] --[128 x 320 x  320] => [64 x 320 x  320] *** [128] ***[ COL] ***[0, 0, 0, 102400, 102400]**** [64], [0],[64] -[10 11 ]---
  IN: DDR, DMA,  19500(103680),  19001(102401),   40(   64), 654400(6636544),   0,   76c800 ||||  L2, DMA,  19140(102720),  19140(102720),    2(    2),  64500( 410880),   0,        0 
 OUT:MSMC, CPU,  19040(102464),  19000(102400),    2(    2),  32080( 204928),   0,        0 |||| DDR, DMA,  19000(102400),  19000(102400),   40(   64), 640400(6554624),   0,   12c400 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  13(TIDL_ConvolutionLayer) [13, 13] --[64 x 320 x  320] => [32 x 320 x  320] *** [64] ***[ROW_L] ***[0, 0, 0, 2688, 102400]**** [39], [1],[39] -[12 ]---
  IN: DDR, DMA,  19000(102400),  19000(102400),   40(   64), 640400(6554624),   0,   12c400 ||||  L2, DMA,   1540(  5440),   1540(  5440),   40(   64),  6d500( 447744),   0,        0 
 OUT:MSMC, CPU,    ac0(  2752),    a80(  2688),   20(   32),  2b000( 176128),   0,        0 |||| DDR, DMA,  1a340(107328),  19000(102400),   20(   32), 346c00(3435520),   0,   76c800 
  WT:DDR_PERSIST, DMA,     40(    64),     40(    64),   20(   32),    880(   2176),   0,     4d00 ||||  L2, DMA,     40(    64),     40(    64),   20(   32),    880(   2176),   0,    6d500 
 STG:MSMC, DMA_ONCE,     40(    64),     40(    64),   20(   32),    880(   2176),   0,   2cf000 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  14(TIDL_BatchNormLayer) [14, 14] --[32 x 320 x  320] => [32 x 320 x  320] *** [32] ***[ COL] ***[0, 0, 0, 102400, 102400]**** [16], [0],[16] -[13 ]---
  IN: DDR, DMA,  1a340(107328),  19000(102400),   20(   32), 346c00(3435520),   0,   76c800 ||||  L2, DMA,  19140(102720),  19140(102720),    4(    4),  64500( 410880),   0,        0 
 OUT:MSMC, CPU,  19040(102464),  19000(102400),    4(    4),  64100( 409856),   0,        0 |||| DDR, DMA,  19000(102400),  19000(102400),   20(   32), 320400(3277824),   0,   ab3400 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  15(TIDL_EltWiseLayer) [15, 15] --[64 x 320 x  320] => [32 x 320 x  320] *** [64] ***[ COL] ***[0, 0, 0, 102400, 102400]**** [32], [0],[32] -[13 14 ]---
  IN: DDR, DMA,  1a340(107328),  19000(102400),   20(   32), 346c00(3435520),   0,   76c800 ||||  L2, DMA,  19140(102720),  19140(102720),    2(    2),  64500( 410880),   0,        0 
 OUT:MSMC, CPU,  19040(102464),  19000(102400),    2(    2),  32080( 204928),   0,        0 |||| DDR, DMA,  19000(102400),  19000(102400),   20(   32), 320400(3277824),   0,   e11c00 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  16(TIDL_ConvolutionLayer) [16, 16] --[32 x 320 x  320] => [64 x 320 x  320] *** [32] ***[ROW_L] ***[642, 704, 321, 4032, 102400]**** [26], [1],[26] -[15 ]---
  IN: DDR, DMA,  19000(102400),  19000(102400),   20(   32), 320400(3277824),   0,   e11c00 ||||  L2, DMA,   2240(  8768),   2240(  8768),   20(   32),  5c280( 377472),   0,        0 
 OUT:MSMC, CPU,    fc0(  4032),    fc0(  4032),   40(   64),  7e000( 516096),   0,        0 |||| DDR, DMA,  1a940(108864),  19000(102400),   40(   64), 6a5400(6968320),   0,   76c800 
  WT:DDR_PERSIST, DMA,    120(   288),    120(   288),   40(   64),   4900(  18688),   0,     5580 ||||  L2, DMA,    140(   320),    120(   288),   40(   64),   5100(  20736),   0,    5c280 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  17(TIDL_BatchNormLayer) [17, 17] --[64 x 320 x  320] => [64 x 320 x  320] *** [64] ***[ COL] ***[0, 0, 0, 102400, 102400]**** [32], [0],[32] -[16 ]---
  IN: DDR, DMA,  1a940(108864),  19000(102400),   40(   64), 6a5400(6968320),   0,   76c800 ||||  L2, DMA,  19140(102720),  19140(102720),    4(    4),  64500( 410880),   0,        0 
 OUT:MSMC, CPU,  19040(102464),  19000(102400),    4(    4),  64100( 409856),   0,        0 |||| DDR, DMA,  19000(102400),  19000(102400),   40(   64), 640400(6554624),   0,   e11c00 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  18(TIDL_EltWiseLayer) [18, 18] --[128 x 320 x  320] => [64 x 320 x  320] *** [128] ***[ COL] ***[0, 0, 0, 102400, 102400]**** [64], [0],[64] -[16 17 ]---
  IN: DDR, DMA,  1a940(108864),  19000(102400),   40(   64), 6a5400(6968320),   0,   76c800 ||||  L2, DMA,  19140(102720),  19140(102720),    2(    2),  64500( 410880),   0,        0 
 OUT:MSMC, CPU,  19040(102464),  19000(102400),    2(    2),  32080( 204928),   0,        0 |||| DDR, DMA,  19000(102400),  19000(102400),   40(   64), 640400(6554624),   0,  1452000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  19(TIDL_EltWiseLayer) [19, 19] --[128 x 320 x  320] => [64 x 320 x  320] *** [128] ***[ COL] ***[0, 0, 0, 102400, 102400]**** [64], [0],[64] -[12 18 ]---
  IN: DDR, DMA,  19000(102400),  19000(102400),   40(   64), 640400(6554624),   0,   12c400 ||||  L2, DMA,  19140(102720),  19140(102720),    2(    2),  64500( 410880),   0,        0 
 OUT:MSMC, CPU,  19040(102464),  19000(102400),    2(    2),  32080( 204928),   0,        0 |||| DDR, DMA,  19000(102400),  19000(102400),   40(   64), 640400(6554624),   0,   76c800 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  20(TIDL_ConvolutionLayer) [20, 20] --[64 x 320 x  320] => [128 x 160 x  160] *** [64] ***[ROW_L] ***[320, 320, 0, 1920, 102400]**** [54], [1],[54] -[19 ]---
  IN: DDR, DMA,  19000(102400),  19000(102400),   40(   64), 640400(6554624),   0,   76c800 ||||  L2, DMA,   1040(  4160),   1040(  4160),   40(   64),  59680( 366208),   0,        0 
 OUT:MSMC, CPU,    240(   576),    1e0(   480),   80(  128),  24000( 147456),   0,        0 |||| DDR, DMA,   6780( 26496),   6401( 25601),   80(  128), 33c400(3392512),   0,   dacc00 
  WT:DDR_PERSIST, DMA,    240(   576),    240(   576),   80(  128),  12200(  74240),   0,     9e80 ||||  L2, DMA,    240(   576),    240(   576),   80(  128),  12200(  74240),   0,    59680 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  21(TIDL_BatchNormLayer) [21, 21] --[128 x 160 x  160] => [128 x 160 x  160] *** [128] ***[ COL] ***[0, 0, 0, 25600, 25600]**** [16], [0],[16] -[20 ]---
  IN: DDR, DMA,   6780( 26496),   6401( 25601),   80(  128), 33c400(3392512),   0,   dacc00 ||||  L2, DMA,   64a0( 25760),   64a0( 25760),   10(   16),  64a00( 412160),   0,        0 
 OUT:MSMC, CPU,   6440( 25664),   6400( 25600),   10(   16),  64400( 410624),   0,        0 |||| DDR, DMA,   6400( 25600),   6400( 25600),   80(  128), 320400(3277824),   0,   44c800 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  22(TIDL_EltWiseLayer) [22, 22] --[256 x 160 x  160] => [128 x 160 x  160] *** [256] ***[ COL] ***[0, 0, 0, 25600, 25600]**** [32], [0],[32] -[20 21 ]---
  IN: DDR, DMA,   6780( 26496),   6401( 25601),   80(  128), 33c400(3392512),   0,   dacc00 ||||  L2, DMA,   64a0( 25760),   64a0( 25760),    8(    8),  64a00( 412160),   0,        0 
 OUT:MSMC, CPU,   6440( 25664),   6400( 25600),    8(    8),  32200( 205312),   0,        0 |||| DDR, DMA,   6400( 25600),   6400( 25600),   80(  128), 320400(3277824),   0,   12c400 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  23(TIDL_ConvolutionLayer) [23, 23] --[128 x 160 x  160] => [64 x 160 x  160] *** [128] ***[ROW_L] ***[0, 0, 0, 1600, 25600]**** [16], [1],[16] -[22 ]---
  IN: DDR, DMA,   6400( 25600),   6400( 25600),   80(  128), 320400(3277824),   0,   12c400 ||||  L2, DMA,    cc0(  3264),    cc0(  3264),   80(  128),  6b800( 440320),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   6440( 25664),   6400( 25600),   40(   64), 191000(1642496),   0,        0 
  WT:DDR_PERSIST, DMA,     80(   128),     80(   128),   40(   64),   2100(   8448),   0,    1c080 ||||  L2, DMA,     c0(   192),     80(   128),   40(   64),   3100(  12544),   0,    6b800 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  24(TIDL_BatchNormLayer) [24, 24] --[64 x 160 x  160] => [64 x 160 x  160] *** [64] ***[ COL] ***[0, 0, 0, 25600, 25600]**** [8], [0],[8] -[23 ]---
  IN:MSMC, DMA,   6440( 25664),   6400( 25600),   40(   64), 191000(1642496),   0,        0 ||||  L2, DMA,   64a0( 25760),   64a0( 25760),   10(   16),  64a00( 412160),   0,        0 
 OUT:MSMC, CPU,   6440( 25664),   6400( 25600),   10(   16),  64400( 410624),   0,   191000 |||| DDR, DMA,   6400( 25600),   6400( 25600),   40(   64), 190400(1639424),   0,   44c800 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  25(TIDL_EltWiseLayer) [25, 25] --[128 x 160 x  160] => [64 x 160 x  160] *** [128] ***[ COL] ***[0, 0, 0, 25600, 25600]**** [16], [0],[16] -[23 24 ]---
  IN:MSMC, DMA,   6440( 25664),   6400( 25600),   40(   64), 191000(1642496),   0,        0 ||||  L2, DMA,   64a0( 25760),   64a0( 25760),    8(    8),  64a00( 412160),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   6440( 25664),   6400( 25600),   40(   64), 191000(1642496),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  26(TIDL_ConvolutionLayer) [26, 26] --[64 x 160 x  160] => [128 x 160 x  160] *** [64] ***[ROW_L] ***[322, 384, 161, 1984, 25600]**** [13], [1],[13] -[25 ]---
  IN:MSMC, DMA,   6440( 25664),   6400( 25600),   40(   64), 191000(1642496),   0,        0 ||||  L2, DMA,   1140(  4416),   1140(  4416),   40(   64),  4a580( 304512),   0,        0 
 OUT:MSMC, CPU,    7c0(  1984),    7c0(  1984),   80(  128),  7c000( 507904),   0,   191000 |||| DDR, DMA,   6c80( 27776),   6400( 25600),   80(  128), 364400(3556352),   0,   44c800 
  WT:DDR_PERSIST, DMA,    240(   576),    240(   576),   80(  128),  12200(  74240),   0,    1e180 ||||  L2, DMA,    240(   576),    240(   576),   80(  128),  12200(  74240),   0,    4a580 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  27(TIDL_BatchNormLayer) [27, 27] --[128 x 160 x  160] => [128 x 160 x  160] *** [128] ***[ COL] ***[0, 0, 0, 25600, 25600]**** [16], [0],[16] -[26 ]---
  IN: DDR, DMA,   6c80( 27776),   6400( 25600),   80(  128), 364400(3556352),   0,   44c800 ||||  L2, DMA,   64a0( 25760),   64a0( 25760),   10(   16),  64a00( 412160),   0,        0 
 OUT:MSMC, CPU,   6440( 25664),   6400( 25600),   10(   16),  64400( 410624),   0,        0 |||| DDR, DMA,   6400( 25600),   6400( 25600),   80(  128), 320400(3277824),   0,   7b0c00 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  28(TIDL_EltWiseLayer) [28, 28] --[256 x 160 x  160] => [128 x 160 x  160] *** [256] ***[ COL] ***[0, 0, 0, 25600, 25600]**** [32], [0],[32] -[26 27 ]---
  IN: DDR, DMA,   6c80( 27776),   6400( 25600),   80(  128), 364400(3556352),   0,   44c800 ||||  L2, DMA,   64a0( 25760),   64a0( 25760),    8(    8),  64a00( 412160),   0,        0 
 OUT:MSMC, CPU,   6440( 25664),   6400( 25600),    8(    8),  32200( 205312),   0,        0 |||| DDR, DMA,   6400( 25600),   6400( 25600),   80(  128), 320400(3277824),   0,   ad1000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  29(TIDL_EltWiseLayer) [29, 29] --[256 x 160 x  160] => [128 x 160 x  160] *** [256] ***[ COL] ***[0, 0, 0, 25600, 25600]**** [32], [0],[32] -[22 28 ]---
  IN: DDR, DMA,   6400( 25600),   6400( 25600),   80(  128), 320400(3277824),   0,   12c400 ||||  L2, DMA,   64a0( 25760),   64a0( 25760),    8(    8),  64a00( 412160),   0,        0 
 OUT:MSMC, CPU,   6440( 25664),   6400( 25600),    8(    8),  32200( 205312),   0,        0 |||| DDR, DMA,   6400( 25600),   6400( 25600),   80(  128), 320400(3277824),   0,   44c800 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  30(TIDL_ConvolutionLayer) [30, 30] --[128 x 160 x  160] => [64 x 160 x  160] *** [128] ***[ROW_L] ***[0, 0, 0, 1600, 25600]**** [16], [1],[16] -[29 ]---
  IN: DDR, DMA,   6400( 25600),   6400( 25600),   80(  128), 320400(3277824),   0,   44c800 ||||  L2, DMA,    cc0(  3264),    cc0(  3264),   80(  128),  6b800( 440320),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   6440( 25664),   6400( 25600),   40(   64), 191000(1642496),   0,        0 
  WT:DDR_PERSIST, DMA,     80(   128),     80(   128),   40(   64),   2100(   8448),   0,    30380 ||||  L2, DMA,     c0(   192),     80(   128),   40(   64),   3100(  12544),   0,    6b800 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  31(TIDL_BatchNormLayer) [31, 31] --[64 x 160 x  160] => [64 x 160 x  160] *** [64] ***[ COL] ***[0, 0, 0, 25600, 25600]**** [8], [0],[8] -[30 ]---
  IN:MSMC, DMA,   6440( 25664),   6400( 25600),   40(   64), 191000(1642496),   0,        0 ||||  L2, DMA,   64a0( 25760),   64a0( 25760),   10(   16),  64a00( 412160),   0,        0 
 OUT:MSMC, CPU,   6440( 25664),   6400( 25600),   10(   16),  64400( 410624),   0,   191000 |||| DDR, DMA,   6400( 25600),   6400( 25600),   40(   64), 190400(1639424),   0,   12c400 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  32(TIDL_EltWiseLayer) [32, 32] --[128 x 160 x  160] => [64 x 160 x  160] *** [128] ***[ COL] ***[0, 0, 0, 25600, 25600]**** [16], [0],[16] -[30 31 ]---
  IN:MSMC, DMA,   6440( 25664),   6400( 25600),   40(   64), 191000(1642496),   0,        0 ||||  L2, DMA,   64a0( 25760),   64a0( 25760),    8(    8),  64a00( 412160),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   6440( 25664),   6400( 25600),   40(   64), 191000(1642496),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  33(TIDL_ConvolutionLayer) [33, 33] --[64 x 160 x  160] => [128 x 160 x  160] *** [64] ***[ROW_L] ***[322, 384, 161, 1984, 25600]**** [13], [1],[13] -[32 ]---
  IN:MSMC, DMA,   6440( 25664),   6400( 25600),   40(   64), 191000(1642496),   0,        0 ||||  L2, DMA,   1140(  4416),   1140(  4416),   40(   64),  4a580( 304512),   0,        0 
 OUT:MSMC, CPU,    7c0(  1984),    7c0(  1984),   80(  128),  7c000( 507904),   0,   191000 |||| DDR, DMA,   6c80( 27776),   6400( 25600),   80(  128), 364400(3556352),   0,   76cc00 
  WT:DDR_PERSIST, DMA,    240(   576),    240(   576),   80(  128),  12200(  74240),   0,    32480 ||||  L2, DMA,    240(   576),    240(   576),   80(  128),  12200(  74240),   0,    4a580 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  34(TIDL_BatchNormLayer) [34, 34] --[128 x 160 x  160] => [128 x 160 x  160] *** [128] ***[ COL] ***[0, 0, 0, 25600, 25600]**** [16], [0],[16] -[33 ]---
  IN: DDR, DMA,   6c80( 27776),   6400( 25600),   80(  128), 364400(3556352),   0,   76cc00 ||||  L2, DMA,   64a0( 25760),   64a0( 25760),   10(   16),  64a00( 412160),   0,        0 
 OUT:MSMC, CPU,   6440( 25664),   6400( 25600),   10(   16),  64400( 410624),   0,        0 |||| DDR, DMA,   6400( 25600),   6400( 25600),   80(  128), 320400(3277824),   0,   12c400 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  35(TIDL_EltWiseLayer) [35, 35] --[256 x 160 x  160] => [128 x 160 x  160] *** [256] ***[ COL] ***[0, 0, 0, 25600, 25600]**** [32], [0],[32] -[33 34 ]---
  IN: DDR, DMA,   6c80( 27776),   6400( 25600),   80(  128), 364400(3556352),   0,   76cc00 ||||  L2, DMA,   64a0( 25760),   64a0( 25760),    8(    8),  64a00( 412160),   0,        0 
 OUT:MSMC, CPU,   6440( 25664),   6400( 25600),    8(    8),  32200( 205312),   0,        0 |||| DDR, DMA,   6400( 25600),   6400( 25600),   80(  128), 320400(3277824),   0,   ad1000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  36(TIDL_EltWiseLayer) [36, 36] --[256 x 160 x  160] => [128 x 160 x  160] *** [256] ***[ COL] ***[0, 0, 0, 25600, 25600]**** [32], [0],[32] -[29 35 ]---
  IN: DDR, DMA,   6400( 25600),   6400( 25600),   80(  128), 320400(3277824),   0,   44c800 ||||  L2, DMA,   64a0( 25760),   64a0( 25760),    8(    8),  64a00( 412160),   0,        0 
 OUT:MSMC, CPU,   6440( 25664),   6400( 25600),    8(    8),  32200( 205312),   0,        0 |||| DDR, DMA,   6400( 25600),   6400( 25600),   80(  128), 320400(3277824),   0,   12c400 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  37(TIDL_ConvolutionLayer) [37, 37] --[128 x 160 x  160] => [256 x 80 x  80] *** [128] ***[ROW_L] ***[160, 160, 0, 320, 25600]**** [80], [1],[80] -[36 ]---
  IN: DDR, DMA,   6400( 25600),   6400( 25600),   80(  128), 320400(3277824),   0,   12c400 ||||  L2, DMA,    340(   832),    340(   832),   80(  128),  20200( 131584),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1940(  6464),   1901(  6401),  100(  256), 194000(1654784),   0,        0 
  WT:DDR_PERSIST, DMA,    480(  1152),    480(  1152),  100(  256),  48400( 295936),   0,    44680 ||||  L2, DMA,    4c0(  1216),    480(  1152),  100(  256),  4c400( 312320),   0,    20200 
 STG:MSMC, DMA_ONCE,    4c0(  1216),    480(  1152),  100(  256),  4c400( 312320),   0,   27db00 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  38(TIDL_BatchNormLayer) [38, 38] --[256 x 80 x  80] => [256 x 80 x  80] *** [256] ***[ COL] ***[0, 0, 0, 6400, 6400]**** [8], [0],[8] -[37 ]---
  IN:MSMC, DMA,   1940(  6464),   1901(  6401),  100(  256), 194000(1654784),   0,        0 ||||  L2, DMA,   1950(  6480),   1950(  6480),   40(   64),  65400( 414720),   0,        0 
 OUT:MSMC, CPU,   1940(  6464),   1900(  6400),   40(   64),  65000( 413696),   0,   194000 |||| DDR, DMA,   1900(  6400),   1900(  6400),  100(  256), 190400(1639424),   0,   12c400 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  39(TIDL_EltWiseLayer) [39, 39] --[512 x 80 x  80] => [256 x 80 x  80] *** [512] ***[ COL] ***[0, 0, 0, 6400, 6400]**** [16], [0],[16] -[37 38 ]---
  IN:MSMC, DMA,   1940(  6464),   1901(  6401),  100(  256), 194000(1654784),   0,        0 ||||  L2, DMA,   1950(  6480),   1950(  6480),   20(   32),  65400( 414720),   0,        0 
 OUT:MSMC, CPU,   1940(  6464),   1900(  6400),   20(   32),  32800( 206848),   0,   194000 |||| DDR, DMA,   1900(  6400),   1900(  6400),  100(  256), 190400(1639424),   0,   2bc800 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  40(TIDL_ConvolutionLayer) [40, 40] --[256 x 80 x  80] => [128 x 80 x  80] *** [256] ***[ROW_L] ***[0, 0, 0, 768, 6400]**** [9], [1],[9] -[39 ]---
  IN: DDR, DMA,   1900(  6400),   1900(  6400),  100(  256), 190400(1639424),   0,   2bc800 ||||  L2, DMA,    640(  1600),    640(  1600),  100(  256),  65580( 415104),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1940(  6464),   1900(  6400),   80(  128),  ca000( 827392),   0,        0 
  WT:DDR_PERSIST, DMA,    100(   256),    100(   256),   80(  128),   8200(  33280),   0,    8ca80 ||||  L2, DMA,    140(   320),    100(   256),   80(  128),   a200(  41472),   0,    65580 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  41(TIDL_BatchNormLayer) [41, 41] --[128 x 80 x  80] => [128 x 80 x  80] *** [128] ***[ COL] ***[0, 0, 0, 6400, 6400]**** [4], [0],[4] -[40 ]---
  IN:MSMC, DMA,   1940(  6464),   1900(  6400),   80(  128),  ca000( 827392),   0,        0 ||||  L2, DMA,   1950(  6480),   1950(  6480),   40(   64),  65400( 414720),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1940(  6464),   1900(  6400),   80(  128),  ca000( 827392),   0,    ca000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  42(TIDL_EltWiseLayer) [42, 42] --[256 x 80 x  80] => [128 x 80 x  80] *** [256] ***[ COL] ***[0, 0, 0, 6400, 6400]**** [8], [0],[8] -[40 41 ]---
  IN:MSMC, DMA,   1940(  6464),   1900(  6400),   80(  128),  ca000( 827392),   0,        0 ||||  L2, DMA,   1950(  6480),   1950(  6480),   20(   32),  65400( 414720),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1940(  6464),   1900(  6400),   80(  128),  ca000( 827392),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  43(TIDL_ConvolutionLayer) [43, 43] --[128 x 80 x  80] => [256 x 80 x  80] *** [128] ***[ROW_L] ***[162, 192, 81, 384, 6400]**** [17], [1],[17] -[42 ]---
  IN:MSMC, DMA,   1940(  6464),   1900(  6400),   80(  128),  ca000( 827392),   0,        0 ||||  L2, DMA,    3c0(   960),    3c0(   960),   80(  128),  1f700( 128768),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1940(  6464),   1900(  6400),  100(  256), 194000(1654784),   0,    ca000 
  WT:DDR_PERSIST, DMA,    480(  1152),    480(  1152),  100(  256),  48400( 295936),   0,    94c80 ||||  L2, DMA,    4c0(  1216),    480(  1152),  100(  256),  4c400( 312320),   0,    1f700 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  44(TIDL_BatchNormLayer) [44, 44] --[256 x 80 x  80] => [256 x 80 x  80] *** [256] ***[ COL] ***[0, 0, 0, 6400, 6400]**** [8], [0],[8] -[43 ]---
  IN:MSMC, DMA,   1940(  6464),   1900(  6400),  100(  256), 194000(1654784),   0,    ca000 ||||  L2, DMA,   1950(  6480),   1950(  6480),   40(   64),  65400( 414720),   0,        0 
 OUT:MSMC, CPU,   1940(  6464),   1900(  6400),   40(   64),  65000( 413696),   0,        0 |||| DDR, DMA,   1900(  6400),   1900(  6400),  100(  256), 190400(1639424),   0,   12c400 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  45(TIDL_EltWiseLayer) [45, 45] --[512 x 80 x  80] => [256 x 80 x  80] *** [512] ***[ COL] ***[0, 0, 0, 6400, 6400]**** [16], [0],[16] -[43 44 ]---
  IN:MSMC, DMA,   1940(  6464),   1900(  6400),  100(  256), 194000(1654784),   0,    ca000 ||||  L2, DMA,   1950(  6480),   1950(  6480),   20(   32),  65400( 414720),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1940(  6464),   1900(  6400),  100(  256), 194000(1654784),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  46(TIDL_EltWiseLayer) [46, 46] --[512 x 80 x  80] => [256 x 80 x  80] *** [512] ***[ COL] ***[0, 0, 0, 6400, 6400]**** [16], [0],[16] -[39 45 ]---
  IN: DDR, DMA,   1900(  6400),   1900(  6400),  100(  256), 190400(1639424),   0,   2bc800 ||||  L2, DMA,   1950(  6480),   1950(  6480),   20(   32),  65400( 414720),   0,        0 
 OUT:MSMC, CPU,   1940(  6464),   1900(  6400),   20(   32),  32800( 206848),   0,   194000 |||| DDR, DMA,   1900(  6400),   1900(  6400),  100(  256), 190400(1639424),   0,   12c400 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  47(TIDL_ConvolutionLayer) [47, 47] --[256 x 80 x  80] => [128 x 80 x  80] *** [256] ***[ROW_L] ***[0, 0, 0, 768, 6400]**** [9], [1],[9] -[46 ]---
  IN: DDR, DMA,   1900(  6400),   1900(  6400),  100(  256), 190400(1639424),   0,   12c400 ||||  L2, DMA,    640(  1600),    640(  1600),  100(  256),  65580( 415104),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1940(  6464),   1900(  6400),   80(  128),  ca000( 827392),   0,        0 
  WT:DDR_PERSIST, DMA,    100(   256),    100(   256),   80(  128),   8200(  33280),   0,    dd080 ||||  L2, DMA,    140(   320),    100(   256),   80(  128),   a200(  41472),   0,    65580 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  48(TIDL_BatchNormLayer) [48, 48] --[128 x 80 x  80] => [128 x 80 x  80] *** [128] ***[ COL] ***[0, 0, 0, 6400, 6400]**** [4], [0],[4] -[47 ]---
  IN:MSMC, DMA,   1940(  6464),   1900(  6400),   80(  128),  ca000( 827392),   0,        0 ||||  L2, DMA,   1950(  6480),   1950(  6480),   40(   64),  65400( 414720),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1940(  6464),   1900(  6400),   80(  128),  ca000( 827392),   0,    ca000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  49(TIDL_EltWiseLayer) [49, 49] --[256 x 80 x  80] => [128 x 80 x  80] *** [256] ***[ COL] ***[0, 0, 0, 6400, 6400]**** [8], [0],[8] -[47 48 ]---
  IN:MSMC, DMA,   1940(  6464),   1900(  6400),   80(  128),  ca000( 827392),   0,        0 ||||  L2, DMA,   1950(  6480),   1950(  6480),   20(   32),  65400( 414720),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1940(  6464),   1900(  6400),   80(  128),  ca000( 827392),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  50(TIDL_ConvolutionLayer) [50, 50] --[128 x 80 x  80] => [256 x 80 x  80] *** [128] ***[ROW_L] ***[162, 192, 81, 384, 6400]**** [17], [1],[17] -[49 ]---
  IN:MSMC, DMA,   1940(  6464),   1900(  6400),   80(  128),  ca000( 827392),   0,        0 ||||  L2, DMA,    3c0(   960),    3c0(   960),   80(  128),  1f700( 128768),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1940(  6464),   1900(  6400),  100(  256), 194000(1654784),   0,    ca000 
  WT:DDR_PERSIST, DMA,    480(  1152),    480(  1152),  100(  256),  48400( 295936),   0,    e5280 ||||  L2, DMA,    4c0(  1216),    480(  1152),  100(  256),  4c400( 312320),   0,    1f700 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  51(TIDL_BatchNormLayer) [51, 51] --[256 x 80 x  80] => [256 x 80 x  80] *** [256] ***[ COL] ***[0, 0, 0, 6400, 6400]**** [8], [0],[8] -[50 ]---
  IN:MSMC, DMA,   1940(  6464),   1900(  6400),  100(  256), 194000(1654784),   0,    ca000 ||||  L2, DMA,   1950(  6480),   1950(  6480),   40(   64),  65400( 414720),   0,        0 
 OUT:MSMC, CPU,   1940(  6464),   1900(  6400),   40(   64),  65000( 413696),   0,        0 |||| DDR, DMA,   1900(  6400),   1900(  6400),  100(  256), 190400(1639424),   0,   2bc800 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  52(TIDL_EltWiseLayer) [52, 52] --[512 x 80 x  80] => [256 x 80 x  80] *** [512] ***[ COL] ***[0, 0, 0, 6400, 6400]**** [16], [0],[16] -[50 51 ]---
  IN:MSMC, DMA,   1940(  6464),   1900(  6400),  100(  256), 194000(1654784),   0,    ca000 ||||  L2, DMA,   1950(  6480),   1950(  6480),   20(   32),  65400( 414720),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1940(  6464),   1900(  6400),  100(  256), 194000(1654784),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  53(TIDL_EltWiseLayer) [53, 53] --[512 x 80 x  80] => [256 x 80 x  80] *** [512] ***[ COL] ***[0, 0, 0, 6400, 6400]**** [16], [0],[16] -[46 52 ]---
  IN: DDR, DMA,   1900(  6400),   1900(  6400),  100(  256), 190400(1639424),   0,   12c400 ||||  L2, DMA,   1950(  6480),   1950(  6480),   20(   32),  65400( 414720),   0,        0 
 OUT:MSMC, CPU,   1940(  6464),   1900(  6400),   20(   32),  32800( 206848),   0,   194000 |||| DDR, DMA,   1900(  6400),   1900(  6400),  100(  256), 190400(1639424),   0,   2bc800 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  54(TIDL_ConvolutionLayer) [54, 54] --[256 x 80 x  80] => [128 x 80 x  80] *** [256] ***[ROW_L] ***[0, 0, 0, 768, 6400]**** [9], [1],[9] -[53 ]---
  IN: DDR, DMA,   1900(  6400),   1900(  6400),  100(  256), 190400(1639424),   0,   2bc800 ||||  L2, DMA,    640(  1600),    640(  1600),  100(  256),  65580( 415104),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1940(  6464),   1900(  6400),   80(  128),  ca000( 827392),   0,        0 
  WT:DDR_PERSIST, DMA,    100(   256),    100(   256),   80(  128),   8200(  33280),   0,   12d680 ||||  L2, DMA,    140(   320),    100(   256),   80(  128),   a200(  41472),   0,    65580 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  55(TIDL_BatchNormLayer) [55, 55] --[128 x 80 x  80] => [128 x 80 x  80] *** [128] ***[ COL] ***[0, 0, 0, 6400, 6400]**** [4], [0],[4] -[54 ]---
  IN:MSMC, DMA,   1940(  6464),   1900(  6400),   80(  128),  ca000( 827392),   0,        0 ||||  L2, DMA,   1950(  6480),   1950(  6480),   40(   64),  65400( 414720),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1940(  6464),   1900(  6400),   80(  128),  ca000( 827392),   0,    ca000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  56(TIDL_EltWiseLayer) [56, 56] --[256 x 80 x  80] => [128 x 80 x  80] *** [256] ***[ COL] ***[0, 0, 0, 6400, 6400]**** [8], [0],[8] -[54 55 ]---
  IN:MSMC, DMA,   1940(  6464),   1900(  6400),   80(  128),  ca000( 827392),   0,        0 ||||  L2, DMA,   1950(  6480),   1950(  6480),   20(   32),  65400( 414720),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1940(  6464),   1900(  6400),   80(  128),  ca000( 827392),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  57(TIDL_ConvolutionLayer) [57, 57] --[128 x 80 x  80] => [256 x 80 x  80] *** [128] ***[ROW_L] ***[162, 192, 81, 384, 6400]**** [17], [1],[17] -[56 ]---
  IN:MSMC, DMA,   1940(  6464),   1900(  6400),   80(  128),  ca000( 827392),   0,        0 ||||  L2, DMA,    3c0(   960),    3c0(   960),   80(  128),  1f700( 128768),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1940(  6464),   1900(  6400),  100(  256), 194000(1654784),   0,    ca000 
  WT:DDR_PERSIST, DMA,    480(  1152),    480(  1152),  100(  256),  48400( 295936),   0,   135880 ||||  L2, DMA,    4c0(  1216),    480(  1152),  100(  256),  4c400( 312320),   0,    1f700 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  58(TIDL_BatchNormLayer) [58, 58] --[256 x 80 x  80] => [256 x 80 x  80] *** [256] ***[ COL] ***[0, 0, 0, 6400, 6400]**** [8], [0],[8] -[57 ]---
  IN:MSMC, DMA,   1940(  6464),   1900(  6400),  100(  256), 194000(1654784),   0,    ca000 ||||  L2, DMA,   1950(  6480),   1950(  6480),   40(   64),  65400( 414720),   0,        0 
 OUT:MSMC, CPU,   1940(  6464),   1900(  6400),   40(   64),  65000( 413696),   0,        0 |||| DDR, DMA,   1900(  6400),   1900(  6400),  100(  256), 190400(1639424),   0,   12c400 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  59(TIDL_EltWiseLayer) [59, 59] --[512 x 80 x  80] => [256 x 80 x  80] *** [512] ***[ COL] ***[0, 0, 0, 6400, 6400]**** [16], [0],[16] -[57 58 ]---
  IN:MSMC, DMA,   1940(  6464),   1900(  6400),  100(  256), 194000(1654784),   0,    ca000 ||||  L2, DMA,   1950(  6480),   1950(  6480),   20(   32),  65400( 414720),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1940(  6464),   1900(  6400),  100(  256), 194000(1654784),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  60(TIDL_EltWiseLayer) [60, 60] --[512 x 80 x  80] => [256 x 80 x  80] *** [512] ***[ COL] ***[0, 0, 0, 6400, 6400]**** [16], [0],[16] -[53 59 ]---
  IN: DDR, DMA,   1900(  6400),   1900(  6400),  100(  256), 190400(1639424),   0,   2bc800 ||||  L2, DMA,   1950(  6480),   1950(  6480),   20(   32),  65400( 414720),   0,        0 
 OUT:MSMC, CPU,   1940(  6464),   1900(  6400),   20(   32),  32800( 206848),   0,   194000 |||| DDR, DMA,   1900(  6400),   1900(  6400),  100(  256), 190400(1639424),   0,   44cc00 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  61(TIDL_ConvolutionLayer) [61, 61] --[256 x 80 x  80] => [128 x 80 x  80] *** [256] ***[ROW_L] ***[0, 0, 0, 768, 6400]**** [9], [1],[9] -[60 ]---
  IN: DDR, DMA,   1900(  6400),   1900(  6400),  100(  256), 190400(1639424),   0,   44cc00 ||||  L2, DMA,    640(  1600),    640(  1600),  100(  256),  65580( 415104),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1940(  6464),   1900(  6400),   80(  128),  ca000( 827392),   0,        0 
  WT:DDR_PERSIST, DMA,    100(   256),    100(   256),   80(  128),   8200(  33280),   0,   17dc80 ||||  L2, DMA,    140(   320),    100(   256),   80(  128),   a200(  41472),   0,    65580 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  62(TIDL_BatchNormLayer) [62, 62] --[128 x 80 x  80] => [128 x 80 x  80] *** [128] ***[ COL] ***[0, 0, 0, 6400, 6400]**** [4], [0],[4] -[61 ]---
  IN:MSMC, DMA,   1940(  6464),   1900(  6400),   80(  128),  ca000( 827392),   0,        0 ||||  L2, DMA,   1950(  6480),   1950(  6480),   40(   64),  65400( 414720),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1940(  6464),   1900(  6400),   80(  128),  ca000( 827392),   0,    ca000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  63(TIDL_EltWiseLayer) [63, 63] --[256 x 80 x  80] => [128 x 80 x  80] *** [256] ***[ COL] ***[0, 0, 0, 6400, 6400]**** [8], [0],[8] -[61 62 ]---
  IN:MSMC, DMA,   1940(  6464),   1900(  6400),   80(  128),  ca000( 827392),   0,        0 ||||  L2, DMA,   1950(  6480),   1950(  6480),   20(   32),  65400( 414720),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1940(  6464),   1900(  6400),   80(  128),  ca000( 827392),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  64(TIDL_ConvolutionLayer) [64, 64] --[128 x 80 x  80] => [256 x 80 x  80] *** [128] ***[ROW_L] ***[162, 192, 81, 384, 6400]**** [17], [1],[17] -[63 ]---
  IN:MSMC, DMA,   1940(  6464),   1900(  6400),   80(  128),  ca000( 827392),   0,        0 ||||  L2, DMA,    3c0(   960),    3c0(   960),   80(  128),  1f700( 128768),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1940(  6464),   1900(  6400),  100(  256), 194000(1654784),   0,    ca000 
  WT:DDR_PERSIST, DMA,    480(  1152),    480(  1152),  100(  256),  48400( 295936),   0,   185e80 ||||  L2, DMA,    4c0(  1216),    480(  1152),  100(  256),  4c400( 312320),   0,    1f700 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  65(TIDL_BatchNormLayer) [65, 65] --[256 x 80 x  80] => [256 x 80 x  80] *** [256] ***[ COL] ***[0, 0, 0, 6400, 6400]**** [8], [0],[8] -[64 ]---
  IN:MSMC, DMA,   1940(  6464),   1900(  6400),  100(  256), 194000(1654784),   0,    ca000 ||||  L2, DMA,   1950(  6480),   1950(  6480),   40(   64),  65400( 414720),   0,        0 
 OUT:MSMC, CPU,   1940(  6464),   1900(  6400),   40(   64),  65000( 413696),   0,        0 |||| DDR, DMA,   1900(  6400),   1900(  6400),  100(  256), 190400(1639424),   0,   12c400 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  66(TIDL_EltWiseLayer) [66, 66] --[512 x 80 x  80] => [256 x 80 x  80] *** [512] ***[ COL] ***[0, 0, 0, 6400, 6400]**** [16], [0],[16] -[64 65 ]---
  IN:MSMC, DMA,   1940(  6464),   1900(  6400),  100(  256), 194000(1654784),   0,    ca000 ||||  L2, DMA,   1950(  6480),   1950(  6480),   20(   32),  65400( 414720),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1940(  6464),   1900(  6400),  100(  256), 194000(1654784),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  67(TIDL_EltWiseLayer) [67, 67] --[512 x 80 x  80] => [256 x 80 x  80] *** [512] ***[ COL] ***[0, 0, 0, 6400, 6400]**** [16], [0],[16] -[60 66 ]---
  IN: DDR, DMA,   1900(  6400),   1900(  6400),  100(  256), 190400(1639424),   0,   44cc00 ||||  L2, DMA,   1950(  6480),   1950(  6480),   20(   32),  65400( 414720),   0,        0 
 OUT:MSMC, CPU,   1940(  6464),   1900(  6400),   20(   32),  32800( 206848),   0,   194000 |||| DDR, DMA,   1900(  6400),   1900(  6400),  100(  256), 190400(1639424),   0,   12c400 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  68(TIDL_ConvolutionLayer) [68, 68] --[256 x 80 x  80] => [128 x 80 x  80] *** [256] ***[ROW_L] ***[0, 0, 0, 768, 6400]**** [9], [1],[9] -[67 ]---
  IN: DDR, DMA,   1900(  6400),   1900(  6400),  100(  256), 190400(1639424),   0,   12c400 ||||  L2, DMA,    640(  1600),    640(  1600),  100(  256),  65580( 415104),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1940(  6464),   1900(  6400),   80(  128),  ca000( 827392),   0,        0 
  WT:DDR_PERSIST, DMA,    100(   256),    100(   256),   80(  128),   8200(  33280),   0,   1ce280 ||||  L2, DMA,    140(   320),    100(   256),   80(  128),   a200(  41472),   0,    65580 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  69(TIDL_BatchNormLayer) [69, 69] --[128 x 80 x  80] => [128 x 80 x  80] *** [128] ***[ COL] ***[0, 0, 0, 6400, 6400]**** [4], [0],[4] -[68 ]---
  IN:MSMC, DMA,   1940(  6464),   1900(  6400),   80(  128),  ca000( 827392),   0,        0 ||||  L2, DMA,   1950(  6480),   1950(  6480),   40(   64),  65400( 414720),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1940(  6464),   1900(  6400),   80(  128),  ca000( 827392),   0,    ca000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  70(TIDL_EltWiseLayer) [70, 70] --[256 x 80 x  80] => [128 x 80 x  80] *** [256] ***[ COL] ***[0, 0, 0, 6400, 6400]**** [8], [0],[8] -[68 69 ]---
  IN:MSMC, DMA,   1940(  6464),   1900(  6400),   80(  128),  ca000( 827392),   0,        0 ||||  L2, DMA,   1950(  6480),   1950(  6480),   20(   32),  65400( 414720),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1940(  6464),   1900(  6400),   80(  128),  ca000( 827392),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  71(TIDL_ConvolutionLayer) [71, 71] --[128 x 80 x  80] => [256 x 80 x  80] *** [128] ***[ROW_L] ***[162, 192, 81, 384, 6400]**** [17], [1],[17] -[70 ]---
  IN:MSMC, DMA,   1940(  6464),   1900(  6400),   80(  128),  ca000( 827392),   0,        0 ||||  L2, DMA,    3c0(   960),    3c0(   960),   80(  128),  1f700( 128768),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1940(  6464),   1900(  6400),  100(  256), 194000(1654784),   0,    ca000 
  WT:DDR_PERSIST, DMA,    480(  1152),    480(  1152),  100(  256),  48400( 295936),   0,   1d6480 ||||  L2, DMA,    4c0(  1216),    480(  1152),  100(  256),  4c400( 312320),   0,    1f700 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  72(TIDL_BatchNormLayer) [72, 72] --[256 x 80 x  80] => [256 x 80 x  80] *** [256] ***[ COL] ***[0, 0, 0, 6400, 6400]**** [8], [0],[8] -[71 ]---
  IN:MSMC, DMA,   1940(  6464),   1900(  6400),  100(  256), 194000(1654784),   0,    ca000 ||||  L2, DMA,   1950(  6480),   1950(  6480),   40(   64),  65400( 414720),   0,        0 
 OUT:MSMC, CPU,   1940(  6464),   1900(  6400),   40(   64),  65000( 413696),   0,        0 |||| DDR, DMA,   1900(  6400),   1900(  6400),  100(  256), 190400(1639424),   0,   2bc800 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  73(TIDL_EltWiseLayer) [73, 73] --[512 x 80 x  80] => [256 x 80 x  80] *** [512] ***[ COL] ***[0, 0, 0, 6400, 6400]**** [16], [0],[16] -[71 72 ]---
  IN:MSMC, DMA,   1940(  6464),   1900(  6400),  100(  256), 194000(1654784),   0,    ca000 ||||  L2, DMA,   1950(  6480),   1950(  6480),   20(   32),  65400( 414720),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1940(  6464),   1900(  6400),  100(  256), 194000(1654784),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  74(TIDL_EltWiseLayer) [74, 74] --[512 x 80 x  80] => [256 x 80 x  80] *** [512] ***[ COL] ***[0, 0, 0, 6400, 6400]**** [16], [0],[16] -[67 73 ]---
  IN: DDR, DMA,   1900(  6400),   1900(  6400),  100(  256), 190400(1639424),   0,   12c400 ||||  L2, DMA,   1950(  6480),   1950(  6480),   20(   32),  65400( 414720),   0,        0 
 OUT:MSMC, CPU,   1940(  6464),   1900(  6400),   20(   32),  32800( 206848),   0,   194000 |||| DDR, DMA,   1900(  6400),   1900(  6400),  100(  256), 190400(1639424),   0,   2bc800 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  75(TIDL_ConvolutionLayer) [75, 75] --[256 x 80 x  80] => [128 x 80 x  80] *** [256] ***[ROW_L] ***[0, 0, 0, 768, 6400]**** [9], [1],[9] -[74 ]---
  IN: DDR, DMA,   1900(  6400),   1900(  6400),  100(  256), 190400(1639424),   0,   2bc800 ||||  L2, DMA,    640(  1600),    640(  1600),  100(  256),  65580( 415104),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1940(  6464),   1900(  6400),   80(  128),  ca000( 827392),   0,        0 
  WT:DDR_PERSIST, DMA,    100(   256),    100(   256),   80(  128),   8200(  33280),   0,   21e880 ||||  L2, DMA,    140(   320),    100(   256),   80(  128),   a200(  41472),   0,    65580 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  76(TIDL_BatchNormLayer) [76, 76] --[128 x 80 x  80] => [128 x 80 x  80] *** [128] ***[ COL] ***[0, 0, 0, 6400, 6400]**** [4], [0],[4] -[75 ]---
  IN:MSMC, DMA,   1940(  6464),   1900(  6400),   80(  128),  ca000( 827392),   0,        0 ||||  L2, DMA,   1950(  6480),   1950(  6480),   40(   64),  65400( 414720),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1940(  6464),   1900(  6400),   80(  128),  ca000( 827392),   0,    ca000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  77(TIDL_EltWiseLayer) [77, 77] --[256 x 80 x  80] => [128 x 80 x  80] *** [256] ***[ COL] ***[0, 0, 0, 6400, 6400]**** [8], [0],[8] -[75 76 ]---
  IN:MSMC, DMA,   1940(  6464),   1900(  6400),   80(  128),  ca000( 827392),   0,        0 ||||  L2, DMA,   1950(  6480),   1950(  6480),   20(   32),  65400( 414720),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1940(  6464),   1900(  6400),   80(  128),  ca000( 827392),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  78(TIDL_ConvolutionLayer) [78, 78] --[128 x 80 x  80] => [256 x 80 x  80] *** [128] ***[ROW_L] ***[162, 192, 81, 384, 6400]**** [17], [1],[17] -[77 ]---
  IN:MSMC, DMA,   1940(  6464),   1900(  6400),   80(  128),  ca000( 827392),   0,        0 ||||  L2, DMA,    3c0(   960),    3c0(   960),   80(  128),  1f700( 128768),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1940(  6464),   1900(  6400),  100(  256), 194000(1654784),   0,    ca000 
  WT:DDR_PERSIST, DMA,    480(  1152),    480(  1152),  100(  256),  48400( 295936),   0,   226a80 ||||  L2, DMA,    4c0(  1216),    480(  1152),  100(  256),  4c400( 312320),   0,    1f700 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  79(TIDL_BatchNormLayer) [79, 79] --[256 x 80 x  80] => [256 x 80 x  80] *** [256] ***[ COL] ***[0, 0, 0, 6400, 6400]**** [8], [0],[8] -[78 ]---
  IN:MSMC, DMA,   1940(  6464),   1900(  6400),  100(  256), 194000(1654784),   0,    ca000 ||||  L2, DMA,   1950(  6480),   1950(  6480),   40(   64),  65400( 414720),   0,        0 
 OUT:MSMC, CPU,   1940(  6464),   1900(  6400),   40(   64),  65000( 413696),   0,        0 |||| DDR, DMA,   1900(  6400),   1900(  6400),  100(  256), 190400(1639424),   0,   12c400 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  80(TIDL_EltWiseLayer) [80, 80] --[512 x 80 x  80] => [256 x 80 x  80] *** [512] ***[ COL] ***[0, 0, 0, 6400, 6400]**** [16], [0],[16] -[78 79 ]---
  IN:MSMC, DMA,   1940(  6464),   1900(  6400),  100(  256), 194000(1654784),   0,    ca000 ||||  L2, DMA,   1950(  6480),   1950(  6480),   20(   32),  65400( 414720),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1940(  6464),   1900(  6400),  100(  256), 194000(1654784),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  81(TIDL_EltWiseLayer) [81, 81] --[512 x 80 x  80] => [256 x 80 x  80] *** [512] ***[ COL] ***[0, 0, 0, 6400, 6400]**** [16], [0],[16] -[74 80 ]---
  IN: DDR, DMA,   1900(  6400),   1900(  6400),  100(  256), 190400(1639424),   0,   2bc800 ||||  L2, DMA,   1950(  6480),   1950(  6480),   20(   32),  65400( 414720),   0,        0 
 OUT:MSMC, CPU,   1940(  6464),   1900(  6400),   20(   32),  32800( 206848),   0,   194000 |||| DDR, DMA,   1900(  6400),   1900(  6400),  100(  256), 190400(1639424),   0,   12c400 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  82(TIDL_ConvolutionLayer) [82, 82] --[256 x 80 x  80] => [128 x 80 x  80] *** [256] ***[ROW_L] ***[0, 0, 0, 768, 6400]**** [9], [1],[9] -[81 ]---
  IN: DDR, DMA,   1900(  6400),   1900(  6400),  100(  256), 190400(1639424),   0,   12c400 ||||  L2, DMA,    640(  1600),    640(  1600),  100(  256),  65580( 415104),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1940(  6464),   1900(  6400),   80(  128),  ca000( 827392),   0,        0 
  WT:DDR_PERSIST, DMA,    100(   256),    100(   256),   80(  128),   8200(  33280),   0,   26ee80 ||||  L2, DMA,    140(   320),    100(   256),   80(  128),   a200(  41472),   0,    65580 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  83(TIDL_BatchNormLayer) [83, 83] --[128 x 80 x  80] => [128 x 80 x  80] *** [128] ***[ COL] ***[0, 0, 0, 6400, 6400]**** [4], [0],[4] -[82 ]---
  IN:MSMC, DMA,   1940(  6464),   1900(  6400),   80(  128),  ca000( 827392),   0,        0 ||||  L2, DMA,   1950(  6480),   1950(  6480),   40(   64),  65400( 414720),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1940(  6464),   1900(  6400),   80(  128),  ca000( 827392),   0,    ca000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  84(TIDL_EltWiseLayer) [84, 84] --[256 x 80 x  80] => [128 x 80 x  80] *** [256] ***[ COL] ***[0, 0, 0, 6400, 6400]**** [8], [0],[8] -[82 83 ]---
  IN:MSMC, DMA,   1940(  6464),   1900(  6400),   80(  128),  ca000( 827392),   0,        0 ||||  L2, DMA,   1950(  6480),   1950(  6480),   20(   32),  65400( 414720),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1940(  6464),   1900(  6400),   80(  128),  ca000( 827392),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  85(TIDL_ConvolutionLayer) [85, 85] --[128 x 80 x  80] => [256 x 80 x  80] *** [128] ***[ROW_L] ***[162, 192, 81, 384, 6400]**** [17], [1],[17] -[84 ]---
  IN:MSMC, DMA,   1940(  6464),   1900(  6400),   80(  128),  ca000( 827392),   0,        0 ||||  L2, DMA,    3c0(   960),    3c0(   960),   80(  128),  1f700( 128768),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1940(  6464),   1900(  6400),  100(  256), 194000(1654784),   0,    ca000 
  WT:DDR_PERSIST, DMA,    480(  1152),    480(  1152),  100(  256),  48400( 295936),   0,   277080 ||||  L2, DMA,    4c0(  1216),    480(  1152),  100(  256),  4c400( 312320),   0,    1f700 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  86(TIDL_BatchNormLayer) [86, 86] --[256 x 80 x  80] => [256 x 80 x  80] *** [256] ***[ COL] ***[0, 0, 0, 6400, 6400]**** [8], [0],[8] -[85 ]---
  IN:MSMC, DMA,   1940(  6464),   1900(  6400),  100(  256), 194000(1654784),   0,    ca000 ||||  L2, DMA,   1950(  6480),   1950(  6480),   40(   64),  65400( 414720),   0,        0 
 OUT:MSMC, CPU,   1940(  6464),   1900(  6400),   40(   64),  65000( 413696),   0,        0 |||| DDR, DMA,   1900(  6400),   1900(  6400),  100(  256), 190400(1639424),   0,   2bc800 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  87(TIDL_EltWiseLayer) [87, 87] --[512 x 80 x  80] => [256 x 80 x  80] *** [512] ***[ COL] ***[0, 0, 0, 6400, 6400]**** [16], [0],[16] -[85 86 ]---
  IN:MSMC, DMA,   1940(  6464),   1900(  6400),  100(  256), 194000(1654784),   0,    ca000 ||||  L2, DMA,   1950(  6480),   1950(  6480),   20(   32),  65400( 414720),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1940(  6464),   1900(  6400),  100(  256), 194000(1654784),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  88(TIDL_EltWiseLayer) [88, 88] --[512 x 80 x  80] => [256 x 80 x  80] *** [512] ***[ COL] ***[0, 0, 0, 6400, 6400]**** [16], [0],[16] -[81 87 ]---
  IN: DDR, DMA,   1900(  6400),   1900(  6400),  100(  256), 190400(1639424),   0,   12c400 ||||  L2, DMA,   1950(  6480),   1950(  6480),   20(   32),  65400( 414720),   0,        0 
 OUT:MSMC, CPU,   1940(  6464),   1900(  6400),   20(   32),  32800( 206848),   0,   194000 |||| DDR, DMA,   1900(  6400),   1900(  6400),  100(  256), 190400(1639424),   0,   2bc800 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  89(TIDL_ConvolutionLayer) [89, 89] --[256 x 80 x  80] => [128 x 80 x  80] *** [256] ***[ROW_L] ***[0, 0, 0, 768, 6400]**** [9], [1],[9] -[88 ]---
  IN: DDR, DMA,   1900(  6400),   1900(  6400),  100(  256), 190400(1639424),   0,   2bc800 ||||  L2, DMA,    640(  1600),    640(  1600),  100(  256),  65580( 415104),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1940(  6464),   1900(  6400),   80(  128),  ca000( 827392),   0,        0 
  WT:DDR_PERSIST, DMA,    100(   256),    100(   256),   80(  128),   8200(  33280),   0,   2bf480 ||||  L2, DMA,    140(   320),    100(   256),   80(  128),   a200(  41472),   0,    65580 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  90(TIDL_BatchNormLayer) [90, 90] --[128 x 80 x  80] => [128 x 80 x  80] *** [128] ***[ COL] ***[0, 0, 0, 6400, 6400]**** [4], [0],[4] -[89 ]---
  IN:MSMC, DMA,   1940(  6464),   1900(  6400),   80(  128),  ca000( 827392),   0,        0 ||||  L2, DMA,   1950(  6480),   1950(  6480),   40(   64),  65400( 414720),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1940(  6464),   1900(  6400),   80(  128),  ca000( 827392),   0,    ca000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  91(TIDL_EltWiseLayer) [91, 91] --[256 x 80 x  80] => [128 x 80 x  80] *** [256] ***[ COL] ***[0, 0, 0, 6400, 6400]**** [8], [0],[8] -[89 90 ]---
  IN:MSMC, DMA,   1940(  6464),   1900(  6400),   80(  128),  ca000( 827392),   0,        0 ||||  L2, DMA,   1950(  6480),   1950(  6480),   20(   32),  65400( 414720),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1940(  6464),   1900(  6400),   80(  128),  ca000( 827392),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  92(TIDL_ConvolutionLayer) [92, 92] --[128 x 80 x  80] => [256 x 80 x  80] *** [128] ***[ROW_L] ***[162, 192, 81, 384, 6400]**** [17], [1],[17] -[91 ]---
  IN:MSMC, DMA,   1940(  6464),   1900(  6400),   80(  128),  ca000( 827392),   0,        0 ||||  L2, DMA,    3c0(   960),    3c0(   960),   80(  128),  1f700( 128768),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1940(  6464),   1900(  6400),  100(  256), 194000(1654784),   0,    ca000 
  WT:DDR_PERSIST, DMA,    480(  1152),    480(  1152),  100(  256),  48400( 295936),   0,   2c7680 ||||  L2, DMA,    4c0(  1216),    480(  1152),  100(  256),  4c400( 312320),   0,    1f700 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  93(TIDL_BatchNormLayer) [93, 93] --[256 x 80 x  80] => [256 x 80 x  80] *** [256] ***[ COL] ***[0, 0, 0, 6400, 6400]**** [8], [0],[8] -[92 ]---
  IN:MSMC, DMA,   1940(  6464),   1900(  6400),  100(  256), 194000(1654784),   0,    ca000 ||||  L2, DMA,   1950(  6480),   1950(  6480),   40(   64),  65400( 414720),   0,        0 
 OUT:MSMC, CPU,   1940(  6464),   1900(  6400),   40(   64),  65000( 413696),   0,        0 |||| DDR, DMA,   1900(  6400),   1900(  6400),  100(  256), 190400(1639424),   0,   12c400 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  94(TIDL_EltWiseLayer) [94, 94] --[512 x 80 x  80] => [256 x 80 x  80] *** [512] ***[ COL] ***[0, 0, 0, 6400, 6400]**** [16], [0],[16] -[92 93 ]---
  IN:MSMC, DMA,   1940(  6464),   1900(  6400),  100(  256), 194000(1654784),   0,    ca000 ||||  L2, DMA,   1950(  6480),   1950(  6480),   20(   32),  65400( 414720),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1940(  6464),   1900(  6400),  100(  256), 194000(1654784),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  95(TIDL_EltWiseLayer) [95, 95] --[512 x 80 x  80] => [256 x 80 x  80] *** [512] ***[ COL] ***[0, 0, 0, 6400, 6400]**** [16], [0],[16] -[88 94 ]---
  IN: DDR, DMA,   1900(  6400),   1900(  6400),  100(  256), 190400(1639424),   0,   2bc800 ||||  L2, DMA,   1950(  6480),   1950(  6480),   20(   32),  65400( 414720),   0,        0 
 OUT:MSMC, CPU,   1940(  6464),   1900(  6400),   20(   32),  32800( 206848),   0,   194000 |||| DDR, DMA,   1900(  6400),   1900(  6400),  100(  256), 190400(1639424),   0,   12c400 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  96(TIDL_ConvolutionLayer) [96, 96] --[256 x 80 x  80] => [512 x 40 x  40] *** [256] ***[ROW_L] ***[80, 80, 0, 160, 6400]**** [40], [320],[320] -[95 ]---
  IN: DDR, DMA,   1900(  6400),   1900(  6400),  100(  256), 190400(1639424),   0,   12c400 ||||  L2, DMA,    1c0(   448),    1c0(   448),  100(  256),  1d880( 120960),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    6c0(  1728),    641(  1601),  200(  512),  d8000( 884736),   0,   128800 
  WT:DDR_PERSIST, DMA,    900(  2304),    900(  2304),  200(  512), 120800(1181696),   0,   30fa80 ||||  L2, DMA,    940(  2368),    900(  2304),   80(  128),  4a800( 305152),   0,    1d880 
 STG:MSMC, DMA,    944(  2372),    900(  2304),  200(  512), 128800(1214464),   0,        0 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  97(TIDL_BatchNormLayer) [97, 97] --[512 x 40 x  40] => [512 x 40 x  40] *** [512] ***[ COL] ***[0, 0, 0, 1600, 1600]**** [4], [0],[4] -[96 ]---
  IN:MSMC, DMA,    6c0(  1728),    641(  1601),  200(  512),  d8000( 884736),   0,   128800 ||||  L2, DMA,    640(  1600),    640(  1600),  100(  256),  64000( 409600),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    640(  1600),    640(  1600),  200(  512),  c8000( 819200),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  98(TIDL_EltWiseLayer) [98, 98] --[1024 x 40 x  40] => [512 x 40 x  40] *** [1024] ***[ COL] ***[0, 0, 0, 1600, 1600]**** [8], [0],[8] -[96 97 ]---
  IN:MSMC, DMA,    6c0(  1728),    641(  1601),  200(  512),  d8000( 884736),   0,   128800 ||||  L2, DMA,    640(  1600),    640(  1600),   80(  128),  64000( 409600),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    640(  1600),    640(  1600),  200(  512),  c8000( 819200),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  99(TIDL_ConvolutionLayer) [99, 99] --[512 x 40 x  40] => [256 x 40 x  40] *** [512] ***[ROW_L] ***[0, 0, 0, 256, 1600]**** [7], [1],[7] -[98 ]---
  IN:MSMC, DMA,    640(  1600),    640(  1600),  200(  512),  c8000( 819200),   0,        0 ||||  L2, DMA,    240(   576),    240(   576),  200(  512),  48580( 296320),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    640(  1600),    640(  1600),  100(  256),  64000( 409600),   0,    c8000 
  WT:DDR_PERSIST, DMA,    200(   512),    200(   512),  100(  256),  20400( 132096),   0,   430280 ||||  L2, DMA,    240(   576),    200(   512),  100(  256),  24400( 148480),   0,    48580 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  100(TIDL_BatchNormLayer) [100, 100] --[256 x 40 x  40] => [256 x 40 x  40] *** [256] ***[ COL] ***[0, 0, 0, 1600, 1600]**** [1], [0],[1] -[99 ]---
  IN:MSMC, DMA,    640(  1600),    640(  1600),  100(  256),  64000( 409600),   0,    c8000 ||||  L2, DMA,    640(  1600),    640(  1600),  100(  256),  64000( 409600),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    640(  1600),    640(  1600),  100(  256),  64000( 409600),   0,   12c000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  101(TIDL_EltWiseLayer) [101, 101] --[512 x 40 x  40] => [256 x 40 x  40] *** [512] ***[ COL] ***[0, 0, 0, 1600, 1600]**** [4], [0],[4] -[99 100 ]---
  IN:MSMC, DMA,    640(  1600),    640(  1600),  100(  256),  64000( 409600),   0,    c8000 ||||  L2, DMA,    640(  1600),    640(  1600),   80(  128),  64000( 409600),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    640(  1600),    640(  1600),  100(  256),  64000( 409600),   0,   190000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  102(TIDL_ConvolutionLayer) [102, 102] --[256 x 40 x  40] => [512 x 40 x  40] *** [256] ***[ROW_L] ***[82, 128, 41, 192, 1600]**** [9], [72],[72] -[101 ]---
  IN:MSMC, DMA,    640(  1600),    640(  1600),  100(  256),  64000( 409600),   0,   190000 ||||  L2, DMA,    240(   576),    240(   576),  100(  256),  24580( 148864),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    640(  1600),    640(  1600),  200(  512),  c8000( 819200),   0,    c8000 
  WT:DDR_PERSIST, DMA,    900(  2304),    900(  2304),  200(  512), 120800(1181696),   0,   450680 ||||  L2, DMA,    940(  2368),    900(  2304),   80(  128),  4a800( 305152),   0,    24580 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  103(TIDL_BatchNormLayer) [103, 103] --[512 x 40 x  40] => [512 x 40 x  40] *** [512] ***[ COL] ***[0, 0, 0, 1600, 1600]**** [4], [0],[4] -[102 ]---
  IN:MSMC, DMA,    640(  1600),    640(  1600),  200(  512),  c8000( 819200),   0,    c8000 ||||  L2, DMA,    640(  1600),    640(  1600),  100(  256),  64000( 409600),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    640(  1600),    640(  1600),  200(  512),  c8000( 819200),   0,   190000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  104(TIDL_EltWiseLayer) [104, 104] --[1024 x 40 x  40] => [512 x 40 x  40] *** [1024] ***[ COL] ***[0, 0, 0, 1600, 1600]**** [8], [0],[8] -[102 103 ]---
  IN:MSMC, DMA,    640(  1600),    640(  1600),  200(  512),  c8000( 819200),   0,    c8000 ||||  L2, DMA,    640(  1600),    640(  1600),   80(  128),  64000( 409600),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    640(  1600),    640(  1600),  200(  512),  c8000( 819200),   0,    c8000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  105(TIDL_EltWiseLayer) [105, 105] --[1024 x 40 x  40] => [512 x 40 x  40] *** [1024] ***[ COL] ***[0, 0, 0, 1600, 1600]**** [8], [0],[8] -[98 104 ]---
  IN:MSMC, DMA,    640(  1600),    640(  1600),  200(  512),  c8000( 819200),   0,        0 ||||  L2, DMA,    640(  1600),    640(  1600),   80(  128),  64000( 409600),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    640(  1600),    640(  1600),  200(  512),  c8000( 819200),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  106(TIDL_ConvolutionLayer) [106, 106] --[512 x 40 x  40] => [256 x 40 x  40] *** [512] ***[ROW_L] ***[0, 0, 0, 256, 1600]**** [7], [1],[7] -[105 ]---
  IN:MSMC, DMA,    640(  1600),    640(  1600),  200(  512),  c8000( 819200),   0,        0 ||||  L2, DMA,    240(   576),    240(   576),  200(  512),  48580( 296320),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    640(  1600),    640(  1600),  100(  256),  64000( 409600),   0,    c8000 
  WT:DDR_PERSIST, DMA,    200(   512),    200(   512),  100(  256),  20400( 132096),   0,   570e80 ||||  L2, DMA,    240(   576),    200(   512),  100(  256),  24400( 148480),   0,    48580 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  107(TIDL_BatchNormLayer) [107, 107] --[256 x 40 x  40] => [256 x 40 x  40] *** [256] ***[ COL] ***[0, 0, 0, 1600, 1600]**** [1], [0],[1] -[106 ]---
  IN:MSMC, DMA,    640(  1600),    640(  1600),  100(  256),  64000( 409600),   0,    c8000 ||||  L2, DMA,    640(  1600),    640(  1600),  100(  256),  64000( 409600),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    640(  1600),    640(  1600),  100(  256),  64000( 409600),   0,   12c000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  108(TIDL_EltWiseLayer) [108, 108] --[512 x 40 x  40] => [256 x 40 x  40] *** [512] ***[ COL] ***[0, 0, 0, 1600, 1600]**** [4], [0],[4] -[106 107 ]---
  IN:MSMC, DMA,    640(  1600),    640(  1600),  100(  256),  64000( 409600),   0,    c8000 ||||  L2, DMA,    640(  1600),    640(  1600),   80(  128),  64000( 409600),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    640(  1600),    640(  1600),  100(  256),  64000( 409600),   0,   190000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  109(TIDL_ConvolutionLayer) [109, 109] --[256 x 40 x  40] => [512 x 40 x  40] *** [256] ***[ROW_L] ***[82, 128, 41, 192, 1600]**** [9], [72],[72] -[108 ]---
  IN:MSMC, DMA,    640(  1600),    640(  1600),  100(  256),  64000( 409600),   0,   190000 ||||  L2, DMA,    240(   576),    240(   576),  100(  256),  24580( 148864),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    640(  1600),    640(  1600),  200(  512),  c8000( 819200),   0,    c8000 
  WT:DDR_PERSIST, DMA,    900(  2304),    900(  2304),  200(  512), 120800(1181696),   0,   591280 ||||  L2, DMA,    940(  2368),    900(  2304),   80(  128),  4a800( 305152),   0,    24580 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  110(TIDL_BatchNormLayer) [110, 110] --[512 x 40 x  40] => [512 x 40 x  40] *** [512] ***[ COL] ***[0, 0, 0, 1600, 1600]**** [4], [0],[4] -[109 ]---
  IN:MSMC, DMA,    640(  1600),    640(  1600),  200(  512),  c8000( 819200),   0,    c8000 ||||  L2, DMA,    640(  1600),    640(  1600),  100(  256),  64000( 409600),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    640(  1600),    640(  1600),  200(  512),  c8000( 819200),   0,   190000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  111(TIDL_EltWiseLayer) [111, 111] --[1024 x 40 x  40] => [512 x 40 x  40] *** [1024] ***[ COL] ***[0, 0, 0, 1600, 1600]**** [8], [0],[8] -[109 110 ]---
  IN:MSMC, DMA,    640(  1600),    640(  1600),  200(  512),  c8000( 819200),   0,    c8000 ||||  L2, DMA,    640(  1600),    640(  1600),   80(  128),  64000( 409600),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    640(  1600),    640(  1600),  200(  512),  c8000( 819200),   0,    c8000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  112(TIDL_EltWiseLayer) [112, 112] --[1024 x 40 x  40] => [512 x 40 x  40] *** [1024] ***[ COL] ***[0, 0, 0, 1600, 1600]**** [8], [0],[8] -[105 111 ]---
  IN:MSMC, DMA,    640(  1600),    640(  1600),  200(  512),  c8000( 819200),   0,        0 ||||  L2, DMA,    640(  1600),    640(  1600),   80(  128),  64000( 409600),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    640(  1600),    640(  1600),  200(  512),  c8000( 819200),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  113(TIDL_ConvolutionLayer) [113, 113] --[512 x 40 x  40] => [256 x 40 x  40] *** [512] ***[ROW_L] ***[0, 0, 0, 256, 1600]**** [7], [1],[7] -[112 ]---
  IN:MSMC, DMA,    640(  1600),    640(  1600),  200(  512),  c8000( 819200),   0,        0 ||||  L2, DMA,    240(   576),    240(   576),  200(  512),  48580( 296320),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    640(  1600),    640(  1600),  100(  256),  64000( 409600),   0,    c8000 
  WT:DDR_PERSIST, DMA,    200(   512),    200(   512),  100(  256),  20400( 132096),   0,   6b1a80 ||||  L2, DMA,    240(   576),    200(   512),  100(  256),  24400( 148480),   0,    48580 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  114(TIDL_BatchNormLayer) [114, 114] --[256 x 40 x  40] => [256 x 40 x  40] *** [256] ***[ COL] ***[0, 0, 0, 1600, 1600]**** [1], [0],[1] -[113 ]---
  IN:MSMC, DMA,    640(  1600),    640(  1600),  100(  256),  64000( 409600),   0,    c8000 ||||  L2, DMA,    640(  1600),    640(  1600),  100(  256),  64000( 409600),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    640(  1600),    640(  1600),  100(  256),  64000( 409600),   0,   12c000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  115(TIDL_EltWiseLayer) [115, 115] --[512 x 40 x  40] => [256 x 40 x  40] *** [512] ***[ COL] ***[0, 0, 0, 1600, 1600]**** [4], [0],[4] -[113 114 ]---
  IN:MSMC, DMA,    640(  1600),    640(  1600),  100(  256),  64000( 409600),   0,    c8000 ||||  L2, DMA,    640(  1600),    640(  1600),   80(  128),  64000( 409600),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    640(  1600),    640(  1600),  100(  256),  64000( 409600),   0,   190000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  116(TIDL_ConvolutionLayer) [116, 116] --[256 x 40 x  40] => [512 x 40 x  40] *** [256] ***[ROW_L] ***[82, 128, 41, 192, 1600]**** [9], [72],[72] -[115 ]---
  IN:MSMC, DMA,    640(  1600),    640(  1600),  100(  256),  64000( 409600),   0,   190000 ||||  L2, DMA,    240(   576),    240(   576),  100(  256),  24580( 148864),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    640(  1600),    640(  1600),  200(  512),  c8000( 819200),   0,    c8000 
  WT:DDR_PERSIST, DMA,    900(  2304),    900(  2304),  200(  512), 120800(1181696),   0,   6d1e80 ||||  L2, DMA,    940(  2368),    900(  2304),   80(  128),  4a800( 305152),   0,    24580 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  117(TIDL_BatchNormLayer) [117, 117] --[512 x 40 x  40] => [512 x 40 x  40] *** [512] ***[ COL] ***[0, 0, 0, 1600, 1600]**** [4], [0],[4] -[116 ]---
  IN:MSMC, DMA,    640(  1600),    640(  1600),  200(  512),  c8000( 819200),   0,    c8000 ||||  L2, DMA,    640(  1600),    640(  1600),  100(  256),  64000( 409600),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    640(  1600),    640(  1600),  200(  512),  c8000( 819200),   0,   190000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  118(TIDL_EltWiseLayer) [118, 118] --[1024 x 40 x  40] => [512 x 40 x  40] *** [1024] ***[ COL] ***[0, 0, 0, 1600, 1600]**** [8], [0],[8] -[116 117 ]---
  IN:MSMC, DMA,    640(  1600),    640(  1600),  200(  512),  c8000( 819200),   0,    c8000 ||||  L2, DMA,    640(  1600),    640(  1600),   80(  128),  64000( 409600),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    640(  1600),    640(  1600),  200(  512),  c8000( 819200),   0,    c8000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  119(TIDL_EltWiseLayer) [119, 119] --[1024 x 40 x  40] => [512 x 40 x  40] *** [1024] ***[ COL] ***[0, 0, 0, 1600, 1600]**** [8], [0],[8] -[112 118 ]---
  IN:MSMC, DMA,    640(  1600),    640(  1600),  200(  512),  c8000( 819200),   0,        0 ||||  L2, DMA,    640(  1600),    640(  1600),   80(  128),  64000( 409600),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    640(  1600),    640(  1600),  200(  512),  c8000( 819200),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  120(TIDL_ConvolutionLayer) [120, 120] --[512 x 40 x  40] => [256 x 40 x  40] *** [512] ***[ROW_L] ***[0, 0, 0, 256, 1600]**** [7], [1],[7] -[119 ]---
  IN:MSMC, DMA,    640(  1600),    640(  1600),  200(  512),  c8000( 819200),   0,        0 ||||  L2, DMA,    240(   576),    240(   576),  200(  512),  48580( 296320),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    640(  1600),    640(  1600),  100(  256),  64000( 409600),   0,    c8000 
  WT:DDR_PERSIST, DMA,    200(   512),    200(   512),  100(  256),  20400( 132096),   0,   7f2680 ||||  L2, DMA,    240(   576),    200(   512),  100(  256),  24400( 148480),   0,    48580 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  121(TIDL_BatchNormLayer) [121, 121] --[256 x 40 x  40] => [256 x 40 x  40] *** [256] ***[ COL] ***[0, 0, 0, 1600, 1600]**** [1], [0],[1] -[120 ]---
  IN:MSMC, DMA,    640(  1600),    640(  1600),  100(  256),  64000( 409600),   0,    c8000 ||||  L2, DMA,    640(  1600),    640(  1600),  100(  256),  64000( 409600),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    640(  1600),    640(  1600),  100(  256),  64000( 409600),   0,   12c000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  122(TIDL_EltWiseLayer) [122, 122] --[512 x 40 x  40] => [256 x 40 x  40] *** [512] ***[ COL] ***[0, 0, 0, 1600, 1600]**** [4], [0],[4] -[120 121 ]---
  IN:MSMC, DMA,    640(  1600),    640(  1600),  100(  256),  64000( 409600),   0,    c8000 ||||  L2, DMA,    640(  1600),    640(  1600),   80(  128),  64000( 409600),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    640(  1600),    640(  1600),  100(  256),  64000( 409600),   0,   190000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  123(TIDL_ConvolutionLayer) [123, 123] --[256 x 40 x  40] => [512 x 40 x  40] *** [256] ***[ROW_L] ***[82, 128, 41, 192, 1600]**** [9], [72],[72] -[122 ]---
  IN:MSMC, DMA,    640(  1600),    640(  1600),  100(  256),  64000( 409600),   0,   190000 ||||  L2, DMA,    240(   576),    240(   576),  100(  256),  24580( 148864),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    640(  1600),    640(  1600),  200(  512),  c8000( 819200),   0,    c8000 
  WT:DDR_PERSIST, DMA,    900(  2304),    900(  2304),  200(  512), 120800(1181696),   0,   812a80 ||||  L2, DMA,    940(  2368),    900(  2304),   80(  128),  4a800( 305152),   0,    24580 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  124(TIDL_BatchNormLayer) [124, 124] --[512 x 40 x  40] => [512 x 40 x  40] *** [512] ***[ COL] ***[0, 0, 0, 1600, 1600]**** [4], [0],[4] -[123 ]---
  IN:MSMC, DMA,    640(  1600),    640(  1600),  200(  512),  c8000( 819200),   0,    c8000 ||||  L2, DMA,    640(  1600),    640(  1600),  100(  256),  64000( 409600),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    640(  1600),    640(  1600),  200(  512),  c8000( 819200),   0,   190000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  125(TIDL_EltWiseLayer) [125, 125] --[1024 x 40 x  40] => [512 x 40 x  40] *** [1024] ***[ COL] ***[0, 0, 0, 1600, 1600]**** [8], [0],[8] -[123 124 ]---
  IN:MSMC, DMA,    640(  1600),    640(  1600),  200(  512),  c8000( 819200),   0,    c8000 ||||  L2, DMA,    640(  1600),    640(  1600),   80(  128),  64000( 409600),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    640(  1600),    640(  1600),  200(  512),  c8000( 819200),   0,    c8000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  126(TIDL_EltWiseLayer) [126, 126] --[1024 x 40 x  40] => [512 x 40 x  40] *** [1024] ***[ COL] ***[0, 0, 0, 1600, 1600]**** [8], [0],[8] -[119 125 ]---
  IN:MSMC, DMA,    640(  1600),    640(  1600),  200(  512),  c8000( 819200),   0,        0 ||||  L2, DMA,    640(  1600),    640(  1600),   80(  128),  64000( 409600),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    640(  1600),    640(  1600),  200(  512),  c8000( 819200),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  127(TIDL_ConvolutionLayer) [127, 127] --[512 x 40 x  40] => [256 x 40 x  40] *** [512] ***[ROW_L] ***[0, 0, 0, 256, 1600]**** [7], [1],[7] -[126 ]---
  IN:MSMC, DMA,    640(  1600),    640(  1600),  200(  512),  c8000( 819200),   0,        0 ||||  L2, DMA,    240(   576),    240(   576),  200(  512),  48580( 296320),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    640(  1600),    640(  1600),  100(  256),  64000( 409600),   0,    c8000 
  WT:DDR_PERSIST, DMA,    200(   512),    200(   512),  100(  256),  20400( 132096),   0,   933280 ||||  L2, DMA,    240(   576),    200(   512),  100(  256),  24400( 148480),   0,    48580 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  128(TIDL_BatchNormLayer) [128, 128] --[256 x 40 x  40] => [256 x 40 x  40] *** [256] ***[ COL] ***[0, 0, 0, 1600, 1600]**** [1], [0],[1] -[127 ]---
  IN:MSMC, DMA,    640(  1600),    640(  1600),  100(  256),  64000( 409600),   0,    c8000 ||||  L2, DMA,    640(  1600),    640(  1600),  100(  256),  64000( 409600),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    640(  1600),    640(  1600),  100(  256),  64000( 409600),   0,   12c000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  129(TIDL_EltWiseLayer) [129, 129] --[512 x 40 x  40] => [256 x 40 x  40] *** [512] ***[ COL] ***[0, 0, 0, 1600, 1600]**** [4], [0],[4] -[127 128 ]---
  IN:MSMC, DMA,    640(  1600),    640(  1600),  100(  256),  64000( 409600),   0,    c8000 ||||  L2, DMA,    640(  1600),    640(  1600),   80(  128),  64000( 409600),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    640(  1600),    640(  1600),  100(  256),  64000( 409600),   0,   190000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  130(TIDL_ConvolutionLayer) [130, 130] --[256 x 40 x  40] => [512 x 40 x  40] *** [256] ***[ROW_L] ***[82, 128, 41, 192, 1600]**** [9], [72],[72] -[129 ]---
  IN:MSMC, DMA,    640(  1600),    640(  1600),  100(  256),  64000( 409600),   0,   190000 ||||  L2, DMA,    240(   576),    240(   576),  100(  256),  24580( 148864),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    640(  1600),    640(  1600),  200(  512),  c8000( 819200),   0,    c8000 
  WT:DDR_PERSIST, DMA,    900(  2304),    900(  2304),  200(  512), 120800(1181696),   0,   953680 ||||  L2, DMA,    940(  2368),    900(  2304),   80(  128),  4a800( 305152),   0,    24580 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  131(TIDL_BatchNormLayer) [131, 131] --[512 x 40 x  40] => [512 x 40 x  40] *** [512] ***[ COL] ***[0, 0, 0, 1600, 1600]**** [4], [0],[4] -[130 ]---
  IN:MSMC, DMA,    640(  1600),    640(  1600),  200(  512),  c8000( 819200),   0,    c8000 ||||  L2, DMA,    640(  1600),    640(  1600),  100(  256),  64000( 409600),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    640(  1600),    640(  1600),  200(  512),  c8000( 819200),   0,   190000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  132(TIDL_EltWiseLayer) [132, 132] --[1024 x 40 x  40] => [512 x 40 x  40] *** [1024] ***[ COL] ***[0, 0, 0, 1600, 1600]**** [8], [0],[8] -[130 131 ]---
  IN:MSMC, DMA,    640(  1600),    640(  1600),  200(  512),  c8000( 819200),   0,    c8000 ||||  L2, DMA,    640(  1600),    640(  1600),   80(  128),  64000( 409600),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    640(  1600),    640(  1600),  200(  512),  c8000( 819200),   0,    c8000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  133(TIDL_EltWiseLayer) [133, 133] --[1024 x 40 x  40] => [512 x 40 x  40] *** [1024] ***[ COL] ***[0, 0, 0, 1600, 1600]**** [8], [0],[8] -[126 132 ]---
  IN:MSMC, DMA,    640(  1600),    640(  1600),  200(  512),  c8000( 819200),   0,        0 ||||  L2, DMA,    640(  1600),    640(  1600),   80(  128),  64000( 409600),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    640(  1600),    640(  1600),  200(  512),  c8000( 819200),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  134(TIDL_ConvolutionLayer) [134, 134] --[512 x 40 x  40] => [256 x 40 x  40] *** [512] ***[ROW_L] ***[0, 0, 0, 256, 1600]**** [7], [1],[7] -[133 ]---
  IN:MSMC, DMA,    640(  1600),    640(  1600),  200(  512),  c8000( 819200),   0,        0 ||||  L2, DMA,    240(   576),    240(   576),  200(  512),  48580( 296320),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    640(  1600),    640(  1600),  100(  256),  64000( 409600),   0,    c8000 
  WT:DDR_PERSIST, DMA,    200(   512),    200(   512),  100(  256),  20400( 132096),   0,   a73e80 ||||  L2, DMA,    240(   576),    200(   512),  100(  256),  24400( 148480),   0,    48580 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  135(TIDL_BatchNormLayer) [135, 135] --[256 x 40 x  40] => [256 x 40 x  40] *** [256] ***[ COL] ***[0, 0, 0, 1600, 1600]**** [1], [0],[1] -[134 ]---
  IN:MSMC, DMA,    640(  1600),    640(  1600),  100(  256),  64000( 409600),   0,    c8000 ||||  L2, DMA,    640(  1600),    640(  1600),  100(  256),  64000( 409600),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    640(  1600),    640(  1600),  100(  256),  64000( 409600),   0,   12c000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  136(TIDL_EltWiseLayer) [136, 136] --[512 x 40 x  40] => [256 x 40 x  40] *** [512] ***[ COL] ***[0, 0, 0, 1600, 1600]**** [4], [0],[4] -[134 135 ]---
  IN:MSMC, DMA,    640(  1600),    640(  1600),  100(  256),  64000( 409600),   0,    c8000 ||||  L2, DMA,    640(  1600),    640(  1600),   80(  128),  64000( 409600),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    640(  1600),    640(  1600),  100(  256),  64000( 409600),   0,   190000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  137(TIDL_ConvolutionLayer) [137, 137] --[256 x 40 x  40] => [512 x 40 x  40] *** [256] ***[ROW_L] ***[82, 128, 41, 192, 1600]**** [9], [72],[72] -[136 ]---
  IN:MSMC, DMA,    640(  1600),    640(  1600),  100(  256),  64000( 409600),   0,   190000 ||||  L2, DMA,    240(   576),    240(   576),  100(  256),  24580( 148864),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    640(  1600),    640(  1600),  200(  512),  c8000( 819200),   0,    c8000 
  WT:DDR_PERSIST, DMA,    900(  2304),    900(  2304),  200(  512), 120800(1181696),   0,   a94280 ||||  L2, DMA,    940(  2368),    900(  2304),   80(  128),  4a800( 305152),   0,    24580 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  138(TIDL_BatchNormLayer) [138, 138] --[512 x 40 x  40] => [512 x 40 x  40] *** [512] ***[ COL] ***[0, 0, 0, 1600, 1600]**** [4], [0],[4] -[137 ]---
  IN:MSMC, DMA,    640(  1600),    640(  1600),  200(  512),  c8000( 819200),   0,    c8000 ||||  L2, DMA,    640(  1600),    640(  1600),  100(  256),  64000( 409600),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    640(  1600),    640(  1600),  200(  512),  c8000( 819200),   0,   190000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  139(TIDL_EltWiseLayer) [139, 139] --[1024 x 40 x  40] => [512 x 40 x  40] *** [1024] ***[ COL] ***[0, 0, 0, 1600, 1600]**** [8], [0],[8] -[137 138 ]---
  IN:MSMC, DMA,    640(  1600),    640(  1600),  200(  512),  c8000( 819200),   0,    c8000 ||||  L2, DMA,    640(  1600),    640(  1600),   80(  128),  64000( 409600),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    640(  1600),    640(  1600),  200(  512),  c8000( 819200),   0,    c8000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  140(TIDL_EltWiseLayer) [140, 140] --[1024 x 40 x  40] => [512 x 40 x  40] *** [1024] ***[ COL] ***[0, 0, 0, 1600, 1600]**** [8], [0],[8] -[133 139 ]---
  IN:MSMC, DMA,    640(  1600),    640(  1600),  200(  512),  c8000( 819200),   0,        0 ||||  L2, DMA,    640(  1600),    640(  1600),   80(  128),  64000( 409600),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    640(  1600),    640(  1600),  200(  512),  c8000( 819200),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  141(TIDL_ConvolutionLayer) [141, 141] --[512 x 40 x  40] => [256 x 40 x  40] *** [512] ***[ROW_L] ***[0, 0, 0, 256, 1600]**** [7], [1],[7] -[140 ]---
  IN:MSMC, DMA,    640(  1600),    640(  1600),  200(  512),  c8000( 819200),   0,        0 ||||  L2, DMA,    240(   576),    240(   576),  200(  512),  48580( 296320),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    640(  1600),    640(  1600),  100(  256),  64000( 409600),   0,    c8000 
  WT:DDR_PERSIST, DMA,    200(   512),    200(   512),  100(  256),  20400( 132096),   0,   bb4a80 ||||  L2, DMA,    240(   576),    200(   512),  100(  256),  24400( 148480),   0,    48580 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  142(TIDL_BatchNormLayer) [142, 142] --[256 x 40 x  40] => [256 x 40 x  40] *** [256] ***[ COL] ***[0, 0, 0, 1600, 1600]**** [1], [0],[1] -[141 ]---
  IN:MSMC, DMA,    640(  1600),    640(  1600),  100(  256),  64000( 409600),   0,    c8000 ||||  L2, DMA,    640(  1600),    640(  1600),  100(  256),  64000( 409600),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    640(  1600),    640(  1600),  100(  256),  64000( 409600),   0,   12c000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  143(TIDL_EltWiseLayer) [143, 143] --[512 x 40 x  40] => [256 x 40 x  40] *** [512] ***[ COL] ***[0, 0, 0, 1600, 1600]**** [4], [0],[4] -[141 142 ]---
  IN:MSMC, DMA,    640(  1600),    640(  1600),  100(  256),  64000( 409600),   0,    c8000 ||||  L2, DMA,    640(  1600),    640(  1600),   80(  128),  64000( 409600),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    640(  1600),    640(  1600),  100(  256),  64000( 409600),   0,   190000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  144(TIDL_ConvolutionLayer) [144, 144] --[256 x 40 x  40] => [512 x 40 x  40] *** [256] ***[ROW_L] ***[82, 128, 41, 192, 1600]**** [9], [72],[72] -[143 ]---
  IN:MSMC, DMA,    640(  1600),    640(  1600),  100(  256),  64000( 409600),   0,   190000 ||||  L2, DMA,    240(   576),    240(   576),  100(  256),  24580( 148864),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    640(  1600),    640(  1600),  200(  512),  c8000( 819200),   0,    c8000 
  WT:DDR_PERSIST, DMA,    900(  2304),    900(  2304),  200(  512), 120800(1181696),   0,   bd4e80 ||||  L2, DMA,    940(  2368),    900(  2304),   80(  128),  4a800( 305152),   0,    24580 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  145(TIDL_BatchNormLayer) [145, 145] --[512 x 40 x  40] => [512 x 40 x  40] *** [512] ***[ COL] ***[0, 0, 0, 1600, 1600]**** [4], [0],[4] -[144 ]---
  IN:MSMC, DMA,    640(  1600),    640(  1600),  200(  512),  c8000( 819200),   0,    c8000 ||||  L2, DMA,    640(  1600),    640(  1600),  100(  256),  64000( 409600),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    640(  1600),    640(  1600),  200(  512),  c8000( 819200),   0,   190000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  146(TIDL_EltWiseLayer) [146, 146] --[1024 x 40 x  40] => [512 x 40 x  40] *** [1024] ***[ COL] ***[0, 0, 0, 1600, 1600]**** [8], [0],[8] -[144 145 ]---
  IN:MSMC, DMA,    640(  1600),    640(  1600),  200(  512),  c8000( 819200),   0,    c8000 ||||  L2, DMA,    640(  1600),    640(  1600),   80(  128),  64000( 409600),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    640(  1600),    640(  1600),  200(  512),  c8000( 819200),   0,    c8000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  147(TIDL_EltWiseLayer) [147, 147] --[1024 x 40 x  40] => [512 x 40 x  40] *** [1024] ***[ COL] ***[0, 0, 0, 1600, 1600]**** [8], [0],[8] -[140 146 ]---
  IN:MSMC, DMA,    640(  1600),    640(  1600),  200(  512),  c8000( 819200),   0,        0 ||||  L2, DMA,    640(  1600),    640(  1600),   80(  128),  64000( 409600),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    640(  1600),    640(  1600),  200(  512),  c8000( 819200),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  148(TIDL_ConvolutionLayer) [148, 148] --[512 x 40 x  40] => [256 x 40 x  40] *** [512] ***[ROW_L] ***[0, 0, 0, 256, 1600]**** [7], [1],[7] -[147 ]---
  IN:MSMC, DMA,    640(  1600),    640(  1600),  200(  512),  c8000( 819200),   0,        0 ||||  L2, DMA,    240(   576),    240(   576),  200(  512),  48580( 296320),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    640(  1600),    640(  1600),  100(  256),  64000( 409600),   0,    c8000 
  WT:DDR_PERSIST, DMA,    200(   512),    200(   512),  100(  256),  20400( 132096),   0,   cf5680 ||||  L2, DMA,    240(   576),    200(   512),  100(  256),  24400( 148480),   0,    48580 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  149(TIDL_BatchNormLayer) [149, 149] --[256 x 40 x  40] => [256 x 40 x  40] *** [256] ***[ COL] ***[0, 0, 0, 1600, 1600]**** [1], [0],[1] -[148 ]---
  IN:MSMC, DMA,    640(  1600),    640(  1600),  100(  256),  64000( 409600),   0,    c8000 ||||  L2, DMA,    640(  1600),    640(  1600),  100(  256),  64000( 409600),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    640(  1600),    640(  1600),  100(  256),  64000( 409600),   0,   12c000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  150(TIDL_EltWiseLayer) [150, 150] --[512 x 40 x  40] => [256 x 40 x  40] *** [512] ***[ COL] ***[0, 0, 0, 1600, 1600]**** [4], [0],[4] -[148 149 ]---
  IN:MSMC, DMA,    640(  1600),    640(  1600),  100(  256),  64000( 409600),   0,    c8000 ||||  L2, DMA,    640(  1600),    640(  1600),   80(  128),  64000( 409600),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    640(  1600),    640(  1600),  100(  256),  64000( 409600),   0,   190000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  151(TIDL_ConvolutionLayer) [151, 151] --[256 x 40 x  40] => [512 x 40 x  40] *** [256] ***[ROW_L] ***[82, 128, 41, 192, 1600]**** [9], [72],[72] -[150 ]---
  IN:MSMC, DMA,    640(  1600),    640(  1600),  100(  256),  64000( 409600),   0,   190000 ||||  L2, DMA,    240(   576),    240(   576),  100(  256),  24580( 148864),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    640(  1600),    640(  1600),  200(  512),  c8000( 819200),   0,    c8000 
  WT:DDR_PERSIST, DMA,    900(  2304),    900(  2304),  200(  512), 120800(1181696),   0,   d15a80 ||||  L2, DMA,    940(  2368),    900(  2304),   80(  128),  4a800( 305152),   0,    24580 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  152(TIDL_BatchNormLayer) [152, 152] --[512 x 40 x  40] => [512 x 40 x  40] *** [512] ***[ COL] ***[0, 0, 0, 1600, 1600]**** [4], [0],[4] -[151 ]---
  IN:MSMC, DMA,    640(  1600),    640(  1600),  200(  512),  c8000( 819200),   0,    c8000 ||||  L2, DMA,    640(  1600),    640(  1600),  100(  256),  64000( 409600),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    640(  1600),    640(  1600),  200(  512),  c8000( 819200),   0,   190000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  153(TIDL_EltWiseLayer) [153, 153] --[1024 x 40 x  40] => [512 x 40 x  40] *** [1024] ***[ COL] ***[0, 0, 0, 1600, 1600]**** [8], [0],[8] -[151 152 ]---
  IN:MSMC, DMA,    640(  1600),    640(  1600),  200(  512),  c8000( 819200),   0,    c8000 ||||  L2, DMA,    640(  1600),    640(  1600),   80(  128),  64000( 409600),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    640(  1600),    640(  1600),  200(  512),  c8000( 819200),   0,    c8000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  154(TIDL_EltWiseLayer) [154, 154] --[1024 x 40 x  40] => [512 x 40 x  40] *** [1024] ***[ COL] ***[0, 0, 0, 1600, 1600]**** [8], [0],[8] -[147 153 ]---
  IN:MSMC, DMA,    640(  1600),    640(  1600),  200(  512),  c8000( 819200),   0,        0 ||||  L2, DMA,    640(  1600),    640(  1600),   80(  128),  64000( 409600),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    640(  1600),    640(  1600),  200(  512),  c8000( 819200),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  155(TIDL_ConvolutionLayer) [155, 155] --[512 x 40 x  40] => [1024 x 20 x  20] *** [512] ***[ROW_L] ***[40, 40, 0, 80, 1600]**** [20], [640],[640] -[154 ]---
  IN:MSMC, DMA,    640(  1600),    640(  1600),  200(  512),  c8000( 819200),   0,        0 ||||  L2, DMA,    100(   256),    100(   256),  200(  512),  20600( 132608),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    1b9(   441),  400( 1024),  70014( 458772),  14,    c806c 
  WT:DDR_PERSIST, DMA,   1200(  4608),   1200(  4608),  400( 1024), 481000(4722688),   0,   e36280 ||||  L2, DMA,   1240(  4672),   1200(  4608),   40(   64),  4a000( 303104),   0,    20600 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  156(TIDL_BatchNormLayer) [156, 156] --[1024 x 20 x  20] => [1024 x 20 x  20] *** [1024] ***[ COL] ***[0, 0, 0, 400, 400]**** [4], [0],[4] -[155 ]---
  IN:MSMC, DMA,    1c0(   448),    1b9(   441),  400( 1024),  70014( 458772),  14,    c806c ||||  L2, DMA,    1cc(   460),    1cc(   460),  200(  512),  39800( 235520),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    1b8(   440),  400( 1024),  70014( 458772),  14,   1380ec 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  157(TIDL_EltWiseLayer) [157, 157] --[2048 x 20 x  20] => [1024 x 20 x  20] *** [2048] ***[ COL] ***[0, 0, 0, 400, 400]**** [8], [0],[8] -[155 156 ]---
  IN:MSMC, DMA,    1c0(   448),    1b9(   441),  400( 1024),  70014( 458772),  14,    c806c ||||  L2, DMA,    1cc(   460),    1cc(   460),  100(  256),  39800( 235520),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    1b8(   440),  400( 1024),  70014( 458772),  14,    c806c 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  158(TIDL_ConvolutionLayer) [158, 158] --[1024 x 20 x  20] => [512 x 20 x  20] *** [1024] ***[ROW_L] ***[0, 0, 0, 64, 400]**** [7], [56],[56] -[157 ]---
  IN:MSMC, DMA,    1c0(   448),    1b8(   440),  400( 1024),  70014( 458772),  14,    c806c ||||  L2, DMA,     c0(   192),     c0(   192),  400( 1024),  30180( 196992),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    1b8(   440),  200(  512),  38014( 229396),  14,   1380ec 
  WT:DDR_PERSIST, DMA,    400(  1024),    400(  1024),  200(  512),  80800( 526336),   0,  12b7280 ||||  L2, DMA,    440(  1088),    400(  1024),   80(  128),  22800( 141312),   0,    30180 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  159(TIDL_BatchNormLayer) [159, 159] --[512 x 20 x  20] => [512 x 20 x  20] *** [512] ***[ COL] ***[0, 0, 0, 400, 400]**** [1], [0],[1] -[158 ]---
  IN:MSMC, DMA,    1c0(   448),    1b8(   440),  200(  512),  38014( 229396),  14,   1380ec ||||  L2, DMA,    1cc(   460),    1cc(   460),  200(  512),  39800( 235520),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    1b8(   440),  200(  512),  38014( 229396),  14,   1a816c 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  160(TIDL_EltWiseLayer) [160, 160] --[1024 x 20 x  20] => [512 x 20 x  20] *** [1024] ***[ COL] ***[0, 0, 0, 400, 400]**** [4], [0],[4] -[158 159 ]---
  IN:MSMC, DMA,    1c0(   448),    1b8(   440),  200(  512),  38014( 229396),  14,   1380ec ||||  L2, DMA,    1cc(   460),    1cc(   460),  100(  256),  39800( 235520),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    1b8(   440),  200(  512),  38014( 229396),  14,   1a816c 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  161(TIDL_ConvolutionLayer) [161, 161] --[512 x 20 x  20] => [1024 x 20 x  20] *** [512] ***[ROW_L] ***[42, 64, 21, 64, 400]**** [6], [192],[192] -[160 ]---
  IN:MSMC, DMA,    1c0(   448),    1b8(   440),  200(  512),  38014( 229396),  14,   1a816c ||||  L2, DMA,     c0(   192),     c0(   192),  200(  512),  18180(  98688),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    1b8(   440),  400( 1024),  70014( 458772),  14,   1380ec 
  WT:DDR_PERSIST, DMA,   1200(  4608),   1200(  4608),  400( 1024), 481000(4722688),   0,  1337a80 ||||  L2, DMA,   1240(  4672),   1200(  4608),   40(   64),  4a000( 303104),   0,    18180 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  162(TIDL_BatchNormLayer) [162, 162] --[1024 x 20 x  20] => [1024 x 20 x  20] *** [1024] ***[ COL] ***[0, 0, 0, 400, 400]**** [4], [0],[4] -[161 ]---
  IN:MSMC, DMA,    1c0(   448),    1b8(   440),  400( 1024),  70014( 458772),  14,   1380ec ||||  L2, DMA,    1cc(   460),    1cc(   460),  200(  512),  39800( 235520),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    1b8(   440),  400( 1024),  70014( 458772),  14,   1a816c 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  163(TIDL_EltWiseLayer) [163, 163] --[2048 x 20 x  20] => [1024 x 20 x  20] *** [2048] ***[ COL] ***[0, 0, 0, 400, 400]**** [8], [0],[8] -[161 162 ]---
  IN:MSMC, DMA,    1c0(   448),    1b8(   440),  400( 1024),  70014( 458772),  14,   1380ec ||||  L2, DMA,    1cc(   460),    1cc(   460),  100(  256),  39800( 235520),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    1b8(   440),  400( 1024),  70014( 458772),  14,   1380ec 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  164(TIDL_EltWiseLayer) [164, 164] --[2048 x 20 x  20] => [1024 x 20 x  20] *** [2048] ***[ COL] ***[0, 0, 0, 400, 400]**** [8], [0],[8] -[157 163 ]---
  IN:MSMC, DMA,    1c0(   448),    1b8(   440),  400( 1024),  70014( 458772),  14,    c806c ||||  L2, DMA,    1cc(   460),    1cc(   460),  100(  256),  39800( 235520),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    1b8(   440),  400( 1024),  70014( 458772),  14,    c806c 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  165(TIDL_ConvolutionLayer) [165, 165] --[1024 x 20 x  20] => [512 x 20 x  20] *** [1024] ***[ROW_L] ***[0, 0, 0, 64, 400]**** [7], [56],[56] -[164 ]---
  IN:MSMC, DMA,    1c0(   448),    1b8(   440),  400( 1024),  70014( 458772),  14,    c806c ||||  L2, DMA,     c0(   192),     c0(   192),  400( 1024),  30180( 196992),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    1b8(   440),  200(  512),  38014( 229396),  14,   1380ec 
  WT:DDR_PERSIST, DMA,    400(  1024),    400(  1024),  200(  512),  80800( 526336),   0,  17b8a80 ||||  L2, DMA,    440(  1088),    400(  1024),   80(  128),  22800( 141312),   0,    30180 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  166(TIDL_BatchNormLayer) [166, 166] --[512 x 20 x  20] => [512 x 20 x  20] *** [512] ***[ COL] ***[0, 0, 0, 400, 400]**** [1], [0],[1] -[165 ]---
  IN:MSMC, DMA,    1c0(   448),    1b8(   440),  200(  512),  38014( 229396),  14,   1380ec ||||  L2, DMA,    1cc(   460),    1cc(   460),  200(  512),  39800( 235520),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    1b8(   440),  200(  512),  38014( 229396),  14,   1a816c 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  167(TIDL_EltWiseLayer) [167, 167] --[1024 x 20 x  20] => [512 x 20 x  20] *** [1024] ***[ COL] ***[0, 0, 0, 400, 400]**** [4], [0],[4] -[165 166 ]---
  IN:MSMC, DMA,    1c0(   448),    1b8(   440),  200(  512),  38014( 229396),  14,   1380ec ||||  L2, DMA,    1cc(   460),    1cc(   460),  100(  256),  39800( 235520),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    1b8(   440),  200(  512),  38014( 229396),  14,   1a816c 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  168(TIDL_ConvolutionLayer) [168, 168] --[512 x 20 x  20] => [1024 x 20 x  20] *** [512] ***[ROW_L] ***[42, 64, 21, 64, 400]**** [6], [192],[192] -[167 ]---
  IN:MSMC, DMA,    1c0(   448),    1b8(   440),  200(  512),  38014( 229396),  14,   1a816c ||||  L2, DMA,     c0(   192),     c0(   192),  200(  512),  18180(  98688),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    1b8(   440),  400( 1024),  70014( 458772),  14,   1380ec 
  WT:DDR_PERSIST, DMA,   1200(  4608),   1200(  4608),  400( 1024), 481000(4722688),   0,  1839280 ||||  L2, DMA,   1240(  4672),   1200(  4608),   40(   64),  4a000( 303104),   0,    18180 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  169(TIDL_BatchNormLayer) [169, 169] --[1024 x 20 x  20] => [1024 x 20 x  20] *** [1024] ***[ COL] ***[0, 0, 0, 400, 400]**** [4], [0],[4] -[168 ]---
  IN:MSMC, DMA,    1c0(   448),    1b8(   440),  400( 1024),  70014( 458772),  14,   1380ec ||||  L2, DMA,    1cc(   460),    1cc(   460),  200(  512),  39800( 235520),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    1b8(   440),  400( 1024),  70014( 458772),  14,   1a816c 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  170(TIDL_EltWiseLayer) [170, 170] --[2048 x 20 x  20] => [1024 x 20 x  20] *** [2048] ***[ COL] ***[0, 0, 0, 400, 400]**** [8], [0],[8] -[168 169 ]---
  IN:MSMC, DMA,    1c0(   448),    1b8(   440),  400( 1024),  70014( 458772),  14,   1380ec ||||  L2, DMA,    1cc(   460),    1cc(   460),  100(  256),  39800( 235520),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    1b8(   440),  400( 1024),  70014( 458772),  14,   1380ec 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  171(TIDL_EltWiseLayer) [171, 171] --[2048 x 20 x  20] => [1024 x 20 x  20] *** [2048] ***[ COL] ***[0, 0, 0, 400, 400]**** [8], [0],[8] -[164 170 ]---
  IN:MSMC, DMA,    1c0(   448),    1b8(   440),  400( 1024),  70014( 458772),  14,    c806c ||||  L2, DMA,    1cc(   460),    1cc(   460),  100(  256),  39800( 235520),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    1b8(   440),  400( 1024),  70014( 458772),  14,    c806c 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  172(TIDL_ConvolutionLayer) [172, 172] --[1024 x 20 x  20] => [512 x 20 x  20] *** [1024] ***[ROW_L] ***[0, 0, 0, 64, 400]**** [7], [56],[56] -[171 ]---
  IN:MSMC, DMA,    1c0(   448),    1b8(   440),  400( 1024),  70014( 458772),  14,    c806c ||||  L2, DMA,     c0(   192),     c0(   192),  400( 1024),  30180( 196992),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    1b8(   440),  200(  512),  38014( 229396),  14,   1380ec 
  WT:DDR_PERSIST, DMA,    400(  1024),    400(  1024),  200(  512),  80800( 526336),   0,  1cba280 ||||  L2, DMA,    440(  1088),    400(  1024),   80(  128),  22800( 141312),   0,    30180 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  173(TIDL_BatchNormLayer) [173, 173] --[512 x 20 x  20] => [512 x 20 x  20] *** [512] ***[ COL] ***[0, 0, 0, 400, 400]**** [1], [0],[1] -[172 ]---
  IN:MSMC, DMA,    1c0(   448),    1b8(   440),  200(  512),  38014( 229396),  14,   1380ec ||||  L2, DMA,    1cc(   460),    1cc(   460),  200(  512),  39800( 235520),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    1b8(   440),  200(  512),  38014( 229396),  14,   1a816c 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  174(TIDL_EltWiseLayer) [174, 174] --[1024 x 20 x  20] => [512 x 20 x  20] *** [1024] ***[ COL] ***[0, 0, 0, 400, 400]**** [4], [0],[4] -[172 173 ]---
  IN:MSMC, DMA,    1c0(   448),    1b8(   440),  200(  512),  38014( 229396),  14,   1380ec ||||  L2, DMA,    1cc(   460),    1cc(   460),  100(  256),  39800( 235520),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    1b8(   440),  200(  512),  38014( 229396),  14,   1a816c 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  175(TIDL_ConvolutionLayer) [175, 175] --[512 x 20 x  20] => [1024 x 20 x  20] *** [512] ***[ROW_L] ***[42, 64, 21, 64, 400]**** [6], [192],[192] -[174 ]---
  IN:MSMC, DMA,    1c0(   448),    1b8(   440),  200(  512),  38014( 229396),  14,   1a816c ||||  L2, DMA,     c0(   192),     c0(   192),  200(  512),  18180(  98688),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    1b8(   440),  400( 1024),  70014( 458772),  14,   1380ec 
  WT:DDR_PERSIST, DMA,   1200(  4608),   1200(  4608),  400( 1024), 481000(4722688),   0,  1d3aa80 ||||  L2, DMA,   1240(  4672),   1200(  4608),   40(   64),  4a000( 303104),   0,    18180 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  176(TIDL_BatchNormLayer) [176, 176] --[1024 x 20 x  20] => [1024 x 20 x  20] *** [1024] ***[ COL] ***[0, 0, 0, 400, 400]**** [4], [0],[4] -[175 ]---
  IN:MSMC, DMA,    1c0(   448),    1b8(   440),  400( 1024),  70014( 458772),  14,   1380ec ||||  L2, DMA,    1cc(   460),    1cc(   460),  200(  512),  39800( 235520),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    1b8(   440),  400( 1024),  70014( 458772),  14,   1a816c 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  177(TIDL_EltWiseLayer) [177, 177] --[2048 x 20 x  20] => [1024 x 20 x  20] *** [2048] ***[ COL] ***[0, 0, 0, 400, 400]**** [8], [0],[8] -[175 176 ]---
  IN:MSMC, DMA,    1c0(   448),    1b8(   440),  400( 1024),  70014( 458772),  14,   1380ec ||||  L2, DMA,    1cc(   460),    1cc(   460),  100(  256),  39800( 235520),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    1b8(   440),  400( 1024),  70014( 458772),  14,   1380ec 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  178(TIDL_EltWiseLayer) [178, 178] --[2048 x 20 x  20] => [1024 x 20 x  20] *** [2048] ***[ COL] ***[0, 0, 0, 400, 400]**** [8], [0],[8] -[171 177 ]---
  IN:MSMC, DMA,    1c0(   448),    1b8(   440),  400( 1024),  70014( 458772),  14,    c806c ||||  L2, DMA,    1cc(   460),    1cc(   460),  100(  256),  39800( 235520),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    1b8(   440),  400( 1024),  70014( 458772),  14,    c806c 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  179(TIDL_ConvolutionLayer) [179, 179] --[1024 x 20 x  20] => [512 x 20 x  20] *** [1024] ***[ROW_L] ***[0, 0, 0, 64, 400]**** [7], [56],[56] -[178 ]---
  IN:MSMC, DMA,    1c0(   448),    1b8(   440),  400( 1024),  70014( 458772),  14,    c806c ||||  L2, DMA,     c0(   192),     c0(   192),  400( 1024),  30180( 196992),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    1b8(   440),  200(  512),  38014( 229396),  14,   1380ec 
  WT:DDR_PERSIST, DMA,    400(  1024),    400(  1024),  200(  512),  80800( 526336),   0,  21bba80 ||||  L2, DMA,    440(  1088),    400(  1024),   80(  128),  22800( 141312),   0,    30180 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  180(TIDL_BatchNormLayer) [180, 180] --[512 x 20 x  20] => [512 x 20 x  20] *** [512] ***[ COL] ***[0, 0, 0, 400, 400]**** [1], [0],[1] -[179 ]---
  IN:MSMC, DMA,    1c0(   448),    1b8(   440),  200(  512),  38014( 229396),  14,   1380ec ||||  L2, DMA,    1cc(   460),    1cc(   460),  200(  512),  39800( 235520),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    1b8(   440),  200(  512),  38014( 229396),  14,   1a816c 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  181(TIDL_EltWiseLayer) [181, 181] --[1024 x 20 x  20] => [512 x 20 x  20] *** [1024] ***[ COL] ***[0, 0, 0, 400, 400]**** [4], [0],[4] -[179 180 ]---
  IN:MSMC, DMA,    1c0(   448),    1b8(   440),  200(  512),  38014( 229396),  14,   1380ec ||||  L2, DMA,    1cc(   460),    1cc(   460),  100(  256),  39800( 235520),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    1b8(   440),  200(  512),  38014( 229396),  14,   1a816c 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  182(TIDL_ConvolutionLayer) [182, 182] --[512 x 20 x  20] => [1024 x 20 x  20] *** [512] ***[ROW_L] ***[42, 64, 21, 64, 400]**** [6], [192],[192] -[181 ]---
  IN:MSMC, DMA,    1c0(   448),    1b8(   440),  200(  512),  38014( 229396),  14,   1a816c ||||  L2, DMA,     c0(   192),     c0(   192),  200(  512),  18180(  98688),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    1b8(   440),  400( 1024),  70014( 458772),  14,   1380ec 
  WT:DDR_PERSIST, DMA,   1200(  4608),   1200(  4608),  400( 1024), 481000(4722688),   0,  223c280 ||||  L2, DMA,   1240(  4672),   1200(  4608),   40(   64),  4a000( 303104),   0,    18180 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  183(TIDL_BatchNormLayer) [183, 183] --[1024 x 20 x  20] => [1024 x 20 x  20] *** [1024] ***[ COL] ***[0, 0, 0, 400, 400]**** [4], [0],[4] -[182 ]---
  IN:MSMC, DMA,    1c0(   448),    1b8(   440),  400( 1024),  70014( 458772),  14,   1380ec ||||  L2, DMA,    1cc(   460),    1cc(   460),  200(  512),  39800( 235520),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    1b8(   440),  400( 1024),  70014( 458772),  14,   1a816c 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  184(TIDL_EltWiseLayer) [184, 184] --[2048 x 20 x  20] => [1024 x 20 x  20] *** [2048] ***[ COL] ***[0, 0, 0, 400, 400]**** [8], [0],[8] -[182 183 ]---
  IN:MSMC, DMA,    1c0(   448),    1b8(   440),  400( 1024),  70014( 458772),  14,   1380ec ||||  L2, DMA,    1cc(   460),    1cc(   460),  100(  256),  39800( 235520),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    1b8(   440),  400( 1024),  70014( 458772),  14,   1380ec 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  185(TIDL_EltWiseLayer) [185, 185] --[2048 x 20 x  20] => [1024 x 20 x  20] *** [2048] ***[ COL] ***[0, 0, 0, 400, 400]**** [8], [0],[8] -[178 184 ]---
  IN:MSMC, DMA,    1c0(   448),    1b8(   440),  400( 1024),  70014( 458772),  14,    c806c ||||  L2, DMA,    1cc(   460),    1cc(   460),  100(  256),  39800( 235520),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    1b8(   440),  400( 1024),  70014( 458772),  14,    c806c 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  186(TIDL_ConvolutionLayer) [186, 186] --[1024 x 20 x  20] => [512 x 20 x  20] *** [1024] ***[ROW_L] ***[0, 0, 0, 64, 400]**** [7], [56],[56] -[185 ]---
  IN:MSMC, DMA,    1c0(   448),    1b8(   440),  400( 1024),  70014( 458772),  14,    c806c ||||  L2, DMA,     c0(   192),     c0(   192),  400( 1024),  30180( 196992),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    1b8(   440),  200(  512),  38014( 229396),  14,   1380ec 
  WT:DDR_PERSIST, DMA,    400(  1024),    400(  1024),  200(  512),  80800( 526336),   0,  26bd280 ||||  L2, DMA,    440(  1088),    400(  1024),   80(  128),  22800( 141312),   0,    30180 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  187(TIDL_BatchNormLayer) [187, 187] --[512 x 20 x  20] => [512 x 20 x  20] *** [512] ***[ COL] ***[0, 0, 0, 400, 400]**** [1], [0],[1] -[186 ]---
  IN:MSMC, DMA,    1c0(   448),    1b8(   440),  200(  512),  38014( 229396),  14,   1380ec ||||  L2, DMA,    1cc(   460),    1cc(   460),  200(  512),  39800( 235520),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    1b8(   440),  200(  512),  38014( 229396),  14,    c806c 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  188(TIDL_EltWiseLayer) [188, 188] --[1024 x 20 x  20] => [512 x 20 x  20] *** [1024] ***[ COL] ***[0, 0, 0, 400, 400]**** [4], [0],[4] -[186 187 ]---
  IN:MSMC, DMA,    1c0(   448),    1b8(   440),  200(  512),  38014( 229396),  14,   1380ec ||||  L2, DMA,    1cc(   460),    1cc(   460),  100(  256),  39800( 235520),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    1b8(   440),  200(  512),  38014( 229396),  14,   1380ec 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  189(TIDL_ConvolutionLayer) [189, 189] --[512 x 20 x  20] => [1024 x 20 x  20] *** [512] ***[ROW_L] ***[42, 64, 21, 64, 400]**** [6], [192],[192] -[188 ]---
  IN:MSMC, DMA,    1c0(   448),    1b8(   440),  200(  512),  38014( 229396),  14,   1380ec ||||  L2, DMA,     c0(   192),     c0(   192),  200(  512),  18180(  98688),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    1b8(   440),  400( 1024),  70014( 458772),  14,    c806c 
  WT:DDR_PERSIST, DMA,   1200(  4608),   1200(  4608),  400( 1024), 481000(4722688),   0,  273da80 ||||  L2, DMA,   1240(  4672),   1200(  4608),   40(   64),  4a000( 303104),   0,    18180 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  190(TIDL_BatchNormLayer) [190, 190] --[1024 x 20 x  20] => [1024 x 20 x  20] *** [1024] ***[ COL] ***[0, 0, 0, 400, 400]**** [4], [0],[4] -[189 ]---
  IN:MSMC, DMA,    1c0(   448),    1b8(   440),  400( 1024),  70014( 458772),  14,    c806c ||||  L2, DMA,    1cc(   460),    1cc(   460),  200(  512),  39800( 235520),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    1b8(   440),  400( 1024),  70014( 458772),  14,   1380ec 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  191(TIDL_EltWiseLayer) [191, 191] --[2048 x 20 x  20] => [1024 x 20 x  20] *** [2048] ***[ COL] ***[0, 0, 0, 400, 400]**** [8], [0],[8] -[189 190 ]---
  IN:MSMC, DMA,    1c0(   448),    1b8(   440),  400( 1024),  70014( 458772),  14,    c806c ||||  L2, DMA,    1cc(   460),    1cc(   460),  100(  256),  39800( 235520),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    1b8(   440),  400( 1024),  70014( 458772),  14,    c806c 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  192(TIDL_ConvolutionLayer) [192, 192] --[1024 x 20 x  20] => [512 x 20 x  20] *** [1024] ***[ROW_L] ***[0, 0, 0, 64, 400]**** [7], [56],[56] -[191 ]---
  IN:MSMC, DMA,    1c0(   448),    1b8(   440),  400( 1024),  70014( 458772),  14,    c806c ||||  L2, DMA,     c0(   192),     c0(   192),  400( 1024),  30180( 196992),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    1b8(   440),  200(  512),  38014( 229396),  14,   1380ec 
  WT:DDR_PERSIST, DMA,    400(  1024),    400(  1024),  200(  512),  80800( 526336),   0,  2bbea80 ||||  L2, DMA,    440(  1088),    400(  1024),   80(  128),  22800( 141312),   0,    30180 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  193(TIDL_BatchNormLayer) [193, 193] --[512 x 20 x  20] => [512 x 20 x  20] *** [512] ***[ COL] ***[0, 0, 0, 400, 400]**** [1], [0],[1] -[192 ]---
  IN:MSMC, DMA,    1c0(   448),    1b8(   440),  200(  512),  38014( 229396),  14,   1380ec ||||  L2, DMA,    1cc(   460),    1cc(   460),  200(  512),  39800( 235520),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    1b8(   440),  200(  512),  38014( 229396),  14,    c806c 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  194(TIDL_EltWiseLayer) [194, 194] --[1024 x 20 x  20] => [512 x 20 x  20] *** [1024] ***[ COL] ***[0, 0, 0, 400, 400]**** [4], [0],[4] -[192 193 ]---
  IN:MSMC, DMA,    1c0(   448),    1b8(   440),  200(  512),  38014( 229396),  14,   1380ec ||||  L2, DMA,    1cc(   460),    1cc(   460),  100(  256),  39800( 235520),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    1b8(   440),  200(  512),  38014( 229396),  14,   1380ec 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  195(TIDL_ConvolutionLayer) [195, 195] --[512 x 20 x  20] => [1024 x 20 x  20] *** [512] ***[ROW_L] ***[42, 64, 21, 64, 400]**** [6], [192],[192] -[194 ]---
  IN:MSMC, DMA,    1c0(   448),    1b8(   440),  200(  512),  38014( 229396),  14,   1380ec ||||  L2, DMA,     c0(   192),     c0(   192),  200(  512),  18180(  98688),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    1b8(   440),  400( 1024),  70014( 458772),  14,    c806c 
  WT:DDR_PERSIST, DMA,   1200(  4608),   1200(  4608),  400( 1024), 481000(4722688),   0,  2c3f280 ||||  L2, DMA,   1240(  4672),   1200(  4608),   40(   64),  4a000( 303104),   0,    18180 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  196(TIDL_BatchNormLayer) [196, 196] --[1024 x 20 x  20] => [1024 x 20 x  20] *** [1024] ***[ COL] ***[0, 0, 0, 400, 400]**** [4], [0],[4] -[195 ]---
  IN:MSMC, DMA,    1c0(   448),    1b8(   440),  400( 1024),  70014( 458772),  14,    c806c ||||  L2, DMA,    1cc(   460),    1cc(   460),  200(  512),  39800( 235520),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    1b8(   440),  400( 1024),  70014( 458772),  14,   1380ec 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  197(TIDL_EltWiseLayer) [197, 197] --[2048 x 20 x  20] => [1024 x 20 x  20] *** [2048] ***[ COL] ***[0, 0, 0, 400, 400]**** [8], [0],[8] -[195 196 ]---
  IN:MSMC, DMA,    1c0(   448),    1b8(   440),  400( 1024),  70014( 458772),  14,    c806c ||||  L2, DMA,    1cc(   460),    1cc(   460),  100(  256),  39800( 235520),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    1b8(   440),  400( 1024),  70014( 458772),  14,    c806c 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  198(TIDL_ConvolutionLayer) [198, 198] --[1024 x 20 x  20] => [512 x 20 x  20] *** [1024] ***[ROW_L] ***[0, 0, 0, 64, 400]**** [7], [56],[56] -[197 ]---
  IN:MSMC, DMA,    1c0(   448),    1b8(   440),  400( 1024),  70014( 458772),  14,    c806c ||||  L2, DMA,     c0(   192),     c0(   192),  400( 1024),  30180( 196992),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    1b8(   440),  200(  512),  38014( 229396),  14,   1380ec 
  WT:DDR_PERSIST, DMA,    400(  1024),    400(  1024),  200(  512),  80800( 526336),   0,  30c0280 ||||  L2, DMA,    440(  1088),    400(  1024),   80(  128),  22800( 141312),   0,    30180 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  199(TIDL_BatchNormLayer) [199, 199] --[512 x 20 x  20] => [512 x 20 x  20] *** [512] ***[ COL] ***[0, 0, 0, 400, 400]**** [1], [0],[1] -[198 ]---
  IN:MSMC, DMA,    1c0(   448),    1b8(   440),  200(  512),  38014( 229396),  14,   1380ec ||||  L2, DMA,    1cc(   460),    1cc(   460),  200(  512),  39800( 235520),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    1b8(   440),  200(  512),  38014( 229396),  14,    cd9ec 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  200(TIDL_EltWiseLayer) [200, 200] --[1024 x 20 x  20] => [512 x 20 x  20] *** [1024] ***[ COL] ***[0, 0, 0, 400, 400]**** [4], [0],[4] -[198 199 ]---
  IN:MSMC, DMA,    1c0(   448),    1b8(   440),  200(  512),  38014( 229396),  14,   1380ec ||||  L2, DMA,    1cc(   460),    1cc(   460),  100(  256),  39800( 235520),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    1b8(   440),  200(  512),  38014( 229396),  14,    cd9ec 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  201(TIDL_ConvolutionLayer) [201, 201] --[512 x 20 x  20] => [1024 x 20 x  20] *** [512] ***[ROW_L] ***[42, 64, 21, 64, 400]**** [6], [192],[192] -[200 ]---
  IN:MSMC, DMA,    1c0(   448),    1b8(   440),  200(  512),  38014( 229396),  14,    cd9ec ||||  L2, DMA,     c0(   192),     c0(   192),  200(  512),  18180(  98688),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    1b8(   440),  400( 1024),  70014( 458772),  14,   105a6c 
  WT:DDR_PERSIST, DMA,   1200(  4608),   1200(  4608),  400( 1024), 481000(4722688),   0,  3140a80 ||||  L2, DMA,   1240(  4672),   1200(  4608),   40(   64),  4a000( 303104),   0,    18180 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  203(TIDL_BatchNormLayer) [202, 203] --[1024 x 20 x  20] => [1024 x 20 x  20] *** [1024] ***[ COL] ***[0, 0, 0, 400, 400]**** [4], [0],[4] -[201 ]---
  IN:MSMC, DMA,    1c0(   448),    1b8(   440),  400( 1024),  70014( 458772),  14,   105a6c ||||  L2, DMA,    1cc(   460),    1cc(   460),  200(  512),  39800( 235520),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    1b8(   440),  400( 1024),  70014( 458772),  14,   175aec 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  205(TIDL_EltWiseLayer) [203, 205] --[2048 x 20 x  20] => [1024 x 20 x  20] *** [2048] ***[ COL] ***[0, 0, 0, 400, 400]**** [8], [0],[8] -[201 203 ]---
  IN:MSMC, DMA,    1c0(   448),    1b8(   440),  400( 1024),  70014( 458772),  14,   105a6c ||||  L2, DMA,    1cc(   460),    1cc(   460),  100(  256),  39800( 235520),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    1b8(   440),  400( 1024),  70014( 458772),  14,   105a6c 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  207(TIDL_ConvolutionLayer) [204, 207] --[1024 x 20 x  20] => [57 x 20 x  20] *** [1024] ***[ROW_L] ***[0, 0, 0, 128, 400]**** [4], [1],[4] -[205 ]---
  IN:MSMC, DMA,    1c0(   448),    1b8(   440),  400( 1024),  70014( 458772),  14,   105a6c ||||  L2, DMA,    140(   320),    140(   320),  400( 1024),  50180( 328064),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    1b8(   440),   39(   57),   6414(  25620),  14,   105a6c 
  WT:DDR_PERSIST, DMA,    400(  1024),    400(  1024),   39(   57),   e500(  58624),   0,  35c1a80 ||||  L2, DMA,    440(  1088),    400(  1024),   39(   57),   f380(  62336),   0,    50180 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  209(TIDL_DataConvertLayer) [205, 209] --[57 x 20 x  20] => [57 x 20 x  20] *** [57] ***[ COL] ***[0, 0, 0, 400, 400]**** [3], [0],[3] -[207 ]---
  IN:MSMC, DMA,    1c0(   448),    1b8(   440),   39(   57),   6414(  25620),  14,   105a6c ||||  L2, DMA,    1b8(   440),    1b8(   440),   26(   38),   4180(  16768),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    190(   400),    190(   400),   39(   57),   5980(  22912),   0,   10be80 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  211(TIDL_ReshapeLayer) [206, 211] --[57 x 20 x  20] => [19 x 20 x  20] *** [57] ***[ COL] ***[0, 0, 0, 400, 400]**** [9], [0],[9] -[209 ]---
  IN:MSMC, DMA,    190(   400),    190(   400),   39(   57),   5980(  22912),   0,   10be80 ||||  L2, DMA,    190(   400),    190(   400),   26(   38),   3b80(  15232),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    190(   400),    190(   400),   13(   19),   5980(  22912),   0,   10be80 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  213(TIDL_TransposeLayer) [207, 213] --[19 x 20 x  20] => [20 x 19 x  20] *** [19] ***[ COL] ***[0, 0, 0, 22800, 400]**** [1], [0],[1] -[211 ]---
  IN:MSMC, DMA,    190(   400),    190(   400),   13(   19),   5980(  22912),   0,   10be80 ||||  L2, DMA,  6f800(456704),  6f800(456704),    2(    2),  6f800( 456704),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    17c(   380),    17c(   380),   14(   20),   5980(  22912),   0,    c8000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  215(TIDL_BatchNormLayer) [208, 215] --[20 x 19 x  20] => [20 x 19 x  20] *** [20] ***[ COL] ***[0, 0, 0, 380, 380]**** [6], [0],[6] -[213 ]---
  IN:MSMC, DMA,    17c(   380),    17c(   380),   14(   20),   5980(  22912),   0,    c8000 ||||  L2, DMA,    1c8(   456),    1c8(   456),   14(   20),   2400(   9216),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    17c(   380),   14(   20),   6900(  26880),   0,   105a00 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  217(TIDL_SliceLayer) [209, 217] --[20 x 19 x  20] => [20 x 2 x  20] *** [20] ***[ COL] ***[0, 0, 0, 380, 380]**** [6], [0],[6] -[215 ]---
  IN:MSMC, DMA,    1c0(   448),    17c(   380),   14(   20),   6900(  26880),   0,   105a00 ||||  L2, DMA,    1c8(   456),    1c8(   456),   14(   20),   2400(   9216),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     28(    40),     28(    40),   14(   20),    980(   2432),   0,    c8000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  221(TIDL_BatchNormLayer) [210, 221] --[20 x 2 x  20] => [20 x 2 x  20] *** [20] ***[ COL] ***[0, 0, 0, 40, 40]**** [6], [0],[6] -[217 ]---
  IN:MSMC, DMA,     28(    40),     28(    40),   14(   20),    980(   2432),   0,    c8000 ||||  L2, DMA,     28(    40),     28(    40),   14(   20),    380(    896),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     28(    40),     28(    40),   14(   20),    980(   2432),   0,    c8000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  224(TIDL_EltWiseLayer) [211, 224] --[40 x 2 x  20] => [20 x 2 x  20] *** [40] ***[ COL] ***[0, 0, 0, 40, 40]**** [4], [0],[4] -[221 5 ]---
  IN:MSMC, DMA,     28(    40),     28(    40),   14(   20),    980(   2432),   0,    c8000 ||||  L2, DMA,     28(    40),     28(    40),   1e(   30),    980(   2432),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     28(    40),     28(    40),   14(   20),    980(   2432),   0,    c8000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  227(TIDL_BatchNormLayer) [212, 227] --[20 x 2 x  20] => [20 x 2 x  20] *** [20] ***[ COL] ***[0, 0, 0, 40, 40]**** [6], [0],[6] -[224 ]---
  IN:MSMC, DMA,     28(    40),     28(    40),   14(   20),    980(   2432),   0,    c8000 ||||  L2, DMA,     28(    40),     28(    40),   14(   20),    380(    896),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     28(    40),     28(    40),   14(   20),    980(   2432),   0,   10c300 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  218(TIDL_SliceLayer) [213, 218] --[20 x 19 x  20] => [20 x 2 x  20] *** [20] ***[ COL] ***[0, 0, 0, 380, 380]**** [6], [0],[6] -[215 ]---
  IN:MSMC, DMA,    1c0(   448),    17c(   380),   14(   20),   6900(  26880),   0,   105a00 ||||  L2, DMA,    1c8(   456),    1c8(   456),   14(   20),   2400(   9216),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     28(    40),     28(    40),   14(   20),    980(   2432),   0,    c8000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  222(TIDL_BatchNormLayer) [214, 222] --[20 x 2 x  20] => [20 x 2 x  20] *** [20] ***[ COL] ***[0, 0, 0, 40, 40]**** [6], [0],[6] -[218 ]---
  IN:MSMC, DMA,     28(    40),     28(    40),   14(   20),    980(   2432),   0,    c8000 ||||  L2, DMA,     28(    40),     28(    40),   14(   20),    380(    896),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     28(    40),     28(    40),   14(   20),    980(   2432),   0,    c8000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  225(TIDL_BatchNormLayer) [215, 225] --[20 x 2 x  20] => [20 x 2 x  20] *** [20] ***[ COL] ***[0, 0, 0, 40, 40]**** [6], [0],[6] -[222 ]---
  IN:MSMC, DMA,     28(    40),     28(    40),   14(   20),    980(   2432),   0,    c8000 ||||  L2, DMA,     28(    40),     28(    40),   14(   20),    380(    896),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     28(    40),     28(    40),   14(   20),    980(   2432),   0,    c8000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  228(TIDL_EltWiseLayer) [216, 228] --[40 x 2 x  20] => [20 x 2 x  20] *** [40] ***[ COL] ***[0, 0, 0, 40, 40]**** [4], [0],[4] -[225 2 ]---
  IN:MSMC, DMA,     28(    40),     28(    40),   14(   20),    980(   2432),   0,    c8000 ||||  L2, DMA,     28(    40),     28(    40),   1e(   30),    980(   2432),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     28(    40),     28(    40),   14(   20),    980(   2432),   0,   10cc80 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  219(TIDL_SliceLayer) [217, 219] --[20 x 19 x  20] => [20 x 15 x  20] *** [20] ***[ COL] ***[0, 0, 0, 380, 380]**** [6], [0],[6] -[215 ]---
  IN:MSMC, DMA,    1c0(   448),    17c(   380),   14(   20),   6900(  26880),   0,   105a00 ||||  L2, DMA,    1c8(   456),    1c8(   456),   14(   20),   2400(   9216),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    140(   320),    12c(   300),   14(   20),   4b00(  19200),   0,   10d600 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  230(TIDL_ConcatLayer) [218, 230] --[20 x 15 x  20] => [20 x 19 x  20] *** [20] ***[ COL] ***[0, 0, 0, 300, 300]**** [6], [0],[6] -[227 228 219 ]---
  IN:MSMC, DMA,     28(    40),     28(    40),   14(   20),    980(   2432),   0,   10c300 ||||  L2, DMA,    12c(   300),    12c(   300),   14(   20),   1780(   6016),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    17c(   380),    17c(   380),   14(   20),   5980(  22912),   0,    c8000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  232(TIDL_ReshapeLayer) [219, 232] --[20 x 19 x  20] => [1 x 19 x  1200] *** [20] ***[ COL] ***[0, 0, 0, 380, 380]**** [1], [0],[1] -[230 ]---
  IN:MSMC, DMA,    17c(   380),    17c(   380),   14(   20),   5980(  22912),   0,    c8000 ||||  L2, DMA,    17c(   380),    17c(   380),   14(   20),   1e00(   7680),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   5910( 22800),   5910( 22800),    1(    1),   5980(  22912),   0,    c8000 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  202(TIDL_ConvolutionLayer) [220, 202] --[512 x 20 x  20] => [256 x 20 x  20] *** [512] ***[ROW_L] ***[0, 0, 0, 256, 400]**** [2], [1],[2] -[200 ]---
  IN:MSMC, DMA,    1c0(   448),    1b8(   440),  200(  512),  38014( 229396),  14,    cd9ec ||||  L2, DMA,    240(   576),    240(   576),  200(  512),  48080( 295040),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    1b8(   440),  100(  256),  1c014( 114708),  14,    cd9ec 
  WT:DDR_PERSIST, DMA,    200(   512),    200(   512),  100(  256),  20400( 132096),   0,  35cff80 ||||  L2, DMA,    240(   576),    200(   512),  100(  256),  24400( 148480),   0,    48080 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  204(TIDL_BatchNormLayer) [221, 204] --[256 x 20 x  20] => [256 x 20 x  20] *** [256] ***[ COL] ***[0, 0, 0, 400, 400]**** [1], [0],[1] -[202 ]---
  IN:MSMC, DMA,    1c0(   448),    1b8(   440),  100(  256),  1c014( 114708),  14,    cd9ec ||||  L2, DMA,    1cc(   460),    1cc(   460),  100(  256),  1cc00( 117760),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    1b8(   440),  100(  256),  1c014( 114708),  14,    e9a6c 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  206(TIDL_EltWiseLayer) [222, 206] --[512 x 20 x  20] => [256 x 20 x  20] *** [512] ***[ COL] ***[0, 0, 0, 400, 400]**** [2], [0],[2] -[202 204 ]---
  IN:MSMC, DMA,    1c0(   448),    1b8(   440),  100(  256),  1c014( 114708),  14,    cd9ec ||||  L2, DMA,    1cc(   460),    1cc(   460),  100(  256),  39800( 235520),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    1c0(   448),    1b8(   440),  100(  256),  1c014( 114708),  14,   139aec 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 1,  0],  To fill zero OUT: [ 1,  0]
------  208(TIDL_ResizeLayer) [223, 208] --[256 x 20 x  20] => [256 x 40 x  40] *** [256] ***[ COL] ***[0, 0, 0, 440, 440]**** [1], [0],[1] -[206 ]---
  IN:MSMC, DMA,    1c0(   448),    1b8(   440),  100(  256),  1c014( 114708),   0,   139aec ||||  L2, DMA,    1cc(   460),    1cc(   460),  100(  256),  1cc00( 117760),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    6c0(  1728),    690(  1680),  100(  256),  6c028( 442408),  28,    cda58 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  210(TIDL_ConcatLayer) [224, 210] --[768 x 40 x  40] => [768 x 40 x  40] *** [768] ***[ COL] ***[0, 0, 0, 1600, 1600]**** [6], [0],[6] -[208 154 ]---
  IN:MSMC, DMA,    6c0(  1728),    690(  1680),  100(  256),  6c0a8( 442536),  28,    cda58 ||||  L2, DMA,    6e0(  1760),    6e0(  1760),  100(  256),  6e000( 450560),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    6c0(  1728),    690(  1680),  300(  768), 144028(1327144),  28,   139ad8 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  212(TIDL_ConvolutionLayer) [225, 212] --[768 x 40 x  40] => [256 x 40 x  40] *** [768] ***[ROW_L] ***[0, 0, 0, 64, 1600]**** [25], [1],[25] -[210 ]---
  IN:MSMC, DMA,    6c0(  1728),    690(  1680),  300(  768), 144028(1327144),  28,   139ad8 ||||  L2, DMA,     c0(   192),     c0(   192),  300(  768),  24600( 148992),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    6c0(  1728),    690(  1680),  100(  256),  6c028( 442408),  28,       58 
  WT:DDR_PERSIST, DMA,    300(   768),    300(   768),  100(  256),  30400( 197632),   0,  35f0380 ||||  L2, DMA,    340(   832),    300(   768),  100(  256),  34400( 214016),   0,    24600 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  214(TIDL_BatchNormLayer) [226, 214] --[256 x 40 x  40] => [256 x 40 x  40] *** [256] ***[ COL] ***[0, 0, 0, 1600, 1600]**** [1], [0],[1] -[212 ]---
  IN:MSMC, DMA,    6c0(  1728),    690(  1680),  100(  256),  6c028( 442408),  28,       58 ||||  L2, DMA,    6e0(  1760),    6e0(  1760),  100(  256),  6e000( 450560),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    6c0(  1728),    690(  1680),  100(  256),  6c028( 442408),  28,    cd9d8 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  216(TIDL_EltWiseLayer) [227, 216] --[512 x 40 x  40] => [256 x 40 x  40] *** [512] ***[ COL] ***[0, 0, 0, 1600, 1600]**** [4], [0],[4] -[212 214 ]---
  IN:MSMC, DMA,    6c0(  1728),    690(  1680),  100(  256),  6c028( 442408),  28,       58 ||||  L2, DMA,    6e0(  1760),    6e0(  1760),   80(  128),  6e000( 450560),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    6c0(  1728),    690(  1680),  100(  256),  6c028( 442408),  28,       58 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  220(TIDL_ConvolutionLayer) [228, 220] --[256 x 40 x  40] => [512 x 40 x  40] *** [256] ***[ROW_L] ***[82, 128, 41, 192, 1600]**** [9], [72],[72] -[216 ]---
  IN:MSMC, DMA,    6c0(  1728),    690(  1680),  100(  256),  6c028( 442408),  28,       58 ||||  L2, DMA,    240(   576),    240(   576),  100(  256),  24580( 148864),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    6c0(  1728),    690(  1680),  200(  512),  d8028( 884776),  28,    cd9d8 
  WT:DDR_PERSIST, DMA,    900(  2304),    900(  2304),  200(  512), 120800(1181696),   0,  3620780 ||||  L2, DMA,    940(  2368),    900(  2304),   80(  128),  4a800( 305152),   0,    24580 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  223(TIDL_BatchNormLayer) [229, 223] --[512 x 40 x  40] => [512 x 40 x  40] *** [512] ***[ COL] ***[0, 0, 0, 1600, 1600]**** [4], [0],[4] -[220 ]---
  IN:MSMC, DMA,    6c0(  1728),    690(  1680),  200(  512),  d8028( 884776),  28,    cd9d8 ||||  L2, DMA,    6e0(  1760),    6e0(  1760),  100(  256),  6e000( 450560),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    6c0(  1728),    690(  1680),  200(  512),  d8028( 884776),  28,   1a5a58 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  226(TIDL_EltWiseLayer) [230, 226] --[1024 x 40 x  40] => [512 x 40 x  40] *** [1024] ***[ COL] ***[0, 0, 0, 1600, 1600]**** [8], [0],[8] -[220 223 ]---
  IN:MSMC, DMA,    6c0(  1728),    690(  1680),  200(  512),  d8028( 884776),  28,    cd9d8 ||||  L2, DMA,    6e0(  1760),    6e0(  1760),   80(  128),  6e000( 450560),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    6c0(  1728),    690(  1680),  200(  512),  d8028( 884776),  28,    cd9d8 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  229(TIDL_ConvolutionLayer) [231, 229] --[512 x 40 x  40] => [256 x 40 x  40] *** [512] ***[ROW_L] ***[0, 0, 0, 256, 1600]**** [7], [1],[7] -[226 ]---
  IN:MSMC, DMA,    6c0(  1728),    690(  1680),  200(  512),  d8028( 884776),  28,    cd9d8 ||||  L2, DMA,    240(   576),    240(   576),  200(  512),  48580( 296320),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    6c0(  1728),    690(  1680),  100(  256),  6c028( 442408),  28,       58 
  WT:DDR_PERSIST, DMA,    200(   512),    200(   512),  100(  256),  20400( 132096),   0,  3740f80 ||||  L2, DMA,    240(   576),    200(   512),  100(  256),  24400( 148480),   0,    48580 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  231(TIDL_BatchNormLayer) [232, 231] --[256 x 40 x  40] => [256 x 40 x  40] *** [256] ***[ COL] ***[0, 0, 0, 1600, 1600]**** [1], [0],[1] -[229 ]---
  IN:MSMC, DMA,    6c0(  1728),    690(  1680),  100(  256),  6c028( 442408),  28,       58 ||||  L2, DMA,    6e0(  1760),    6e0(  1760),  100(  256),  6e000( 450560),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    6c0(  1728),    690(  1680),  100(  256),  6c028( 442408),  28,    cd9d8 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  233(TIDL_EltWiseLayer) [233, 233] --[512 x 40 x  40] => [256 x 40 x  40] *** [512] ***[ COL] ***[0, 0, 0, 1600, 1600]**** [4], [0],[4] -[229 231 ]---
  IN:MSMC, DMA,    6c0(  1728),    690(  1680),  100(  256),  6c028( 442408),  28,       58 ||||  L2, DMA,    6e0(  1760),    6e0(  1760),   80(  128),  6e000( 450560),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    6c0(  1728),    690(  1680),  100(  256),  6c028( 442408),  28,       58 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  234(TIDL_ConvolutionLayer) [234, 234] --[256 x 40 x  40] => [512 x 40 x  40] *** [256] ***[ROW_L] ***[82, 128, 41, 192, 1600]**** [9], [72],[72] -[233 ]---
  IN:MSMC, DMA,    6c0(  1728),    690(  1680),  100(  256),  6c028( 442408),  28,       58 ||||  L2, DMA,    240(   576),    240(   576),  100(  256),  24580( 148864),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    6c0(  1728),    690(  1680),  200(  512),  d8028( 884776),  28,    cd9d8 
  WT:DDR_PERSIST, DMA,    900(  2304),    900(  2304),  200(  512), 120800(1181696),   0,  3761380 ||||  L2, DMA,    940(  2368),    900(  2304),   80(  128),  4a800( 305152),   0,    24580 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  235(TIDL_BatchNormLayer) [235, 235] --[512 x 40 x  40] => [512 x 40 x  40] *** [512] ***[ COL] ***[0, 0, 0, 1600, 1600]**** [4], [0],[4] -[234 ]---
  IN:MSMC, DMA,    6c0(  1728),    690(  1680),  200(  512),  d8028( 884776),  28,    cd9d8 ||||  L2, DMA,    6e0(  1760),    6e0(  1760),  100(  256),  6e000( 450560),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    6c0(  1728),    690(  1680),  200(  512),  d8028( 884776),  28,   1a5a58 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  236(TIDL_EltWiseLayer) [236, 236] --[1024 x 40 x  40] => [512 x 40 x  40] *** [1024] ***[ COL] ***[0, 0, 0, 1600, 1600]**** [8], [0],[8] -[234 235 ]---
  IN:MSMC, DMA,    6c0(  1728),    690(  1680),  200(  512),  d8028( 884776),  28,    cd9d8 ||||  L2, DMA,    6e0(  1760),    6e0(  1760),   80(  128),  6e000( 450560),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    6c0(  1728),    690(  1680),  200(  512),  d8028( 884776),  28,    cd9d8 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  237(TIDL_ConvolutionLayer) [237, 237] --[512 x 40 x  40] => [256 x 40 x  40] *** [512] ***[ROW_L] ***[0, 0, 0, 256, 1600]**** [7], [1],[7] -[236 ]---
  IN:MSMC, DMA,    6c0(  1728),    690(  1680),  200(  512),  d8028( 884776),  28,    cd9d8 ||||  L2, DMA,    240(   576),    240(   576),  200(  512),  48580( 296320),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    6c0(  1728),    690(  1680),  100(  256),  6c028( 442408),  28,       58 
  WT:DDR_PERSIST, DMA,    200(   512),    200(   512),  100(  256),  20400( 132096),   0,  3881b80 ||||  L2, DMA,    240(   576),    200(   512),  100(  256),  24400( 148480),   0,    48580 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  238(TIDL_BatchNormLayer) [238, 238] --[256 x 40 x  40] => [256 x 40 x  40] *** [256] ***[ COL] ***[0, 0, 0, 1600, 1600]**** [1], [0],[1] -[237 ]---
  IN:MSMC, DMA,    6c0(  1728),    690(  1680),  100(  256),  6c028( 442408),  28,       58 ||||  L2, DMA,    6e0(  1760),    6e0(  1760),  100(  256),  6e000( 450560),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    6c0(  1728),    690(  1680),  100(  256),  6c028( 442408),  28,    cd9d8 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  239(TIDL_EltWiseLayer) [239, 239] --[512 x 40 x  40] => [256 x 40 x  40] *** [512] ***[ COL] ***[0, 0, 0, 1600, 1600]**** [4], [0],[4] -[237 238 ]---
  IN:MSMC, DMA,    6c0(  1728),    690(  1680),  100(  256),  6c028( 442408),  28,       58 ||||  L2, DMA,    6e0(  1760),    6e0(  1760),   80(  128),  6e000( 450560),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    6c0(  1728),    690(  1680),  100(  256),  6c028( 442408),  28,       58 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  240(TIDL_ConvolutionLayer) [240, 240] --[256 x 40 x  40] => [512 x 40 x  40] *** [256] ***[ROW_L] ***[82, 128, 41, 192, 1600]**** [9], [72],[72] -[239 ]---
  IN:MSMC, DMA,    6c0(  1728),    690(  1680),  100(  256),  6c028( 442408),  28,       58 ||||  L2, DMA,    240(   576),    240(   576),  100(  256),  24580( 148864),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    6c0(  1728),    690(  1680),  200(  512),  d8028( 884776),  28,    cd9d8 
  WT:DDR_PERSIST, DMA,    900(  2304),    900(  2304),  200(  512), 120800(1181696),   0,  38a1f80 ||||  L2, DMA,    940(  2368),    900(  2304),   80(  128),  4a800( 305152),   0,    24580 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  242(TIDL_BatchNormLayer) [241, 242] --[512 x 40 x  40] => [512 x 40 x  40] *** [512] ***[ COL] ***[0, 0, 0, 1600, 1600]**** [4], [0],[4] -[240 ]---
  IN:MSMC, DMA,    6c0(  1728),    690(  1680),  200(  512),  d8028( 884776),  28,    cd9d8 ||||  L2, DMA,    6e0(  1760),    6e0(  1760),  100(  256),  6e000( 450560),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    6c0(  1728),    690(  1680),  200(  512),  d8028( 884776),  28,   1a5a58 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  244(TIDL_EltWiseLayer) [242, 244] --[1024 x 40 x  40] => [512 x 40 x  40] *** [1024] ***[ COL] ***[0, 0, 0, 1600, 1600]**** [8], [0],[8] -[240 242 ]---
  IN:MSMC, DMA,    6c0(  1728),    690(  1680),  200(  512),  d8028( 884776),  28,    cd9d8 ||||  L2, DMA,    6e0(  1760),    6e0(  1760),   80(  128),  6e000( 450560),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    6c0(  1728),    690(  1680),  200(  512),  d8028( 884776),  28,    cd9d8 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  246(TIDL_ConvolutionLayer) [243, 246] --[512 x 40 x  40] => [57 x 40 x  40] *** [512] ***[ROW_L] ***[0, 0, 0, 320, 1600]**** [5], [1],[5] -[244 ]---
  IN:MSMC, DMA,    6c0(  1728),    690(  1680),  200(  512),  d8028( 884776),  28,    cd9d8 ||||  L2, DMA,    2c0(   704),    2c0(   704),  200(  512),  58400( 361472),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    6c0(  1728),    690(  1680),   39(   57),  18128(  98600),  28,    6c0d8 
  WT:DDR_PERSIST, DMA,    200(   512),    200(   512),   39(   57),   7300(  29440),   0,  39c2780 ||||  L2, DMA,    240(   576),    200(   512),   39(   57),   8180(  33152),   0,    58400 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  248(TIDL_DataConvertLayer) [244, 248] --[57 x 40 x  40] => [57 x 40 x  40] *** [57] ***[ COL] ***[0, 0, 0, 1600, 1600]**** [3], [0],[3] -[246 ]---
  IN:MSMC, DMA,    6c0(  1728),    690(  1680),   39(   57),  18128(  98600),  28,    6c0d8 ||||  L2, DMA,    690(  1680),    690(  1680),   26(   38),   f980(  63872),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    640(  1600),    640(  1600),   39(   57),  16480(  91264),   0,    9ab00 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  250(TIDL_ReshapeLayer) [245, 250] --[57 x 40 x  40] => [19 x 40 x  40] *** [57] ***[ COL] ***[0, 0, 0, 1600, 1600]**** [9], [0],[9] -[248 ]---
  IN:MSMC, DMA,    640(  1600),    640(  1600),   39(   57),  16480(  91264),   0,    9ab00 ||||  L2, DMA,    640(  1600),    640(  1600),   26(   38),   ed80(  60800),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    640(  1600),    640(  1600),   13(   19),  16480(  91264),   0,    9ab00 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  252(TIDL_TransposeLayer) [246, 252] --[19 x 40 x  40] => [40 x 19 x  40] *** [19] ***[ COL] ***[0, 0, 0, 91200, 1600]**** [1], [0],[1] -[250 ]---
  IN:MSMC, DMA,    640(  1600),    640(  1600),   13(   19),  16480(  91264),   0,    9ab00 ||||  L2, DMA,  6f800(456704),  6f800(456704),    2(    2),  6f800( 456704),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    2f8(   760),    2f8(   760),   28(   40),  16480(  91264),   0,    84680 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  254(TIDL_BatchNormLayer) [247, 254] --[40 x 19 x  40] => [40 x 19 x  40] *** [40] ***[ COL] ***[0, 0, 0, 760, 760]**** [6], [0],[6] -[252 ]---
  IN:MSMC, DMA,    2f8(   760),    2f8(   760),   28(   40),  16480(  91264),   0,    84680 ||||  L2, DMA,    344(   836),    344(   836),   28(   40),   8300(  33536),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    340(   832),    2f8(   760),   28(   40),  18600(  99840),   0,    6c080 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  256(TIDL_SliceLayer) [248, 256] --[40 x 19 x  40] => [40 x 2 x  40] *** [40] ***[ COL] ***[0, 0, 0, 760, 760]**** [6], [0],[6] -[254 ]---
  IN:MSMC, DMA,    340(   832),    2f8(   760),   28(   40),  18600(  99840),   0,    6c080 ||||  L2, DMA,    344(   836),    344(   836),   28(   40),   8300(  33536),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     c0(   192),     50(    80),   28(   40),   5a00(  23040),   0,    84680 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  260(TIDL_BatchNormLayer) [249, 260] --[40 x 2 x  40] => [40 x 2 x  40] *** [40] ***[ COL] ***[0, 0, 0, 80, 80]**** [6], [0],[6] -[256 ]---
  IN:MSMC, DMA,     c0(   192),     50(    80),   28(   40),   5a00(  23040),   0,    84680 ||||  L2, DMA,     c0(   192),     c0(   192),   28(   40),   1e00(   7680),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     c0(   192),     50(    80),   28(   40),   5a00(  23040),   0,    84680 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  263(TIDL_EltWiseLayer) [250, 263] --[80 x 2 x  40] => [40 x 2 x  40] *** [80] ***[ COL] ***[0, 0, 0, 80, 80]**** [4], [0],[4] -[260 4 ]---
  IN:MSMC, DMA,     c0(   192),     50(    80),   28(   40),   5a00(  23040),   0,    84680 ||||  L2, DMA,     c0(   192),     c0(   192),   3c(   60),   5a00(  23040),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     c0(   192),     50(    80),   28(   40),   5a00(  23040),   0,    84680 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  266(TIDL_BatchNormLayer) [251, 266] --[40 x 2 x  40] => [40 x 2 x  40] *** [40] ***[ COL] ***[0, 0, 0, 80, 80]**** [6], [0],[6] -[263 ]---
  IN:MSMC, DMA,     c0(   192),     50(    80),   28(   40),   5a00(  23040),   0,    84680 ||||  L2, DMA,     c0(   192),     c0(   192),   28(   40),   1e00(   7680),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     c0(   192),     50(    80),   28(   40),   5a00(  23040),   0,    84680 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  257(TIDL_SliceLayer) [252, 257] --[40 x 19 x  40] => [40 x 2 x  40] *** [40] ***[ COL] ***[0, 0, 0, 760, 760]**** [6], [0],[6] -[254 ]---
  IN:MSMC, DMA,    340(   832),    2f8(   760),   28(   40),  18600(  99840),   0,    6c080 ||||  L2, DMA,    344(   836),    344(   836),   28(   40),   8300(  33536),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     c0(   192),     50(    80),   28(   40),   5a00(  23040),   0,    8a080 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  261(TIDL_BatchNormLayer) [253, 261] --[40 x 2 x  40] => [40 x 2 x  40] *** [40] ***[ COL] ***[0, 0, 0, 80, 80]**** [6], [0],[6] -[257 ]---
  IN:MSMC, DMA,     c0(   192),     50(    80),   28(   40),   5a00(  23040),   0,    8a080 ||||  L2, DMA,     c0(   192),     c0(   192),   28(   40),   1e00(   7680),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     c0(   192),     50(    80),   28(   40),   5a00(  23040),   0,    8a080 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  264(TIDL_BatchNormLayer) [254, 264] --[40 x 2 x  40] => [40 x 2 x  40] *** [40] ***[ COL] ***[0, 0, 0, 80, 80]**** [6], [0],[6] -[261 ]---
  IN:MSMC, DMA,     c0(   192),     50(    80),   28(   40),   5a00(  23040),   0,    8a080 ||||  L2, DMA,     c0(   192),     c0(   192),   28(   40),   1e00(   7680),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     c0(   192),     50(    80),   28(   40),   5a00(  23040),   0,    8a080 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  267(TIDL_EltWiseLayer) [255, 267] --[80 x 2 x  40] => [40 x 2 x  40] *** [80] ***[ COL] ***[0, 0, 0, 80, 80]**** [4], [0],[4] -[264 1 ]---
  IN:MSMC, DMA,     c0(   192),     50(    80),   28(   40),   5a00(  23040),   0,    8a080 ||||  L2, DMA,     c0(   192),     c0(   192),   3c(   60),   5a00(  23040),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     c0(   192),     50(    80),   28(   40),   5a00(  23040),   0,    8a080 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  258(TIDL_SliceLayer) [256, 258] --[40 x 19 x  40] => [40 x 15 x  40] *** [40] ***[ COL] ***[0, 0, 0, 760, 760]**** [6], [0],[6] -[254 ]---
  IN:MSMC, DMA,    340(   832),    2f8(   760),   28(   40),  18600(  99840),   0,    6c080 ||||  L2, DMA,    344(   836),    344(   836),   28(   40),   8300(  33536),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    2c0(   704),    258(   600),   28(   40),  14a00(  84480),   0,    8fa80 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  269(TIDL_ConcatLayer) [257, 269] --[40 x 15 x  40] => [40 x 19 x  40] *** [40] ***[ COL] ***[0, 0, 0, 600, 600]**** [6], [0],[6] -[266 267 258 ]---
  IN:MSMC, DMA,     c0(   192),     50(    80),   28(   40),   5a00(  23040),   0,    84680 ||||  L2, DMA,    258(   600),    258(   600),   28(   40),   5e00(  24064),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    2f8(   760),    2f8(   760),   28(   40),  16480(  91264),   0,    6c080 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  271(TIDL_ReshapeLayer) [258, 271] --[40 x 19 x  40] => [1 x 19 x  4800] *** [40] ***[ COL] ***[0, 0, 0, 760, 760]**** [1], [0],[1] -[269 ]---
  IN:MSMC, DMA,    2f8(   760),    2f8(   760),   28(   40),  16480(  91264),   0,    6c080 ||||  L2, DMA,    2f8(   760),    2f8(   760),   28(   40),   7700(  30464),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,  16440( 91200),  16440( 91200),    1(    1),  16480(  91264),   0,    6c080 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  241(TIDL_ConvolutionLayer) [259, 241] --[256 x 40 x  40] => [128 x 40 x  40] *** [256] ***[ROW_L] ***[0, 0, 0, 768, 1600]**** [3], [1],[3] -[239 ]---
  IN:MSMC, DMA,    6c0(  1728),    690(  1680),  100(  256),  6c028( 442408),  28,       58 ||||  L2, DMA,    640(  1600),    640(  1600),  100(  256),  64380( 410496),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    6c0(  1728),    690(  1680),   80(  128),  36028( 221224),  28,       58 
  WT:DDR_PERSIST, DMA,    100(   256),    100(   256),   80(  128),   8200(  33280),   0,  39c9a80 ||||  L2, DMA,    140(   320),    100(   256),   80(  128),   a200(  41472),   0,    64380 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  243(TIDL_BatchNormLayer) [260, 243] --[128 x 40 x  40] => [128 x 40 x  40] *** [128] ***[ COL] ***[0, 0, 0, 1600, 1600]**** [1], [0],[1] -[241 ]---
  IN:MSMC, DMA,    6c0(  1728),    690(  1680),   80(  128),  36028( 221224),  28,       58 ||||  L2, DMA,    6e0(  1760),    6e0(  1760),   80(  128),  37000( 225280),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    6c0(  1728),    690(  1680),   80(  128),  36028( 221224),  28,    846d8 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  245(TIDL_EltWiseLayer) [261, 245] --[256 x 40 x  40] => [128 x 40 x  40] *** [256] ***[ COL] ***[0, 0, 0, 1600, 1600]**** [2], [0],[2] -[241 243 ]---
  IN:MSMC, DMA,    6c0(  1728),    690(  1680),   80(  128),  36028( 221224),  28,       58 ||||  L2, DMA,    6e0(  1760),    6e0(  1760),   80(  128),  6e000( 450560),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    6c0(  1728),    690(  1680),   80(  128),  36028( 221224),  28,       58 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 1,  0]
------  247(TIDL_ResizeLayer) [262, 247] --[128 x 40 x  40] => [128 x 80 x  80] *** [128] ***[ COL] ***[0, 0, 0, 1680, 1680]**** [4], [0],[4] -[245 ]---
  IN:MSMC, DMA,    6c0(  1728),    690(  1680),   80(  128),  36028( 221224),   0,       58 ||||  L2, DMA,    6e0(  1760),    6e0(  1760),   40(   64),  1b800( 112640),   0,        0 
 OUT:MSMC, CPU,   1b40(  6976),   1ae0(  6880),   40(   64),  6d000( 446464),   0,    cd980 |||| DDR, DMA,   19a0(  6560),   19a0(  6560),   80(  128),  cd450( 840784),  50,   2bc8b0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 1,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  249(TIDL_ConcatLayer) [263, 249] --[384 x 80 x  80] => [384 x 80 x  80] *** [384] ***[ COL] ***[0, 0, 0, 6400, 6400]**** [12], [0],[12] -[247 95 ]---
  IN: DDR, DMA,   19a0(  6560),   19a0(  6560),   80(  128),  cd4d0( 840912),  50,   2bc8b0 ||||  L2, DMA,   19f0(  6640),   19f0(  6640),   40(   64),  67c00( 424960),   0,        0 
 OUT:MSMC, CPU,   1940(  6464),   1900(  6400),   40(   64),  65000( 413696),   0,        0 |||| DDR, DMA,   1900(  6400),   1900(  6400),  180(  384), 258400(2458624),   0,   389d00 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  251(TIDL_ConvolutionLayer) [264, 251] --[384 x 80 x  80] => [128 x 80 x  80] *** [384] ***[ROW_L] ***[0, 0, 0, 448, 6400]**** [15], [1],[15] -[249 ]---
  IN: DDR, DMA,   1900(  6400),   1900(  6400),  180(  384), 258400(2458624),   0,   389d00 ||||  L2, DMA,    3c0(   960),    3c0(   960),  180(  384),  5b700( 374528),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1940(  6464),   1900(  6400),   80(  128),  ca000( 827392),   0,    cd980 
  WT:DDR_PERSIST, DMA,    180(   384),    180(   384),   80(  128),   c200(  49664),   0,  39d1c80 ||||  L2, DMA,    1c0(   448),    180(   384),   80(  128),   e200(  57856),   0,    5b700 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  253(TIDL_BatchNormLayer) [265, 253] --[128 x 80 x  80] => [128 x 80 x  80] *** [128] ***[ COL] ***[0, 0, 0, 6400, 6400]**** [4], [0],[4] -[251 ]---
  IN:MSMC, DMA,   1940(  6464),   1900(  6400),   80(  128),  ca000( 827392),   0,    cd980 ||||  L2, DMA,   1950(  6480),   1950(  6480),   40(   64),  65400( 414720),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1940(  6464),   1900(  6400),   80(  128),  ca000( 827392),   0,   197980 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  255(TIDL_EltWiseLayer) [266, 255] --[256 x 80 x  80] => [128 x 80 x  80] *** [256] ***[ COL] ***[0, 0, 0, 6400, 6400]**** [8], [0],[8] -[251 253 ]---
  IN:MSMC, DMA,   1940(  6464),   1900(  6400),   80(  128),  ca000( 827392),   0,    cd980 ||||  L2, DMA,   1950(  6480),   1950(  6480),   20(   32),  65400( 414720),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1940(  6464),   1900(  6400),   80(  128),  ca000( 827392),   0,    cd980 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  259(TIDL_ConvolutionLayer) [267, 259] --[128 x 80 x  80] => [256 x 80 x  80] *** [128] ***[ROW_L] ***[162, 192, 81, 384, 6400]**** [17], [1],[17] -[255 ]---
  IN:MSMC, DMA,   1940(  6464),   1900(  6400),   80(  128),  ca000( 827392),   0,    cd980 ||||  L2, DMA,    3c0(   960),    3c0(   960),   80(  128),  1f700( 128768),   0,        0 
 OUT:MSMC, CPU,    1c0(   448),    180(   384),  100(  256),  38000( 229376),   0,        0 |||| DDR, DMA,   1c00(  7168),   1900(  6400),  100(  256), 1c0400(1836032),   0,   12c400 
  WT:DDR_PERSIST, DMA,    480(  1152),    480(  1152),  100(  256),  48400( 295936),   0,  39dde80 ||||  L2, DMA,    4c0(  1216),    480(  1152),  100(  256),  4c400( 312320),   0,    1f700 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  262(TIDL_BatchNormLayer) [268, 262] --[256 x 80 x  80] => [256 x 80 x  80] *** [256] ***[ COL] ***[0, 0, 0, 6400, 6400]**** [8], [0],[8] -[259 ]---
  IN: DDR, DMA,   1c00(  7168),   1900(  6400),  100(  256), 1c0400(1836032),   0,   12c400 ||||  L2, DMA,   1950(  6480),   1950(  6480),   40(   64),  65400( 414720),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1940(  6464),   1900(  6400),  100(  256), 194000(1654784),   0,    cd980 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  265(TIDL_EltWiseLayer) [269, 265] --[512 x 80 x  80] => [256 x 80 x  80] *** [512] ***[ COL] ***[0, 0, 0, 6400, 6400]**** [16], [0],[16] -[259 262 ]---
  IN: DDR, DMA,   1c00(  7168),   1900(  6400),  100(  256), 1c0400(1836032),   0,   12c400 ||||  L2, DMA,   1950(  6480),   1950(  6480),   20(   32),  65400( 414720),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1940(  6464),   1900(  6400),  100(  256), 194000(1654784),   0,    cd980 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  268(TIDL_ConvolutionLayer) [270, 268] --[256 x 80 x  80] => [128 x 80 x  80] *** [256] ***[ROW_L] ***[0, 0, 0, 768, 6400]**** [9], [1],[9] -[265 ]---
  IN:MSMC, DMA,   1940(  6464),   1900(  6400),  100(  256), 194000(1654784),   0,    cd980 ||||  L2, DMA,    640(  1600),    640(  1600),  100(  256),  65580( 415104),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1940(  6464),   1900(  6400),   80(  128),  ca000( 827392),   0,    cd980 
  WT:DDR_PERSIST, DMA,    100(   256),    100(   256),   80(  128),   8200(  33280),   0,  3a26280 ||||  L2, DMA,    140(   320),    100(   256),   80(  128),   a200(  41472),   0,    65580 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  270(TIDL_BatchNormLayer) [271, 270] --[128 x 80 x  80] => [128 x 80 x  80] *** [128] ***[ COL] ***[0, 0, 0, 6400, 6400]**** [4], [0],[4] -[268 ]---
  IN:MSMC, DMA,   1940(  6464),   1900(  6400),   80(  128),  ca000( 827392),   0,    cd980 ||||  L2, DMA,   1950(  6480),   1950(  6480),   40(   64),  65400( 414720),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1940(  6464),   1900(  6400),   80(  128),  ca000( 827392),   0,   197980 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  272(TIDL_EltWiseLayer) [272, 272] --[256 x 80 x  80] => [128 x 80 x  80] *** [256] ***[ COL] ***[0, 0, 0, 6400, 6400]**** [8], [0],[8] -[268 270 ]---
  IN:MSMC, DMA,   1940(  6464),   1900(  6400),   80(  128),  ca000( 827392),   0,    cd980 ||||  L2, DMA,   1950(  6480),   1950(  6480),   20(   32),  65400( 414720),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1940(  6464),   1900(  6400),   80(  128),  ca000( 827392),   0,    cd980 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  273(TIDL_ConvolutionLayer) [273, 273] --[128 x 80 x  80] => [256 x 80 x  80] *** [128] ***[ROW_L] ***[162, 192, 81, 384, 6400]**** [17], [1],[17] -[272 ]---
  IN:MSMC, DMA,   1940(  6464),   1900(  6400),   80(  128),  ca000( 827392),   0,    cd980 ||||  L2, DMA,    3c0(   960),    3c0(   960),   80(  128),  1f700( 128768),   0,        0 
 OUT:MSMC, CPU,    1c0(   448),    180(   384),  100(  256),  38000( 229376),   0,        0 |||| DDR, DMA,   1c00(  7168),   1900(  6400),  100(  256), 1c0400(1836032),   0,   12c400 
  WT:DDR_PERSIST, DMA,    480(  1152),    480(  1152),  100(  256),  48400( 295936),   0,  3a2e480 ||||  L2, DMA,    4c0(  1216),    480(  1152),  100(  256),  4c400( 312320),   0,    1f700 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  274(TIDL_BatchNormLayer) [274, 274] --[256 x 80 x  80] => [256 x 80 x  80] *** [256] ***[ COL] ***[0, 0, 0, 6400, 6400]**** [8], [0],[8] -[273 ]---
  IN: DDR, DMA,   1c00(  7168),   1900(  6400),  100(  256), 1c0400(1836032),   0,   12c400 ||||  L2, DMA,   1950(  6480),   1950(  6480),   40(   64),  65400( 414720),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1940(  6464),   1900(  6400),  100(  256), 194000(1654784),   0,    cd980 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  275(TIDL_EltWiseLayer) [275, 275] --[512 x 80 x  80] => [256 x 80 x  80] *** [512] ***[ COL] ***[0, 0, 0, 6400, 6400]**** [16], [0],[16] -[273 274 ]---
  IN: DDR, DMA,   1c00(  7168),   1900(  6400),  100(  256), 1c0400(1836032),   0,   12c400 ||||  L2, DMA,   1950(  6480),   1950(  6480),   20(   32),  65400( 414720),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1940(  6464),   1900(  6400),  100(  256), 194000(1654784),   0,    cd980 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  276(TIDL_ConvolutionLayer) [276, 276] --[256 x 80 x  80] => [128 x 80 x  80] *** [256] ***[ROW_L] ***[0, 0, 0, 768, 6400]**** [9], [1],[9] -[275 ]---
  IN:MSMC, DMA,   1940(  6464),   1900(  6400),  100(  256), 194000(1654784),   0,    cd980 ||||  L2, DMA,    640(  1600),    640(  1600),  100(  256),  65580( 415104),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1940(  6464),   1900(  6400),   80(  128),  ca000( 827392),   0,    cd980 
  WT:DDR_PERSIST, DMA,    100(   256),    100(   256),   80(  128),   8200(  33280),   0,  3a76880 ||||  L2, DMA,    140(   320),    100(   256),   80(  128),   a200(  41472),   0,    65580 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  277(TIDL_BatchNormLayer) [277, 277] --[128 x 80 x  80] => [128 x 80 x  80] *** [128] ***[ COL] ***[0, 0, 0, 6400, 6400]**** [4], [0],[4] -[276 ]---
  IN:MSMC, DMA,   1940(  6464),   1900(  6400),   80(  128),  ca000( 827392),   0,    cd980 ||||  L2, DMA,   1950(  6480),   1950(  6480),   40(   64),  65400( 414720),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1940(  6464),   1900(  6400),   80(  128),  ca000( 827392),   0,   197980 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  278(TIDL_EltWiseLayer) [278, 278] --[256 x 80 x  80] => [128 x 80 x  80] *** [256] ***[ COL] ***[0, 0, 0, 6400, 6400]**** [8], [0],[8] -[276 277 ]---
  IN:MSMC, DMA,   1940(  6464),   1900(  6400),   80(  128),  ca000( 827392),   0,    cd980 ||||  L2, DMA,   1950(  6480),   1950(  6480),   20(   32),  65400( 414720),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1940(  6464),   1900(  6400),   80(  128),  ca000( 827392),   0,    cd980 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  279(TIDL_ConvolutionLayer) [279, 279] --[128 x 80 x  80] => [256 x 80 x  80] *** [128] ***[ROW_L] ***[162, 192, 81, 384, 6400]**** [17], [1],[17] -[278 ]---
  IN:MSMC, DMA,   1940(  6464),   1900(  6400),   80(  128),  ca000( 827392),   0,    cd980 ||||  L2, DMA,    3c0(   960),    3c0(   960),   80(  128),  1f700( 128768),   0,        0 
 OUT:MSMC, CPU,    1c0(   448),    180(   384),  100(  256),  38000( 229376),   0,        0 |||| DDR, DMA,   1c00(  7168),   1900(  6400),  100(  256), 1c0400(1836032),   0,   12c400 
  WT:DDR_PERSIST, DMA,    480(  1152),    480(  1152),  100(  256),  48400( 295936),   0,  3a7ea80 ||||  L2, DMA,    4c0(  1216),    480(  1152),  100(  256),  4c400( 312320),   0,    1f700 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  280(TIDL_BatchNormLayer) [280, 280] --[256 x 80 x  80] => [256 x 80 x  80] *** [256] ***[ COL] ***[0, 0, 0, 6400, 6400]**** [8], [0],[8] -[279 ]---
  IN: DDR, DMA,   1c00(  7168),   1900(  6400),  100(  256), 1c0400(1836032),   0,   12c400 ||||  L2, DMA,   1950(  6480),   1950(  6480),   40(   64),  65400( 414720),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1940(  6464),   1900(  6400),  100(  256), 194000(1654784),   0,    cd980 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  281(TIDL_EltWiseLayer) [281, 281] --[512 x 80 x  80] => [256 x 80 x  80] *** [512] ***[ COL] ***[0, 0, 0, 6400, 6400]**** [16], [0],[16] -[279 280 ]---
  IN: DDR, DMA,   1c00(  7168),   1900(  6400),  100(  256), 1c0400(1836032),   0,   12c400 ||||  L2, DMA,   1950(  6480),   1950(  6480),   20(   32),  65400( 414720),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1940(  6464),   1900(  6400),  100(  256), 194000(1654784),   0,    cd980 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  282(TIDL_ConvolutionLayer) [282, 282] --[256 x 80 x  80] => [57 x 80 x  80] *** [256] ***[ROW_L] ***[0, 0, 0, 832, 6400]**** [8], [1],[8] -[281 ]---
  IN:MSMC, DMA,   1940(  6464),   1900(  6400),  100(  256), 194000(1654784),   0,    cd980 ||||  L2, DMA,    680(  1664),    680(  1664),  100(  256),  69400( 431104),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1900(  6400),   1900(  6400),   39(   57),  59100( 364800),   0,        0 
  WT:DDR_PERSIST, DMA,    100(   256),    100(   256),   39(   57),   3a00(  14848),   0,  3ac6e80 ||||  L2, DMA,    100(   256),    100(   256),   39(   57),   3a00(  14848),   0,    69400 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  283(TIDL_ReshapeLayer) [283, 283] --[57 x 80 x  80] => [19 x 80 x  80] *** [57] ***[ COL] ***[0, 0, 0, 6400, 6400]**** [9], [0],[9] -[282 ]---
  IN:MSMC, DMA,   1900(  6400),   1900(  6400),   39(   57),  59100( 364800),   0,        0 ||||  L2, DMA,   1900(  6400),   1900(  6400),   26(   38),  3b600( 243200),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   1900(  6400),   1900(  6400),   13(   19),  59100( 364800),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  284(TIDL_TransposeLayer) [284, 284] --[19 x 80 x  80] => [80 x 19 x  80] *** [19] ***[ COL] ***[0, 0, 0, 121600, 6400]**** [3], [0],[3] -[283 ]---
  IN:MSMC, DMA,   1900(  6400),   1900(  6400),   13(   19),  59100( 364800),   0,        0 ||||  L2, DMA,  6f800(456704),  6f800(456704),    2(    2),  6f800( 456704),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    5f0(  1520),    5f0(  1520),   50(   80),  59100( 364800),   0,    cd980 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  285(TIDL_BatchNormLayer) [285, 285] --[80 x 19 x  80] => [80 x 19 x  80] *** [80] ***[ COL] ***[0, 0, 0, 1520, 1520]**** [6], [0],[6] -[284 ]---
  IN:MSMC, DMA,    5f0(  1520),    5f0(  1520),   50(   80),  59100( 364800),   0,    cd980 ||||  L2, DMA,    64f(  1615),    64f(  1615),   50(   80),  1f900( 129280),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    640(  1600),    5f0(  1520),   50(   80),  5dc00( 384000),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  286(TIDL_SliceLayer) [286, 286] --[80 x 19 x  80] => [80 x 2 x  80] *** [80] ***[ COL] ***[0, 0, 0, 1520, 1520]**** [6], [0],[6] -[285 ]---
  IN:MSMC, DMA,    640(  1600),    5f0(  1520),   50(   80),  5dc00( 384000),   0,        0 ||||  L2, DMA,    64f(  1615),    64f(  1615),   50(   80),  1f900( 129280),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     c0(   192),     a0(   160),   50(   80),   b400(  46080),   0,    5dc00 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  289(TIDL_BatchNormLayer) [287, 289] --[80 x 2 x  80] => [80 x 2 x  80] *** [80] ***[ COL] ***[0, 0, 0, 160, 160]**** [6], [0],[6] -[286 ]---
  IN:MSMC, DMA,     c0(   192),     a0(   160),   50(   80),   b400(  46080),   0,    5dc00 ||||  L2, DMA,     c0(   192),     c0(   192),   50(   80),   3c00(  15360),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     c0(   192),     a0(   160),   50(   80),   b400(  46080),   0,    5dc00 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  291(TIDL_EltWiseLayer) [288, 291] --[160 x 2 x  80] => [80 x 2 x  80] *** [160] ***[ COL] ***[0, 0, 0, 160, 160]**** [4], [0],[4] -[289 3 ]---
  IN:MSMC, DMA,     c0(   192),     a0(   160),   50(   80),   b400(  46080),   0,    5dc00 ||||  L2, DMA,     c0(   192),     c0(   192),   78(  120),   b400(  46080),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     c0(   192),     a0(   160),   50(   80),   b400(  46080),   0,    5dc00 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  293(TIDL_BatchNormLayer) [289, 293] --[80 x 2 x  80] => [80 x 2 x  80] *** [80] ***[ COL] ***[0, 0, 0, 160, 160]**** [6], [0],[6] -[291 ]---
  IN:MSMC, DMA,     c0(   192),     a0(   160),   50(   80),   b400(  46080),   0,    5dc00 ||||  L2, DMA,     c0(   192),     c0(   192),   50(   80),   3c00(  15360),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     c0(   192),     a0(   160),   50(   80),   b400(  46080),   0,    5dc00 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  287(TIDL_SliceLayer) [290, 287] --[80 x 19 x  80] => [80 x 2 x  80] *** [80] ***[ COL] ***[0, 0, 0, 1520, 1520]**** [6], [0],[6] -[285 ]---
  IN:MSMC, DMA,    640(  1600),    5f0(  1520),   50(   80),  5dc00( 384000),   0,        0 ||||  L2, DMA,    64f(  1615),    64f(  1615),   50(   80),  1f900( 129280),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     c0(   192),     a0(   160),   50(   80),   b400(  46080),   0,    84680 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  290(TIDL_BatchNormLayer) [291, 290] --[80 x 2 x  80] => [80 x 2 x  80] *** [80] ***[ COL] ***[0, 0, 0, 160, 160]**** [6], [0],[6] -[287 ]---
  IN:MSMC, DMA,     c0(   192),     a0(   160),   50(   80),   b400(  46080),   0,    84680 ||||  L2, DMA,     c0(   192),     c0(   192),   50(   80),   3c00(  15360),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     c0(   192),     a0(   160),   50(   80),   b400(  46080),   0,    84680 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  292(TIDL_BatchNormLayer) [292, 292] --[80 x 2 x  80] => [80 x 2 x  80] *** [80] ***[ COL] ***[0, 0, 0, 160, 160]**** [6], [0],[6] -[290 ]---
  IN:MSMC, DMA,     c0(   192),     a0(   160),   50(   80),   b400(  46080),   0,    84680 ||||  L2, DMA,     c0(   192),     c0(   192),   50(   80),   3c00(  15360),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     c0(   192),     a0(   160),   50(   80),   b400(  46080),   0,    84680 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  294(TIDL_EltWiseLayer) [293, 294] --[160 x 2 x  80] => [80 x 2 x  80] *** [160] ***[ COL] ***[0, 0, 0, 160, 160]**** [4], [0],[4] -[292 0 ]---
  IN:MSMC, DMA,     c0(   192),     a0(   160),   50(   80),   b400(  46080),   0,    84680 ||||  L2, DMA,     c0(   192),     c0(   192),   78(  120),   b400(  46080),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     c0(   192),     a0(   160),   50(   80),   b400(  46080),   0,    82500 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  288(TIDL_SliceLayer) [294, 288] --[80 x 19 x  80] => [80 x 15 x  80] *** [80] ***[ COL] ***[0, 0, 0, 1520, 1520]**** [6], [0],[6] -[285 ]---
  IN:MSMC, DMA,    640(  1600),    5f0(  1520),   50(   80),  5dc00( 384000),   0,        0 ||||  L2, DMA,    64f(  1615),    64f(  1615),   50(   80),  1f900( 129280),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    4c0(  1216),    4b0(  1200),   50(   80),  47400( 291840),   0,    cd980 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  295(TIDL_ConcatLayer) [295, 295] --[80 x 15 x  80] => [80 x 19 x  80] *** [80] ***[ COL] ***[0, 0, 0, 1200, 1200]**** [6], [0],[6] -[293 294 288 ]---
  IN:MSMC, DMA,     c0(   192),     a0(   160),   50(   80),   b400(  46080),   0,    5dc00 ||||  L2, DMA,    4b0(  1200),    4b0(  1200),   50(   80),  17700(  96000),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    5f0(  1520),    5f0(  1520),   50(   80),  59100( 364800),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  296(TIDL_ReshapeLayer) [296, 296] --[80 x 19 x  80] => [1 x 19 x  19200] *** [80] ***[ COL] ***[0, 0, 0, 1520, 1520]**** [1], [0],[1] -[295 ]---
  IN:MSMC, DMA,    5f0(  1520),    5f0(  1520),   50(   80),  59100( 364800),   0,        0 ||||  L2, DMA,    5f0(  1520),    5f0(  1520),   50(   80),  1db00( 121600),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,  59100(364800),  59100(364800),    1(    1),  59100( 364800),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  297(TIDL_ConcatLayer) [297, 297] --[1 x 19 x  19200] => [1 x 19 x  25200] *** [1] ***[ COL] ***[0, 0, 0, 121600, 364800]**** [3], [0],[3] -[296 271 232 ]---
  IN:MSMC, DMA,  59100(364800),  59100(364800),    1(    1),  59100( 364800),   0,        0 ||||  L2, DMA,  3b600(243200),  3b600(243200),    1(    1),  3b600( 243200),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff |||| DDR, CPU,  74e50(478800),  74e50(478800),    1(    1),  75280( 479872),   0,   12c400 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
