From ab4eb9f30b087a6d8cbae869482863a75cabbc34 Mon Sep 17 00:00:00 2001
From: Zijian.He <Zijian.He@desaysv.com>
Date: Tue, 11 Mar 2025 14:24:44 +0800
Subject: [PATCH] [DDR][Feature][适配512M DDR][TASK20250228_33247][Testable]

[root_cause]:平台默认DDR 2G
[solution]:适配512M DDR
[affected_area]:DDR
[self_test_result]:Pass
[test_suggestion]:NA
[others]:NA

Change-Id: I5dc67ddcadd9b1d03e2b5159264629e4fae7a501
---

diff --git a/board-support/ti-linux-kernel/arch/arm64/boot/dts/ti/k3-am625-sk.dts b/board-support/ti-linux-kernel/arch/arm64/boot/dts/ti/k3-am625-sk.dts
index 910feb7..60e2d74 100644
--- a/board-support/ti-linux-kernel/arch/arm64/boot/dts/ti/k3-am625-sk.dts
+++ b/board-support/ti-linux-kernel/arch/arm64/boot/dts/ti/k3-am625-sk.dts
@@ -24,8 +24,8 @@
 
 	memory@80000000 {
 		device_type = "memory";
-		/* 2G RAM */
-		reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
+		/* 512M RAM */
+		reg = <0x00000000 0x80000000 0x00000000 0x20000000>;
 
 	};
 
diff --git a/board-support/ti-u-boot/arch/arm/dts/k3-am62-lp4-50-800-800.dtsi b/board-support/ti-u-boot/arch/arm/dts/k3-am62-lp4-50-800-800.dtsi
index ee9e213..9310719 100644
--- a/board-support/ti-u-boot/arch/arm/dts/k3-am62-lp4-50-800-800.dtsi
+++ b/board-support/ti-u-boot/arch/arm/dts/k3-am62-lp4-50-800-800.dtsi
@@ -1,21 +1,23 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * This file was generated with the
- * AM623/AM625 SysConfig DDR Configuration Tool for AM64x, AM625, AM623, AM62Ax, AM62Px v0.10.02
- * Tue Sep 17 2024 13:07:19 GMT+0530 (India Standard Time)
+ * AM623/AM625 SysConfig DDR Configuration Tool for AM64x, AM625, AM623, AM62Ax, AM62Px, AM62Dx v0.10.10
+ * Mon Mar 03 2025 09:17:36 GMT+0800 (China Standard Time)
  * DDR Type: LPDDR4
  * F0 = 50MHz    F1 = NA     F2 = 800MHz
- * Density (per channel): 16Gb
+ * Density (per channel): 4Gb
  * Write DBI: Enable
  * Number of Ranks: 1
- */
+*/
+
 
 #define DDRSS_PLL_FHS_CNT 3
 #define DDRSS_PLL_FREQUENCY_1 400000000
 #define DDRSS_PLL_FREQUENCY_2 400000000
-#define DDRSS_SDRAM_IDX 15
+#define DDRSS_SDRAM_IDX 13
 #define DDRSS_REGION_IDX 16
 
+
 #define DDRSS_CTL_0_DATA 0x00000B00
 #define DDRSS_CTL_1_DATA 0x00000000
 #define DDRSS_CTL_2_DATA 0x00000000
@@ -88,18 +90,18 @@
 #define DDRSS_CTL_69_DATA 0x00000101
 #define DDRSS_CTL_70_DATA 0x00000000
 #define DDRSS_CTL_71_DATA 0x01000000
-#define DDRSS_CTL_72_DATA 0x00130803
+#define DDRSS_CTL_72_DATA 0x00090803
 #define DDRSS_CTL_73_DATA 0x000000BB
-#define DDRSS_CTL_74_DATA 0x00000130
+#define DDRSS_CTL_74_DATA 0x00000090
 #define DDRSS_CTL_75_DATA 0x00000C28
-#define DDRSS_CTL_76_DATA 0x00000130
+#define DDRSS_CTL_76_DATA 0x00000090
 #define DDRSS_CTL_77_DATA 0x00000C28
 #define DDRSS_CTL_78_DATA 0x00000005
-#define DDRSS_CTL_79_DATA 0x0000000A
+#define DDRSS_CTL_79_DATA 0x00000005
 #define DDRSS_CTL_80_DATA 0x00000010
-#define DDRSS_CTL_81_DATA 0x00000098
+#define DDRSS_CTL_81_DATA 0x00000048
 #define DDRSS_CTL_82_DATA 0x0000017E
-#define DDRSS_CTL_83_DATA 0x00000098
+#define DDRSS_CTL_83_DATA 0x00000048
 #define DDRSS_CTL_84_DATA 0x0000017E
 #define DDRSS_CTL_85_DATA 0x03004000
 #define DDRSS_CTL_86_DATA 0x00001201
@@ -111,10 +113,10 @@
 #define DDRSS_CTL_92_DATA 0x05030C06
 #define DDRSS_CTL_93_DATA 0x01030C06
 #define DDRSS_CTL_94_DATA 0x02010201
-#define DDRSS_CTL_95_DATA 0x00001401
-#define DDRSS_CTL_96_DATA 0x01360014
-#define DDRSS_CTL_97_DATA 0x01360136
-#define DDRSS_CTL_98_DATA 0x00000136
+#define DDRSS_CTL_95_DATA 0x00000A01
+#define DDRSS_CTL_96_DATA 0x0096000A
+#define DDRSS_CTL_97_DATA 0x00960096
+#define DDRSS_CTL_98_DATA 0x00000096
 #define DDRSS_CTL_99_DATA 0x00000000
 #define DDRSS_CTL_100_DATA 0x05010303
 #define DDRSS_CTL_101_DATA 0x0C040505
@@ -333,8 +335,8 @@
 #define DDRSS_CTL_314_DATA 0x00280028
 #define DDRSS_CTL_315_DATA 0x00000100
 #define DDRSS_CTL_316_DATA 0x01010000
-#define DDRSS_CTL_317_DATA 0x00000000
-#define DDRSS_CTL_318_DATA 0x3FFF0000
+#define DDRSS_CTL_317_DATA 0x00000202
+#define DDRSS_CTL_318_DATA 0x0FFF0000
 #define DDRSS_CTL_319_DATA 0x000FFF00
 #define DDRSS_CTL_320_DATA 0xFFFFFFFF
 #define DDRSS_CTL_321_DATA 0x00FFFF00
@@ -516,7 +518,7 @@
 #define DDRSS_PI_74_DATA 0x00000000
 #define DDRSS_PI_75_DATA 0x00000000
 #define DDRSS_PI_76_DATA 0x01000000
-#define DDRSS_PI_77_DATA 0x08000100
+#define DDRSS_PI_77_DATA 0x08020100
 #define DDRSS_PI_78_DATA 0x00020000
 #define DDRSS_PI_79_DATA 0x00010002
 #define DDRSS_PI_80_DATA 0x00000001
@@ -614,11 +616,11 @@
 #define DDRSS_PI_172_DATA 0x0000080C
 #define DDRSS_PI_173_DATA 0x00081C00
 #define DDRSS_PI_174_DATA 0x001C0000
-#define DDRSS_PI_175_DATA 0x00000013
+#define DDRSS_PI_175_DATA 0x00000009
 #define DDRSS_PI_176_DATA 0x000000BB
-#define DDRSS_PI_177_DATA 0x00000130
+#define DDRSS_PI_177_DATA 0x00000090
 #define DDRSS_PI_178_DATA 0x00000C28
-#define DDRSS_PI_179_DATA 0x00000130
+#define DDRSS_PI_179_DATA 0x00000090
 #define DDRSS_PI_180_DATA 0x04000C28
 #define DDRSS_PI_181_DATA 0x01010404
 #define DDRSS_PI_182_DATA 0x00001501
@@ -646,8 +648,8 @@
 #define DDRSS_PI_204_DATA 0x00C90100
 #define DDRSS_PI_205_DATA 0x010000C9
 #define DDRSS_PI_206_DATA 0x00C900C9
-#define DDRSS_PI_207_DATA 0x32103200
-#define DDRSS_PI_208_DATA 0x01013210
+#define DDRSS_PI_207_DATA 0x321E3200
+#define DDRSS_PI_208_DATA 0x0101321E
 #define DDRSS_PI_209_DATA 0x0A070601
 #define DDRSS_PI_210_DATA 0x0D09070D
 #define DDRSS_PI_211_DATA 0x0D09070D
@@ -692,8 +694,8 @@
 #define DDRSS_PI_250_DATA 0x0000F320
 #define DDRSS_PI_251_DATA 0x00001850
 #define DDRSS_PI_252_DATA 0x0000F320
-#define DDRSS_PI_253_DATA 0x01360014
-#define DDRSS_PI_254_DATA 0x03030136
+#define DDRSS_PI_253_DATA 0x0096000A
+#define DDRSS_PI_254_DATA 0x03030096
 #define DDRSS_PI_255_DATA 0x00000003
 #define DDRSS_PI_256_DATA 0x00000000
 #define DDRSS_PI_257_DATA 0x05030503
@@ -702,17 +704,17 @@
 #define DDRSS_PI_260_DATA 0x000186A0
 #define DDRSS_PI_261_DATA 0x00000005
 #define DDRSS_PI_262_DATA 0x00000064
-#define DDRSS_PI_263_DATA 0x00000014
+#define DDRSS_PI_263_DATA 0x0000000A
 #define DDRSS_PI_264_DATA 0x00027100
 #define DDRSS_PI_265_DATA 0x000186A0
 #define DDRSS_PI_266_DATA 0x00000005
 #define DDRSS_PI_267_DATA 0x00000640
-#define DDRSS_PI_268_DATA 0x00000136
+#define DDRSS_PI_268_DATA 0x00000096
 #define DDRSS_PI_269_DATA 0x00027100
 #define DDRSS_PI_270_DATA 0x000186A0
 #define DDRSS_PI_271_DATA 0x00000005
 #define DDRSS_PI_272_DATA 0x00000640
-#define DDRSS_PI_273_DATA 0x01000136
+#define DDRSS_PI_273_DATA 0x01000096
 #define DDRSS_PI_274_DATA 0x00320040
 #define DDRSS_PI_275_DATA 0x00010008
 #define DDRSS_PI_276_DATA 0x03200040
diff --git a/board-support/ti-u-boot/arch/arm/dts/k3-am625-r5-sk.dts b/board-support/ti-u-boot/arch/arm/dts/k3-am625-r5-sk.dts
index 0912b95..73e3769 100644
--- a/board-support/ti-u-boot/arch/arm/dts/k3-am625-r5-sk.dts
+++ b/board-support/ti-u-boot/arch/arm/dts/k3-am625-r5-sk.dts
@@ -5,7 +5,7 @@
  */
 
 #include "k3-am625-sk.dts"
-#include "k3-am62x-sk-ddr4-1600MTs.dtsi"
+#include "k3-am62-lp4-50-800-800.dtsi"
 #include "k3-am62-ddr.dtsi"
 
 #include "k3-am625-sk-u-boot.dtsi"
diff --git a/board-support/ti-u-boot/arch/arm/dts/k3-am625-sk.dts b/board-support/ti-u-boot/arch/arm/dts/k3-am625-sk.dts
index 5ca722a..ad567a0 100644
--- a/board-support/ti-u-boot/arch/arm/dts/k3-am625-sk.dts
+++ b/board-support/ti-u-boot/arch/arm/dts/k3-am625-sk.dts
@@ -24,8 +24,8 @@
 
 	memory@80000000 {
 		device_type = "memory";
-		/* 2G RAM */
-		reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
+		/* 512M RAM */
+		reg = <0x00000000 0x80000000 0x00000000 0x20000000>;
 
 	};
 
diff --git a/board-support/ti-u-boot/configs/am62x_evm_a53_defconfig b/board-support/ti-u-boot/configs/am62x_evm_a53_defconfig
index 34e598b..9e74316 100644
--- a/board-support/ti-u-boot/configs/am62x_evm_a53_defconfig
+++ b/board-support/ti-u-boot/configs/am62x_evm_a53_defconfig
@@ -143,6 +143,8 @@
 CONFIG_CMD_REMOTEPROC=y
 CONFIG_SYS_MALLOC_LEN=0x2000000
 CONFIG_SPL_GZIP=y
+CONFIG_SYS_MEM_TOP_HIDE=0x3800000
+
 
 #include <configs/am62x_a53_usbdfu.config>
 #include <configs/am62x_a53_usbmsc.config>
diff --git a/board-support/ti-u-boot/configs/am62x_evm_r5_defconfig b/board-support/ti-u-boot/configs/am62x_evm_r5_defconfig
index 4dae2c1..6cac6e1 100644
--- a/board-support/ti-u-boot/configs/am62x_evm_r5_defconfig
+++ b/board-support/ti-u-boot/configs/am62x_evm_r5_defconfig
@@ -131,3 +131,5 @@
 CONFIG_OMAP_TIMER=y
 CONFIG_LIB_RATIONAL=y
 CONFIG_SPL_LIB_RATIONAL=y
+CONFIG_SYS_MEM_TOP_HIDE=0x3800000
+
diff --git a/board-support/ti-u-boot/lib/lmb.c b/board-support/ti-u-boot/lib/lmb.c
index 44f9820..d482581 100644
--- a/board-support/ti-u-boot/lib/lmb.c
+++ b/board-support/ti-u-boot/lib/lmb.c
@@ -201,12 +201,24 @@
 
 	for (i = 0, map = memmap; i < map_size / sizeof(*map); ++map, ++i) {
 		if (map->type != EFI_CONVENTIONAL_MEMORY) {
-			lmb_reserve_flags(lmb,
-					  map_to_sysmem((void *)(uintptr_t)
-							map->physical_start),
-					  map->num_pages * EFI_PAGE_SIZE,
-					  map->type == EFI_RESERVED_MEMORY_TYPE
-					      ? LMB_NOMAP : LMB_NONE);
+			/* TODO it is depending on kernel reserve memory */
+			if (map->physical_start == gd->ram_top)
+			{
+				lmb_reserve_flags(lmb,
+						map_to_sysmem((void *)(uintptr_t)
+								map->physical_start),
+						map->num_pages * EFI_PAGE_SIZE,
+							LMB_NOMAP);
+			}
+			else
+			{
+				lmb_reserve_flags(lmb,
+						map_to_sysmem((void *)(uintptr_t)
+								map->physical_start),
+						map->num_pages * EFI_PAGE_SIZE,
+						map->type == EFI_RESERVED_MEMORY_TYPE
+							? LMB_NOMAP : LMB_NONE);
+			}
 		}
 	}
 	efi_free_pool(memmap);
