diff --git a/psdkla/board-support/ti-linux-kernel-6.6.32+git-ti/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/psdkla/board-support/ti-linux-kernel-6.6.32+git-ti/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
index e99e58300..10177a7ca 100644
--- a/psdkla/board-support/ti-linux-kernel-6.6.32+git-ti/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
+++ b/psdkla/board-support/ti-linux-kernel-6.6.32+git-ti/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
@@ -141,7 +141,8 @@ J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
 			J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */
 			J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */
 			J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */
-			J721E_IOPAD(0x25c, PIN_INPUT, 0) /* (R28) MMC1_SDWP */
+			// J721E_IOPAD(0x25c, PIN_INPUT, 0) /* (R28) MMC1_SDWP */
+			J721E_IOPAD(0x25c, PIN_INPUT, 6) /* (R28) MMC1_SDWP.PCIE3_CLKREQn */
 		>;
 	};
 
@@ -316,11 +317,11 @@ J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */
 	};
 
 	// add
-	main_pcie3_pins_default: main-pcie3-default-pins {
-		pinctrl-single,pins = <
-			J721E_IOPAD(0x25c, PIN_INPUT, 6) /* (R28) MMC1_SDWP.PCIE3_CLKREQn */
-		>;
-	};
+	// main_pcie3_pins_default: main-pcie3-default-pins {
+	// 	pinctrl-single,pins = <
+	// 		J721E_IOPAD(0x25c, PIN_INPUT, 6) /* (R28) MMC1_SDWP.PCIE3_CLKREQn */
+	// 	>;
+	// };
 
 	/* AG190W SPI <---> TDA4 SPI3 */
 	main_spi3_pins_default: main-spi3-default-pins {
@@ -437,6 +438,12 @@ J721E_WKUP_IOPAD(0xc8, PIN_INPUT, 7) /* (F29) WKUP_GPIO0_6 */
 		>;
 	};
 
+/* Reset for  PCIe3  */
+	mkey_reset_pins_default: mkey-reset-pns-default-pins {
+		pinctrl-single,pins = <
+			J721E_WKUP_IOPAD(0xdc, PIN_OUTPUT, 7) /* (H27) WKUP_GPIO0_11 */
+		>;
+	};
 
 	// add
 	mcu_rgmii1_pins_default: mcu-rgmii1-default-pins {
@@ -594,28 +601,30 @@ ufs@4e84000 {
 
 &serdes_ln_ctrl { /*disable serdes for cpsw9g*/
 	idle-states = <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>,
-		      <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>,
+		      <J721E_SERDES3_LANE0_PCIE3_LANE0>, <J721E_SERDES3_LANE1_PCIE3_LANE1>,
 		      <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
 		      <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
 };
 
-&serdes_wiz3 {
-	typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>;
-	typec-dir-debounce-ms = <700>;	/* TUSB321, tCCB_DEFAULT 133 ms */
-};
+/* delete for PCIE */
+// &serdes_wiz3 {
+// 	typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>;
+// 	typec-dir-debounce-ms = <700>;	/* TUSB321, tCCB_DEFAULT 133 ms */
+// };
 
 &serdes3 {
-	serdes3_usb_link: phy@0 {
+	assigned-clocks = <&serdes3 CDNS_SIERRA_PLL_CMNLC>;
+	assigned-clock-parents = <&wiz3_pll1_refclk>;
+
+	serdes3_pcie_link: phy@0 {
 		reg = <0>;
 		cdns,num-lanes = <2>;
 		#phy-cells = <0>;
-		cdns,phy-type = <PHY_TYPE_USB3>;
+		cdns,phy-type = <PHY_TYPE_PCIE>;
 		resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>;
-		status = "disabled"; /*disable serdes for cpsw9g*/
 	};
 };
 
-
 &ospi0 {
 	status = "okay";
 	flash@0 {
@@ -742,41 +751,42 @@ &cmn_refclk1 {
 	clock-frequency = <100000000>;
 };
 
-&wiz0_pll1_refclk {
-	assigned-clocks = <&wiz0_pll1_refclk>;
-	assigned-clock-parents = <&cmn_refclk1>;
-	status = "disabled";/*disable serdes for cpsw9g*/
-};
 
-&wiz0_refclk_dig {
-	assigned-clocks = <&wiz0_refclk_dig>;
-	assigned-clock-parents = <&cmn_refclk1>;
-	status = "disabled";
-};
+// &wiz0_pll1_refclk {
+// 	assigned-clocks = <&wiz0_pll1_refclk>;
+// 	assigned-clock-parents = <&cmn_refclk1>;
+// 	status = "disabled";/*disable serdes for cpsw9g*/
+// };
 
-&wiz1_pll1_refclk {
-	assigned-clocks = <&wiz1_pll1_refclk>;
-	assigned-clock-parents = <&cmn_refclk1>;
-	status = "disabled";
-};
+// &wiz0_refclk_dig {
+// 	assigned-clocks = <&wiz0_refclk_dig>;
+// 	assigned-clock-parents = <&cmn_refclk1>;
+// 	status = "disabled";
+// };
 
-&wiz1_refclk_dig {
-	assigned-clocks = <&wiz1_refclk_dig>;
-	assigned-clock-parents = <&cmn_refclk1>;
-	status = "disabled";
-};
+// &wiz1_pll1_refclk {
+// 	assigned-clocks = <&wiz1_pll1_refclk>;
+// 	assigned-clock-parents = <&cmn_refclk1>;
+// 	status = "disabled";
+// };
 
-&wiz2_pll1_refclk {
-	assigned-clocks = <&wiz2_pll1_refclk>;
-	assigned-clock-parents = <&cmn_refclk1>;
-	status = "disabled";
-};
+// &wiz1_refclk_dig {
+// 	assigned-clocks = <&wiz1_refclk_dig>;
+// 	assigned-clock-parents = <&cmn_refclk1>;
+// 	status = "disabled";
+// };
 
-&wiz2_refclk_dig {
-	assigned-clocks = <&wiz2_refclk_dig>;
-	assigned-clock-parents = <&cmn_refclk1>;
-	status = "disabled";
-};
+// &wiz2_pll1_refclk {
+// 	assigned-clocks = <&wiz2_pll1_refclk>;
+// 	assigned-clock-parents = <&cmn_refclk1>;
+// 	status = "disabled";
+// };
+
+// &wiz2_refclk_dig {
+// 	assigned-clocks = <&wiz2_refclk_dig>;
+// 	assigned-clock-parents = <&cmn_refclk1>;
+// 	status = "disabled";
+// };
 
 &serdes0 {
 	assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>;
@@ -818,10 +828,6 @@ &serdes_wiz2 {
 	status = "disabled";
 };
 
-&serdes_wiz3 {
-	status = "disabled";
-};
-
 &serdes2 {
 	assigned-clocks = <&serdes2 CDNS_SIERRA_PLL_CMNLC>;
 	assigned-clock-parents = <&wiz2_pll1_refclk>;
@@ -855,7 +861,7 @@ &mhdp {
 };
 
 &pcie0_rc {
-	status = "okay";
+	status = "disabled";
 	//reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;
 	phys = <&serdes0_pcie_link>;
 	phy-names = "pcie-phy";
@@ -863,7 +869,7 @@ &pcie0_rc {
 };
 
 &pcie1_rc {
-	status = "okay";
+	status = "disabled";
 	//reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
 	phys = <&serdes1_pcie_link>;
 	phy-names = "pcie-phy";
@@ -871,13 +877,24 @@ &pcie1_rc {
 };
 
 &pcie2_rc {
-	status = "okay";
+	status = "disabled";
 	//reset-gpios = <&exp2 20 GPIO_ACTIVE_HIGH>;
 	phys = <&serdes2_pcie_link>;
 	phy-names = "pcie-phy";
 	num-lanes = <2>;
 };
 
+&pcie3_rc {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&mkey_reset_pins_default>;
+	reset-gpios = <&wkup_gpio0 11 GPIO_ACTIVE_HIGH>;
+	//reset-gpios = <&exp2 20 GPIO_ACTIVE_HIGH>;
+	phys = <&serdes3_pcie_link>;
+	phy-names = "pcie-phy";
+	num-lanes = <2>;
+};
+
 #define K3_TS_OFFSET(pa, val)	(0x4+(pa)*4) (0x10000 | val)
 
 &timesync_router {
diff --git a/psdkla/board-support/ti-linux-kernel-6.6.32+git-ti/arch/arm64/boot/dts/ti/k3-j721e-evm-ethfw.dtso b/psdkla/board-support/ti-linux-kernel-6.6.32+git-ti/arch/arm64/boot/dts/ti/k3-j721e-evm-ethfw.dtso
index 93a13fd29..548eaa8e3 100644
--- a/psdkla/board-support/ti-linux-kernel-6.6.32+git-ti/arch/arm64/boot/dts/ti/k3-j721e-evm-ethfw.dtso
+++ b/psdkla/board-support/ti-linux-kernel-6.6.32+git-ti/arch/arm64/boot/dts/ti/k3-j721e-evm-ethfw.dtso
@@ -15,7 +15,7 @@ &serdes_ln_ctrl {
 	idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_QSGMII_LANE2>,
 		      <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
 		      <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>,
-		      <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>,
+		      <J721E_SERDES3_LANE0_PCIE3_LANE0>, <J721E_SERDES3_LANE1_PCIE3_LANE1>,
 		      <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
 		      <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
 };
diff --git a/psdkla/board-support/ti-linux-kernel-6.6.32+git-ti/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/psdkla/board-support/ti-linux-kernel-6.6.32+git-ti/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index bb54a4f6f..01cea3172 100644
--- a/psdkla/board-support/ti-linux-kernel-6.6.32+git-ti/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/psdkla/board-support/ti-linux-kernel-6.6.32+git-ti/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -7,6 +7,7 @@
 #include <dt-bindings/phy/phy.h>
 #include <dt-bindings/phy/phy-ti.h>
 #include <dt-bindings/mux/mux.h>
+#include <dt-bindings/phy/phy-cadence.h>
 
 #include "k3-serdes.h"
 
@@ -81,6 +82,16 @@ ehrpwm_tbclk: clock-controller@4140 {
 			reg = <0x4140 0x18>;
 			#clock-cells = <1>;
 		};
+
+		pcie3_ctrl: pcie3-ctrl@407c {
+ 			compatible = "ti,j784s4-pcie-ctrl", "syscon";
+ 			reg = <0x407c 0x4>;
+ 		};
+
+		acspcie1_proxy_ctrl: acspcie1-ctrl@18094 {
+			compatible = "ti,j784s4-acspcie-proxy-ctrl", "syscon";
+			reg = <0x18094 0x4>;
+		};
 	};
 
 	main_ehrpwm0: pwm@3000000 {
@@ -904,7 +915,7 @@ serdes_wiz3: wiz@5030000 {
 		num-lanes = <2>;
 		#reset-cells = <1>;
 		ranges = <0x5030000 0x0 0x5030000 0x10000>;
-		status = "disabled";
+		status = "okay";
 
 		wiz3_pll0_refclk: pll0-refclk {
 			clocks = <&k3_clks 295 9>, <&cmn_refclk>;
@@ -950,7 +961,6 @@ serdes3: serdes@5030000 {
 				 <&wiz3_pll0_refclk>, <&wiz3_pll1_refclk>;
 			clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
 				      "pll0_refclk", "pll1_refclk";
-			status = "disabled";
 		};
 	};
 
@@ -1051,12 +1061,16 @@ pcie3_rc: pcie@2930000 {
 		interrupt-names = "link_state";
 		interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>;
 		device_type = "pci";
-		ti,syscon-pcie-ctrl = <&scm_conf 0x407c>;
+		// ti,syscon-pcie-ctrl = <&scm_conf 0x407c>;
+		ti,syscon-pcie-ctrl = <&pcie3_ctrl 0x0>;
+		ti,syscon-acspcie-proxy-ctrl = <&acspcie1_proxy_ctrl 0x1>;
 		max-link-speed = <3>;
 		num-lanes = <2>;
 		power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
-		clocks = <&k3_clks 242 1>;
-		clock-names = "fck";
+		// clocks = <&k3_clks 242 1>;
+		// clock-names = "fck";
+		clocks = <&k3_clks 242 1>, <&serdes3 CDNS_SIERRA_PLL_CMNLC>;
+		clock-names = "fck","pcie_refclk";
 		#address-cells = <3>;
 		#size-cells = <2>;
 		bus-range = <0x0 0xff>;
diff --git a/psdkla/board-support/ti-linux-kernel-6.6.32+git-ti/drivers/Makefile b/psdkla/board-support/ti-linux-kernel-6.6.32+git-ti/drivers/Makefile
index 1bec7819a..4470f6fad 100644
--- a/psdkla/board-support/ti-linux-kernel-6.6.32+git-ti/drivers/Makefile
+++ b/psdkla/board-support/ti-linux-kernel-6.6.32+git-ti/drivers/Makefile
@@ -23,6 +23,7 @@ obj-$(CONFIG_GPIOLIB)		+= gpio/
 obj-y				+= pwm/
 
 obj-y				+= pci/
+obj-y				+= nogpl/
 
 obj-$(CONFIG_PARISC)		+= parisc/
 obj-$(CONFIG_RAPIDIO)		+= rapidio/
