diff --git a/psdkla/board-support/ti-linux-kernel-6.6.32+git-ti/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/psdkla/board-support/ti-linux-kernel-6.6.32+git-ti/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
index a974d15cc..1601469d6 100644
--- a/psdkla/board-support/ti-linux-kernel-6.6.32+git-ti/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
+++ b/psdkla/board-support/ti-linux-kernel-6.6.32+git-ti/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
@@ -527,7 +527,7 @@ &serdes_ln_ctrl {
 	idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>,
 		      <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
 		      <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>,
-		      <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>,
+		      <J721E_SERDES3_LANE0_PCIE3_LANE0>, <J721E_SERDES3_LANE1_PCIE3_LANE1>,
 		      <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
 		      <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
 };
@@ -538,11 +538,14 @@ &serdes_wiz3 {
 };
 
 &serdes3 {
-	serdes3_usb_link: phy@0 {
+	assigned-clocks = <&serdes3 CDNS_SIERRA_PLL_CMNLC>;
+	assigned-clock-parents = <&wiz3_pll1_refclk>;
+
+	serdes3_pcie_link: phy@0 {
 		reg = <0>;
 		cdns,num-lanes = <2>;
 		#phy-cells = <0>;
-		cdns,phy-type = <PHY_TYPE_USB3>;
+		cdns,phy-type = <PHY_TYPE_PCIE>;
 		resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>;
 	};
 };
@@ -672,36 +675,57 @@ &cmn_refclk1 {
 	clock-frequency = <100000000>;
 };
 
-&wiz0_pll1_refclk {
-	assigned-clocks = <&wiz0_pll1_refclk>;
-	assigned-clock-parents = <&cmn_refclk1>;
-};
+// &wiz0_pll1_refclk {
+// 	assigned-clocks = <&wiz0_pll1_refclk>;
+// 	assigned-clock-parents = <&cmn_refclk1>;
+// };
 
-&wiz0_refclk_dig {
-	assigned-clocks = <&wiz0_refclk_dig>;
-	assigned-clock-parents = <&cmn_refclk1>;
-};
+// &wiz0_refclk_dig {
+// 	assigned-clocks = <&wiz0_refclk_dig>;
+// 	assigned-clock-parents = <&cmn_refclk1>;
+// };
 
-&wiz1_pll1_refclk {
-	assigned-clocks = <&wiz1_pll1_refclk>;
-	assigned-clock-parents = <&cmn_refclk1>;
-};
+// &wiz1_pll1_refclk {
+// 	assigned-clocks = <&wiz1_pll1_refclk>;
+// 	assigned-clock-parents = <&cmn_refclk1>;
+// };
+
+// &wiz1_refclk_dig {
+// 	assigned-clocks = <&wiz1_refclk_dig>;
+// 	assigned-clock-parents = <&cmn_refclk1>;
+// };
 
-&wiz1_refclk_dig {
-	assigned-clocks = <&wiz1_refclk_dig>;
-	assigned-clock-parents = <&cmn_refclk1>;
+// &wiz2_pll1_refclk {
+// 	assigned-clocks = <&wiz2_pll1_refclk>;
+// 	assigned-clock-parents = <&cmn_refclk1>;
+// };
+
+// &wiz2_refclk_dig {
+// 	assigned-clocks = <&wiz2_refclk_dig>;
+// 	assigned-clock-parents = <&cmn_refclk1>;
+// };
+&wiz3_pll0_refclk {
+ assigned-clocks = <&wiz3_pll0_refclk>;
+ assigned-clock-parents = <&cmn_refclk1>;
 };
 
-&wiz2_pll1_refclk {
-	assigned-clocks = <&wiz2_pll1_refclk>;
-	assigned-clock-parents = <&cmn_refclk1>;
+
+&wiz3_refclk_dig {
+ assigned-clocks = <&wiz3_refclk_dig>;
+ assigned-clock-parents = <&cmn_refclk1>;
 };
 
-&wiz2_refclk_dig {
-	assigned-clocks = <&wiz2_refclk_dig>;
-	assigned-clock-parents = <&cmn_refclk1>;
+&wiz3_pll1_refclk {
+ assigned-clocks = <&wiz3_pll1_refclk>;
+ assigned-clock-parents = <&cmn_refclk1>;
 };
 
+
+&wiz3_refclk_dig {
+
+ assigned-clocks = <&wiz3_refclk_dig>;
+ assigned-clock-parents = <&cmn_refclk1>;
+};
 &serdes0 {
 	assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>;
 	assigned-clock-parents = <&wiz0_pll1_refclk>;
@@ -783,6 +807,13 @@ &pcie2_rc {
 	num-lanes = <2>;
 };
 
+&pcie3_rc {
+	status = "okay";
+	//reset-gpios = <&exp2 20 GPIO_ACTIVE_HIGH>;
+	phys = <&serdes3_pcie_link>;
+	phy-names = "pcie-phy";
+	num-lanes = <2>;
+};
 #define K3_TS_OFFSET(pa, val)	(0x4+(pa)*4) (0x10000 | val)
 
 &timesync_router {
diff --git a/psdkla/board-support/ti-u-boot-2024.04+git/configs/j721e_evm_a72_defconfig b/psdkla/board-support/ti-u-boot-2024.04+git/configs/j721e_evm_a72_defconfig
index fdcdc6c27..8f9faf73f 100644
--- a/psdkla/board-support/ti-u-boot-2024.04+git/configs/j721e_evm_a72_defconfig
+++ b/psdkla/board-support/ti-u-boot-2024.04+git/configs/j721e_evm_a72_defconfig
@@ -158,8 +158,8 @@ CONFIG_PHY_FIXED=y
 CONFIG_TI_AM65_CPSW_NUSS=y
 CONFIG_PHY=y
 CONFIG_SPL_PHY=y
-CONFIG_PHY_CADENCE_SIERRA=y
-CONFIG_PHY_J721E_WIZ=y
+#CONFIG_PHY_CADENCE_SIERRA=y
+#CONFIG_PHY_J721E_WIZ=y
 CONFIG_PINCTRL=y
 # CONFIG_PINCTRL_GENERIC is not set
 CONFIG_SPL_PINCTRL=y