diff --git a/psdkla/board-support/ti-linux-kernel-6.6.32+git-ti/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/psdkla/board-support/ti-linux-kernel-6.6.32+git-ti/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
index d5509536a..e042c5a97 100644
--- a/psdkla/board-support/ti-linux-kernel-6.6.32+git-ti/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
+++ b/psdkla/board-support/ti-linux-kernel-6.6.32+git-ti/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
@@ -585,22 +585,25 @@ &serdes_ln_ctrl {
 	idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>,
 		      <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
 		      <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>,
-		      <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>,
+		      <J721E_SERDES3_LANE0_PCIE3_LANE0>, <J721E_SERDES3_LANE1_PCIE3_LANE1>,
 		      <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
 		      <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
 };
 
-&serdes_wiz3 {
-	typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>;
-	typec-dir-debounce-ms = <700>;	/* TUSB321, tCCB_DEFAULT 133 ms */
-};
+// &serdes_wiz3 {
+// 	typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>;
+// 	typec-dir-debounce-ms = <700>;	/* TUSB321, tCCB_DEFAULT 133 ms */
+// };
 
 &serdes3 {
-	serdes3_usb_link: phy@0 {
+	assigned-clocks = <&serdes3 CDNS_SIERRA_PLL_CMNLC>;
+	assigned-clock-parents = <&wiz3_pll1_refclk>;
+
+	serdes3_pcie_link: phy@0 {
 		reg = <0>;
 		cdns,num-lanes = <2>;
 		#phy-cells = <0>;
-		cdns,phy-type = <PHY_TYPE_USB3>;
+		cdns,phy-type = <PHY_TYPE_PCIE>;
 		resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>;
 	};
 };
@@ -755,6 +758,16 @@ &wiz2_refclk_dig {
 	assigned-clock-parents = <&cmn_refclk1>;
 };
 
+&wiz3_pll1_refclk {
+       assigned-clocks = <&wiz3_pll1_refclk>;
+       assigned-clock-parents = <&cmn_refclk1>;
+};
+
+&wiz3_refclk_dig {
+       assigned-clocks = <&wiz3_refclk_dig>;
+       assigned-clock-parents = <&cmn_refclk1>;
+};
+
 &serdes0 {
 	assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>;
 	assigned-clock-parents = <&wiz0_pll1_refclk>;
@@ -822,7 +835,7 @@ &pcie0_rc {
 
 &pcie1_rc {
 	status = "okay";
-	//reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
+	reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
 	phys = <&serdes1_pcie_link>;
 	phy-names = "pcie-phy";
 	num-lanes = <2>;
@@ -830,12 +843,19 @@ &pcie1_rc {
 
 &pcie2_rc {
 	status = "okay";
-	//reset-gpios = <&exp2 20 GPIO_ACTIVE_HIGH>;
+	reset-gpios = <&exp2 20 GPIO_ACTIVE_HIGH>;
 	phys = <&serdes2_pcie_link>;
 	phy-names = "pcie-phy";
 	num-lanes = <2>;
 };
 
+&pcie3_rc {
+	status = "okay";
+	//reset-gpios = <&exp2 20 GPIO_ACTIVE_HIGH>;
+	phys = <&serdes3_pcie_link>;
+	phy-names = "pcie-phy";
+	num-lanes = <2>;
+};
 #define K3_TS_OFFSET(pa, val)	(0x4+(pa)*4) (0x10000 | val)
 
 &timesync_router {