{"text_format":"1","workbook":"xlsx","n_sheets":8,"sheets":["revision History","Use Case","Results","PWRCALC","MDB","Power Scaling","Notes","Internal Sheet"],"not_rendered":{"charts":0,"images":6,"macros":1,"external_links":0,"defined_names":48,"comments":1,"pivot_tables":0},"unopened":[],"bounds":{"document_bytes":16777216,"sheet_cells":100000,"rows_first":2000,"rows_last":500,"rows_between":2000,"halvings":0,"cell_chars":16384,"cell_head_chars":4096},"cells_cut":0,"cells_raw":0,"read":"whole","date_system":"1900"}

{"sheet":"revision History","index":0,"n_rows":12,"n_cols":5,"rows_kept":12,"cut":false,"hidden":false,"merged":[]}
["Date","Release",null,null,{"$f":"MATCH(TRUE,E$2:E$100,0)+1","v":5}]
["2024-05-17","Beta","AM62P release of J722S Power Estimation Tool",null,{"$f":"ISBLANK(B2)","v":false}]
["2024-06-09",1,"AM62P Power Estimation Tool",null,{"$f":"ISBLANK(B3)","v":false}]
["2024-08-27",1.1000000000000001,"Dynamic result bugfix. \nRemove PDN information as not applicable for AM62P. \nUpdate data",null,false]
[null,null,null,null,true]
[null,null,null,null,true]
[null,null,null,null,true]
[null,null,null,null,true]
[null,null,null,null,true]
[null,null,null,null,true]
[null,null,null,null,true]
[null,null,null,null,true]

{"sheet":"Use Case","index":1,"n_rows":55,"n_cols":13,"rows_kept":55,"cut":false,"hidden":false,"merged":[]}
["J722S, AM62P Power Estimation Tool",null,null,null,null,null,null,null,null,null,null,"Status:"]
[null,null,null,"Starting Use Case",null,null,null,null,null,null,null,"Start Reset","Done Reset"]
[null,"Modifiable Field",null,"UC1 0.75V Automotive Cluster",null,null,null,null,null,null,null,"Load Use Case","Done Load Use Case"]
[null,"Descriptor",null,null,null,null,null,null,null,null,null,"Start Calculate","Done Calculate"]
[]
[]
["Tj",150,"C"]
["SRAM_Voltage",0.85,"V"]
["CORE_Voltage",0.75,"V",null,"Processor Core Utilization (%)",null,null,null,{"$f":"IF(C17>D17, B17&\" exceeds \"&D17&\" MHz\",\"\")","v":""}]
["Process_Corner","Strong",null,null,"MAIN SMS 0",1,null,null,""]
["OPP","high",null,null,"MAIN (WKUP) R5FSS 0",1,null,null,""]
[null,null,null,null,"MAIN A53SS 0: 0",1,null,null,""]
["UC_Description","Add Test Description",null,null,"MAIN A53SS 0: 1",1,null,null,""]
["UC_Name","Add Test Name",null,null,"MAIN A53SS 0: 2",1,null,null,""]
[null,null,null,null,"MAIN A53SS 0: 3",1,null,null,""]
["Key IP Frequency selection",null,"Frequency [MHz]",null,"MAIN GPU 0",1,null,null,""]
["MAIN PLL 15 HSDIV 0","MAIN SMS 0 Frequency [MHz]",400,{"$f":"IF(B$11=\"high\",400,133)","v":400},"MAIN Video Encoder/Decoder 0",1,null,null,""]
["MAIN PLL 15 HSDIV 2\nMCU PLL 0 HSDIV 0","Domain Manager (WKUP) R5FSS 0 Frequency [MHz]",800,{"$f":"IF(B$11=\"high\",800,400)","v":800},"MCU R5FSS",1,null,null,""]
["MCU PLL 0 HSDIV 3","MCU R5FSS 0 Frequency [MHz]",800,{"$f":"IF(B$11=\"high\",800,400)","v":800},null,null,null,null,{"$f":"IF(F10>1, E10&\" exceeds 100%\",\"\")","v":""}]
["MAIN PLL 8 HSDIV0","MAIN A53SS Frequency [MHz]",1250,{"$f":"IF(B$9=0.85,1400,1250)","v":1250},null,null,null,null,{"$f":"IF(F11>1, E11&\" exceeds 100%\",\"\")","v":""}]
["MAIN PLL 6 HSDIV 0","MAIN GPU 0 Frequency [MHz]",720,{"$f":"IF(B$9=0.85,800,720)","v":720},"Memory Interfaces","Mode","Utilization",null,""]
["MAIN PLL 2 HSDIV 4","MAIN Video Encoder/Decoder 0 Frequency [MHz]",100,500,"DDRSS 0","lpddr4_2400_32",1,null,""]
["MAIN PLL 12 HSDIV0","LPDDR4 EMIF 0 [MT/s]",2133,{"$f":"IF(B$9=0.85,4000,3733)","v":3733},"GPMC / ELM","unused",0,null,""]
["MCU PLL 0 HSDIV 0","MCU SS / WKUP Modules CLK [MHz] (MCU SYSCLK)",400,{"$f":"IF(B$11=\"high\",400,200)","v":400},null,null,null,null,""]
["MAIN PLL 0 HSDIV 0","MAIN Modules CLK [MHz] (SYSCLK)",500,{"$f":"IF(B$11=\"high\",500,250)","v":500},"PHYs","Mode","Utilization","Instances",""]
["MAIN PLL 15 HSDIV 0\nMCU PLL 0 HSDIV 0","Device Manager Domain CLK [MHz]",400,{"$f":"IF(B$11=\"high\",400,133)","v":400},"CSI2.0 D_PHY 4L Rx","1p5g4l",0.1,1,""]
["MAIN PLL 15 HSDIV 0","HSM Domain CLK",400,null,"DSI D_PHY 4L Tx","off",0,0,""]
[null,null,null,null,"MAIN MMCSD0","hs400",1,1]
["IP for Complex IOs","Mode","Utilization","Instances","OLDI (2 Link)","oldi_dual_24b_modes",1,1]
["DSI Tx ports","ulps",0,0]
["USB 2.0","host_hs",1,2]
[]
["LVCMOS IO","Mode","Utilization","Instances"]
["WKUP I2C","i2c_400k_3p3v",1,1]
["WKUP UART","1m_3p3v",1,1]
["MCU I2C","i2c_400k_3p3v",1,1]
["MCU UART","112k_3p3v",1,1]
["MCU McSPI","Controller_2.083_Mbaud_3p3v",1,1]
["MCU MCAN","5mbs_3p3v",1,1]
["MCU GPIO","1mbs_3p3v_20pf",1,5]
[]
["LVCMOS IO","Mode","Utilization","Instances"]
["MAIN GPIO","1mbs_1p8v_20pf",1,30]
["MAIN I2C","i2c_400k_3p3v",1,3.0000000000000004]
["MAIN UART","3p6m_1p8v",1,5]
["MAIN McSPI","Controller_3.125_Mbaud_3p3v",1,3]
["MAIN McASP","16Ch_TX_48_ksps_24b_3p3v",1,3]
["MAIN ECAP","unused",1,0]
["MAIN EPWM","on_1p8v",1,3.0000000000000004]
["MAIN EQEP","off",1,0]
["MAIN MCAN","1mbs_3p3v",1,1]
["MAIN MMCSD1","hs200_200mbs",1,3]
["MAIN DSS 0: DPI","HD_|_1280x720x60_fps_24b_|_3p3V",1,1]
["MAIN FSS OSPI1 (QSPI)","ospi_ddr_controller_133_3p3v",1,1]
["MAIN Ethernet","rgmii_1000_1p8v",1,2]

{"sheet":"Results","index":2,"n_rows":70,"n_cols":35,"rows_kept":70,"cut":false,"hidden":false,"merged":[[0,4,4,13]]}
["UC_Name:","Add Test Name",null,"Caution:","This power estimation spreadsheet is subject to change. SoC power estimates provide approximate power and current consumption based on measured and simulated data; they are provided “as is” and are not guaranteed within a specified precision. Power consumption depends on electrical parameters, silicon process variations, environmental conditions, and uses cases running on the processor during operation. Actual power consumption should be verified in the real system. An end product’s SoC power, PDN integrity & thermal performance can vary depending on final use cases, features supported, software characteristics and system thermal design.  ",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"J722S, AM62P Power Estimation Tool"]
["UC_Description:","Add Test Description",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"Starting Use Case"]
["Based on Loaded Use Case:","UC1 0.75V Automotive Cluster",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"Modifiable Field",null,"UC1 0.75V Automotive Cluster"]
["Internal Reference Date:","2023-09-12",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"Descriptor"]
["Internal Reference Revision:",2.1]
["Date:","2025-05-26T10:41:42.220",null,"Conditions: Strong Process"]
["Tool Revision / Date",1.1000000000000001,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"Tj",150,"C"]
[null,"Power Estimation Tool Sitara 2.0.xlsm",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"SRAM_Voltage",0.85,"V"]
["Thermal Power",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"CORE_Voltage",0.75,"V",null,"Processor Core Utilization (%)",null,null,null,""]
["Tj [C]","Leakage Power [mW]","Dynamic Power [mW]","Total Power [mW]",null,null,null,"150C",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"Process_Corner","Strong",null,null,"MAIN SMS 0",1,null,null,""]
[125,2,2286,2288,null,null,null,"IP","Total Power [mW]",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"OPP","high",null,null,"MAIN (WKUP) R5FSS 0",1,null,null,""]
[120,2,2286,2288,null,null,null,"A53",170,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"MAIN A53SS 0: 0",1,null,null,""]
[115,2,2286,2288,null,null,null,"Pulsar",90,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"UC_Description","Add Test Description",null,null,"MAIN A53SS 0: 1",1,null,null,""]
[110,2,2286,2288,null,null,null,"GPU",270,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"UC_Name","Add Test Name",null,null,"MAIN A53SS 0: 2",1,null,null,""]
[105,2,2286,2288,null,null,null,"WAVE512CL",60,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"MAIN A53SS 0: 3",1,null,null,""]
[100,2,2286,2288,null,null,null,"DDR",390,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"Key IP Frequency selection",null,"Frequency [MHz]",null,"MAIN GPU 0",1,null,null,""]
[95,2,2286,2288,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"MAIN PLL 15 HSDIV 0","MAIN SMS 0 Frequency [MHz]",400,null,"MAIN Video Encoder/Decoder 0",1,null,null,""]
[90,2,2286,2288,null,null,null,"PD","PSC","State",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"MAIN PLL 15 HSDIV 2\nMCU PLL 0 HSDIV 0","Domain Manager (WKUP) R5FSS 0 Frequency [MHz]",800,null,"MCU R5FSS",1,null,null,""]
[85,2,2286,2288,null,null,null,"PD_Pulsar_MCU",null,"ON",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"MCU PLL 0 HSDIV 3","MCU R5FSS 0 Frequency [MHz]",800,null,null,null,null,null,""]
[80,2,2286,2288,null,null,null,"GP_Core_CTL",null,"ON",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"MAIN PLL 8 HSDIV0","MAIN A53SS Frequency [MHz]",1250,null,null,null,null,null,""]
[75,2,2286,2288,null,null,null,"PD_A53_0",null,"ON",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"MAIN PLL 6 HSDIV 0","MAIN GPU 0 Frequency [MHz]",720,null,"Memory Interfaces","Mode","Utilization",null,""]
[50,2,2286,2288,null,null,null,"PD_A53_1",null,"ON",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"MAIN PLL 2 HSDIV 4","MAIN Video Encoder/Decoder 0 Frequency [MHz]",100,null,"DDRSS 0","lpddr4_2400_32",1,null,""]
[25,2,2286,2288,null,null,null,"PD_A53_2",null,"ON",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"MAIN PLL 12 HSDIV0","LPDDR4 EMIF 0 [MT/s]",2133,null,"GPMC / ELM","unused",0,null,""]
[0,2,2286,2288,null,null,null,"PD_A53_3",null,"ON",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"MCU PLL 0 HSDIV 0","MCU SS / WKUP Modules CLK [MHz] (MCU SYSCLK)",400,null,null,null,null,null,""]
[-20,2,2286,2288,null,null,null,"PD_A53_Cluster_0",null,"ON",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"MAIN PLL 0 HSDIV 0","MAIN Modules CLK [MHz] (SYSCLK)",500,null,"PHYs","Mode","Utilization","Instances",""]
[-40,2,2286,2288,null,null,null,"PD_DSS",null,"ON",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"MAIN PLL 15 HSDIV 0\nMCU PLL 0 HSDIV 0","Device Manager Domain CLK [MHz]",400,null,"CSI2.0 D_PHY 4L Rx","1p5g4l",0.1,1,""]
[null,null,null,null,null,null,null,"PD_GPU",null,"ON",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"MAIN PLL 15 HSDIV 0","HSM Domain CLK",400,null,"DSI D_PHY 4L Tx","off",0,0,""]
["Tj = 150C",null,"",null,null,null,null,"PD_CPSW",null,"ON",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"MAIN MMCSD0","hs400",1,1]
["Thermal Power",null,"not suitable for designing a PDN",null,null,null,null,"PD_ENCODE",null,"ON",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"IP for Complex IOs","Mode","Utilization","Instances","OLDI (2 Link)","oldi_dual_24b_modes",1,1]
[null,"Leakage Power [mW]","Dynamic Power [mW]","Total Power [mW]","Voltage [V]","Total Current [mA]",null,"PD_DDR",null,"ON",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"DSI Tx ports","ulps",0,0]
["VDD_CORE",0,1024,1024,0.75,1366,null,"PD_Debug",null,"OFF",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"USB 2.0","host_hs",1,2]
["VDDR_CORE",0,0,0,0.85,0,null,"PD_HSM",null,"ON"]
["VDD_CANUART",0,0,0,0.75,0,null,"GP_Core_CTL_MCU",null,"ON",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"LVCMOS IO","Mode","Utilization","Instances"]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"WKUP I2C","i2c_400k_3p3v",1,1]
["VDDS_DDR/VDDS_DDR_C",0,216,216,1.1000000000000001,197,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"WKUP UART","1m_3p3v",1,1]
[null,null,null,null,null,null,null,"Core","Frequency","Utilization",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"MCU I2C","i2c_400k_3p3v",1,1]
["VDDA_1P8_CSI_DSI",0,19,19,1.8,11,null,"A53 CPU ",1250,1,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"MCU UART","112k_3p3v",1,1]
["VDDA_CORE_CSI_DSI",0,3,3,0.75,4,null,"A53 CPU ",1250,1,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"MCU McSPI","Controller_2.083_Mbaud_3p3v",1,1]
["VDDA_CORE_DSI_CLK",0,0,0,0.75,0,null,"A53 CPU ",1250,1,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"MCU MCAN","5mbs_3p3v",1,1]
[null,null,null,null,null,null,null,"R5F",800,1,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"MCU GPIO","1mbs_3p3v_20pf",1,5]
["VDDA_3P3_USB",0,4,4,3.3,2,null,"R5F",800,1]
["VDDA_1P8_USB",0,26,26,1.8,15,null,"Double DSS7UL + DSI + OLDI wrap",320,0.76,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"LVCMOS IO","Mode","Utilization","Instances"]
["VDDA_CORE_USB",0,0,0,0.75,0,null,"GPU BXS4-64-256KB DUST AM67",720,1,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"MAIN GPIO","1mbs_1p8v_20pf",1,30]
[null,null,null,null,null,null,null,"GPU BXS4-64-256KB Rascal AM67",720,1,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"MAIN I2C","i2c_400k_3p3v",1,3.0000000000000004]
["VDDA_1P8_OLDI0",0,149,149,1.8,83,null,"GPU BXS4-64-256KB Wrap AM67",720,1,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"MAIN UART","3p6m_1p8v",1,5]
[null,null,null,null,null,null,null,"WAVE521CL Video Codec",100,1,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"MAIN McSPI","Controller_3.125_Mbaud_3p3v",1,3]
["VDDA_PLL0",0,19,19,1.8,11,null,"CSI_RX",720,0.1,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"MAIN McASP","16Ch_TX_48_ksps_24b_3p3v",1,3]
["VDDA_PLL1",0,29,29,1.8,17,null,"CPSW3x",250,1,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"MAIN ECAP","unused",1,0]
["VDDA_PLL2",0,8,8,1.8,5,null,"USB2 Controller",125,1,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"MAIN EPWM","on_1p8v",1,3.0000000000000004]
["VDDA_PLL3",0,7,7,1.8,4,null,"LP/DDR4-32 PHY 3733",533.25,1.1000000000000001,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"MAIN EQEP","off",1,0]
["VDDA_PLL4",0,20,20,1.8,12,null,"EMMC 4",250,1,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"MAIN MCAN","1mbs_3p3v",1,1]
[null,null,null,null,null,null,null,"EMMC 4",250,1,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"MAIN MMCSD1","hs200_200mbs",1,3]
["VDDA_TEMP0",0,3,3,1.8,2,null,"EMMC 8",250,1,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"MAIN DSS 0: DPI","HD_|_1280x720x60_fps_24b_|_3p3V",1,1]
["VDDA_TEMP1",0,1,1,1.8,1,null,"GPMC_ELM",166.66666670000001,0,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"MAIN FSS OSPI1 (QSPI)","ospi_ddr_controller_133_3p3v",1,1]
["VDDA_TEMP2",0,1,1,1.8,1,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"MAIN Ethernet","rgmii_1000_1p8v",1,2]
["VDDS_OSC0",0,6,6,1.8,4]
[]
["VDDA_MCU",0,10,10,1.8,6]
[]
["VDDA_DDR_PLL0",1,4,5,0.75,7]
[]
["VDDS_MMC0",0,99,99,1.8,55]
["VDD_MMC0",0,0,0,0.85,0]
["VDDA_0P85_DLL_MMC0",1,4,5,0.85,6]
[]
["VDDSHV3P3",0,534,534,3.3,162]
["VDDSHV1P8",0,96,96,1.8,54]
["VDDSHV3P3_MCU",0,4,4,3.3,2]
["VDDSHV1P8_MCU",0,0,0,1.8,0]
["VDDSHV_CANUART",0,0,0]

{"sheet":"PWRCALC","index":3,"n_rows":252,"n_cols":90,"rows_kept":252,"cut":false,"hidden":true,"merged":[]}
[]
[]
["Physical Name","Insance Name","qty","scan_partition","vdd","vdda","vddh1","vddh2","Dyn_calc_method","pd","description","tag","type","function","Total mW","Power Domain Status","freq_trk","Use Case Mode","Util","pinmux","vdd_lkg","vdd_dyn_int_trk","vdd_dyn_sw_trk","vddr_lkg","vdda_lkg","vdda_dyn","vddh1_lkg","vddh1_dyn","vddh2_lkg","vddh2_dyn","vdd_dyn_idle","vdd_dyn_max","vdd_dyn_peak","vdd_dyn_int_trk","vdd_dyn_sw_trk","ulvt20_pct","ulvt16_pct","lvt20_pct","lvt16_pct","svt20_pct","svt16_pct","unit_leakage","unit_dyn_int","Notes","Long name to check for match with SoCDB","Utilization pointers","Utilization pointers","Utilization pointers","Utilization pointers","Utilization pointers","Utilization pointers","Utilization pointers","Utilization pointers","Utilization pointers","Utilization pointers","Frequency pointer","Frequency pointer","Frequency iteration",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"Tj",150,"C",null,"Thermal"]
["sam62a_mcu_pulsar_ul_wrap","_0",1,5,"VDD_CORE","N/A","N/A","N/A","SI","PD_Pulsar_MCU","Pulsar ULS","sam62p_nov_power","1 Processor","ARM_MCU",{"$f":"SUM(U4:AD4)","v":30.972365702479344},{"$f":"INDEX(PD_State_Table,MATCH(J4,PD_Table_Row_Header,0),2)","v":"ON"},800,{"$f":"IF(ISBLANK(BD4),0,INDIRECT(BD4))","v":800},{"$f":"IF(IF(ISBLANK(AT4),0,INDIRECT(AT4))=0,0,IF($CE$3=\"PDN\",1,IF(ISBLANK(AT4),0,INDIRECT(AT4))))","v":1},0,{"$f":"IFERROR(IF($I4=\"SI\",AP4*$C4*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ4*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK4*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL4*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM4*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN4*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO4*'Power Scaling'!F$4)*IF(P4=\"OFF\",0.06,1),VLOOKUP($A4&\"_\"&U$3,MDB,5,0)*$C4*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P4=\"OFF\",0.06,1)),0)","v":0},{"$f":"C4*IFERROR(IF($I4=\"SI\",(AE4*IF(S4=0,0,1)+(AF4-AE4)*S4)*IF(R4>0,R4,Q4)/Q4*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ4*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK4*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL4*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM4*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN4*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO4*'Power Scaling'!I$4)*AQ4,IF(OR($I4=\"AO\",$I4=\"LU\"),VLOOKUP($A4&\"_\"&\"vdd_dyn\"&\"_\"&$R4&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I4=\"LUUA\",$I4=\"LUUB\"),VLOOKUP($A4&\"_\"&\"vdd_dyn\"&\"_\"&$R4&\"\",MDB,5,0)*$C4*$S4*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A4&\"_\"&\"vdd_dyn\"&\"_\"&$R4&\"_idle\",MDB,5,0)*(1-$S4)+VLOOKUP($A4&\"_\"&\"vdd_dyn\"&\"_\"&$R4&\"_read\",MDB,5,0)*($S4/2)+VLOOKUP($A4&\"_\"&\"vdd_dyn\"&\"_\"&$R4&\"_write\",MDB,5,0)*($S4/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},{"$f":"C4*IFERROR(IF($I4=\"SI\",(AE4*IF(S4=0,0,1)+(AF4-AE4)*S4)*(IF(R4>0,R4,Q4)/Q4)*VLOOKUP(\"vdd_sw\",pwr_scale_table,2,0)*AI4,0),0)","v":30.972365702479344},{"$f":"IFERROR(VLOOKUP($A4&\"_\"&X$3,MDB,5,0)*$C4*VLOOKUP(\"vddr_lkg\",pwr_scale_table,2,0)*IF(P4=\"OFF\",0.06,1),0)","v":0},{"$f":"IFERROR(VLOOKUP($A4&\"_\"&Y$3,MDB,5,0)*$C4*(VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*0.5+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*0.5),0)","v":0},{"$f":"IFERROR(IF(I4=\"LUUB\",VLOOKUP($A4&\"_\"&Z$3&\"_\"&$R4&\"\",MDB,5,0)*$C4*$S4*((VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)/4+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)/4+VLOOKUP(\"vdd_sw\",pwr_scale_table,2,0)/2)),VLOOKUP($A4&\"_\"&Z$3&\"_\"&$R4&\"\",MDB,5,0)*$C4*((VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)/4+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)/4+VLOOKUP(\"vdd_sw\",pwr_scale_table,2,0)/2))),0)","v":0},{"$f":"IFERROR(VLOOKUP($A4&\"_\"&AA$3,MDB,5,0)*$C4*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0),0)","v":0},{"$f":"IFERROR(IF(OR($I4=\"LUUA\",$I4=\"LUUB\"),VLOOKUP($A4&\"_\"&AB$3&\"_\"&$R4&\"\",MDB,5,0)*$C4*$S4,IF(I4=\"LUUD\",VLOOKUP($A4&\"_\"&AB$3&\"_\"&$R4&\"_idle\",MDB,5,0)*(1-$S4)+VLOOKUP($A4&\"_\"&AB$3&\"_\"&$R4&\"_read\",MDB,5,0)*($S4/2)+VLOOKUP($A4&\"_\"&AB$3&\"_\"&$R4&\"_write\",MDB,5,0)*($S4/2),VLOOKUP($A4&\"_\"&AB$3&\"_\"&$R4&\"\",MDB,5,0)*$C4)),0)","v":0},{"$f":"IFERROR(VLOOKUP($A4&\"_\"&AC$3,MDB,5,0)*$C4*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0),0)","v":0},{"$f":"IFERROR(IF(OR($I4=\"LUUA\",$I4=\"LUUB\"),VLOOKUP($A4&\"_\"&AD$3&\"_\"&$R4&\"\",MDB,5,0)*$C4*$S4,IF(I4=\"LUUD\",VLOOKUP($A4&\"_\"&AD$3&\"_\"&$R4&\"_idle\",MDB,5,0)*(1-$S4)+VLOOKUP($A4&\"_\"&AD$3&\"_\"&$R4&\"_read\",MDB,5,0)*($S4/2)+VLOOKUP($A4&\"_\"&AD$3&\"_\"&$R4&\"_write\",MDB,5,0)*($S4/2),VLOOKUP($A4&\"_\"&AD$3&\"_\"&$R4&\"\",MDB,5,0)*$C4)),0)","v":0},0.111,0.4,0.36,122.6,106.6,0.01,0,0.27,0.11,0.31,0.3,3.5249461990040873,112.27334680747808,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.",{"$f":"A4&B4","v":"sam62a_mcu_pulsar_ul_wrap_0"},"CF$21",null,null,null,null,null,null,null,null,null,"CC$16",null,null,"Pulsar",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"SRAM_Voltage",0.85,"V",null,null,null,null,null,null,{"$f":"Tj&\"C\"","v":"150C"}]
["sam67_dm_wrap","_0",1,2,"VDD_CORE","N/A","N/A","N/A","SI","GP_Core_CTL","Pulsar UL (DM) AM67","sam67_feb_power","1 Processor","ARM_MCU",54.259749483471076,"ON",800,800,{"$f":"IF(IF(ISBLANK(AT5),0,INDIRECT(AT5))=0,0,IF($CE$3=\"PDN\",1,IF(ISBLANK(AT5),0,INDIRECT(AT5))))","v":1},0,{"$f":"IFERROR(IF($I5=\"SI\",AP5*$C5*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ5*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK5*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL5*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM5*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN5*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO5*'Power Scaling'!F$4)*IF(P5=\"OFF\",0.06,1),VLOOKUP($A5&\"_\"&U$3,MDB,5,0)*$C5*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P5=\"OFF\",0.06,1)),0)","v":0},{"$f":"C5*IFERROR(IF($I5=\"SI\",(AE5*IF(S5=0,0,1)+(AF5-AE5)*S5)*IF(R5>0,R5,Q5)/Q5*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ5*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK5*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL5*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM5*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN5*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO5*'Power Scaling'!I$4)*AQ5,IF(OR($I5=\"AO\",$I5=\"LU\"),VLOOKUP($A5&\"_\"&\"vdd_dyn\"&\"_\"&$R5&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I5=\"LUUA\",$I5=\"LUUB\"),VLOOKUP($A5&\"_\"&\"vdd_dyn\"&\"_\"&$R5&\"\",MDB,5,0)*$C5*$S5*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A5&\"_\"&\"vdd_dyn\"&\"_\"&$R5&\"_idle\",MDB,5,0)*(1-$S5)+VLOOKUP($A5&\"_\"&\"vdd_dyn\"&\"_\"&$R5&\"_read\",MDB,5,0)*($S5/2)+VLOOKUP($A5&\"_\"&\"vdd_dyn\"&\"_\"&$R5&\"_write\",MDB,5,0)*($S5/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},54.259749483471076,0,0,0,0,0,0,0,0.17299999999999999,0.3,0.36,244.9,249,0,0,0.12,0.13,0.63,0.1,9.3936372372129995,235.67270652156131,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","sam67_dm_wrap_0","CF$7",null,null,null,null,null,null,null,null,null,"CC$14",null,null,"Pulsar",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"CORE_Voltage",0.75,"V",null,"Processor Core Utilization (%)",null,null,null,null,"IP","Total Power [mW]"]
[{"$error":"#N/A"},{"$error":"#N/A"},0,{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},0,{"$error":"#N/A"},800,0,{"$f":"IF(IF(ISBLANK(AT6),0,INDIRECT(AT6))=0,0,IF($CE$3=\"PDN\",1,IF(ISBLANK(AT6),0,INDIRECT(AT6))))","v":0},0,{"$f":"IFERROR(IF($I6=\"SI\",AP6*$C6*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ6*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK6*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL6*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM6*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN6*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO6*'Power Scaling'!F$4)*IF(P6=\"OFF\",0.06,1),VLOOKUP($A6&\"_\"&U$3,MDB,5,0)*$C6*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P6=\"OFF\",0.06,1)),0)","v":0},{"$f":"C6*IFERROR(IF($I6=\"SI\",(AE6*IF(S6=0,0,1)+(AF6-AE6)*S6)*IF(R6>0,R6,Q6)/Q6*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ6*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK6*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL6*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM6*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN6*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO6*'Power Scaling'!I$4)*AQ6,IF(OR($I6=\"AO\",$I6=\"LU\"),VLOOKUP($A6&\"_\"&\"vdd_dyn\"&\"_\"&$R6&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I6=\"LUUA\",$I6=\"LUUB\"),VLOOKUP($A6&\"_\"&\"vdd_dyn\"&\"_\"&$R6&\"\",MDB,5,0)*$C6*$S6*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A6&\"_\"&\"vdd_dyn\"&\"_\"&$R6&\"_idle\",MDB,5,0)*(1-$S6)+VLOOKUP($A6&\"_\"&\"vdd_dyn\"&\"_\"&$R6&\"_read\",MDB,5,0)*($S6/2)+VLOOKUP($A6&\"_\"&\"vdd_dyn\"&\"_\"&$R6&\"_write\",MDB,5,0)*($S6/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,{"$error":"#N/A"},{"$error":"#N/A"},"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.",{"$error":"#N/A"},"CF$8",null,null,null,null,null,null,null,null,null,"CC$15",null,null,"Pulsar",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"Process_Corner","Strong",null,null,"MAIN SMS 0",1,null,null,null,"A53",{"$f":"ROUNDUP(SUMIF(BG$1:BG$84,CJ6,O$1:O$84)/10,0)*10","v":170}]
["sam62a_a53_512kb_wrap","_0",1,4,"VDD_CORE","N/A","N/A","N/A","SI","PD_A53_Cluster_0","A53 Quad Cluster 1.4 GHz 512KB AM62A","sam62a_april_power","1 Processor","ARM_MPU",60.070699896694222,"ON",1250,1250,{"$f":"AVERAGE(S8:S11)","v":1},0,{"$f":"IFERROR(IF($I7=\"SI\",AP7*$C7*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ7*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK7*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL7*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM7*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN7*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO7*'Power Scaling'!F$4)*IF(P7=\"OFF\",0.06,1),VLOOKUP($A7&\"_\"&U$3,MDB,5,0)*$C7*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P7=\"OFF\",0.06,1)),0)","v":0},{"$f":"C7*IFERROR(IF($I7=\"SI\",(AE7*IF(S7=0,0,1)+(AF7-AE7)*S7)*IF(R7>0,R7,Q7)/Q7*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ7*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK7*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL7*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM7*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN7*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO7*'Power Scaling'!I$4)*AQ7,IF(OR($I7=\"AO\",$I7=\"LU\"),VLOOKUP($A7&\"_\"&\"vdd_dyn\"&\"_\"&$R7&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I7=\"LUUA\",$I7=\"LUUB\"),VLOOKUP($A7&\"_\"&\"vdd_dyn\"&\"_\"&$R7&\"\",MDB,5,0)*$C7*$S7*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A7&\"_\"&\"vdd_dyn\"&\"_\"&$R7&\"_idle\",MDB,5,0)*(1-$S7)+VLOOKUP($A7&\"_\"&\"vdd_dyn\"&\"_\"&$R7&\"_read\",MDB,5,0)*($S7/2)+VLOOKUP($A7&\"_\"&\"vdd_dyn\"&\"_\"&$R7&\"_write\",MDB,5,0)*($S7/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},60.070699896694222,0,0,0,0,0,0,0,0.14599999999999999,0.25,0.15,302.60000000000002,330.8,0.17,0.02,0.18,0.12,0.11,0.41,6.0744864098112199,257.98844905742271,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","sam62a_a53_512kb_wrap_0",null,null,null,null,null,null,null,null,null,null,"CC$17",null,null,"A53",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"OPP","high",null,null,"MAIN (WKUP) R5FSS 0",1,null,null,null,"C7",0]
["sam62_a53_dual_wrap_cba_cpu_phys","_0",1,4,"VDD_CORE","N/A","N/A","N/A","SI","PD_A53_0","A53 CPU 1.4 GHz AM62","SAM62A_c3signoff_20220411","1 Processor","ARM_MPU",26.247336647727273,"ON",1250,1250,{"$f":"IF(IF(ISBLANK(AT8),0,INDIRECT(AT8))=0,0,IF($CE$3=\"PDN\",1,IF(ISBLANK(AT8),0,INDIRECT(AT8))))","v":1},0,{"$f":"IFERROR(IF($I8=\"SI\",AP8*$C8*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ8*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK8*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL8*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM8*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN8*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO8*'Power Scaling'!F$4)*IF(P8=\"OFF\",0.06,1),VLOOKUP($A8&\"_\"&U$3,MDB,5,0)*$C8*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P8=\"OFF\",0.06,1)),0)","v":0},{"$f":"C8*IFERROR(IF($I8=\"SI\",(AE8*IF(S8=0,0,1)+(AF8-AE8)*S8)*IF(R8>0,R8,Q8)/Q8*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ8*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK8*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL8*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM8*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN8*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO8*'Power Scaling'!I$4)*AQ8,IF(OR($I8=\"AO\",$I8=\"LU\"),VLOOKUP($A8&\"_\"&\"vdd_dyn\"&\"_\"&$R8&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I8=\"LUUA\",$I8=\"LUUB\"),VLOOKUP($A8&\"_\"&\"vdd_dyn\"&\"_\"&$R8&\"\",MDB,5,0)*$C8*$S8*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A8&\"_\"&\"vdd_dyn\"&\"_\"&$R8&\"_idle\",MDB,5,0)*(1-$S8)+VLOOKUP($A8&\"_\"&\"vdd_dyn\"&\"_\"&$R8&\"_read\",MDB,5,0)*($S8/2)+VLOOKUP($A8&\"_\"&\"vdd_dyn\"&\"_\"&$R8&\"_write\",MDB,5,0)*($S8/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},26.247336647727273,0,0,0,0,0,0,0,1.2E-2,0.15,0.18,301.2,240.9,0.24,0.03,0.34,0.12,0.05,0.22,2.8782766369027746,241.38045385391541,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","sam62_a53_dual_wrap_cba_cpu_phys_0","CF$9",null,null,null,null,null,null,null,null,null,"CC$17",null,null,"A53",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"MAIN R5FSS 2",0,null,null,null,"Pulsar",90]
["sam62_a53_dual_wrap_cba_cpu_phys","_1",1,4,"VDD_CORE","N/A","N/A","N/A","SI","PD_A53_1","A53 CPU 1.4 GHz AM62","SAM62A_c3signoff_20220411","1 Processor","ARM_MPU",26.247336647727273,"ON",1250,1250,{"$f":"IF(IF(ISBLANK(AT9),0,INDIRECT(AT9))=0,0,IF($CE$3=\"PDN\",1,IF(ISBLANK(AT9),0,INDIRECT(AT9))))","v":1},0,{"$f":"IFERROR(IF($I9=\"SI\",AP9*$C9*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ9*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK9*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL9*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM9*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN9*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO9*'Power Scaling'!F$4)*IF(P9=\"OFF\",0.06,1),VLOOKUP($A9&\"_\"&U$3,MDB,5,0)*$C9*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P9=\"OFF\",0.06,1)),0)","v":0},{"$f":"C9*IFERROR(IF($I9=\"SI\",(AE9*IF(S9=0,0,1)+(AF9-AE9)*S9)*IF(R9>0,R9,Q9)/Q9*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ9*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK9*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL9*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM9*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN9*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO9*'Power Scaling'!I$4)*AQ9,IF(OR($I9=\"AO\",$I9=\"LU\"),VLOOKUP($A9&\"_\"&\"vdd_dyn\"&\"_\"&$R9&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I9=\"LUUA\",$I9=\"LUUB\"),VLOOKUP($A9&\"_\"&\"vdd_dyn\"&\"_\"&$R9&\"\",MDB,5,0)*$C9*$S9*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A9&\"_\"&\"vdd_dyn\"&\"_\"&$R9&\"_idle\",MDB,5,0)*(1-$S9)+VLOOKUP($A9&\"_\"&\"vdd_dyn\"&\"_\"&$R9&\"_read\",MDB,5,0)*($S9/2)+VLOOKUP($A9&\"_\"&\"vdd_dyn\"&\"_\"&$R9&\"_write\",MDB,5,0)*($S9/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},26.247336647727273,0,0,0,0,0,0,0,1.2E-2,0.15,0.18,301.2,240.9,0.24,0.03,0.34,0.12,0.05,0.22,2.8782766369027746,241.38045385391541,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","sam62_a53_dual_wrap_cba_cpu_phys_1","CF$10",null,null,null,null,null,null,null,null,null,"CC$17",null,null,"A53",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"UC_Description","Add Test Description",null,null,"MAIN A53SS 0: 0",1,null,null,null,"GPU",270]
["sam62_a53_dual_wrap_cba_cpu_phys","_2",1,4,"VDD_CORE","N/A","N/A","N/A","SI","PD_A53_2","A53 CPU 1.4 GHz AM62","SAM62A_c3signoff_20220411","1 Processor","ARM_MPU",26.247336647727273,"ON",1250,1250,{"$f":"IF(IF(ISBLANK(AT10),0,INDIRECT(AT10))=0,0,IF($CE$3=\"PDN\",1,IF(ISBLANK(AT10),0,INDIRECT(AT10))))","v":1},0,{"$f":"IFERROR(IF($I10=\"SI\",AP10*$C10*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ10*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK10*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL10*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM10*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN10*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO10*'Power Scaling'!F$4)*IF(P10=\"OFF\",0.06,1),VLOOKUP($A10&\"_\"&U$3,MDB,5,0)*$C10*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P10=\"OFF\",0.06,1)),0)","v":0},{"$f":"C10*IFERROR(IF($I10=\"SI\",(AE10*IF(S10=0,0,1)+(AF10-AE10)*S10)*IF(R10>0,R10,Q10)/Q10*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ10*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK10*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL10*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM10*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN10*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO10*'Power Scaling'!I$4)*AQ10,IF(OR($I10=\"AO\",$I10=\"LU\"),VLOOKUP($A10&\"_\"&\"vdd_dyn\"&\"_\"&$R10&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I10=\"LUUA\",$I10=\"LUUB\"),VLOOKUP($A10&\"_\"&\"vdd_dyn\"&\"_\"&$R10&\"\",MDB,5,0)*$C10*$S10*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A10&\"_\"&\"vdd_dyn\"&\"_\"&$R10&\"_idle\",MDB,5,0)*(1-$S10)+VLOOKUP($A10&\"_\"&\"vdd_dyn\"&\"_\"&$R10&\"_read\",MDB,5,0)*($S10/2)+VLOOKUP($A10&\"_\"&\"vdd_dyn\"&\"_\"&$R10&\"_write\",MDB,5,0)*($S10/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},26.247336647727273,0,0,0,0,0,0,0,1.2E-2,0.15,0.18,301.2,240.9,0.24,0.03,0.34,0.12,0.05,0.22,2.8782766369027746,241.38045385391541,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","sam62_a53_dual_wrap_cba_cpu_phys_2","CF$11",null,null,null,null,null,null,null,null,null,"CC$17",null,null,"A53",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"UC_Name","Add Test Name",null,null,"MAIN A53SS 0: 1",1,null,null,null,"VPAC",0]
["sam62_a53_dual_wrap_cba_cpu_phys","_3",1,4,"VDD_CORE","N/A","N/A","N/A","SI","PD_A53_3","A53 CPU 1.4 GHz AM62","SAM62A_c3signoff_20220411","1 Processor","ARM_MPU",26.247336647727273,"ON",1250,1250,{"$f":"IF(IF(ISBLANK(AT11),0,INDIRECT(AT11))=0,0,IF($CE$3=\"PDN\",1,IF(ISBLANK(AT11),0,INDIRECT(AT11))))","v":1},0,{"$f":"IFERROR(IF($I11=\"SI\",AP11*$C11*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ11*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK11*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL11*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM11*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN11*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO11*'Power Scaling'!F$4)*IF(P11=\"OFF\",0.06,1),VLOOKUP($A11&\"_\"&U$3,MDB,5,0)*$C11*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P11=\"OFF\",0.06,1)),0)","v":0},{"$f":"C11*IFERROR(IF($I11=\"SI\",(AE11*IF(S11=0,0,1)+(AF11-AE11)*S11)*IF(R11>0,R11,Q11)/Q11*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ11*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK11*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL11*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM11*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN11*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO11*'Power Scaling'!I$4)*AQ11,IF(OR($I11=\"AO\",$I11=\"LU\"),VLOOKUP($A11&\"_\"&\"vdd_dyn\"&\"_\"&$R11&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I11=\"LUUA\",$I11=\"LUUB\"),VLOOKUP($A11&\"_\"&\"vdd_dyn\"&\"_\"&$R11&\"\",MDB,5,0)*$C11*$S11*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A11&\"_\"&\"vdd_dyn\"&\"_\"&$R11&\"_idle\",MDB,5,0)*(1-$S11)+VLOOKUP($A11&\"_\"&\"vdd_dyn\"&\"_\"&$R11&\"_read\",MDB,5,0)*($S11/2)+VLOOKUP($A11&\"_\"&\"vdd_dyn\"&\"_\"&$R11&\"_write\",MDB,5,0)*($S11/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},26.247336647727273,0,0,0,0,0,0,0,1.2E-2,0.15,0.18,301.2,240.9,0.24,0.03,0.34,0.12,0.05,0.22,2.8782766369027746,241.38045385391541,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","sam62_a53_dual_wrap_cba_cpu_phys_3","CF$12",null,null,null,null,null,null,null,null,null,"CC$17",null,null,"A53",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"MAIN A53SS 0: 2",1,null,null,null,"DMPAC",0]
["sam67_dss_dsi_oldi_wrap","_0",1,3,"VDD_CORE","N/A","N/A","N/A","SI","PD_DSS","Double DSS7UL + DSI + OLDI wrap","sam62p_march_c2end_power","2 ASPE","Display",46.076629648760331,"ON",320,0,{"$f":"IF(OR(INDIRECT(AT12)=\"unused\",INDIRECT(AV12)=0),0,INDIRECT(AU12))*0.38+IF(OR(INDIRECT(AW12)=\"ulps\",INDIRECT(AY12)=0),0,INDIRECT(AX12))*(0.38+0.23)+IF(OR(INDIRECT(AZ12)=\"unused\",INDIRECT(BB12)=0),0,INDIRECT(BA12))*0.38","v":0.76},0,{"$f":"IFERROR(IF($I12=\"SI\",AP12*$C12*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ12*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK12*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL12*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM12*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN12*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO12*'Power Scaling'!F$4)*IF(P12=\"OFF\",0.06,1),VLOOKUP($A12&\"_\"&U$3,MDB,5,0)*$C12*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P12=\"OFF\",0.06,1)),0)","v":0},{"$f":"C12*IFERROR(IF($I12=\"SI\",(AE12*IF(S12=0,0,1)+(AF12-AE12)*S12)*IF(R12>0,R12,Q12)/Q12*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ12*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK12*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL12*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM12*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN12*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO12*'Power Scaling'!I$4)*AQ12,IF(OR($I12=\"AO\",$I12=\"LU\"),VLOOKUP($A12&\"_\"&\"vdd_dyn\"&\"_\"&$R12&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I12=\"LUUA\",$I12=\"LUUB\"),VLOOKUP($A12&\"_\"&\"vdd_dyn\"&\"_\"&$R12&\"\",MDB,5,0)*$C12*$S12*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A12&\"_\"&\"vdd_dyn\"&\"_\"&$R12&\"_idle\",MDB,5,0)*(1-$S12)+VLOOKUP($A12&\"_\"&\"vdd_dyn\"&\"_\"&$R12&\"_read\",MDB,5,0)*($S12/2)+VLOOKUP($A12&\"_\"&\"vdd_dyn\"&\"_\"&$R12&\"_write\",MDB,5,0)*($S12/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},46.076629648760331,0,0,0,0,0,0,0,7.8E-2,0.48,0.57999999999999996,193,165.4,0,0,0.08,0.06,0.42,0.43,6.6828968147970471,190.12187610178952,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","sam67_dss_dsi_oldi_wrap_0","CF$32","CG$32","CH$32","CB$36","CC$36","CD$36","CB$63","CC$63","CD$63",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"Key IP Frequency selection",null,"Frequency [MHz]",null,"MAIN A53SS 0: 3",1,null,null,null,"WAVE512CL",60]
[{"$error":"#N/A"},{"$error":"#N/A"},0,{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},0,{"$error":"#N/A"},912.5,0,{"$f":"IF(IF(ISBLANK(AT13),0,INDIRECT(AT13))*0.66+IF(ISBLANK(AU13),0,INDIRECT(AU13))*0.8=0,0,IF($CE$3=\"PDN\",1,IF(ISBLANK(AT13),0,INDIRECT(AT13))*0.66+IF(ISBLANK(AU13),0,INDIRECT(AU13))*0.8))","v":0},0,{"$f":"IFERROR(IF($I13=\"SI\",AP13*$C13*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ13*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK13*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL13*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM13*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN13*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO13*'Power Scaling'!F$4)*IF(P13=\"OFF\",0.06,1),VLOOKUP($A13&\"_\"&U$3,MDB,5,0)*$C13*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P13=\"OFF\",0.06,1)),0)","v":0},{"$f":"C13*IFERROR(IF($I13=\"SI\",(AE13*IF(S13=0,0,1)+(AF13-AE13)*S13)*IF(R13>0,R13,Q13)/Q13*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ13*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK13*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL13*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM13*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN13*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO13*'Power Scaling'!I$4)*AQ13,IF(OR($I13=\"AO\",$I13=\"LU\"),VLOOKUP($A13&\"_\"&\"vdd_dyn\"&\"_\"&$R13&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I13=\"LUUA\",$I13=\"LUUB\"),VLOOKUP($A13&\"_\"&\"vdd_dyn\"&\"_\"&$R13&\"\",MDB,5,0)*$C13*$S13*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A13&\"_\"&\"vdd_dyn\"&\"_\"&$R13&\"_idle\",MDB,5,0)*(1-$S13)+VLOOKUP($A13&\"_\"&\"vdd_dyn\"&\"_\"&$R13&\"_read\",MDB,5,0)*($S13/2)+VLOOKUP($A13&\"_\"&\"vdd_dyn\"&\"_\"&$R13&\"_write\",MDB,5,0)*($S13/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,{"$error":"#N/A"},{"$error":"#N/A"},"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.",{"$error":"#N/A"},"CF$15","CF$16",null,null,null,null,null,null,null,null,"CC$18",null,null,"C7",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"MAIN PLL 15 HSDIV 0","MAIN SMS 0 Frequency [MHz]",400,400,"MAIN C71SS 0: C71x",0,null,null,null,"DDR",390]
[{"$error":"#N/A"},{"$error":"#N/A"},0,{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},0,{"$error":"#N/A"},912.5,0,{"$f":"IF(IF(ISBLANK(AT14),0,INDIRECT(AT14))=0,0,IF($CE$3=\"PDN\",1,IF(ISBLANK(AT14),0,INDIRECT(AT14))))","v":0},0,{"$f":"IFERROR(IF($I14=\"SI\",AP14*$C14*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ14*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK14*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL14*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM14*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN14*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO14*'Power Scaling'!F$4)*IF(P14=\"OFF\",0.06,1),VLOOKUP($A14&\"_\"&U$3,MDB,5,0)*$C14*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P14=\"OFF\",0.06,1)),0)","v":0},{"$f":"C14*IFERROR(IF($I14=\"SI\",(AE14*IF(S14=0,0,1)+(AF14-AE14)*S14)*IF(R14>0,R14,Q14)/Q14*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ14*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK14*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL14*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM14*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN14*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO14*'Power Scaling'!I$4)*AQ14,IF(OR($I14=\"AO\",$I14=\"LU\"),VLOOKUP($A14&\"_\"&\"vdd_dyn\"&\"_\"&$R14&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I14=\"LUUA\",$I14=\"LUUB\"),VLOOKUP($A14&\"_\"&\"vdd_dyn\"&\"_\"&$R14&\"\",MDB,5,0)*$C14*$S14*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A14&\"_\"&\"vdd_dyn\"&\"_\"&$R14&\"_idle\",MDB,5,0)*(1-$S14)+VLOOKUP($A14&\"_\"&\"vdd_dyn\"&\"_\"&$R14&\"_read\",MDB,5,0)*($S14/2)+VLOOKUP($A14&\"_\"&\"vdd_dyn\"&\"_\"&$R14&\"_write\",MDB,5,0)*($S14/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,{"$error":"#N/A"},{"$error":"#N/A"},"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.",{"$error":"#N/A"},"CF$16",null,null,null,null,null,null,null,null,null,"CC$18",null,null,"C7",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"MAIN PLL 15 HSDIV 2\nMCU PLL 0 HSDIV 0","Domain Manager (WKUP) R5FSS 0 Frequency [MHz]",800,800,"MAIN C71SS 0: MMA",0]
[{"$error":"#N/A"},{"$error":"#N/A"},0,{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},0,{"$error":"#N/A"},912.5,0,{"$f":"IF(IF(ISBLANK(AT15),0,INDIRECT(AT15))*0.66+IF(ISBLANK(AU15),0,INDIRECT(AU15))*0.8=0,0,IF($CE$3=\"PDN\",1,IF(ISBLANK(AT15),0,INDIRECT(AT15))*0.66+IF(ISBLANK(AU15),0,INDIRECT(AU15))*0.8))","v":0},0,{"$f":"IFERROR(IF($I15=\"SI\",AP15*$C15*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ15*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK15*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL15*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM15*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN15*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO15*'Power Scaling'!F$4)*IF(P15=\"OFF\",0.06,1),VLOOKUP($A15&\"_\"&U$3,MDB,5,0)*$C15*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P15=\"OFF\",0.06,1)),0)","v":0},{"$f":"C15*IFERROR(IF($I15=\"SI\",(AE15*IF(S15=0,0,1)+(AF15-AE15)*S15)*IF(R15>0,R15,Q15)/Q15*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ15*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK15*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL15*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM15*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN15*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO15*'Power Scaling'!I$4)*AQ15,IF(OR($I15=\"AO\",$I15=\"LU\"),VLOOKUP($A15&\"_\"&\"vdd_dyn\"&\"_\"&$R15&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I15=\"LUUA\",$I15=\"LUUB\"),VLOOKUP($A15&\"_\"&\"vdd_dyn\"&\"_\"&$R15&\"\",MDB,5,0)*$C15*$S15*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A15&\"_\"&\"vdd_dyn\"&\"_\"&$R15&\"_idle\",MDB,5,0)*(1-$S15)+VLOOKUP($A15&\"_\"&\"vdd_dyn\"&\"_\"&$R15&\"_read\",MDB,5,0)*($S15/2)+VLOOKUP($A15&\"_\"&\"vdd_dyn\"&\"_\"&$R15&\"_write\",MDB,5,0)*($S15/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,{"$error":"#N/A"},{"$error":"#N/A"},"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.",{"$error":"#N/A"},"CF$13","CF$14",null,null,null,null,null,null,null,null,"CC$18",null,null,"C7",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"MAIN PLL 15 HSDIV 3","MAIN R5FSS 1 Frequency [MHz]",0,800,"MAIN C71SS 1: C71x",0,null,null,null,"PD","PSC","State"]
[{"$error":"#N/A"},{"$error":"#N/A"},0,{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},0,{"$error":"#N/A"},912.5,0,{"$f":"IF(IF(ISBLANK(AT16),0,INDIRECT(AT16))=0,0,IF($CE$3=\"PDN\",1,IF(ISBLANK(AT16),0,INDIRECT(AT16))))","v":0},0,{"$f":"IFERROR(IF($I16=\"SI\",AP16*$C16*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ16*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK16*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL16*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM16*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN16*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO16*'Power Scaling'!F$4)*IF(P16=\"OFF\",0.06,1),VLOOKUP($A16&\"_\"&U$3,MDB,5,0)*$C16*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P16=\"OFF\",0.06,1)),0)","v":0},{"$f":"C16*IFERROR(IF($I16=\"SI\",(AE16*IF(S16=0,0,1)+(AF16-AE16)*S16)*IF(R16>0,R16,Q16)/Q16*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ16*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK16*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL16*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM16*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN16*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO16*'Power Scaling'!I$4)*AQ16,IF(OR($I16=\"AO\",$I16=\"LU\"),VLOOKUP($A16&\"_\"&\"vdd_dyn\"&\"_\"&$R16&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I16=\"LUUA\",$I16=\"LUUB\"),VLOOKUP($A16&\"_\"&\"vdd_dyn\"&\"_\"&$R16&\"\",MDB,5,0)*$C16*$S16*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A16&\"_\"&\"vdd_dyn\"&\"_\"&$R16&\"_idle\",MDB,5,0)*(1-$S16)+VLOOKUP($A16&\"_\"&\"vdd_dyn\"&\"_\"&$R16&\"_read\",MDB,5,0)*($S16/2)+VLOOKUP($A16&\"_\"&\"vdd_dyn\"&\"_\"&$R16&\"_write\",MDB,5,0)*($S16/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,{"$error":"#N/A"},{"$error":"#N/A"},"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.",{"$error":"#N/A"},"CF$14",null,null,null,null,null,null,null,null,null,"CC$18",null,null,"C7",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"MCU PLL 0 HSDIV 3","MCU R5FSS 0 Frequency [MHz]",800,800,"MAIN C71SS 1: MMA",0,null,null,null,"PD_Pulsar_MCU",null,{"$f":"INDEX(PD_State_Table,MATCH(CJ16,PD_Table_Row_Header,0),2)","v":"ON"}]
["sam67_gpu_bxs464_dust","_0",1,7,"VDD_CORE","N/A","N/A","N/A","SI","PD_GPU","GPU BXS4-64-256KB DUST AM67","sam62p_dec_power","2 ASPE","GPU",152.53657670454547,"ON",800,720,1,0,{"$f":"IFERROR(IF($I17=\"SI\",AP17*$C17*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ17*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK17*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL17*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM17*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN17*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO17*'Power Scaling'!F$4)*IF(P17=\"OFF\",0.06,1),VLOOKUP($A17&\"_\"&U$3,MDB,5,0)*$C17*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P17=\"OFF\",0.06,1)),0)","v":0},{"$f":"C17*IFERROR(IF($I17=\"SI\",(AE17*IF(S17=0,0,1)+(AF17-AE17)*S17)*IF(R17>0,R17,Q17)/Q17*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ17*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK17*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL17*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM17*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN17*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO17*'Power Scaling'!I$4)*AQ17,IF(OR($I17=\"AO\",$I17=\"LU\"),VLOOKUP($A17&\"_\"&\"vdd_dyn\"&\"_\"&$R17&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I17=\"LUUA\",$I17=\"LUUB\"),VLOOKUP($A17&\"_\"&\"vdd_dyn\"&\"_\"&$R17&\"\",MDB,5,0)*$C17*$S17*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A17&\"_\"&\"vdd_dyn\"&\"_\"&$R17&\"_idle\",MDB,5,0)*(1-$S17)+VLOOKUP($A17&\"_\"&\"vdd_dyn\"&\"_\"&$R17&\"_read\",MDB,5,0)*($S17/2)+VLOOKUP($A17&\"_\"&\"vdd_dyn\"&\"_\"&$R17&\"_write\",MDB,5,0)*($S17/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},152.53657670454547,0,0,0,0,0,0,0,3.0000000000000001E-3,0.22,0.36,1090.0999999999999,1060.5999999999999,0.02,0,0.23,0.06,0.38,0.31,27.01402795877166,1014.264149126771,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","sam67_gpu_bxs464_dust_0","CF$19",null,null,null,null,null,null,null,null,null,"CC$21",null,null,"GPU",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"MAIN PLL 8 HSDIV0","MAIN A53SS Frequency [MHz]",1250,1400,"MAIN VPAC 0",0,null,null,null,"GP_Core_CTL",null,"ON"]
["sam67_gpu_bxs464_rslc256","_0",1,8,"VDD_CORE","N/A","N/A","N/A","SI","PD_GPU","GPU BXS4-64-256KB Rascal AM67","sam62p_may_c3end_base_pg_power","2 ASPE","GPU",90.894886363636388,"ON",800,720,1,0,{"$f":"IFERROR(IF($I18=\"SI\",AP18*$C18*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ18*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK18*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL18*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM18*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN18*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO18*'Power Scaling'!F$4)*IF(P18=\"OFF\",0.06,1),VLOOKUP($A18&\"_\"&U$3,MDB,5,0)*$C18*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P18=\"OFF\",0.06,1)),0)","v":0},{"$f":"C18*IFERROR(IF($I18=\"SI\",(AE18*IF(S18=0,0,1)+(AF18-AE18)*S18)*IF(R18>0,R18,Q18)/Q18*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ18*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK18*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL18*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM18*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN18*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO18*'Power Scaling'!I$4)*AQ18,IF(OR($I18=\"AO\",$I18=\"LU\"),VLOOKUP($A18&\"_\"&\"vdd_dyn\"&\"_\"&$R18&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I18=\"LUUA\",$I18=\"LUUB\"),VLOOKUP($A18&\"_\"&\"vdd_dyn\"&\"_\"&$R18&\"\",MDB,5,0)*$C18*$S18*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A18&\"_\"&\"vdd_dyn\"&\"_\"&$R18&\"_idle\",MDB,5,0)*(1-$S18)+VLOOKUP($A18&\"_\"&\"vdd_dyn\"&\"_\"&$R18&\"_read\",MDB,5,0)*($S18/2)+VLOOKUP($A18&\"_\"&\"vdd_dyn\"&\"_\"&$R18&\"_write\",MDB,5,0)*($S18/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},90.894886363636388,0,0,0,0,0,0,0,1.0999999999999999E-2,0.22,0.36,977.8,632,0,0,0.14000000000000001,0.08,0.18,0.6,21.958030698691399,939.15129460344349,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","sam67_gpu_bxs464_rslc256_0","CF$19",null,null,null,null,null,null,null,null,null,"CC$21",null,null,"GPU",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"MAIN PLL 7 HSDIV 0","MAIN C71SS 0 and 1 Frequency [MHz]",0,1000,"MAIN DMPAC 0",0,null,null,null,"PD_A53_0",null,"ON"]
["sam67_gpu_bxs464_wrap","_0",1,7,"VDD_CORE","N/A","N/A","N/A","SI","PD_GPU","GPU BXS4-64-256KB Wrap AM67","sam62p_may_c3end_base_pg_power","2 ASPE","GPU",23.251936983471079,"ON",800,720,1,0,{"$f":"IFERROR(IF($I19=\"SI\",AP19*$C19*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ19*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK19*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL19*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM19*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN19*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO19*'Power Scaling'!F$4)*IF(P19=\"OFF\",0.06,1),VLOOKUP($A19&\"_\"&U$3,MDB,5,0)*$C19*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P19=\"OFF\",0.06,1)),0)","v":0},{"$f":"C19*IFERROR(IF($I19=\"SI\",(AE19*IF(S19=0,0,1)+(AF19-AE19)*S19)*IF(R19>0,R19,Q19)/Q19*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ19*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK19*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL19*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM19*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN19*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO19*'Power Scaling'!I$4)*AQ19,IF(OR($I19=\"AO\",$I19=\"LU\"),VLOOKUP($A19&\"_\"&\"vdd_dyn\"&\"_\"&$R19&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I19=\"LUUA\",$I19=\"LUUB\"),VLOOKUP($A19&\"_\"&\"vdd_dyn\"&\"_\"&$R19&\"\",MDB,5,0)*$C19*$S19*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A19&\"_\"&\"vdd_dyn\"&\"_\"&$R19&\"_idle\",MDB,5,0)*(1-$S19)+VLOOKUP($A19&\"_\"&\"vdd_dyn\"&\"_\"&$R19&\"_read\",MDB,5,0)*($S19/2)+VLOOKUP($A19&\"_\"&\"vdd_dyn\"&\"_\"&$R19&\"_write\",MDB,5,0)*($S19/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},23.251936983471079,0,0,0,0,0,0,0,0.26300000000000001,0.36,0.47,100.5,98.8,0.02,0,0.2,0.17,0.2,0.41,3.1460122524154208,92.023795833607537,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","sam67_gpu_bxs464_wrap_0","CF$19",null,null,null,null,null,null,null,null,null,"CC$21",null,null,"GPU",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"MAIN PLL 5 HSDIV 0","MAIN VPAC 0 Frequency [MHz]",0,600,"MAIN GPU 0",1,null,null,null,"PD_A53_1",null,"ON"]
[{"$error":"#N/A"},{"$error":"#N/A"},0,{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},0,{"$error":"#N/A"},600,0,0,0,{"$f":"IFERROR(IF($I20=\"SI\",AP20*$C20*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ20*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK20*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL20*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM20*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN20*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO20*'Power Scaling'!F$4)*IF(P20=\"OFF\",0.06,1),VLOOKUP($A20&\"_\"&U$3,MDB,5,0)*$C20*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P20=\"OFF\",0.06,1)),0)","v":0},{"$f":"C20*IFERROR(IF($I20=\"SI\",(AE20*IF(S20=0,0,1)+(AF20-AE20)*S20)*IF(R20>0,R20,Q20)/Q20*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ20*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK20*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL20*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM20*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN20*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO20*'Power Scaling'!I$4)*AQ20,IF(OR($I20=\"AO\",$I20=\"LU\"),VLOOKUP($A20&\"_\"&\"vdd_dyn\"&\"_\"&$R20&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I20=\"LUUA\",$I20=\"LUUB\"),VLOOKUP($A20&\"_\"&\"vdd_dyn\"&\"_\"&$R20&\"\",MDB,5,0)*$C20*$S20*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A20&\"_\"&\"vdd_dyn\"&\"_\"&$R20&\"_idle\",MDB,5,0)*(1-$S20)+VLOOKUP($A20&\"_\"&\"vdd_dyn\"&\"_\"&$R20&\"_read\",MDB,5,0)*($S20/2)+VLOOKUP($A20&\"_\"&\"vdd_dyn\"&\"_\"&$R20&\"_write\",MDB,5,0)*($S20/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,{"$error":"#N/A"},{"$error":"#N/A"},"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.",{"$error":"#N/A"},"CF$17",null,null,null,null,null,null,null,null,null,"CC$19",null,null,"VPAC",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"MAIN PLL 5 HSDIV 2","MAIN DMPAC 0 Frequency [MHz]",0,428,"MAIN Video Encoder/Decoder 0",1,null,null,null,"PD_A53_2",null,"ON"]
[{"$error":"#N/A"},{"$error":"#N/A"},0,{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},0,{"$error":"#N/A"},428,0,0,0,{"$f":"IFERROR(IF($I21=\"SI\",AP21*$C21*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ21*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK21*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL21*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM21*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN21*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO21*'Power Scaling'!F$4)*IF(P21=\"OFF\",0.06,1),VLOOKUP($A21&\"_\"&U$3,MDB,5,0)*$C21*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P21=\"OFF\",0.06,1)),0)","v":0},{"$f":"C21*IFERROR(IF($I21=\"SI\",(AE21*IF(S21=0,0,1)+(AF21-AE21)*S21)*IF(R21>0,R21,Q21)/Q21*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ21*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK21*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL21*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM21*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN21*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO21*'Power Scaling'!I$4)*AQ21,IF(OR($I21=\"AO\",$I21=\"LU\"),VLOOKUP($A21&\"_\"&\"vdd_dyn\"&\"_\"&$R21&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I21=\"LUUA\",$I21=\"LUUB\"),VLOOKUP($A21&\"_\"&\"vdd_dyn\"&\"_\"&$R21&\"\",MDB,5,0)*$C21*$S21*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A21&\"_\"&\"vdd_dyn\"&\"_\"&$R21&\"_idle\",MDB,5,0)*(1-$S21)+VLOOKUP($A21&\"_\"&\"vdd_dyn\"&\"_\"&$R21&\"_read\",MDB,5,0)*($S21/2)+VLOOKUP($A21&\"_\"&\"vdd_dyn\"&\"_\"&$R21&\"_write\",MDB,5,0)*($S21/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,{"$error":"#N/A"},{"$error":"#N/A"},"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.",{"$error":"#N/A"},"CF$18",null,null,null,null,null,null,null,null,null,"CC$20",null,null,"DMPAC",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"MAIN PLL 6 HSDIV 0","MAIN GPU 0 Frequency [MHz]",720,800,"MCU R5FSS",1,null,null,null,"PD_A53_3",null,"ON"]
["sam67_cpsw3_wrap","_0",1,3,"VDD_CORE","N/A","N/A","N/A","SI","PD_CPSW","CPSW3x eAVB AM62","sam62p_pg10_weekly_20230328","2 ASPE","Networking",19.629390495867767,"ON",250,0,{"$f":"IF(ISBLANK(AW22),0,AW22)*IF(ISBLANK(AU22),0,INDIRECT(AU22))*IF(ISBLANK(AV22),0,INDIRECT(AV22))/(1000*1*2)","v":1},0,{"$f":"IFERROR(IF($I22=\"SI\",AP22*$C22*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ22*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK22*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL22*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM22*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN22*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO22*'Power Scaling'!F$4)*IF(P22=\"OFF\",0.06,1),VLOOKUP($A22&\"_\"&U$3,MDB,5,0)*$C22*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P22=\"OFF\",0.06,1)),0)","v":0},{"$f":"C22*IFERROR(IF($I22=\"SI\",(AE22*IF(S22=0,0,1)+(AF22-AE22)*S22)*IF(R22>0,R22,Q22)/Q22*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ22*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK22*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL22*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM22*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN22*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO22*'Power Scaling'!I$4)*AQ22,IF(OR($I22=\"AO\",$I22=\"LU\"),VLOOKUP($A22&\"_\"&\"vdd_dyn\"&\"_\"&$R22&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I22=\"LUUA\",$I22=\"LUUB\"),VLOOKUP($A22&\"_\"&\"vdd_dyn\"&\"_\"&$R22&\"\",MDB,5,0)*$C22*$S22*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A22&\"_\"&\"vdd_dyn\"&\"_\"&$R22&\"_idle\",MDB,5,0)*(1-$S22)+VLOOKUP($A22&\"_\"&\"vdd_dyn\"&\"_\"&$R22&\"_read\",MDB,5,0)*($S22/2)+VLOOKUP($A22&\"_\"&\"vdd_dyn\"&\"_\"&$R22&\"_write\",MDB,5,0)*($S22/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},19.629390495867767,0,0,0,0,0,0,0,0.33900000000000002,0.48,0.57999999999999996,85.3,56.3,0,0,0.01,0.06,0.9,0.03,4.7349955094797851,83.917525069327638,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","sam67_cpsw3_wrap_0","CB$65","CC$65","CD$65",{"$f":"IF(OR(ISBLANK(AT22),ISNUMBER(FIND(\"unused\",INDIRECT(AT22)))),0,IF(ISNUMBER(FIND(1000,INDIRECT(AT22))),1000,IF(ISNUMBER(FIND(100,INDIRECT(AT22))),100,10)))","v":1000},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"MAIN PLL 2 HSDIV 4","MAIN Video Encoder/Decoder 0 Frequency [MHz]",100,500,null,null,null,null,null,"PD_A53_Cluster_0",null,"ON"]
["sam67_vpu_wave521cl_wrap","_0",1,5,"VDD_CORE","N/A","N/A","N/A","SI","PD_ENCODE","WAVE521CL Video Codec AM62A","sam62p_may_c3end_base_pg_power","2 ASPE","Video",55.279571280991746,"ON",500,100,{"$f":"IF(ISBLANK(AT23),0,INDIRECT(AT23))","v":1},0,{"$f":"IFERROR(IF($I23=\"SI\",AP23*$C23*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ23*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK23*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL23*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM23*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN23*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO23*'Power Scaling'!F$4)*IF(P23=\"OFF\",0.06,1),VLOOKUP($A23&\"_\"&U$3,MDB,5,0)*$C23*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P23=\"OFF\",0.06,1)),0)","v":0},{"$f":"C23*IFERROR(IF($I23=\"SI\",(AE23*IF(S23=0,0,1)+(AF23-AE23)*S23)*IF(R23>0,R23,Q23)/Q23*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ23*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK23*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL23*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM23*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN23*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO23*'Power Scaling'!I$4)*AQ23,IF(OR($I23=\"AO\",$I23=\"LU\"),VLOOKUP($A23&\"_\"&\"vdd_dyn\"&\"_\"&$R23&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I23=\"LUUA\",$I23=\"LUUB\"),VLOOKUP($A23&\"_\"&\"vdd_dyn\"&\"_\"&$R23&\"\",MDB,5,0)*$C23*$S23*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A23&\"_\"&\"vdd_dyn\"&\"_\"&$R23&\"_idle\",MDB,5,0)*(1-$S23)+VLOOKUP($A23&\"_\"&\"vdd_dyn\"&\"_\"&$R23&\"_read\",MDB,5,0)*($S23/2)+VLOOKUP($A23&\"_\"&\"vdd_dyn\"&\"_\"&$R23&\"_write\",MDB,5,0)*($S23/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},55.279571280991746,0,0,0,0,0,0,0,0.104,0.4,0.6,813.2,951.3,0,0,0.16,7.0000000000000007E-2,0.45,0.32,31.886504993896473,774.74732252489059,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","sam67_vpu_wave521cl_wrap_0","CF$20",null,null,null,null,null,null,null,null,null,"CC$22",null,null,"WAVE512CL",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"MAIN PLL 0 HSDIV 0 div 2","MAIN JPEG Encoder 0 Frequency [MHz]",250,null,null,null,null,null,null,"PD_DSS",null,"ON"]
["sam62_mcasp_wrap","_0",1,4,"VDD_CORE","N/A","N/A","N/A","SI","GP_Core_CTL","MCASP AM62","sam62a_april_power","3 Periph","Audio",1.568956611570248,"ON",250,0,{"$f":"IF(ISBLANK(AT24),0,IF(AND(INDIRECT(AT24)<>\"unused\",INDIRECT(AV24)>AW24),INDIRECT(AU24),0))","v":1},0,{"$f":"IFERROR(IF($I24=\"SI\",AP24*$C24*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ24*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK24*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL24*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM24*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN24*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO24*'Power Scaling'!F$4)*IF(P24=\"OFF\",0.06,1),VLOOKUP($A24&\"_\"&U$3,MDB,5,0)*$C24*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P24=\"OFF\",0.06,1)),0)","v":0},{"$f":"C24*IFERROR(IF($I24=\"SI\",(AE24*IF(S24=0,0,1)+(AF24-AE24)*S24)*IF(R24>0,R24,Q24)/Q24*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ24*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK24*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL24*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM24*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN24*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO24*'Power Scaling'!I$4)*AQ24,IF(OR($I24=\"AO\",$I24=\"LU\"),VLOOKUP($A24&\"_\"&\"vdd_dyn\"&\"_\"&$R24&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I24=\"LUUA\",$I24=\"LUUB\"),VLOOKUP($A24&\"_\"&\"vdd_dyn\"&\"_\"&$R24&\"\",MDB,5,0)*$C24*$S24*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A24&\"_\"&\"vdd_dyn\"&\"_\"&$R24&\"_idle\",MDB,5,0)*(1-$S24)+VLOOKUP($A24&\"_\"&\"vdd_dyn\"&\"_\"&$R24&\"_read\",MDB,5,0)*($S24/2)+VLOOKUP($A24&\"_\"&\"vdd_dyn\"&\"_\"&$R24&\"_write\",MDB,5,0)*($S24/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},1.568956611570248,0,0,0,0,0,0,0,0.40200000000000002,0.72,0.86,2.9,3,0,0,0.02,0.11,0.78,0.08,0.20880841598144445,2.8429213601092607,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","sam62_mcasp_wrap_0","CB$57","CC$57","CD$57",0,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"MAIN PLL 12 HSDIV0","LPDDR4 EMIF 0 [MT/s]",2133,4000,"Memory Interfaces","Mode","Utilization",null,null,"PD_GPU",null,"ON"]
["sam62_mcasp_wrap","_1",1,4,"VDD_CORE","N/A","N/A","N/A","SI","GP_Core_CTL","MCASP AM62","sam62a_april_power","3 Periph","Audio",1.568956611570248,"ON",250,0,{"$f":"IF(ISBLANK(AT25),0,IF(AND(INDIRECT(AT25)<>\"unused\",INDIRECT(AV25)>AW25),INDIRECT(AU25),0))","v":1},0,{"$f":"IFERROR(IF($I25=\"SI\",AP25*$C25*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ25*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK25*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL25*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM25*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN25*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO25*'Power Scaling'!F$4)*IF(P25=\"OFF\",0.06,1),VLOOKUP($A25&\"_\"&U$3,MDB,5,0)*$C25*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P25=\"OFF\",0.06,1)),0)","v":0},{"$f":"C25*IFERROR(IF($I25=\"SI\",(AE25*IF(S25=0,0,1)+(AF25-AE25)*S25)*IF(R25>0,R25,Q25)/Q25*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ25*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK25*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL25*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM25*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN25*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO25*'Power Scaling'!I$4)*AQ25,IF(OR($I25=\"AO\",$I25=\"LU\"),VLOOKUP($A25&\"_\"&\"vdd_dyn\"&\"_\"&$R25&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I25=\"LUUA\",$I25=\"LUUB\"),VLOOKUP($A25&\"_\"&\"vdd_dyn\"&\"_\"&$R25&\"\",MDB,5,0)*$C25*$S25*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A25&\"_\"&\"vdd_dyn\"&\"_\"&$R25&\"_idle\",MDB,5,0)*(1-$S25)+VLOOKUP($A25&\"_\"&\"vdd_dyn\"&\"_\"&$R25&\"_read\",MDB,5,0)*($S25/2)+VLOOKUP($A25&\"_\"&\"vdd_dyn\"&\"_\"&$R25&\"_write\",MDB,5,0)*($S25/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},1.568956611570248,0,0,0,0,0,0,0,0.40200000000000002,0.72,0.86,2.9,3,0,0,0.02,0.11,0.78,0.08,0.20880841598144445,2.8429213601092607,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","sam62_mcasp_wrap_1","CB$57","CC$57","CD$57",1,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"MCU PLL 0 HSDIV 0","MCU SS / WKUP Modules CLK [MHz] (MCU SYSCLK)",400,400,"DDRSS 0","lpddr4_2400_32",1,null,null,"PD_CPSW",null,"ON"]
["sam62_mcasp_wrap","_2",1,4,"VDD_CORE","N/A","N/A","N/A","SI","GP_Core_CTL","MCASP AM62","sam62a_april_power","3 Periph","Audio",1.568956611570248,"ON",250,0,{"$f":"IF(ISBLANK(AT26),0,IF(AND(INDIRECT(AT26)<>\"unused\",INDIRECT(AV26)>AW26),INDIRECT(AU26),0))","v":1},0,{"$f":"IFERROR(IF($I26=\"SI\",AP26*$C26*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ26*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK26*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL26*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM26*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN26*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO26*'Power Scaling'!F$4)*IF(P26=\"OFF\",0.06,1),VLOOKUP($A26&\"_\"&U$3,MDB,5,0)*$C26*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P26=\"OFF\",0.06,1)),0)","v":0},{"$f":"C26*IFERROR(IF($I26=\"SI\",(AE26*IF(S26=0,0,1)+(AF26-AE26)*S26)*IF(R26>0,R26,Q26)/Q26*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ26*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK26*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL26*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM26*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN26*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO26*'Power Scaling'!I$4)*AQ26,IF(OR($I26=\"AO\",$I26=\"LU\"),VLOOKUP($A26&\"_\"&\"vdd_dyn\"&\"_\"&$R26&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I26=\"LUUA\",$I26=\"LUUB\"),VLOOKUP($A26&\"_\"&\"vdd_dyn\"&\"_\"&$R26&\"\",MDB,5,0)*$C26*$S26*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A26&\"_\"&\"vdd_dyn\"&\"_\"&$R26&\"_idle\",MDB,5,0)*(1-$S26)+VLOOKUP($A26&\"_\"&\"vdd_dyn\"&\"_\"&$R26&\"_read\",MDB,5,0)*($S26/2)+VLOOKUP($A26&\"_\"&\"vdd_dyn\"&\"_\"&$R26&\"_write\",MDB,5,0)*($S26/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},1.568956611570248,0,0,0,0,0,0,0,0.40200000000000002,0.72,0.86,2.9,3,0,0,0.02,0.11,0.78,0.08,0.20880841598144445,2.8429213601092607,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","sam62_mcasp_wrap_2","CB$57","CC$57","CD$57",2,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"MAIN PLL 0 HSDIV 0","MAIN Modules CLK [MHz] (SYSCLK)",500,500,"GPMC / ELM","unused",0,null,null,"PD_ENCODE",null,"ON"]
[{"$error":"#N/A"},{"$error":"#N/A"},0,{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},0,{"$error":"#N/A"},250,0,{"$f":"IF(ISBLANK(AT27),0,IF(AND(INDIRECT(AT27)<>\"unused\",INDIRECT(AV27)>AW27),INDIRECT(AU27),0))","v":0},0,{"$f":"IFERROR(IF($I27=\"SI\",AP27*$C27*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ27*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK27*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL27*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM27*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN27*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO27*'Power Scaling'!F$4)*IF(P27=\"OFF\",0.06,1),VLOOKUP($A27&\"_\"&U$3,MDB,5,0)*$C27*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P27=\"OFF\",0.06,1)),0)","v":0},{"$f":"C27*IFERROR(IF($I27=\"SI\",(AE27*IF(S27=0,0,1)+(AF27-AE27)*S27)*IF(R27>0,R27,Q27)/Q27*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ27*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK27*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL27*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM27*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN27*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO27*'Power Scaling'!I$4)*AQ27,IF(OR($I27=\"AO\",$I27=\"LU\"),VLOOKUP($A27&\"_\"&\"vdd_dyn\"&\"_\"&$R27&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I27=\"LUUA\",$I27=\"LUUB\"),VLOOKUP($A27&\"_\"&\"vdd_dyn\"&\"_\"&$R27&\"\",MDB,5,0)*$C27*$S27*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A27&\"_\"&\"vdd_dyn\"&\"_\"&$R27&\"_idle\",MDB,5,0)*(1-$S27)+VLOOKUP($A27&\"_\"&\"vdd_dyn\"&\"_\"&$R27&\"_read\",MDB,5,0)*($S27/2)+VLOOKUP($A27&\"_\"&\"vdd_dyn\"&\"_\"&$R27&\"_write\",MDB,5,0)*($S27/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,{"$error":"#N/A"},{"$error":"#N/A"},"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.",{"$error":"#N/A"},"CB$57","CC$57","CD$57",3,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"MAIN PLL 15 HSDIV 0\nMCU PLL 0 HSDIV 0","Device Manager Domain CLK [MHz]",400,400,null,null,null,null,null,"PD_DDR",null,"ON"]
[{"$error":"#N/A"},{"$error":"#N/A"},0,{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},0,{"$error":"#N/A"},250,0,{"$f":"IF(ISBLANK(AT28),0,IF(AND(INDIRECT(AT28)<>\"unused\",INDIRECT(AV28)>AW28),INDIRECT(AU28),0))","v":0},0,{"$f":"IFERROR(IF($I28=\"SI\",AP28*$C28*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ28*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK28*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL28*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM28*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN28*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO28*'Power Scaling'!F$4)*IF(P28=\"OFF\",0.06,1),VLOOKUP($A28&\"_\"&U$3,MDB,5,0)*$C28*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P28=\"OFF\",0.06,1)),0)","v":0},{"$f":"C28*IFERROR(IF($I28=\"SI\",(AE28*IF(S28=0,0,1)+(AF28-AE28)*S28)*IF(R28>0,R28,Q28)/Q28*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ28*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK28*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL28*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM28*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN28*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO28*'Power Scaling'!I$4)*AQ28,IF(OR($I28=\"AO\",$I28=\"LU\"),VLOOKUP($A28&\"_\"&\"vdd_dyn\"&\"_\"&$R28&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I28=\"LUUA\",$I28=\"LUUB\"),VLOOKUP($A28&\"_\"&\"vdd_dyn\"&\"_\"&$R28&\"\",MDB,5,0)*$C28*$S28*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A28&\"_\"&\"vdd_dyn\"&\"_\"&$R28&\"_idle\",MDB,5,0)*(1-$S28)+VLOOKUP($A28&\"_\"&\"vdd_dyn\"&\"_\"&$R28&\"_read\",MDB,5,0)*($S28/2)+VLOOKUP($A28&\"_\"&\"vdd_dyn\"&\"_\"&$R28&\"_write\",MDB,5,0)*($S28/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,{"$error":"#N/A"},{"$error":"#N/A"},"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.",{"$error":"#N/A"},"CB$57","CC$57","CD$57",4,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"MAIN PLL 15 HSDIV 0","HSM Domain CLK",400,null,"PHYs","Mode","Utilization","Instances",null,"PD_Debug",null,"OFF"]
["sam67_csirx_wrap","_0",1,1,"VDD_CORE","N/A","N/A","N/A","SI","GP_Core_CTL","CSI_RX","sam67_feb_power","3 Periph","Camera",5.2600142045454552,"ON",720,0,{"$f":"IF(ISBLANK(AT29),0,IF(AND(INDIRECT(AT29)<>\"ulps\",INDIRECT(AV29)>AW29),IF($CE$3=\"PDN\",1,INDIRECT(AU29)),0))","v":0.1},0,{"$f":"IFERROR(IF($I29=\"SI\",AP29*$C29*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ29*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK29*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL29*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM29*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN29*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO29*'Power Scaling'!F$4)*IF(P29=\"OFF\",0.06,1),VLOOKUP($A29&\"_\"&U$3,MDB,5,0)*$C29*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P29=\"OFF\",0.06,1)),0)","v":0},{"$f":"C29*IFERROR(IF($I29=\"SI\",(AE29*IF(S29=0,0,1)+(AF29-AE29)*S29)*IF(R29>0,R29,Q29)/Q29*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ29*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK29*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL29*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM29*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN29*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO29*'Power Scaling'!I$4)*AQ29,IF(OR($I29=\"AO\",$I29=\"LU\"),VLOOKUP($A29&\"_\"&\"vdd_dyn\"&\"_\"&$R29&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I29=\"LUUA\",$I29=\"LUUB\"),VLOOKUP($A29&\"_\"&\"vdd_dyn\"&\"_\"&$R29&\"\",MDB,5,0)*$C29*$S29*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A29&\"_\"&\"vdd_dyn\"&\"_\"&$R29&\"_idle\",MDB,5,0)*(1-$S29)+VLOOKUP($A29&\"_\"&\"vdd_dyn\"&\"_\"&$R29&\"_read\",MDB,5,0)*($S29/2)+VLOOKUP($A29&\"_\"&\"vdd_dyn\"&\"_\"&$R29&\"_write\",MDB,5,0)*($S29/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},5.2600142045454552,0,0,0,0,0,0,0,0.22800000000000001,0.48,0.57999999999999996,40,28.6,0,0,7.0000000000000007E-2,0.1,0.73,0.09,2.0594595110101714,38.845125484953471,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","sam67_csirx_wrap_0","CF$29","CG$29","CH$29",0,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"CSI2.0 D_PHY 4L Rx","1p5g4l",0.1,1,null,"PD_HSM",null,"ON"]
[{"$error":"#N/A"},{"$error":"#N/A"},0,{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},0,{"$error":"#N/A"},720,0,{"$f":"IF(ISBLANK(AT30),0,IF(AND(INDIRECT(AT30)<>\"ulps\",INDIRECT(AV30)>AW30),IF($CE$3=\"PDN\",1,INDIRECT(AU30)),0))","v":0},0,{"$f":"IFERROR(IF($I30=\"SI\",AP30*$C30*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ30*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK30*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL30*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM30*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN30*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO30*'Power Scaling'!F$4)*IF(P30=\"OFF\",0.06,1),VLOOKUP($A30&\"_\"&U$3,MDB,5,0)*$C30*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P30=\"OFF\",0.06,1)),0)","v":0},{"$f":"C30*IFERROR(IF($I30=\"SI\",(AE30*IF(S30=0,0,1)+(AF30-AE30)*S30)*IF(R30>0,R30,Q30)/Q30*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ30*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK30*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL30*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM30*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN30*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO30*'Power Scaling'!I$4)*AQ30,IF(OR($I30=\"AO\",$I30=\"LU\"),VLOOKUP($A30&\"_\"&\"vdd_dyn\"&\"_\"&$R30&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I30=\"LUUA\",$I30=\"LUUB\"),VLOOKUP($A30&\"_\"&\"vdd_dyn\"&\"_\"&$R30&\"\",MDB,5,0)*$C30*$S30*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A30&\"_\"&\"vdd_dyn\"&\"_\"&$R30&\"_idle\",MDB,5,0)*(1-$S30)+VLOOKUP($A30&\"_\"&\"vdd_dyn\"&\"_\"&$R30&\"_read\",MDB,5,0)*($S30/2)+VLOOKUP($A30&\"_\"&\"vdd_dyn\"&\"_\"&$R30&\"_write\",MDB,5,0)*($S30/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,{"$error":"#N/A"},{"$error":"#N/A"},"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.",{"$error":"#N/A"},"CF$29","CG$29","CH$29",1,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"IP for Complex IOs","Mode","Utilization","Instances","DSI D_PHY 4L Tx","off",0,0,null,"GP_Core_CTL_MCU",null,"ON"]
[{"$error":"#N/A"},{"$error":"#N/A"},0,{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},0,{"$error":"#N/A"},720,0,{"$f":"IF(ISBLANK(AT31),0,IF(AND(INDIRECT(AT31)<>\"ulps\",INDIRECT(AV31)>AW31),IF($CE$3=\"PDN\",1,INDIRECT(AU31)),0))","v":0},0,{"$f":"IFERROR(IF($I31=\"SI\",AP31*$C31*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ31*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK31*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL31*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM31*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN31*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO31*'Power Scaling'!F$4)*IF(P31=\"OFF\",0.06,1),VLOOKUP($A31&\"_\"&U$3,MDB,5,0)*$C31*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P31=\"OFF\",0.06,1)),0)","v":0},{"$f":"C31*IFERROR(IF($I31=\"SI\",(AE31*IF(S31=0,0,1)+(AF31-AE31)*S31)*IF(R31>0,R31,Q31)/Q31*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ31*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK31*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL31*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM31*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN31*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO31*'Power Scaling'!I$4)*AQ31,IF(OR($I31=\"AO\",$I31=\"LU\"),VLOOKUP($A31&\"_\"&\"vdd_dyn\"&\"_\"&$R31&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I31=\"LUUA\",$I31=\"LUUB\"),VLOOKUP($A31&\"_\"&\"vdd_dyn\"&\"_\"&$R31&\"\",MDB,5,0)*$C31*$S31*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A31&\"_\"&\"vdd_dyn\"&\"_\"&$R31&\"_idle\",MDB,5,0)*(1-$S31)+VLOOKUP($A31&\"_\"&\"vdd_dyn\"&\"_\"&$R31&\"_read\",MDB,5,0)*($S31/2)+VLOOKUP($A31&\"_\"&\"vdd_dyn\"&\"_\"&$R31&\"_write\",MDB,5,0)*($S31/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,{"$error":"#N/A"},{"$error":"#N/A"},"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.",{"$error":"#N/A"},"CF$29","CG$29","CH$29",2,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"CPSW3",null,0.2,null,"MAIN MMCSD0","hs400",1,1]
[{"$error":"#N/A"},{"$error":"#N/A"},0,{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},0,{"$error":"#N/A"},720,0,{"$f":"IF(ISBLANK(AT32),0,IF(AND(INDIRECT(AT32)<>\"ulps\",INDIRECT(AV32)>AW32),IF($CE$3=\"PDN\",1,INDIRECT(AU32)),0))","v":0},0,{"$f":"IFERROR(IF($I32=\"SI\",AP32*$C32*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ32*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK32*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL32*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM32*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN32*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO32*'Power Scaling'!F$4)*IF(P32=\"OFF\",0.06,1),VLOOKUP($A32&\"_\"&U$3,MDB,5,0)*$C32*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P32=\"OFF\",0.06,1)),0)","v":0},{"$f":"C32*IFERROR(IF($I32=\"SI\",(AE32*IF(S32=0,0,1)+(AF32-AE32)*S32)*IF(R32>0,R32,Q32)/Q32*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ32*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK32*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL32*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM32*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN32*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO32*'Power Scaling'!I$4)*AQ32,IF(OR($I32=\"AO\",$I32=\"LU\"),VLOOKUP($A32&\"_\"&\"vdd_dyn\"&\"_\"&$R32&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I32=\"LUUA\",$I32=\"LUUB\"),VLOOKUP($A32&\"_\"&\"vdd_dyn\"&\"_\"&$R32&\"\",MDB,5,0)*$C32*$S32*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A32&\"_\"&\"vdd_dyn\"&\"_\"&$R32&\"_idle\",MDB,5,0)*(1-$S32)+VLOOKUP($A32&\"_\"&\"vdd_dyn\"&\"_\"&$R32&\"_read\",MDB,5,0)*($S32/2)+VLOOKUP($A32&\"_\"&\"vdd_dyn\"&\"_\"&$R32&\"_write\",MDB,5,0)*($S32/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,{"$error":"#N/A"},{"$error":"#N/A"},"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.",{"$error":"#N/A"},"CF$29","CG$29","CH$29",3,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"1G SGMII SerDes ports","disable",0,0,"OLDI (2 Link)","oldi_dual_24b_modes",1,1]
[{"$error":"#N/A"},{"$error":"#N/A"},0,{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},0,{"$error":"#N/A"},720,0,{"$f":"IF(ISBLANK(AT33),0,IF(AND(INDIRECT(AT33)<>\"ulps\",INDIRECT(AV33)>AW33),IF($CE$3=\"PDN\",1,INDIRECT(AU33)),0))","v":""},0,{"$f":"IFERROR(IF($I33=\"SI\",AP33*$C33*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ33*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK33*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL33*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM33*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN33*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO33*'Power Scaling'!F$4)*IF(P33=\"OFF\",0.06,1),VLOOKUP($A33&\"_\"&U$3,MDB,5,0)*$C33*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P33=\"OFF\",0.06,1)),0)","v":0},{"$f":"C33*IFERROR(IF($I33=\"SI\",(AE33*IF(S33=0,0,1)+(AF33-AE33)*S33)*IF(R33>0,R33,Q33)/Q33*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ33*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK33*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL33*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM33*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN33*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO33*'Power Scaling'!I$4)*AQ33,IF(OR($I33=\"AO\",$I33=\"LU\"),VLOOKUP($A33&\"_\"&\"vdd_dyn\"&\"_\"&$R33&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I33=\"LUUA\",$I33=\"LUUB\"),VLOOKUP($A33&\"_\"&\"vdd_dyn\"&\"_\"&$R33&\"\",MDB,5,0)*$C33*$S33*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A33&\"_\"&\"vdd_dyn\"&\"_\"&$R33&\"_idle\",MDB,5,0)*(1-$S33)+VLOOKUP($A33&\"_\"&\"vdd_dyn\"&\"_\"&$R33&\"_read\",MDB,5,0)*($S33/2)+VLOOKUP($A33&\"_\"&\"vdd_dyn\"&\"_\"&$R33&\"_write\",MDB,5,0)*($S33/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,{"$error":"#N/A"},{"$error":"#N/A"},"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.",{"$error":"#N/A"},"CB$35","CC$35","CD$35",0,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"LVCMOS ports","rgmii_1000_1p8v",0.2,2]
[{"$error":"#N/A"},{"$error":"#N/A"},0,{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},0,{"$error":"#N/A"},500,{"$f":"IF(ISBLANK(BD34),0,INDIRECT(BD34))","v":0},{"$f":"IF(AND(IF(ISBLANK(AT34),\"disable\",INDIRECT(AT34))<>\"disable\",IF(ISBLANK(AU34),0,INDIRECT(AU34))*IF(ISBLANK(AV34),0,INDIRECT(AV34))),INDIRECT(AU34),0%)","v":{"$error":"#VALUE!"}},0,{"$f":"IFERROR(IF($I34=\"SI\",AP34*$C34*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ34*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK34*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL34*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM34*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN34*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO34*'Power Scaling'!F$4)*IF(P34=\"OFF\",0.06,1),VLOOKUP($A34&\"_\"&U$3,MDB,5,0)*$C34*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P34=\"OFF\",0.06,1)),0)","v":0},{"$f":"C34*IFERROR(IF($I34=\"SI\",(AE34*IF(S34=0,0,1)+(AF34-AE34)*S34)*IF(R34>0,R34,Q34)/Q34*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ34*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK34*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL34*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM34*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN34*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO34*'Power Scaling'!I$4)*AQ34,IF(OR($I34=\"AO\",$I34=\"LU\"),VLOOKUP($A34&\"_\"&\"vdd_dyn\"&\"_\"&$R34&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I34=\"LUUA\",$I34=\"LUUB\"),VLOOKUP($A34&\"_\"&\"vdd_dyn\"&\"_\"&$R34&\"\",MDB,5,0)*$C34*$S34*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A34&\"_\"&\"vdd_dyn\"&\"_\"&$R34&\"_idle\",MDB,5,0)*(1-$S34)+VLOOKUP($A34&\"_\"&\"vdd_dyn\"&\"_\"&$R34&\"_read\",MDB,5,0)*($S34/2)+VLOOKUP($A34&\"_\"&\"vdd_dyn\"&\"_\"&$R34&\"_write\",MDB,5,0)*($S34/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,{"$error":"#N/A"},{"$error":"#N/A"},"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.",{"$error":"#N/A"},"CB$38","CC$38","CD$38",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"CSI (TX) / DSI D-PHY"]
["sam67_usb2_wrap","_0",1,4,"VDD_CORE","N/A","N/A","N/A","SI","GP_Core_CTL","USB2 Controller","sam62p_dec_power","3 Periph","HS_Serial",5.9743833935950414,"ON",125,{"$f":"IF(ISBLANK(BD35),0,INDIRECT(BD35))","v":0},{"$f":"IF(AND(IF(ISBLANK(AT35),\"unused\",INDIRECT(AT35))<>\"suspend\",IF(ISBLANK(AU35),0,INDIRECT(AU35))*IF(ISBLANK(AV35),0,IF(INDIRECT(AV35)>0,1,0))),INDIRECT(AU35),0%)","v":1},0,{"$f":"IFERROR(IF($I35=\"SI\",AP35*$C35*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ35*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK35*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL35*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM35*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN35*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO35*'Power Scaling'!F$4)*IF(P35=\"OFF\",0.06,1),VLOOKUP($A35&\"_\"&U$3,MDB,5,0)*$C35*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P35=\"OFF\",0.06,1)),0)","v":0},{"$f":"C35*IFERROR(IF($I35=\"SI\",(AE35*IF(S35=0,0,1)+(AF35-AE35)*S35)*IF(R35>0,R35,Q35)/Q35*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ35*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK35*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL35*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM35*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN35*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO35*'Power Scaling'!I$4)*AQ35,IF(OR($I35=\"AO\",$I35=\"LU\"),VLOOKUP($A35&\"_\"&\"vdd_dyn\"&\"_\"&$R35&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I35=\"LUUA\",$I35=\"LUUB\"),VLOOKUP($A35&\"_\"&\"vdd_dyn\"&\"_\"&$R35&\"\",MDB,5,0)*$C35*$S35*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A35&\"_\"&\"vdd_dyn\"&\"_\"&$R35&\"_idle\",MDB,5,0)*(1-$S35)+VLOOKUP($A35&\"_\"&\"vdd_dyn\"&\"_\"&$R35&\"_read\",MDB,5,0)*($S35/2)+VLOOKUP($A35&\"_\"&\"vdd_dyn\"&\"_\"&$R35&\"_write\",MDB,5,0)*($S35/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},5.9743833935950414,0,0,0,0,0,0,0,0.27600000000000002,0.35,0.28999999999999998,21,23.5,0,0,0.02,0.06,0.84,0.08,1.869545542456585,20.631420498058993,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","sam67_usb2_wrap_0","CB$41","CC$41","CD$41",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"CSI Tx ports","","",1,"High Speed Serial Interfaces","Mode","Utilization",null,null,"Core","Frequency","Utilization"]
[{"$error":"#N/A"},{"$error":"#N/A"},0,{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$f":"SUM(U36:AD36)","v":0},{"$f":"INDEX(PD_State_Table,MATCH(J36,PD_Table_Row_Header,0),2)","v":{"$error":"#N/A"}},125,{"$f":"IF(ISBLANK(BD36),0,INDIRECT(BD36))","v":0},{"$f":"IF(AND(IF(ISBLANK(AT36),\"unused\",INDIRECT(AT36))<>\"suspend\",IF(ISBLANK(AU36),0,INDIRECT(AU36))*IF(ISBLANK(AV36),0,INDIRECT(AV36))),INDIRECT(AU36),0%)","v":{"$error":"#VALUE!"}},0,{"$f":"IFERROR(IF($I36=\"SI\",AP36*$C36*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ36*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK36*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL36*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM36*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN36*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO36*'Power Scaling'!F$4)*IF(P36=\"OFF\",0.06,1),VLOOKUP($A36&\"_\"&U$3,MDB,5,0)*$C36*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P36=\"OFF\",0.06,1)),0)","v":0},{"$f":"C36*IFERROR(IF($I36=\"SI\",(AE36*IF(S36=0,0,1)+(AF36-AE36)*S36)*IF(R36>0,R36,Q36)/Q36*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ36*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK36*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL36*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM36*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN36*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO36*'Power Scaling'!I$4)*AQ36,IF(OR($I36=\"AO\",$I36=\"LU\"),VLOOKUP($A36&\"_\"&\"vdd_dyn\"&\"_\"&$R36&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I36=\"LUUA\",$I36=\"LUUB\"),VLOOKUP($A36&\"_\"&\"vdd_dyn\"&\"_\"&$R36&\"\",MDB,5,0)*$C36*$S36*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A36&\"_\"&\"vdd_dyn\"&\"_\"&$R36&\"_idle\",MDB,5,0)*(1-$S36)+VLOOKUP($A36&\"_\"&\"vdd_dyn\"&\"_\"&$R36&\"_read\",MDB,5,0)*($S36/2)+VLOOKUP($A36&\"_\"&\"vdd_dyn\"&\"_\"&$R36&\"_write\",MDB,5,0)*($S36/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},{"$f":"C36*IFERROR(IF($I36=\"SI\",(AE36*IF(S36=0,0,1)+(AF36-AE36)*S36)*(IF(R36>0,R36,Q36)/Q36)*VLOOKUP(\"vdd_sw\",pwr_scale_table,2,0)*AI36,0),0)","v":0},{"$f":"IFERROR(VLOOKUP($A36&\"_\"&X$3,MDB,5,0)*$C36*VLOOKUP(\"vddr_lkg\",pwr_scale_table,2,0)*IF(P36=\"OFF\",0.06,1),0)","v":0},{"$f":"IFERROR(VLOOKUP($A36&\"_\"&Y$3,MDB,5,0)*$C36*(VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*0.5+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*0.5),0)","v":0},{"$f":"IFERROR(IF(I36=\"LUUB\",VLOOKUP($A36&\"_\"&Z$3&\"_\"&$R36&\"\",MDB,5,0)*$C36*$S36*((VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)/4+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)/4+VLOOKUP(\"vdd_sw\",pwr_scale_table,2,0)/2)),VLOOKUP($A36&\"_\"&Z$3&\"_\"&$R36&\"\",MDB,5,0)*$C36*((VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)/4+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)/4+VLOOKUP(\"vdd_sw\",pwr_scale_table,2,0)/2))),0)","v":0},{"$f":"IFERROR(VLOOKUP($A36&\"_\"&AA$3,MDB,5,0)*$C36*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0),0)","v":0},{"$f":"IFERROR(IF(OR($I36=\"LUUA\",$I36=\"LUUB\"),VLOOKUP($A36&\"_\"&AB$3&\"_\"&$R36&\"\",MDB,5,0)*$C36*$S36,IF(I36=\"LUUD\",VLOOKUP($A36&\"_\"&AB$3&\"_\"&$R36&\"_idle\",MDB,5,0)*(1-$S36)+VLOOKUP($A36&\"_\"&AB$3&\"_\"&$R36&\"_read\",MDB,5,0)*($S36/2)+VLOOKUP($A36&\"_\"&AB$3&\"_\"&$R36&\"_write\",MDB,5,0)*($S36/2),VLOOKUP($A36&\"_\"&AB$3&\"_\"&$R36&\"\",MDB,5,0)*$C36)),0)","v":0},{"$f":"IFERROR(VLOOKUP($A36&\"_\"&AC$3,MDB,5,0)*$C36*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0),0)","v":0},{"$f":"IFERROR(IF(OR($I36=\"LUUA\",$I36=\"LUUB\"),VLOOKUP($A36&\"_\"&AD$3&\"_\"&$R36&\"\",MDB,5,0)*$C36*$S36,IF(I36=\"LUUD\",VLOOKUP($A36&\"_\"&AD$3&\"_\"&$R36&\"_idle\",MDB,5,0)*(1-$S36)+VLOOKUP($A36&\"_\"&AD$3&\"_\"&$R36&\"_read\",MDB,5,0)*($S36/2)+VLOOKUP($A36&\"_\"&AD$3&\"_\"&$R36&\"_write\",MDB,5,0)*($S36/2),VLOOKUP($A36&\"_\"&AD$3&\"_\"&$R36&\"\",MDB,5,0)*$C36)),0)","v":0},0,0,0,0,0,0,0,0,0,0,0,{"$error":"#N/A"},{"$error":"#N/A"},"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.",{"$f":"A36&B36","v":{"$error":"#N/A"}},"CB$40","CC$40","CD$40",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"DSI Tx ports","ulps",0,0,"SerDes 0 (PCIE_3, PCIE_1, USB_0, Hyperlink_0)",null,null,null,null,"A53 CPU ",{"$f":"IF(R8=0,Q8,R8)","v":1250},{"$f":"IF(C8>0,S8,0)","v":1}]
[{"$error":"#N/A"},{"$error":"#N/A"},0,{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},0,{"$error":"#N/A"},125,{"$f":"IF(ISBLANK(BD37),0,INDIRECT(BD37))","v":0},{"$f":"IF(BB37=\"disable\",0,LEFT(BB37,1)*1)*IF(AZ37=\"disable\",INDIRECT(AX37),INDIRECT(AU37))/10","v":{"$error":"#VALUE!"}},0,{"$f":"IFERROR(IF($I37=\"SI\",AP37*$C37*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ37*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK37*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL37*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM37*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN37*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO37*'Power Scaling'!F$4)*IF(P37=\"OFF\",0.06,1),VLOOKUP($A37&\"_\"&U$3,MDB,5,0)*$C37*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P37=\"OFF\",0.06,1)),0)","v":0},{"$f":"C37*IFERROR(IF($I37=\"SI\",(AE37*IF(S37=0,0,1)+(AF37-AE37)*S37)*IF(R37>0,R37,Q37)/Q37*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ37*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK37*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL37*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM37*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN37*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO37*'Power Scaling'!I$4)*AQ37,IF(OR($I37=\"AO\",$I37=\"LU\"),VLOOKUP($A37&\"_\"&\"vdd_dyn\"&\"_\"&$R37&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I37=\"LUUA\",$I37=\"LUUB\"),VLOOKUP($A37&\"_\"&\"vdd_dyn\"&\"_\"&$R37&\"\",MDB,5,0)*$C37*$S37*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A37&\"_\"&\"vdd_dyn\"&\"_\"&$R37&\"_idle\",MDB,5,0)*(1-$S37)+VLOOKUP($A37&\"_\"&\"vdd_dyn\"&\"_\"&$R37&\"_read\",MDB,5,0)*($S37/2)+VLOOKUP($A37&\"_\"&\"vdd_dyn\"&\"_\"&$R37&\"_write\",MDB,5,0)*($S37/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,{"$error":"#N/A"},{"$error":"#N/A"},"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.",{"$error":"#N/A"},"CB$38","CC$38","CD$38","CB$32","CC$32","CD$32",{"$f":"IF(AND(IF(ISBLANK(AT37),\"disable\",INDIRECT(AT37))<>\"disable\",IF(ISBLANK(AU37),0,INDIRECT(AU37))*IF(ISBLANK(AV37),0,INDIRECT(AV37))),INDIRECT(AT37),\"disable\")","v":{"$error":"#VALUE!"}},{"$f":"IF(AND(IF(ISBLANK(AW37),\"disable\",INDIRECT(AW37))<>\"disable\",IF(ISBLANK(AX37),0,INDIRECT(AX37))*IF(ISBLANK(AY37),0,INDIRECT(AY37))),INDIRECT(AW37),\"disable\")","v":"disable"},{"$f":"IF(AZ37=\"disable\",BA37,AZ37)","v":{"$error":"#VALUE!"}},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"PCIE",null,null,null,"Lane0","","",null,null,"A53 CPU ",{"$f":"IF(R9=0,Q9,R9)","v":1250},{"$f":"IF(C9>0,S9,0)","v":1}]
[{"$error":"#N/A"},{"$error":"#N/A"},0,{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},0,{"$error":"#N/A"},125,{"$f":"IF(ISBLANK(BD38),0,INDIRECT(BD38))","v":0},{"$f":"IF(BB38=\"disable\",0,LEFT(BB38,1)*1)*IF(AZ38=\"disable\",INDIRECT(AU38),INDIRECT(AX38))/10","v":{"$error":"#VALUE!"}},0,{"$f":"IFERROR(IF($I38=\"SI\",AP38*$C38*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ38*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK38*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL38*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM38*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN38*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO38*'Power Scaling'!F$4)*IF(P38=\"OFF\",0.06,1),VLOOKUP($A38&\"_\"&U$3,MDB,5,0)*$C38*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P38=\"OFF\",0.06,1)),0)","v":0},{"$f":"C38*IFERROR(IF($I38=\"SI\",(AE38*IF(S38=0,0,1)+(AF38-AE38)*S38)*IF(R38>0,R38,Q38)/Q38*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ38*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK38*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL38*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM38*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN38*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO38*'Power Scaling'!I$4)*AQ38,IF(OR($I38=\"AO\",$I38=\"LU\"),VLOOKUP($A38&\"_\"&\"vdd_dyn\"&\"_\"&$R38&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I38=\"LUUA\",$I38=\"LUUB\"),VLOOKUP($A38&\"_\"&\"vdd_dyn\"&\"_\"&$R38&\"\",MDB,5,0)*$C38*$S38*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A38&\"_\"&\"vdd_dyn\"&\"_\"&$R38&\"_idle\",MDB,5,0)*(1-$S38)+VLOOKUP($A38&\"_\"&\"vdd_dyn\"&\"_\"&$R38&\"_read\",MDB,5,0)*($S38/2)+VLOOKUP($A38&\"_\"&\"vdd_dyn\"&\"_\"&$R38&\"_write\",MDB,5,0)*($S38/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,{"$error":"#N/A"},{"$error":"#N/A"},"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.",{"$error":"#N/A"},"CB$40","CC$40","CD$40","CB$32","CC$32","CD$32",{"$f":"IF(AND(IF(ISBLANK(AT38),\"unused\",INDIRECT(AT38))=\"5g\",IF(ISBLANK(AU38),0,INDIRECT(AU38))*IF(ISBLANK(AV38),0,INDIRECT(AV38))),\"5g\",\"disable\")","v":{"$error":"#VALUE!"}},{"$f":"IF(AND(IF(ISBLANK(AW38),\"disable\",INDIRECT(AW38))<>\"disable\",IF(ISBLANK(AX38),0,INDIRECT(AX38))*IF(ISBLANK(AY38),0,INDIRECT(AY38))),INDIRECT(AW38),\"disable\")","v":"disable"},{"$f":"IF(IF(IF(AZ38=\"unused\",BA38,AZ38)=\"1g\",1,0)+IF(BA37=\"1g\",1,0)>INDIRECT(AY38),\"unused\",IF(AZ38=\"unused\",BA38,AZ38))","v":{"$error":"#VALUE!"}},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"PCIE_0 (1 Lane)","","",1,"SerDes 1 (CPSW3_0, PCIE_0, PCIE_2, n/a)",0,0,null,null,"A53 CPU ",{"$f":"IF(R10=0,Q10,R10)","v":1250},{"$f":"IF(C10>0,S10,0)","v":1}]
["ddr32_3733_phy","_0",1,3,"VDD_CORE","N/A","N/A","N/A","SI","PD_DDR","LP/DDR4-32 PHY 3733",44468,"3 Periph","Memory",105.49994998282273,"ON",1066.75,{"$f":"IF(ISBLANK(BD39),0,INDIRECT(BD39))/4","v":533.25},{"$f":"S44*1.1","v":1.1000000000000001},0,{"$f":"IFERROR(IF($I39=\"SI\",AP39*$C39*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ39*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK39*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL39*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM39*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN39*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO39*'Power Scaling'!F$4)*IF(P39=\"OFF\",0.06,1),VLOOKUP($A39&\"_\"&U$3,MDB,5,0)*$C39*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P39=\"OFF\",0.06,1)),0)","v":0},{"$f":"C39*IFERROR(IF($I39=\"SI\",(AE39*IF(S39=0,0,1)+(AF39-AE39)*S39)*IF(R39>0,R39,Q39)/Q39*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ39*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK39*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL39*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM39*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN39*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO39*'Power Scaling'!I$4)*AQ39,IF(OR($I39=\"AO\",$I39=\"LU\"),VLOOKUP($A39&\"_\"&\"vdd_dyn\"&\"_\"&$R39&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I39=\"LUUA\",$I39=\"LUUB\"),VLOOKUP($A39&\"_\"&\"vdd_dyn\"&\"_\"&$R39&\"\",MDB,5,0)*$C39*$S39*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A39&\"_\"&\"vdd_dyn\"&\"_\"&$R39&\"_idle\",MDB,5,0)*(1-$S39)+VLOOKUP($A39&\"_\"&\"vdd_dyn\"&\"_\"&$R39&\"_read\",MDB,5,0)*($S39/2)+VLOOKUP($A39&\"_\"&\"vdd_dyn\"&\"_\"&$R39&\"_write\",MDB,5,0)*($S39/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},105.49994998282273,0,0,0,0,0,0,0,0.11,0.95,1,281,281,0.26200000000000001,4.9799999999999997E-2,5.3400000000000003E-2,0.32429999999999998,0.13239999999999999,0.17810000000000001,13.38382660410366,224.61171416336228,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","ddr32_3733_phy_0","CG$25",null,null,null,null,null,null,null,null,null,"CC$24",null,null,"DDR",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"USB",null,null,null,"Lane0","","",null,null,"A53 CPU ",{"$f":"IF(R11=0,Q11,R11)","v":1250},{"$f":"IF(C11>0,S11,0)","v":1}]
["sam62_emmc_4bit_wrap","_1",1,5,"VDD_CORE","N/A","N/A","N/A","SI","GP_Core_CTL","EMMC 4 AM62","sam62a_april_power","3 Periph","Memory",2.6497933884297522,"ON",250,0,{"$f":"IF(ISBLANK(AT40),0,IF(AND(INDIRECT(AT40)<>\"unused\",INDIRECT(AV40)>AW40),INDIRECT(AU40),0))","v":1},0,{"$f":"IFERROR(IF($I40=\"SI\",AP40*$C40*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ40*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK40*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL40*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM40*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN40*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO40*'Power Scaling'!F$4)*IF(P40=\"OFF\",0.06,1),VLOOKUP($A40&\"_\"&U$3,MDB,5,0)*$C40*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P40=\"OFF\",0.06,1)),0)","v":0},{"$f":"C40*IFERROR(IF($I40=\"SI\",(AE40*IF(S40=0,0,1)+(AF40-AE40)*S40)*IF(R40>0,R40,Q40)/Q40*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ40*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK40*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL40*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM40*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN40*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO40*'Power Scaling'!I$4)*AQ40,IF(OR($I40=\"AO\",$I40=\"LU\"),VLOOKUP($A40&\"_\"&\"vdd_dyn\"&\"_\"&$R40&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I40=\"LUUA\",$I40=\"LUUB\"),VLOOKUP($A40&\"_\"&\"vdd_dyn\"&\"_\"&$R40&\"\",MDB,5,0)*$C40*$S40*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A40&\"_\"&\"vdd_dyn\"&\"_\"&$R40&\"_idle\",MDB,5,0)*(1-$S40)+VLOOKUP($A40&\"_\"&\"vdd_dyn\"&\"_\"&$R40&\"_read\",MDB,5,0)*($S40/2)+VLOOKUP($A40&\"_\"&\"vdd_dyn\"&\"_\"&$R40&\"_write\",MDB,5,0)*($S40/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},2.6497933884297522,0,0,0,0,0,0,0,0.26800000000000002,0.48,0.57999999999999996,8.5,7.6,0.01,0,0.01,0.12,0.81,0.06,0.56387150112799667,8.1296738451367911,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","sam62_emmc_4bit_wrap_1","CB$62","CC$62","CD$62",0,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"3.0","","",1,null,null,null,null,null,"C7x",{"$f":"IF(R$15=0,Q$15,R$15)","v":912.5},{"$f":"IF(C15>0,IF($CE$3=\"PDN\",1,(S15-CL41*0.8)/0.66),0)","v":0}]
["sam62_emmc_4bit_wrap","_2",1,5,"VDD_CORE","N/A","N/A","N/A","SI","GP_Core_CTL","EMMC 4 AM62","sam62a_april_power","3 Periph","Memory",2.6497933884297522,"ON",250,0,{"$f":"IF(ISBLANK(AT41),0,IF(AND(INDIRECT(AT41)<>\"unused\",INDIRECT(AV41)>AW41),INDIRECT(AU41),0))","v":1},0,{"$f":"IFERROR(IF($I41=\"SI\",AP41*$C41*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ41*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK41*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL41*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM41*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN41*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO41*'Power Scaling'!F$4)*IF(P41=\"OFF\",0.06,1),VLOOKUP($A41&\"_\"&U$3,MDB,5,0)*$C41*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P41=\"OFF\",0.06,1)),0)","v":0},{"$f":"C41*IFERROR(IF($I41=\"SI\",(AE41*IF(S41=0,0,1)+(AF41-AE41)*S41)*IF(R41>0,R41,Q41)/Q41*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ41*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK41*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL41*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM41*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN41*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO41*'Power Scaling'!I$4)*AQ41,IF(OR($I41=\"AO\",$I41=\"LU\"),VLOOKUP($A41&\"_\"&\"vdd_dyn\"&\"_\"&$R41&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I41=\"LUUA\",$I41=\"LUUB\"),VLOOKUP($A41&\"_\"&\"vdd_dyn\"&\"_\"&$R41&\"\",MDB,5,0)*$C41*$S41*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A41&\"_\"&\"vdd_dyn\"&\"_\"&$R41&\"_idle\",MDB,5,0)*(1-$S41)+VLOOKUP($A41&\"_\"&\"vdd_dyn\"&\"_\"&$R41&\"_read\",MDB,5,0)*($S41/2)+VLOOKUP($A41&\"_\"&\"vdd_dyn\"&\"_\"&$R41&\"_write\",MDB,5,0)*($S41/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},2.6497933884297522,0,0,0,0,0,0,0,0.26800000000000002,0.48,0.57999999999999996,8.5,7.6,0.01,0,0.01,0.12,0.81,0.06,0.56387150112799667,8.1296738451367911,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","sam62_emmc_4bit_wrap_2","CB$62","CC$62","CD$62",1,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"USB 2.0","host_hs",1,2,null,null,null,null,null,"MMA",{"$f":"IF(R$15=0,Q$15,R$15)","v":912.5},{"$f":"IF(C6>0,S16,0)","v":0}]
["sam67_emmc_8bit_wrap","_0",1,2,"VDD_CORE","N/A","N/A","N/A","SI","GP_Core_CTL","EMMC 8 AM62","sam62p_march_c2end_power","3 Periph","Memory",2.8241219008264462,"ON",250,0,{"$f":"IF(ISBLANK(AT42),0,IF(AND(INDIRECT(AT42)<>\"off\",INDIRECT(AV42)>AW42),INDIRECT(AU42),0))","v":1},0,{"$f":"IFERROR(IF($I42=\"SI\",AP42*$C42*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ42*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK42*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL42*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM42*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN42*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO42*'Power Scaling'!F$4)*IF(P42=\"OFF\",0.06,1),VLOOKUP($A42&\"_\"&U$3,MDB,5,0)*$C42*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P42=\"OFF\",0.06,1)),0)","v":0},{"$f":"C42*IFERROR(IF($I42=\"SI\",(AE42*IF(S42=0,0,1)+(AF42-AE42)*S42)*IF(R42>0,R42,Q42)/Q42*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ42*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK42*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL42*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM42*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN42*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO42*'Power Scaling'!I$4)*AQ42,IF(OR($I42=\"AO\",$I42=\"LU\"),VLOOKUP($A42&\"_\"&\"vdd_dyn\"&\"_\"&$R42&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I42=\"LUUA\",$I42=\"LUUB\"),VLOOKUP($A42&\"_\"&\"vdd_dyn\"&\"_\"&$R42&\"\",MDB,5,0)*$C42*$S42*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A42&\"_\"&\"vdd_dyn\"&\"_\"&$R42&\"_idle\",MDB,5,0)*(1-$S42)+VLOOKUP($A42&\"_\"&\"vdd_dyn\"&\"_\"&$R42&\"_read\",MDB,5,0)*($S42/2)+VLOOKUP($A42&\"_\"&\"vdd_dyn\"&\"_\"&$R42&\"_write\",MDB,5,0)*($S42/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},2.8241219008264462,0,0,0,0,0,0,0,0.30299999999999999,0.48,0.57999999999999996,8.3000000000000007,8.1,0,0,0,0.08,0.88,0.04,0.58313641265244531,8.1477744776128027,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","sam67_emmc_8bit_wrap_0","CF$31","CG$31","CH$31",0,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"C7x",{"$f":"IF(R$13=0,Q$13,R$13)","v":912.5},{"$f":"IF(C13>0,IF($CE$3=\"PDN\",1,(S13-0.8*CL43)/0.66),0)","v":0}]
["sam62_gpmc_elm_wrap","_0",1,4,"VDD_CORE","N/A","N/A","N/A","SI","GP_Core_CTL","GPMC_ELM AM62","sam62a_april_power","3 Periph","Memory",0,"ON",166.66666670000001,{"$f":"IF(ISBLANK(BD43),0,INDIRECT(BD43))","v":0},{"$f":"IF(ISBLANK(AT43),0,IF(INDIRECT(AT43)=\"unused\",0,INDIRECT(AU43)))","v":0},0,{"$f":"IFERROR(IF($I43=\"SI\",AP43*$C43*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ43*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK43*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL43*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM43*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN43*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO43*'Power Scaling'!F$4)*IF(P43=\"OFF\",0.06,1),VLOOKUP($A43&\"_\"&U$3,MDB,5,0)*$C43*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P43=\"OFF\",0.06,1)),0)","v":0},{"$f":"C43*IFERROR(IF($I43=\"SI\",(AE43*IF(S43=0,0,1)+(AF43-AE43)*S43)*IF(R43>0,R43,Q43)/Q43*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ43*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK43*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL43*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM43*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN43*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO43*'Power Scaling'!I$4)*AQ43,IF(OR($I43=\"AO\",$I43=\"LU\"),VLOOKUP($A43&\"_\"&\"vdd_dyn\"&\"_\"&$R43&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I43=\"LUUA\",$I43=\"LUUB\"),VLOOKUP($A43&\"_\"&\"vdd_dyn\"&\"_\"&$R43&\"\",MDB,5,0)*$C43*$S43*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A43&\"_\"&\"vdd_dyn\"&\"_\"&$R43&\"_idle\",MDB,5,0)*(1-$S43)+VLOOKUP($A43&\"_\"&\"vdd_dyn\"&\"_\"&$R43&\"_read\",MDB,5,0)*($S43/2)+VLOOKUP($A43&\"_\"&\"vdd_dyn\"&\"_\"&$R43&\"_write\",MDB,5,0)*($S43/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0,0.20599999999999999,0.48,0.57999999999999996,6.5,6.9,0,0,0.02,0.09,0.78,0.11,0.49709079523973609,6.3442501187619209,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","sam62_gpmc_elm_wrap_0","CF$26","CG$26",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"LVCMOS IO","Mode","Utilization","Instances",null,null,null,null,null,"MMA",{"$f":"IF(R$13=0,Q$13,R$13)","v":912.5},{"$f":"IF(C14=0,S14,0)","v":0}]
["sam67_ddr_wrap","_0",1,3,"VDD_CORE","N/A","N/A","N/A","SI","PD_DDR","LP/DDR4-32 EMIF AM62A","sam62p_nov_power","3 Periph","Memory",63.740264184057409,"ON",1066.75,{"$f":"IF(ISBLANK(BD44),0,INDIRECT(BD44))/4","v":533.25},{"$f":"IF(ISBLANK(AT44),0,IF(INDIRECT(AT44)<>\"sleep\",IF($CE$3=\"PDN\",0.91,INDIRECT(AU44)),0))","v":1},0,{"$f":"IFERROR(IF($I44=\"SI\",AP44*$C44*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ44*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK44*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL44*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM44*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN44*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO44*'Power Scaling'!F$4)*IF(P44=\"OFF\",0.06,1),VLOOKUP($A44&\"_\"&U$3,MDB,5,0)*$C44*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P44=\"OFF\",0.06,1)),0)","v":0},{"$f":"C44*IFERROR(IF($I44=\"SI\",(AE44*IF(S44=0,0,1)+(AF44-AE44)*S44)*IF(R44>0,R44,Q44)/Q44*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ44*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK44*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL44*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM44*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN44*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO44*'Power Scaling'!I$4)*AQ44,IF(OR($I44=\"AO\",$I44=\"LU\"),VLOOKUP($A44&\"_\"&\"vdd_dyn\"&\"_\"&$R44&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I44=\"LUUA\",$I44=\"LUUB\"),VLOOKUP($A44&\"_\"&\"vdd_dyn\"&\"_\"&$R44&\"\",MDB,5,0)*$C44*$S44*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A44&\"_\"&\"vdd_dyn\"&\"_\"&$R44&\"_idle\",MDB,5,0)*(1-$S44)+VLOOKUP($A44&\"_\"&\"vdd_dyn\"&\"_\"&$R44&\"_read\",MDB,5,0)*($S44/2)+VLOOKUP($A44&\"_\"&\"vdd_dyn\"&\"_\"&$R44&\"_write\",MDB,5,0)*($S44/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},63.740264184057409,0,0,0,0,0,0,0,0.17299999999999999,0.45,0.75,293.89999999999998,390.1,0.06,0.02,0.16,0.08,0.28000000000000003,0.4,6.1189666896760073,268.96272306609671,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","sam67_ddr_wrap_0","Cf$25","CG$25",null,null,null,null,null,null,null,null,"CC$24",null,null,"DDR",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"WKUP I2C","i2c_400k_3p3v",1,1,null,null,null,null,null,"R5F",{"$f":"IF(R4=0,Q4,R4)","v":800},{"$f":"IF(C4>0,S4,0)","v":1}]
["sam67_debug_wrap","_0",1,4,"VDD_CORE","N/A","N/A","N/A","SI","PD_Debug","Debug SS AM67","sam62p_dec_power","4 Infra","Debug",0,"OFF",250,{"$f":"IF(ISBLANK(BD45),0,INDIRECT(BD45))","v":0},0,0,{"$f":"IFERROR(IF($I45=\"SI\",AP45*$C45*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ45*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK45*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL45*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM45*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN45*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO45*'Power Scaling'!F$4)*IF(P45=\"OFF\",0.06,1),VLOOKUP($A45&\"_\"&U$3,MDB,5,0)*$C45*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P45=\"OFF\",0.06,1)),0)","v":0},{"$f":"C45*IFERROR(IF($I45=\"SI\",(AE45*IF(S45=0,0,1)+(AF45-AE45)*S45)*IF(R45>0,R45,Q45)/Q45*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ45*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK45*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL45*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM45*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN45*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO45*'Power Scaling'!I$4)*AQ45,IF(OR($I45=\"AO\",$I45=\"LU\"),VLOOKUP($A45&\"_\"&\"vdd_dyn\"&\"_\"&$R45&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I45=\"LUUA\",$I45=\"LUUB\"),VLOOKUP($A45&\"_\"&\"vdd_dyn\"&\"_\"&$R45&\"\",MDB,5,0)*$C45*$S45*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A45&\"_\"&\"vdd_dyn\"&\"_\"&$R45&\"_idle\",MDB,5,0)*(1-$S45)+VLOOKUP($A45&\"_\"&\"vdd_dyn\"&\"_\"&$R45&\"_read\",MDB,5,0)*($S45/2)+VLOOKUP($A45&\"_\"&\"vdd_dyn\"&\"_\"&$R45&\"_write\",MDB,5,0)*($S45/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0,0.29899999999999999,0.48,0.57999999999999996,20.6,16.5,0,0,0,0.12,0.65,0.24,1.4521758875434994,19.919384895582972,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","sam67_debug_wrap_0",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"WKUP UART","1m_3p3v",1,1,null,null,null,null,null,"R5F",{"$f":"IF(R5=0,Q5,R5)","v":800},{"$f":"IF(C5>0,S5,0)","v":1}]
["sam62_efuse_ctrl_wrap","_0",1,4,"VDD_CORE","N/A","N/A","N/A","SI","GP_Core_CTL","eFuse Controller AM62","sam62a_april_power","4 Infra","Mix",0,"ON",250,{"$f":"IF(ISBLANK(BD46),0,INDIRECT(BD46))","v":0},0,0,{"$f":"IFERROR(IF($I46=\"SI\",AP46*$C46*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ46*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK46*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL46*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM46*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN46*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO46*'Power Scaling'!F$4)*IF(P46=\"OFF\",0.06,1),VLOOKUP($A46&\"_\"&U$3,MDB,5,0)*$C46*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P46=\"OFF\",0.06,1)),0)","v":0},{"$f":"C46*IFERROR(IF($I46=\"SI\",(AE46*IF(S46=0,0,1)+(AF46-AE46)*S46)*IF(R46>0,R46,Q46)/Q46*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ46*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK46*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL46*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM46*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN46*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO46*'Power Scaling'!I$4)*AQ46,IF(OR($I46=\"AO\",$I46=\"LU\"),VLOOKUP($A46&\"_\"&\"vdd_dyn\"&\"_\"&$R46&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I46=\"LUUA\",$I46=\"LUUB\"),VLOOKUP($A46&\"_\"&\"vdd_dyn\"&\"_\"&$R46&\"\",MDB,5,0)*$C46*$S46*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A46&\"_\"&\"vdd_dyn\"&\"_\"&$R46&\"_idle\",MDB,5,0)*(1-$S46)+VLOOKUP($A46&\"_\"&\"vdd_dyn\"&\"_\"&$R46&\"_read\",MDB,5,0)*($S46/2)+VLOOKUP($A46&\"_\"&\"vdd_dyn\"&\"_\"&$R46&\"_write\",MDB,5,0)*($S46/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0,0.155,0.18,0.22,3.7,3.9,0,0,0,0.16,0.63,0.21,0.19521864907021541,3.5763264471554224,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","sam62_efuse_ctrl_wrap_0",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"MCU I2C","i2c_400k_3p3v",1,1,null,null,null,null,null,"R5F",{"$f":"IF(R6=0,Q6,R6)","v":800},{"$f":"IF(C6>0,S6,0)","v":0}]
["sam62_odp_ctrl_wrap","_0",1,4,"VDD_CORE","N/A","N/A","N/A","SI","GP_Core_CTL","ODP Controller AM62","sam62a_april_power","4 Infra","Mix",0,"ON",500,{"$f":"IF(ISBLANK(BD47),0,INDIRECT(BD47))","v":0},0,0,{"$f":"IFERROR(IF($I47=\"SI\",AP47*$C47*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ47*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK47*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL47*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM47*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN47*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO47*'Power Scaling'!F$4)*IF(P47=\"OFF\",0.06,1),VLOOKUP($A47&\"_\"&U$3,MDB,5,0)*$C47*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P47=\"OFF\",0.06,1)),0)","v":0},{"$f":"C47*IFERROR(IF($I47=\"SI\",(AE47*IF(S47=0,0,1)+(AF47-AE47)*S47)*IF(R47>0,R47,Q47)/Q47*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ47*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK47*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL47*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM47*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN47*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO47*'Power Scaling'!I$4)*AQ47,IF(OR($I47=\"AO\",$I47=\"LU\"),VLOOKUP($A47&\"_\"&\"vdd_dyn\"&\"_\"&$R47&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I47=\"LUUA\",$I47=\"LUUB\"),VLOOKUP($A47&\"_\"&\"vdd_dyn\"&\"_\"&$R47&\"\",MDB,5,0)*$C47*$S47*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A47&\"_\"&\"vdd_dyn\"&\"_\"&$R47&\"_idle\",MDB,5,0)*(1-$S47)+VLOOKUP($A47&\"_\"&\"vdd_dyn\"&\"_\"&$R47&\"_read\",MDB,5,0)*($S47/2)+VLOOKUP($A47&\"_\"&\"vdd_dyn\"&\"_\"&$R47&\"_write\",MDB,5,0)*($S47/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0,0.44,0.5,0.52,1,1,0,0,0,0.44,0.4,0.16,2.5965150613452649E-2,0.90576238055802061,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","sam62_odp_ctrl_wrap_0",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"MCU UART","112k_3p3v",1,1,null,null,null,null,null,"Double DSS7UL + DSI + OLDI wrap",{"$f":"IF(R12=0,Q12,R12)","v":320},{"$f":"IF(C12>0,S12,0)","v":0.76}]
["sam62_pll_ctrl_wrap","_0",2,0,"VDD_CORE","N/A","N/A","N/A","SI","GP_Core_CTL","PLL Controller AM62","sam62a_april_power","4 Infra","Mix",2.1064695247933884,"ON",500,{"$f":"SYSCLK","v":500},1,0,{"$f":"IFERROR(IF($I48=\"SI\",AP48*$C48*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ48*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK48*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL48*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM48*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN48*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO48*'Power Scaling'!F$4)*IF(P48=\"OFF\",0.06,1),VLOOKUP($A48&\"_\"&U$3,MDB,5,0)*$C48*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P48=\"OFF\",0.06,1)),0)","v":0},{"$f":"C48*IFERROR(IF($I48=\"SI\",(AE48*IF(S48=0,0,1)+(AF48-AE48)*S48)*IF(R48>0,R48,Q48)/Q48*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ48*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK48*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL48*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM48*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN48*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO48*'Power Scaling'!I$4)*AQ48,IF(OR($I48=\"AO\",$I48=\"LU\"),VLOOKUP($A48&\"_\"&\"vdd_dyn\"&\"_\"&$R48&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I48=\"LUUA\",$I48=\"LUUB\"),VLOOKUP($A48&\"_\"&\"vdd_dyn\"&\"_\"&$R48&\"\",MDB,5,0)*$C48*$S48*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A48&\"_\"&\"vdd_dyn\"&\"_\"&$R48&\"_idle\",MDB,5,0)*(1-$S48)+VLOOKUP($A48&\"_\"&\"vdd_dyn\"&\"_\"&$R48&\"_read\",MDB,5,0)*($S48/2)+VLOOKUP($A48&\"_\"&\"vdd_dyn\"&\"_\"&$R48&\"_write\",MDB,5,0)*($S48/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},2.1064695247933884,0,0,0,0,0,0,0,0.47499999999999998,0.5,0.31,3.4,2.9,0.01,0,0.05,0.39,0.48,0.06,7.6129647876778381E-2,3.0871273598932221,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","sam62_pll_ctrl_wrap_0",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"MCU McSPI","Controller_2.083_Mbaud_3p3v",1,1,null,null,null,null,null,"GPU BXS4-64-256KB DUST AM67",{"$f":"IF(R$17=0,Q$17,R$17)","v":720},{"$f":"IF(C$17>0,S$17,0)","v":1}]
[{"$error":"#N/A"},{"$error":"#N/A"},0,{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},0,{"$error":"#N/A"},500,{"$f":"SYSCLK","v":500},1,0,{"$f":"IFERROR(IF($I49=\"SI\",AP49*$C49*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ49*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK49*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL49*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM49*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN49*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO49*'Power Scaling'!F$4)*IF(P49=\"OFF\",0.06,1),VLOOKUP($A49&\"_\"&U$3,MDB,5,0)*$C49*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P49=\"OFF\",0.06,1)),0)","v":0},{"$f":"C49*IFERROR(IF($I49=\"SI\",(AE49*IF(S49=0,0,1)+(AF49-AE49)*S49)*IF(R49>0,R49,Q49)/Q49*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ49*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK49*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL49*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM49*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN49*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO49*'Power Scaling'!I$4)*AQ49,IF(OR($I49=\"AO\",$I49=\"LU\"),VLOOKUP($A49&\"_\"&\"vdd_dyn\"&\"_\"&$R49&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I49=\"LUUA\",$I49=\"LUUB\"),VLOOKUP($A49&\"_\"&\"vdd_dyn\"&\"_\"&$R49&\"\",MDB,5,0)*$C49*$S49*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A49&\"_\"&\"vdd_dyn\"&\"_\"&$R49&\"_idle\",MDB,5,0)*(1-$S49)+VLOOKUP($A49&\"_\"&\"vdd_dyn\"&\"_\"&$R49&\"_read\",MDB,5,0)*($S49/2)+VLOOKUP($A49&\"_\"&\"vdd_dyn\"&\"_\"&$R49&\"_write\",MDB,5,0)*($S49/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,{"$error":"#N/A"},{"$error":"#N/A"},"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.",{"$error":"#N/A"},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"MCU MCAN","5mbs_3p3v",1,1,null,null,null,null,null,"GPU BXS4-64-256KB Rascal AM67",{"$f":"IF(R$17=0,Q$17,R$17)","v":720},{"$f":"IF(C$17>0,S$17,0)","v":1}]
["sam67_ls_mcu_can","_0",1,5,"VDD_CORE","N/A","N/A","N/A","SI","GP_Core_CTL","CAN_IO wrap AM62A","sam62a_april_power","4 Infra","Buffering",0.20338326446280994,"ON",1066,{"$f":"IF(ISBLANK(BD50),0,INDIRECT(BD50))","v":0},1,0,{"$f":"IFERROR(IF($I50=\"SI\",AP50*$C50*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ50*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK50*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL50*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM50*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN50*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO50*'Power Scaling'!F$4)*IF(P50=\"OFF\",0.06,1),VLOOKUP($A50&\"_\"&U$3,MDB,5,0)*$C50*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P50=\"OFF\",0.06,1)),0)","v":0},{"$f":"C50*IFERROR(IF($I50=\"SI\",(AE50*IF(S50=0,0,1)+(AF50-AE50)*S50)*IF(R50>0,R50,Q50)/Q50*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ50*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK50*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL50*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM50*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN50*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO50*'Power Scaling'!I$4)*AQ50,IF(OR($I50=\"AO\",$I50=\"LU\"),VLOOKUP($A50&\"_\"&\"vdd_dyn\"&\"_\"&$R50&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I50=\"LUUA\",$I50=\"LUUB\"),VLOOKUP($A50&\"_\"&\"vdd_dyn\"&\"_\"&$R50&\"\",MDB,5,0)*$C50*$S50*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A50&\"_\"&\"vdd_dyn\"&\"_\"&$R50&\"_idle\",MDB,5,0)*(1-$S50)+VLOOKUP($A50&\"_\"&\"vdd_dyn\"&\"_\"&$R50&\"_read\",MDB,5,0)*($S50/2)+VLOOKUP($A50&\"_\"&\"vdd_dyn\"&\"_\"&$R50&\"_write\",MDB,5,0)*($S50/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0.20338326446280994,0,0,0,0,0,0,0,0,0.4,0.48,0.2,0.7,0,0,0.06,0.92,0.02,0,6.5816994714145011E-3,0.16135780657942911,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","sam67_ls_mcu_can_0",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"MCU GPIO","1mbs_3p3v_20pf",1,5,null,null,null,null,null,"GPU BXS4-64-256KB Wrap AM67",{"$f":"IF(R$17=0,Q$17,R$17)","v":720},{"$f":"IF(C$17>0,S$17,0)","v":1}]
["j7_n16_edg_lvl_iopm","_0",1,5,"VDD_CORE","N/A","N/A","N/A","SI","GP_Core_CTL","N16_EDG_LS J7ES","j7aep_pg1","4 Infra","Buffering",0,"ON",200,{"$f":"IF(ISBLANK(BD51),0,INDIRECT(BD51))","v":0},1,0,{"$f":"IFERROR(IF($I51=\"SI\",AP51*$C51*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ51*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK51*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL51*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM51*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN51*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO51*'Power Scaling'!F$4)*IF(P51=\"OFF\",0.06,1),VLOOKUP($A51&\"_\"&U$3,MDB,5,0)*$C51*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P51=\"OFF\",0.06,1)),0)","v":0},{"$f":"C51*IFERROR(IF($I51=\"SI\",(AE51*IF(S51=0,0,1)+(AF51-AE51)*S51)*IF(R51>0,R51,Q51)/Q51*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ51*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK51*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL51*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM51*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN51*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO51*'Power Scaling'!I$4)*AQ51,IF(OR($I51=\"AO\",$I51=\"LU\"),VLOOKUP($A51&\"_\"&\"vdd_dyn\"&\"_\"&$R51&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I51=\"LUUA\",$I51=\"LUUB\"),VLOOKUP($A51&\"_\"&\"vdd_dyn\"&\"_\"&$R51&\"\",MDB,5,0)*$C51*$S51*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A51&\"_\"&\"vdd_dyn\"&\"_\"&$R51&\"_idle\",MDB,5,0)*(1-$S51)+VLOOKUP($A51&\"_\"&\"vdd_dyn\"&\"_\"&$R51&\"_read\",MDB,5,0)*($S51/2)+VLOOKUP($A51&\"_\"&\"vdd_dyn\"&\"_\"&$R51&\"_write\",MDB,5,0)*($S51/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0,0,0.4,0.48,0,0,0,0,0,0,1,0,0,{"$error":"#N/A"},"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","j7_n16_edg_lvl_iopm_0",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"VPAC3L",{"$f":"IF(R20=0,Q20,R20)","v":600},{"$f":"IF(C20>0,S20,0)","v":0}]
["sam62a_can_io_domain","_0",1,5,"VDD_CORE","N/A","N/A","N/A","SI","GP_Core_CTL","CAN_IO wrap AM62A","sam62a_feb_power","4 Infra","Buffering",8.7164256198347126E-2,"ON",1066,{"$f":"IF(ISBLANK(BD52),0,INDIRECT(BD52))","v":0},1,0,{"$f":"IFERROR(IF($I52=\"SI\",AP52*$C52*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ52*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK52*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL52*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM52*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN52*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO52*'Power Scaling'!F$4)*IF(P52=\"OFF\",0.06,1),VLOOKUP($A52&\"_\"&U$3,MDB,5,0)*$C52*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P52=\"OFF\",0.06,1)),0)","v":0},{"$f":"C52*IFERROR(IF($I52=\"SI\",(AE52*IF(S52=0,0,1)+(AF52-AE52)*S52)*IF(R52>0,R52,Q52)/Q52*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ52*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK52*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL52*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM52*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN52*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO52*'Power Scaling'!I$4)*AQ52,IF(OR($I52=\"AO\",$I52=\"LU\"),VLOOKUP($A52&\"_\"&\"vdd_dyn\"&\"_\"&$R52&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I52=\"LUUA\",$I52=\"LUUB\"),VLOOKUP($A52&\"_\"&\"vdd_dyn\"&\"_\"&$R52&\"\",MDB,5,0)*$C52*$S52*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A52&\"_\"&\"vdd_dyn\"&\"_\"&$R52&\"_idle\",MDB,5,0)*(1-$S52)+VLOOKUP($A52&\"_\"&\"vdd_dyn\"&\"_\"&$R52&\"_read\",MDB,5,0)*($S52/2)+VLOOKUP($A52&\"_\"&\"vdd_dyn\"&\"_\"&$R52&\"_write\",MDB,5,0)*($S52/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},8.7164256198347126E-2,0,0,0,0,0,0,0,0,0.4,0.48,0.1,0.3,0,0,0,0,1,0,0,0.1,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","sam62a_can_io_domain_0",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"LVCMOS IO","Mode","Utilization","Instances",null,null,null,null,null,"DMPAC",{"$f":"IF(R21=0,Q21,R21)","v":428},{"$f":"IF(C21>0,S21,0)","v":0}]
["sam67_main_infra_phys","_0",1,4,"VDD_CORE","N/A","N/A","N/A","SI","GP_Core_CTL","Main_infra AM67","sam62p_nov_power","4 Infra","Mix",11.680010330578515,"ON",250,{"$f":"SYSCLK/2","v":250},1,0,{"$f":"IFERROR(IF($I53=\"SI\",AP53*$C53*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ53*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK53*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL53*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM53*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN53*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO53*'Power Scaling'!F$4)*IF(P53=\"OFF\",0.06,1),VLOOKUP($A53&\"_\"&U$3,MDB,5,0)*$C53*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P53=\"OFF\",0.06,1)),0)","v":0},{"$f":"C53*IFERROR(IF($I53=\"SI\",(AE53*IF(S53=0,0,1)+(AF53-AE53)*S53)*IF(R53>0,R53,Q53)/Q53*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ53*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK53*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL53*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM53*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN53*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO53*'Power Scaling'!I$4)*AQ53,IF(OR($I53=\"AO\",$I53=\"LU\"),VLOOKUP($A53&\"_\"&\"vdd_dyn\"&\"_\"&$R53&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I53=\"LUUA\",$I53=\"LUUB\"),VLOOKUP($A53&\"_\"&\"vdd_dyn\"&\"_\"&$R53&\"\",MDB,5,0)*$C53*$S53*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A53&\"_\"&\"vdd_dyn\"&\"_\"&$R53&\"_idle\",MDB,5,0)*(1-$S53)+VLOOKUP($A53&\"_\"&\"vdd_dyn\"&\"_\"&$R53&\"_read\",MDB,5,0)*($S53/2)+VLOOKUP($A53&\"_\"&\"vdd_dyn\"&\"_\"&$R53&\"_write\",MDB,5,0)*($S53/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},11.680010330578515,0,0,0,0,0,0,0,0.219,0.4,0.48,33.299999999999997,40.200000000000003,0,0,0,0.18,0.77,0.05,3.0320276027206678,31.930382943575701,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","sam67_main_infra_phys_0",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"MAIN GPIO","1mbs_1p8v_20pf",1,30,null,null,null,null,null,"WAVE521CL Video Codec",{"$f":"IF(R23=0,Q23,R23)","v":100},{"$f":"IF(C23>0,S23,0)","v":1}]
["sam62p_main_ip_wrap","_0",1,6,"VDD_CORE","N/A","N/A","N/A","SI","PD_HSM","Main_IP AM62P_J7AEN","sam62p_march_c2end_power","4 Infra","Mix",66.714010847107446,"ON",290,{"$f":"SYSCLK*290/500","v":290},{"$f":"MAX(AVERAGE(S8:S11),S44)*0.4","v":0.4},0,{"$f":"IFERROR(IF($I54=\"SI\",AP54*$C54*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ54*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK54*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL54*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM54*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN54*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO54*'Power Scaling'!F$4)*IF(P54=\"OFF\",0.06,1),VLOOKUP($A54&\"_\"&U$3,MDB,5,0)*$C54*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P54=\"OFF\",0.06,1)),0)","v":0},{"$f":"C54*IFERROR(IF($I54=\"SI\",(AE54*IF(S54=0,0,1)+(AF54-AE54)*S54)*IF(R54>0,R54,Q54)/Q54*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ54*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK54*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL54*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM54*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN54*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO54*'Power Scaling'!I$4)*AQ54,IF(OR($I54=\"AO\",$I54=\"LU\"),VLOOKUP($A54&\"_\"&\"vdd_dyn\"&\"_\"&$R54&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I54=\"LUUA\",$I54=\"LUUB\"),VLOOKUP($A54&\"_\"&\"vdd_dyn\"&\"_\"&$R54&\"\",MDB,5,0)*$C54*$S54*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A54&\"_\"&\"vdd_dyn\"&\"_\"&$R54&\"_idle\",MDB,5,0)*(1-$S54)+VLOOKUP($A54&\"_\"&\"vdd_dyn\"&\"_\"&$R54&\"_read\",MDB,5,0)*($S54/2)+VLOOKUP($A54&\"_\"&\"vdd_dyn\"&\"_\"&$R54&\"_write\",MDB,5,0)*($S54/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},66.714010847107446,0,0,0,0,0,0,0,6.8000000000000005E-2,0.4,0.48,379.5,457.4,0,0,0.05,0.09,0.65,0.21,26.567763559041882,368.52060302555708,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","sam62p_main_ip_wrap_0",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"MAIN I2C","i2c_400k_3p3v",1,3.0000000000000004,null,null,null,null,null,"CSI_RX",{"$f":"IF(R29=0,Q29,R29)","v":720},{"$f":"IF(C29>0,S29,0)","v":0.1}]
["sam62p_main_rt_wrap","_0",1,1,"VDD_CORE","N/A","N/A","N/A","SI","PD_HSM","dmss csi + secondary main cbass","sam62p_pg10_weekly_20230328","4 Infra","Mix",17.170613507231408,"ON",290,{"$f":"SYSCLK*290/500","v":290},{"$f":"AVERAGE(S12,S24:S26,S29,S35,S42)*0.8","v":0.66971428571428571},0,{"$f":"IFERROR(IF($I55=\"SI\",AP55*$C55*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ55*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK55*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL55*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM55*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN55*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO55*'Power Scaling'!F$4)*IF(P55=\"OFF\",0.06,1),VLOOKUP($A55&\"_\"&U$3,MDB,5,0)*$C55*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P55=\"OFF\",0.06,1)),0)","v":0},{"$f":"C55*IFERROR(IF($I55=\"SI\",(AE55*IF(S55=0,0,1)+(AF55-AE55)*S55)*IF(R55>0,R55,Q55)/Q55*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ55*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK55*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL55*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM55*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN55*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO55*'Power Scaling'!I$4)*AQ55,IF(OR($I55=\"AO\",$I55=\"LU\"),VLOOKUP($A55&\"_\"&\"vdd_dyn\"&\"_\"&$R55&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I55=\"LUUA\",$I55=\"LUUB\"),VLOOKUP($A55&\"_\"&\"vdd_dyn\"&\"_\"&$R55&\"\",MDB,5,0)*$C55*$S55*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A55&\"_\"&\"vdd_dyn\"&\"_\"&$R55&\"_idle\",MDB,5,0)*(1-$S55)+VLOOKUP($A55&\"_\"&\"vdd_dyn\"&\"_\"&$R55&\"_read\",MDB,5,0)*($S55/2)+VLOOKUP($A55&\"_\"&\"vdd_dyn\"&\"_\"&$R55&\"_write\",MDB,5,0)*($S55/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},17.170613507231408,0,0,0,0,0,0,0,4.2999999999999997E-2,0.4,0.48,86.7,83.8,0,0,0.08,0.15,0.51,0.27,3.7795854828131006,81.750151754023065,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","sam62p_main_rt_wrap_0",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"MAIN UART","3p6m_1p8v",1,5,null,null,null,null,null,"CSI_RX",{"$f":"IF(R30=0,Q30,R30)","v":720},{"$f":"IF(C30>0,S30,0)","v":0}]
["sam67_mcu_infra_phys","_0",1,4,"VDD_CORE","N/A","N/A","N/A","SI","GP_Core_CTL_MCU","MCU_INFRA_WAKEUP AM62A","sam62p_march_c2end_power","4 Infra","Mix",4.0095557851239674,"ON",200,{"$f":"MCU_SYSCLK/2","v":200},1,0,{"$f":"IFERROR(IF($I56=\"SI\",AP56*$C56*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ56*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK56*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL56*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM56*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN56*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO56*'Power Scaling'!F$4)*IF(P56=\"OFF\",0.06,1),VLOOKUP($A56&\"_\"&U$3,MDB,5,0)*$C56*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P56=\"OFF\",0.06,1)),0)","v":0},{"$f":"C56*IFERROR(IF($I56=\"SI\",(AE56*IF(S56=0,0,1)+(AF56-AE56)*S56)*IF(R56>0,R56,Q56)/Q56*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ56*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK56*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL56*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM56*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN56*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO56*'Power Scaling'!I$4)*AQ56,IF(OR($I56=\"AO\",$I56=\"LU\"),VLOOKUP($A56&\"_\"&\"vdd_dyn\"&\"_\"&$R56&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I56=\"LUUA\",$I56=\"LUUB\"),VLOOKUP($A56&\"_\"&\"vdd_dyn\"&\"_\"&$R56&\"\",MDB,5,0)*$C56*$S56*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A56&\"_\"&\"vdd_dyn\"&\"_\"&$R56&\"_idle\",MDB,5,0)*(1-$S56)+VLOOKUP($A56&\"_\"&\"vdd_dyn\"&\"_\"&$R56&\"_read\",MDB,5,0)*($S56/2)+VLOOKUP($A56&\"_\"&\"vdd_dyn\"&\"_\"&$R56&\"_write\",MDB,5,0)*($S56/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},4.0095557851239674,0,0,0,0,0,0,0,0.20499999999999999,0.48,0.57999999999999996,9.1999999999999993,11.5,0,0,0,0.11,0.87,0.02,1.2047702879551585,8.9630261919889556,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","sam67_mcu_infra_phys_0",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"MAIN McSPI","Controller_3.125_Mbaud_3p3v",1,3,null,null,null,null,null,"CSI_RX",{"$f":"IF(R31=0,Q31,R31)","v":720},{"$f":"IF(C31>0,S31,0)","v":0}]
["sam67_mcu_wrap","_0",1,3,"VDD_CORE","N/A","N/A","N/A","SI","PD_Pulsar_MCU","MCUSS AM62A","sam62p_may_c3end_base_pg_power","4 Infra","Mix",23.081097923574056,"ON",266.66666670000001,{"$f":"MCU_WRAP/2*266.6667/400","v":266.66669999999999},{"$f":"S4","v":1},0,{"$f":"IFERROR(IF($I57=\"SI\",AP57*$C57*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ57*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK57*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL57*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM57*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN57*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO57*'Power Scaling'!F$4)*IF(P57=\"OFF\",0.06,1),VLOOKUP($A57&\"_\"&U$3,MDB,5,0)*$C57*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P57=\"OFF\",0.06,1)),0)","v":0},{"$f":"C57*IFERROR(IF($I57=\"SI\",(AE57*IF(S57=0,0,1)+(AF57-AE57)*S57)*IF(R57>0,R57,Q57)/Q57*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ57*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK57*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL57*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM57*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN57*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO57*'Power Scaling'!I$4)*AQ57,IF(OR($I57=\"AO\",$I57=\"LU\"),VLOOKUP($A57&\"_\"&\"vdd_dyn\"&\"_\"&$R57&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I57=\"LUUA\",$I57=\"LUUB\"),VLOOKUP($A57&\"_\"&\"vdd_dyn\"&\"_\"&$R57&\"\",MDB,5,0)*$C57*$S57*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A57&\"_\"&\"vdd_dyn\"&\"_\"&$R57&\"_idle\",MDB,5,0)*(1-$S57)+VLOOKUP($A57&\"_\"&\"vdd_dyn\"&\"_\"&$R57&\"_read\",MDB,5,0)*($S57/2)+VLOOKUP($A57&\"_\"&\"vdd_dyn\"&\"_\"&$R57&\"_write\",MDB,5,0)*($S57/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},23.081097923574056,0,0,0,0,0,0,0,0.126,0.48,0.57999999999999996,65.599999999999994,66.2,0,0,0.04,0.08,0.67,0.22,6.6481323035001001,63.401579399063976,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","sam67_mcu_wrap_0",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"MAIN McASP","16Ch_TX_48_ksps_24b_3p3v",1,3,null,null,null,null,null,"CSI_RX",{"$f":"IF(R32=0,Q32,R32)","v":720},{"$f":"IF(C32>0,S32,0)","v":0}]
["sam67_sec_wrap","_0",1,2,"VDD_CORE","N/A","N/A","N/A","SI","PD_HSM","HSM AM67","sam62p_may_c3end_base_pg_power","4 Infra","Security",30.722927024147729,"ON",400,{"$f":"SEC_WRAP","v":400},0.05,0,{"$f":"IFERROR(IF($I58=\"SI\",AP58*$C58*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ58*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK58*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL58*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM58*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN58*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO58*'Power Scaling'!F$4)*IF(P58=\"OFF\",0.06,1),VLOOKUP($A58&\"_\"&U$3,MDB,5,0)*$C58*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P58=\"OFF\",0.06,1)),0)","v":0},{"$f":"C58*IFERROR(IF($I58=\"SI\",(AE58*IF(S58=0,0,1)+(AF58-AE58)*S58)*IF(R58>0,R58,Q58)/Q58*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ58*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK58*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL58*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM58*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN58*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO58*'Power Scaling'!I$4)*AQ58,IF(OR($I58=\"AO\",$I58=\"LU\"),VLOOKUP($A58&\"_\"&\"vdd_dyn\"&\"_\"&$R58&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I58=\"LUUA\",$I58=\"LUUB\"),VLOOKUP($A58&\"_\"&\"vdd_dyn\"&\"_\"&$R58&\"\",MDB,5,0)*$C58*$S58*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A58&\"_\"&\"vdd_dyn\"&\"_\"&$R58&\"_idle\",MDB,5,0)*(1-$S58)+VLOOKUP($A58&\"_\"&\"vdd_dyn\"&\"_\"&$R58&\"_read\",MDB,5,0)*($S58/2)+VLOOKUP($A58&\"_\"&\"vdd_dyn\"&\"_\"&$R58&\"_write\",MDB,5,0)*($S58/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},30.722927024147729,0,0,0,0,0,0,0,0.11899999999999999,0.4,0.48,305.89999999999998,317.89999999999998,0.01,0,0.05,7.0000000000000007E-2,0.63,0.24,17.632757271455723,297.18321221652081,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","sam67_sec_wrap_0",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"MAIN ECAP","unused",1,0,null,null,null,null,null,"CSI_TX",{"$f":"IF(R33=0,Q33,R33)","v":720},{"$f":"IF(C33>0,S33,0)","v":0}]
["sam62p_core","_0",1,5,"VDD_CORE","N/A","N/A","N/A","SI","GP_Core_CTL","AM62P Top","28-Nov","4 Infra","Top",30.051620609504138,"ON",250,{"$f":"SYSCLK/2","v":250},0.4,0,{"$f":"IFERROR(IF($I59=\"SI\",AP59*$C59*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ59*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK59*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL59*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM59*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN59*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO59*'Power Scaling'!F$4)*IF(P59=\"OFF\",0.06,1),VLOOKUP($A59&\"_\"&U$3,MDB,5,0)*$C59*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P59=\"OFF\",0.06,1)),0)","v":0},{"$f":"C59*IFERROR(IF($I59=\"SI\",(AE59*IF(S59=0,0,1)+(AF59-AE59)*S59)*IF(R59>0,R59,Q59)/Q59*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ59*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK59*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL59*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM59*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN59*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO59*'Power Scaling'!I$4)*AQ59,IF(OR($I59=\"AO\",$I59=\"LU\"),VLOOKUP($A59&\"_\"&\"vdd_dyn\"&\"_\"&$R59&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I59=\"LUUA\",$I59=\"LUUB\"),VLOOKUP($A59&\"_\"&\"vdd_dyn\"&\"_\"&$R59&\"\",MDB,5,0)*$C59*$S59*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A59&\"_\"&\"vdd_dyn\"&\"_\"&$R59&\"_idle\",MDB,5,0)*(1-$S59)+VLOOKUP($A59&\"_\"&\"vdd_dyn\"&\"_\"&$R59&\"_read\",MDB,5,0)*($S59/2)+VLOOKUP($A59&\"_\"&\"vdd_dyn\"&\"_\"&$R59&\"_write\",MDB,5,0)*($S59/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},30.051620609504138,0,0,0,0,0,0,0,0.23300000000000001,0.4,0.48,138,138,1.2E-2,6.0000000000000001E-3,0.29199999999999998,0.34300000000000003,0.21299999999999999,0.13400000000000001,5.2781624088107097,118.71359838909569,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","sam62p_core_0",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"MAIN EPWM","on_1p8v",1,3.0000000000000004,null,null,null,null,null,"CPSW3x",{"$f":"IF(R22=0,Q22,R22)","v":250},{"$f":"IF(C22>0,S22,0)","v":1}]
["DIVTS16FFC1TO128A","_main",40,5,"VDD_CORE","N/A","N/A","N/A","LU","GP_Core_CTL","HSDIVIDER","10/30/2021","5 Analog","Clocking",0,"ON",0,400,1,0,{"$f":"IFERROR(IF($I60=\"SI\",AP60*$C60*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ60*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK60*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL60*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM60*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN60*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO60*'Power Scaling'!F$4)*IF(P60=\"OFF\",0.06,1),VLOOKUP($A60&\"_\"&U$3,MDB,5,0)*$C60*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P60=\"OFF\",0.06,1)),0)","v":0},{"$f":"C60*IFERROR(IF($I60=\"SI\",(AE60*IF(S60=0,0,1)+(AF60-AE60)*S60)*IF(R60>0,R60,Q60)/Q60*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ60*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK60*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL60*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM60*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN60*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO60*'Power Scaling'!I$4)*AQ60,IF(OR($I60=\"AO\",$I60=\"LU\"),VLOOKUP($A60&\"_\"&\"vdd_dyn\"&\"_\"&$R60&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I60=\"LUUA\",$I60=\"LUUB\"),VLOOKUP($A60&\"_\"&\"vdd_dyn\"&\"_\"&$R60&\"\",MDB,5,0)*$C60*$S60*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A60&\"_\"&\"vdd_dyn\"&\"_\"&$R60&\"_idle\",MDB,5,0)*(1-$S60)+VLOOKUP($A60&\"_\"&\"vdd_dyn\"&\"_\"&$R60&\"_read\",MDB,5,0)*($S60/2)+VLOOKUP($A60&\"_\"&\"vdd_dyn\"&\"_\"&$R60&\"_write\",MDB,5,0)*($S60/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","DIVTS16FFC1TO128A_main",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"MAIN EQEP","off",1,0,null,null,null,null,null,"PCIE_G3 4L",{"$f":"IF(R34=0,Q34,R34)","v":500},{"$f":"IF(C34>0,S34,0)","v":0}]
["DIVTS16FFC1TO128A","_wkup",8,5,"VDD_CORE","N/A","N/A","N/A","LU","GP_Core_CTL","HSDIVIDER","10/30/2021","5 Analog","Clocking",0,"ON",0,400,1,0,{"$f":"IFERROR(IF($I61=\"SI\",AP61*$C61*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ61*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK61*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL61*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM61*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN61*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO61*'Power Scaling'!F$4)*IF(P61=\"OFF\",0.06,1),VLOOKUP($A61&\"_\"&U$3,MDB,5,0)*$C61*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P61=\"OFF\",0.06,1)),0)","v":0},{"$f":"C61*IFERROR(IF($I61=\"SI\",(AE61*IF(S61=0,0,1)+(AF61-AE61)*S61)*IF(R61>0,R61,Q61)/Q61*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ61*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK61*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL61*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM61*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN61*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO61*'Power Scaling'!I$4)*AQ61,IF(OR($I61=\"AO\",$I61=\"LU\"),VLOOKUP($A61&\"_\"&\"vdd_dyn\"&\"_\"&$R61&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I61=\"LUUA\",$I61=\"LUUB\"),VLOOKUP($A61&\"_\"&\"vdd_dyn\"&\"_\"&$R61&\"\",MDB,5,0)*$C61*$S61*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A61&\"_\"&\"vdd_dyn\"&\"_\"&$R61&\"_idle\",MDB,5,0)*(1-$S61)+VLOOKUP($A61&\"_\"&\"vdd_dyn\"&\"_\"&$R61&\"_read\",MDB,5,0)*($S61/2)+VLOOKUP($A61&\"_\"&\"vdd_dyn\"&\"_\"&$R61&\"_write\",MDB,5,0)*($S61/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","DIVTS16FFC1TO128A_wkup",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"MAIN MCAN","1mbs_3p3v",1,1,null,null,null,null,null,"USB2 Controller",{"$f":"IF(R35=0,Q35,R35)","v":125},{"$f":"IF(C35>0,S35,0)","v":1}]
["PLLTS16FFCLAFRACF","_ARM0_PLL",1,5,"VDD_CORE","N/A","VDDA_PLL4","N/A","LU","GP_Core_CTL","ADPLL - FRACF","10/30/2021","5 Analog","Clocking",11.208655869999999,"ON",0,3000,1,0,{"$f":"IFERROR(IF($I62=\"SI\",AP62*$C62*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ62*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK62*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL62*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM62*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN62*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO62*'Power Scaling'!F$4)*IF(P62=\"OFF\",0.06,1),VLOOKUP($A62&\"_\"&U$3,MDB,5,0)*$C62*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P62=\"OFF\",0.06,1)),0)","v":0},{"$f":"C62*IFERROR(IF($I62=\"SI\",(AE62*IF(S62=0,0,1)+(AF62-AE62)*S62)*IF(R62>0,R62,Q62)/Q62*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ62*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK62*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL62*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM62*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN62*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO62*'Power Scaling'!I$4)*AQ62,IF(OR($I62=\"AO\",$I62=\"LU\"),VLOOKUP($A62&\"_\"&\"vdd_dyn\"&\"_\"&$R62&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I62=\"LUUA\",$I62=\"LUUB\"),VLOOKUP($A62&\"_\"&\"vdd_dyn\"&\"_\"&$R62&\"\",MDB,5,0)*$C62*$S62*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A62&\"_\"&\"vdd_dyn\"&\"_\"&$R62&\"_idle\",MDB,5,0)*(1-$S62)+VLOOKUP($A62&\"_\"&\"vdd_dyn\"&\"_\"&$R62&\"_read\",MDB,5,0)*($S62/2)+VLOOKUP($A62&\"_\"&\"vdd_dyn\"&\"_\"&$R62&\"_write\",MDB,5,0)*($S62/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,11.208655869999999,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","PLLTS16FFCLAFRACF_ARM0_PLL",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"MAIN MMCSD1","hs200_200mbs",1,3,null,null,null,null,null,"USB3P0TCx1",{"$f":"IF(R36=0,Q36,R36)","v":125},{"$f":"IF(C36>0,S36,0)","v":0}]
[{"$error":"#N/A"},{"$error":"#N/A"},0,{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},0,{"$error":"#N/A"},0,2000,1,0,{"$f":"IFERROR(IF($I63=\"SI\",AP63*$C63*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ63*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK63*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL63*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM63*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN63*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO63*'Power Scaling'!F$4)*IF(P63=\"OFF\",0.06,1),VLOOKUP($A63&\"_\"&U$3,MDB,5,0)*$C63*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P63=\"OFF\",0.06,1)),0)","v":0},{"$f":"C63*IFERROR(IF($I63=\"SI\",(AE63*IF(S63=0,0,1)+(AF63-AE63)*S63)*IF(R63>0,R63,Q63)/Q63*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ63*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK63*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL63*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM63*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN63*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO63*'Power Scaling'!I$4)*AQ63,IF(OR($I63=\"AO\",$I63=\"LU\"),VLOOKUP($A63&\"_\"&\"vdd_dyn\"&\"_\"&$R63&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I63=\"LUUA\",$I63=\"LUUB\"),VLOOKUP($A63&\"_\"&\"vdd_dyn\"&\"_\"&$R63&\"\",MDB,5,0)*$C63*$S63*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A63&\"_\"&\"vdd_dyn\"&\"_\"&$R63&\"_idle\",MDB,5,0)*(1-$S63)+VLOOKUP($A63&\"_\"&\"vdd_dyn\"&\"_\"&$R63&\"_read\",MDB,5,0)*($S63/2)+VLOOKUP($A63&\"_\"&\"vdd_dyn\"&\"_\"&$R63&\"_write\",MDB,5,0)*($S63/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,{"$error":"#N/A"},{"$error":"#N/A"},"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.",{"$error":"#N/A"},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"MAIN DSS 0: DPI","HD_|_1280x720x60_fps_24b_|_3p3V",1,1,null,null,null,null,null,"LP/DDR4-32 PHY 3733",{"$f":"IF(R39=0,Q39,R39)","v":533.25},{"$f":"IF(C39>0,S39,0)","v":1.1000000000000001}]
["PLLTS16FFCLAFRACF","_DSS0_PLL",1,5,"VDD_CORE","N/A","VDDA_PLL1","N/A","LU","GP_Core_CTL","ADPLL - FRACF","10/30/2021","5 Analog","Clocking",8.5267134119999994,"ON",0,2500,1,0,{"$f":"IFERROR(IF($I64=\"SI\",AP64*$C64*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ64*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK64*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL64*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM64*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN64*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO64*'Power Scaling'!F$4)*IF(P64=\"OFF\",0.06,1),VLOOKUP($A64&\"_\"&U$3,MDB,5,0)*$C64*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P64=\"OFF\",0.06,1)),0)","v":0},{"$f":"C64*IFERROR(IF($I64=\"SI\",(AE64*IF(S64=0,0,1)+(AF64-AE64)*S64)*IF(R64>0,R64,Q64)/Q64*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ64*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK64*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL64*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM64*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN64*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO64*'Power Scaling'!I$4)*AQ64,IF(OR($I64=\"AO\",$I64=\"LU\"),VLOOKUP($A64&\"_\"&\"vdd_dyn\"&\"_\"&$R64&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I64=\"LUUA\",$I64=\"LUUB\"),VLOOKUP($A64&\"_\"&\"vdd_dyn\"&\"_\"&$R64&\"\",MDB,5,0)*$C64*$S64*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A64&\"_\"&\"vdd_dyn\"&\"_\"&$R64&\"_idle\",MDB,5,0)*(1-$S64)+VLOOKUP($A64&\"_\"&\"vdd_dyn\"&\"_\"&$R64&\"_read\",MDB,5,0)*($S64/2)+VLOOKUP($A64&\"_\"&\"vdd_dyn\"&\"_\"&$R64&\"_write\",MDB,5,0)*($S64/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,8.5267134119999994,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","PLLTS16FFCLAFRACF_DSS0_PLL",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"MAIN FSS OSPI1 (QSPI)","ospi_ddr_controller_133_3p3v",1,1,null,null,null,null,null,"EMMC 4",{"$f":"IF(R40=0,Q40,R40)","v":250},{"$f":"IF(C40>0,S40,0)","v":1}]
["PLLTS16FFCLAFRACF","_DSS1_PLL",1,5,"VDD_CORE","N/A","VDDA_PLL1","N/A","LU","GP_Core_CTL","ADPLL - FRACF","10/30/2021","5 Analog","Clocking",8.5267134119999994,"ON",0,2500,1,0,{"$f":"IFERROR(IF($I65=\"SI\",AP65*$C65*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ65*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK65*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL65*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM65*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN65*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO65*'Power Scaling'!F$4)*IF(P65=\"OFF\",0.06,1),VLOOKUP($A65&\"_\"&U$3,MDB,5,0)*$C65*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P65=\"OFF\",0.06,1)),0)","v":0},{"$f":"C65*IFERROR(IF($I65=\"SI\",(AE65*IF(S65=0,0,1)+(AF65-AE65)*S65)*IF(R65>0,R65,Q65)/Q65*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ65*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK65*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL65*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM65*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN65*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO65*'Power Scaling'!I$4)*AQ65,IF(OR($I65=\"AO\",$I65=\"LU\"),VLOOKUP($A65&\"_\"&\"vdd_dyn\"&\"_\"&$R65&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I65=\"LUUA\",$I65=\"LUUB\"),VLOOKUP($A65&\"_\"&\"vdd_dyn\"&\"_\"&$R65&\"\",MDB,5,0)*$C65*$S65*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A65&\"_\"&\"vdd_dyn\"&\"_\"&$R65&\"_idle\",MDB,5,0)*(1-$S65)+VLOOKUP($A65&\"_\"&\"vdd_dyn\"&\"_\"&$R65&\"_read\",MDB,5,0)*($S65/2)+VLOOKUP($A65&\"_\"&\"vdd_dyn\"&\"_\"&$R65&\"_write\",MDB,5,0)*($S65/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,8.5267134119999994,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","PLLTS16FFCLAFRACF_DSS1_PLL",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"MAIN Ethernet","rgmii_1000_1p8v",1,2,null,null,null,null,null,"EMMC 4",{"$f":"IF(R41=0,Q41,R41)","v":250},{"$f":"IF(C41>0,S41,0)","v":1}]
["PLLTS16FFCLAFRACF","_GPU_PLL",1,5,"VDD_CORE","N/A","VDDA_PLL2","N/A","LU","GP_Core_CTL","ADPLL - FRACF","10/30/2021","5 Analog","Clocking",7.2802355409999997,"ON",0,2250,1,0,{"$f":"IFERROR(IF($I66=\"SI\",AP66*$C66*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ66*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK66*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL66*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM66*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN66*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO66*'Power Scaling'!F$4)*IF(P66=\"OFF\",0.06,1),VLOOKUP($A66&\"_\"&U$3,MDB,5,0)*$C66*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P66=\"OFF\",0.06,1)),0)","v":0},{"$f":"C66*IFERROR(IF($I66=\"SI\",(AE66*IF(S66=0,0,1)+(AF66-AE66)*S66)*IF(R66>0,R66,Q66)/Q66*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ66*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK66*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL66*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM66*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN66*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO66*'Power Scaling'!I$4)*AQ66,IF(OR($I66=\"AO\",$I66=\"LU\"),VLOOKUP($A66&\"_\"&\"vdd_dyn\"&\"_\"&$R66&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I66=\"LUUA\",$I66=\"LUUB\"),VLOOKUP($A66&\"_\"&\"vdd_dyn\"&\"_\"&$R66&\"\",MDB,5,0)*$C66*$S66*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A66&\"_\"&\"vdd_dyn\"&\"_\"&$R66&\"_idle\",MDB,5,0)*(1-$S66)+VLOOKUP($A66&\"_\"&\"vdd_dyn\"&\"_\"&$R66&\"_read\",MDB,5,0)*($S66/2)+VLOOKUP($A66&\"_\"&\"vdd_dyn\"&\"_\"&$R66&\"_write\",MDB,5,0)*($S66/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,7.2802355409999997,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","PLLTS16FFCLAFRACF_GPU_PLL",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"EMMC 8",{"$f":"IF(R42=0,Q42,R42)","v":250},{"$f":"IF(C42>0,S42,0)","v":1}]
["PLLTS16FFCLAFRACF","_Main",1,5,"VDD_CORE","N/A","VDDA_PLL0","N/A","LU","GP_Core_CTL","ADPLL - FRACF","10/30/2021","5 Analog","Clocking",6.1012194610000003,"ON",0,2000,1,0,{"$f":"IFERROR(IF($I67=\"SI\",AP67*$C67*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ67*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK67*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL67*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM67*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN67*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO67*'Power Scaling'!F$4)*IF(P67=\"OFF\",0.06,1),VLOOKUP($A67&\"_\"&U$3,MDB,5,0)*$C67*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P67=\"OFF\",0.06,1)),0)","v":0},{"$f":"C67*IFERROR(IF($I67=\"SI\",(AE67*IF(S67=0,0,1)+(AF67-AE67)*S67)*IF(R67>0,R67,Q67)/Q67*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ67*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK67*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL67*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM67*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN67*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO67*'Power Scaling'!I$4)*AQ67,IF(OR($I67=\"AO\",$I67=\"LU\"),VLOOKUP($A67&\"_\"&\"vdd_dyn\"&\"_\"&$R67&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I67=\"LUUA\",$I67=\"LUUB\"),VLOOKUP($A67&\"_\"&\"vdd_dyn\"&\"_\"&$R67&\"\",MDB,5,0)*$C67*$S67*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A67&\"_\"&\"vdd_dyn\"&\"_\"&$R67&\"_idle\",MDB,5,0)*(1-$S67)+VLOOKUP($A67&\"_\"&\"vdd_dyn\"&\"_\"&$R67&\"_read\",MDB,5,0)*($S67/2)+VLOOKUP($A67&\"_\"&\"vdd_dyn\"&\"_\"&$R67&\"_write\",MDB,5,0)*($S67/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,6.1012194610000003,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","PLLTS16FFCLAFRACF_Main",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"GPMC_ELM",{"$f":"IF(R43=0,Q43,R43)","v":166.66666670000001},{"$f":"IF(C43>0,S43,0)","v":0}]
["PLLTS16FFCLAFRACF","_SMS",1,5,"VDD_CORE","N/A","VDDA_PLL4","N/A","LU","GP_Core_CTL","ADPLL - FRACF","10/30/2021","5 Analog","Clocking",{"$f":"SUM(U68:AD68)","v":8.5267134119999994},{"$f":"INDEX(PD_State_Table,MATCH(J68,PD_Table_Row_Header,0),2)","v":"ON"},0,2500,1,0,{"$f":"IFERROR(IF($I68=\"SI\",AP68*$C68*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ68*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK68*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL68*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM68*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN68*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO68*'Power Scaling'!F$4)*IF(P68=\"OFF\",0.06,1),VLOOKUP($A68&\"_\"&U$3,MDB,5,0)*$C68*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P68=\"OFF\",0.06,1)),0)","v":0},{"$f":"C68*IFERROR(IF($I68=\"SI\",(AE68*IF(S68=0,0,1)+(AF68-AE68)*S68)*IF(R68>0,R68,Q68)/Q68*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ68*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK68*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL68*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM68*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN68*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO68*'Power Scaling'!I$4)*AQ68,IF(OR($I68=\"AO\",$I68=\"LU\"),VLOOKUP($A68&\"_\"&\"vdd_dyn\"&\"_\"&$R68&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I68=\"LUUA\",$I68=\"LUUB\"),VLOOKUP($A68&\"_\"&\"vdd_dyn\"&\"_\"&$R68&\"\",MDB,5,0)*$C68*$S68*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A68&\"_\"&\"vdd_dyn\"&\"_\"&$R68&\"_idle\",MDB,5,0)*(1-$S68)+VLOOKUP($A68&\"_\"&\"vdd_dyn\"&\"_\"&$R68&\"_read\",MDB,5,0)*($S68/2)+VLOOKUP($A68&\"_\"&\"vdd_dyn\"&\"_\"&$R68&\"_write\",MDB,5,0)*($S68/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},{"$f":"C68*IFERROR(IF($I68=\"SI\",(AE68*IF(S68=0,0,1)+(AF68-AE68)*S68)*(IF(R68>0,R68,Q68)/Q68)*VLOOKUP(\"vdd_sw\",pwr_scale_table,2,0)*AI68,0),0)","v":0},{"$f":"IFERROR(VLOOKUP($A68&\"_\"&X$3,MDB,5,0)*$C68*VLOOKUP(\"vddr_lkg\",pwr_scale_table,2,0)*IF(P68=\"OFF\",0.06,1),0)","v":0},{"$f":"IFERROR(VLOOKUP($A68&\"_\"&Y$3,MDB,5,0)*$C68*(VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*0.5+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*0.5),0)","v":0},{"$f":"IFERROR(IF(I68=\"LUUB\",VLOOKUP($A68&\"_\"&Z$3&\"_\"&$R68&\"\",MDB,5,0)*$C68*$S68*((VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)/4+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)/4+VLOOKUP(\"vdd_sw\",pwr_scale_table,2,0)/2)),VLOOKUP($A68&\"_\"&Z$3&\"_\"&$R68&\"\",MDB,5,0)*$C68*((VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)/4+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)/4+VLOOKUP(\"vdd_sw\",pwr_scale_table,2,0)/2))),0)","v":0},{"$f":"IFERROR(VLOOKUP($A68&\"_\"&AA$3,MDB,5,0)*$C68*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0),0)","v":0},{"$f":"IFERROR(IF(OR($I68=\"LUUA\",$I68=\"LUUB\"),VLOOKUP($A68&\"_\"&AB$3&\"_\"&$R68&\"\",MDB,5,0)*$C68*$S68,IF(I68=\"LUUD\",VLOOKUP($A68&\"_\"&AB$3&\"_\"&$R68&\"_idle\",MDB,5,0)*(1-$S68)+VLOOKUP($A68&\"_\"&AB$3&\"_\"&$R68&\"_read\",MDB,5,0)*($S68/2)+VLOOKUP($A68&\"_\"&AB$3&\"_\"&$R68&\"_write\",MDB,5,0)*($S68/2),VLOOKUP($A68&\"_\"&AB$3&\"_\"&$R68&\"\",MDB,5,0)*$C68)),0)","v":8.5267134119999994},{"$f":"IFERROR(VLOOKUP($A68&\"_\"&AC$3,MDB,5,0)*$C68*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0),0)","v":0},{"$f":"IFERROR(IF(OR($I68=\"LUUA\",$I68=\"LUUB\"),VLOOKUP($A68&\"_\"&AD$3&\"_\"&$R68&\"\",MDB,5,0)*$C68*$S68,IF(I68=\"LUUD\",VLOOKUP($A68&\"_\"&AD$3&\"_\"&$R68&\"_idle\",MDB,5,0)*(1-$S68)+VLOOKUP($A68&\"_\"&AD$3&\"_\"&$R68&\"_read\",MDB,5,0)*($S68/2)+VLOOKUP($A68&\"_\"&AD$3&\"_\"&$R68&\"_write\",MDB,5,0)*($S68/2),VLOOKUP($A68&\"_\"&AD$3&\"_\"&$R68&\"\",MDB,5,0)*$C68)),0)","v":0},0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.",{"$f":"A68&B68","v":"PLLTS16FFCLAFRACF_SMS"}]
["PLLTS16FFCLAFRACF","_Per0",1,5,"VDD_CORE","N/A","VDDA_PLL0","N/A","LU","GP_Core_CTL","ADPLL - FRACF","10/30/2021","5 Analog","Clocking",6.1012194610000003,"ON",0,2000,1,0,{"$f":"IFERROR(IF($I69=\"SI\",AP69*$C69*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ69*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK69*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL69*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM69*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN69*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO69*'Power Scaling'!F$4)*IF(P69=\"OFF\",0.06,1),VLOOKUP($A69&\"_\"&U$3,MDB,5,0)*$C69*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P69=\"OFF\",0.06,1)),0)","v":0},{"$f":"C69*IFERROR(IF($I69=\"SI\",(AE69*IF(S69=0,0,1)+(AF69-AE69)*S69)*IF(R69>0,R69,Q69)/Q69*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ69*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK69*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL69*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM69*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN69*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO69*'Power Scaling'!I$4)*AQ69,IF(OR($I69=\"AO\",$I69=\"LU\"),VLOOKUP($A69&\"_\"&\"vdd_dyn\"&\"_\"&$R69&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I69=\"LUUA\",$I69=\"LUUB\"),VLOOKUP($A69&\"_\"&\"vdd_dyn\"&\"_\"&$R69&\"\",MDB,5,0)*$C69*$S69*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A69&\"_\"&\"vdd_dyn\"&\"_\"&$R69&\"_idle\",MDB,5,0)*(1-$S69)+VLOOKUP($A69&\"_\"&\"vdd_dyn\"&\"_\"&$R69&\"_read\",MDB,5,0)*($S69/2)+VLOOKUP($A69&\"_\"&\"vdd_dyn\"&\"_\"&$R69&\"_write\",MDB,5,0)*($S69/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,6.1012194610000003,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","PLLTS16FFCLAFRACF_Per0",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"SerDes 10G Common",{"$f":"IF(C91>0,R91,\"disable\")","v":"disable"},{"$f":"IF(C91>0,S91,0)","v":0}]
["PLLTS16FFCLAFRACF","_Per1",1,5,"VDD_CORE","N/A","VDDA_PLL0","N/A","LU","GP_Core_CTL","ADPLL - FRACF","10/30/2021","5 Analog","Clocking",6.1012194610000003,"ON",0,2000,1,0,{"$f":"IFERROR(IF($I70=\"SI\",AP70*$C70*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ70*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK70*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL70*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM70*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN70*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO70*'Power Scaling'!F$4)*IF(P70=\"OFF\",0.06,1),VLOOKUP($A70&\"_\"&U$3,MDB,5,0)*$C70*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P70=\"OFF\",0.06,1)),0)","v":0},{"$f":"C70*IFERROR(IF($I70=\"SI\",(AE70*IF(S70=0,0,1)+(AF70-AE70)*S70)*IF(R70>0,R70,Q70)/Q70*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ70*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK70*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL70*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM70*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN70*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO70*'Power Scaling'!I$4)*AQ70,IF(OR($I70=\"AO\",$I70=\"LU\"),VLOOKUP($A70&\"_\"&\"vdd_dyn\"&\"_\"&$R70&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I70=\"LUUA\",$I70=\"LUUB\"),VLOOKUP($A70&\"_\"&\"vdd_dyn\"&\"_\"&$R70&\"\",MDB,5,0)*$C70*$S70*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A70&\"_\"&\"vdd_dyn\"&\"_\"&$R70&\"_idle\",MDB,5,0)*(1-$S70)+VLOOKUP($A70&\"_\"&\"vdd_dyn\"&\"_\"&$R70&\"_read\",MDB,5,0)*($S70/2)+VLOOKUP($A70&\"_\"&\"vdd_dyn\"&\"_\"&$R70&\"_write\",MDB,5,0)*($S70/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,6.1012194610000003,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","PLLTS16FFCLAFRACF_Per1",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"SerDes 10G Lane",{"$f":"IF(C93>0,R93,\"unused\")","v":"unused"},{"$f":"IF(C93>0,S93,0)","v":0}]
["PLLTS16FFCLAFRACF","_DSS2_PLL",1,5,"VDD_CORE","N/A","VDDA_PLL1","N/A","LU","GP_Core_CTL","ADPLL - FRACF","10/30/2021","5 Analog","Clocking",11.208655869999999,"ON",0,3000,1,0,{"$f":"IFERROR(IF($I71=\"SI\",AP71*$C71*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ71*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK71*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL71*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM71*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN71*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO71*'Power Scaling'!F$4)*IF(P71=\"OFF\",0.06,1),VLOOKUP($A71&\"_\"&U$3,MDB,5,0)*$C71*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P71=\"OFF\",0.06,1)),0)","v":0},{"$f":"C71*IFERROR(IF($I71=\"SI\",(AE71*IF(S71=0,0,1)+(AF71-AE71)*S71)*IF(R71>0,R71,Q71)/Q71*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ71*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK71*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL71*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM71*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN71*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO71*'Power Scaling'!I$4)*AQ71,IF(OR($I71=\"AO\",$I71=\"LU\"),VLOOKUP($A71&\"_\"&\"vdd_dyn\"&\"_\"&$R71&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I71=\"LUUA\",$I71=\"LUUB\"),VLOOKUP($A71&\"_\"&\"vdd_dyn\"&\"_\"&$R71&\"\",MDB,5,0)*$C71*$S71*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A71&\"_\"&\"vdd_dyn\"&\"_\"&$R71&\"_idle\",MDB,5,0)*(1-$S71)+VLOOKUP($A71&\"_\"&\"vdd_dyn\"&\"_\"&$R71&\"_read\",MDB,5,0)*($S71/2)+VLOOKUP($A71&\"_\"&\"vdd_dyn\"&\"_\"&$R71&\"_write\",MDB,5,0)*($S71/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,11.208655869999999,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","PLLTS16FFCLAFRACF_DSS2_PLL",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"SerDes 10G Common",{"$f":"IF(C92>0,R92,\"disabled\")","v":"disabled"},{"$f":"IF(C92>0,S92,0)","v":0}]
[{"$error":"#N/A"},{"$error":"#N/A"},0,{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},0,{"$error":"#N/A"},0,2250,1,0,{"$f":"IFERROR(IF($I72=\"SI\",AP72*$C72*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ72*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK72*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL72*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM72*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN72*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO72*'Power Scaling'!F$4)*IF(P72=\"OFF\",0.06,1),VLOOKUP($A72&\"_\"&U$3,MDB,5,0)*$C72*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P72=\"OFF\",0.06,1)),0)","v":0},{"$f":"C72*IFERROR(IF($I72=\"SI\",(AE72*IF(S72=0,0,1)+(AF72-AE72)*S72)*IF(R72>0,R72,Q72)/Q72*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ72*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK72*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL72*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM72*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN72*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO72*'Power Scaling'!I$4)*AQ72,IF(OR($I72=\"AO\",$I72=\"LU\"),VLOOKUP($A72&\"_\"&\"vdd_dyn\"&\"_\"&$R72&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I72=\"LUUA\",$I72=\"LUUB\"),VLOOKUP($A72&\"_\"&\"vdd_dyn\"&\"_\"&$R72&\"\",MDB,5,0)*$C72*$S72*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A72&\"_\"&\"vdd_dyn\"&\"_\"&$R72&\"_idle\",MDB,5,0)*(1-$S72)+VLOOKUP($A72&\"_\"&\"vdd_dyn\"&\"_\"&$R72&\"_read\",MDB,5,0)*($S72/2)+VLOOKUP($A72&\"_\"&\"vdd_dyn\"&\"_\"&$R72&\"_write\",MDB,5,0)*($S72/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,{"$error":"#N/A"},{"$error":"#N/A"},"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.",{"$error":"#N/A"},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"SerDes 10G Lane",{"$f":"IF(C94>0,R94,\"unused\")","v":"unused"},{"$f":"IF(C94>0,S94,0)","v":0}]
["PLLTS16FFCLAFRACF","DDR_PHY",1,5,"VDD_CORE","N/A","VDDA_PLL3","N/A","LU","GP_Core_CTL","ADPLL - FRACF","10/30/2021","5 Analog","Clocking",6.1012194610000003,"ON",0,2000,1,0,{"$f":"IFERROR(IF($I73=\"SI\",AP73*$C73*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ73*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK73*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL73*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM73*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN73*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO73*'Power Scaling'!F$4)*IF(P73=\"OFF\",0.06,1),VLOOKUP($A73&\"_\"&U$3,MDB,5,0)*$C73*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P73=\"OFF\",0.06,1)),0)","v":0},{"$f":"C73*IFERROR(IF($I73=\"SI\",(AE73*IF(S73=0,0,1)+(AF73-AE73)*S73)*IF(R73>0,R73,Q73)/Q73*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ73*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK73*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL73*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM73*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN73*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO73*'Power Scaling'!I$4)*AQ73,IF(OR($I73=\"AO\",$I73=\"LU\"),VLOOKUP($A73&\"_\"&\"vdd_dyn\"&\"_\"&$R73&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I73=\"LUUA\",$I73=\"LUUB\"),VLOOKUP($A73&\"_\"&\"vdd_dyn\"&\"_\"&$R73&\"\",MDB,5,0)*$C73*$S73*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A73&\"_\"&\"vdd_dyn\"&\"_\"&$R73&\"_idle\",MDB,5,0)*(1-$S73)+VLOOKUP($A73&\"_\"&\"vdd_dyn\"&\"_\"&$R73&\"_read\",MDB,5,0)*($S73/2)+VLOOKUP($A73&\"_\"&\"vdd_dyn\"&\"_\"&$R73&\"_write\",MDB,5,0)*($S73/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,6.1012194610000003,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","PLLTS16FFCLAFRACFDDR_PHY"]
["PLLTS16FFCLAFRACF","_MCU_PERIPHERIAL",1,5,"VDD_CORE","N/A","VDDA_MCU","N/A","LU","GP_Core_CTL","ADPLL - FRACF","10/30/2021","5 Analog","Clocking",8.5267134119999994,"ON",0,2500,1,0,{"$f":"IFERROR(IF($I74=\"SI\",AP74*$C74*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ74*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK74*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL74*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM74*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN74*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO74*'Power Scaling'!F$4)*IF(P74=\"OFF\",0.06,1),VLOOKUP($A74&\"_\"&U$3,MDB,5,0)*$C74*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P74=\"OFF\",0.06,1)),0)","v":0},{"$f":"C74*IFERROR(IF($I74=\"SI\",(AE74*IF(S74=0,0,1)+(AF74-AE74)*S74)*IF(R74>0,R74,Q74)/Q74*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ74*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK74*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL74*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM74*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN74*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO74*'Power Scaling'!I$4)*AQ74,IF(OR($I74=\"AO\",$I74=\"LU\"),VLOOKUP($A74&\"_\"&\"vdd_dyn\"&\"_\"&$R74&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I74=\"LUUA\",$I74=\"LUUB\"),VLOOKUP($A74&\"_\"&\"vdd_dyn\"&\"_\"&$R74&\"\",MDB,5,0)*$C74*$S74*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A74&\"_\"&\"vdd_dyn\"&\"_\"&$R74&\"_idle\",MDB,5,0)*(1-$S74)+VLOOKUP($A74&\"_\"&\"vdd_dyn\"&\"_\"&$R74&\"_read\",MDB,5,0)*($S74/2)+VLOOKUP($A74&\"_\"&\"vdd_dyn\"&\"_\"&$R74&\"_write\",MDB,5,0)*($S74/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,8.5267134119999994,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","PLLTS16FFCLAFRACF_MCU_PERIPHERIAL"]
["TEF16FCLL256X32HD18_PHRM","_main",2,5,"VDD_CORE","N/A","N/A","VPP","LU","GP_Core_CTL","eFuse","10/30/2021","5 Analog","eFuse",0,"ON",0,"on",1,0,{"$f":"IFERROR(IF($I75=\"SI\",AP75*$C75*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ75*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK75*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL75*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM75*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN75*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO75*'Power Scaling'!F$4)*IF(P75=\"OFF\",0.06,1),VLOOKUP($A75&\"_\"&U$3,MDB,5,0)*$C75*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P75=\"OFF\",0.06,1)),0)","v":0},{"$f":"C75*IFERROR(IF($I75=\"SI\",(AE75*IF(S75=0,0,1)+(AF75-AE75)*S75)*IF(R75>0,R75,Q75)/Q75*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ75*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK75*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL75*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM75*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN75*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO75*'Power Scaling'!I$4)*AQ75,IF(OR($I75=\"AO\",$I75=\"LU\"),VLOOKUP($A75&\"_\"&\"vdd_dyn\"&\"_\"&$R75&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I75=\"LUUA\",$I75=\"LUUB\"),VLOOKUP($A75&\"_\"&\"vdd_dyn\"&\"_\"&$R75&\"\",MDB,5,0)*$C75*$S75*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A75&\"_\"&\"vdd_dyn\"&\"_\"&$R75&\"_idle\",MDB,5,0)*(1-$S75)+VLOOKUP($A75&\"_\"&\"vdd_dyn\"&\"_\"&$R75&\"_read\",MDB,5,0)*($S75/2)+VLOOKUP($A75&\"_\"&\"vdd_dyn\"&\"_\"&$R75&\"_write\",MDB,5,0)*($S75/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},{"$f":"C75*IFERROR(IF($I75=\"SI\",(AE75*IF(S75=0,0,1)+(AF75-AE75)*S75)*VLOOKUP(\"vdd_sw\",pwr_scale_table,2,0)*AI75,0),0)","v":0},0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","TEF16FCLL256X32HD18_PHRM_main"]
["N16FFC_POK","_PMIC_IN_OV",1,5,"VDD_CORE","N/A","VDDA_MCU","N/A","LU","GP_Core_CTL","POK","10/30/2021","5 Analog","Power",0.02,"ON",0,"on",1,0,{"$f":"IFERROR(IF($I76=\"SI\",AP76*$C76*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ76*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK76*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL76*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM76*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN76*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO76*'Power Scaling'!F$4)*IF(P76=\"OFF\",0.06,1),VLOOKUP($A76&\"_\"&U$3,MDB,5,0)*$C76*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P76=\"OFF\",0.06,1)),0)","v":0},{"$f":"C76*IFERROR(IF($I76=\"SI\",(AE76*IF(S76=0,0,1)+(AF76-AE76)*S76)*IF(R76>0,R76,Q76)/Q76*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ76*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK76*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL76*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM76*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN76*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO76*'Power Scaling'!I$4)*AQ76,IF(OR($I76=\"AO\",$I76=\"LU\"),VLOOKUP($A76&\"_\"&\"vdd_dyn\"&\"_\"&$R76&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I76=\"LUUA\",$I76=\"LUUB\"),VLOOKUP($A76&\"_\"&\"vdd_dyn\"&\"_\"&$R76&\"\",MDB,5,0)*$C76*$S76*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A76&\"_\"&\"vdd_dyn\"&\"_\"&$R76&\"_idle\",MDB,5,0)*(1-$S76)+VLOOKUP($A76&\"_\"&\"vdd_dyn\"&\"_\"&$R76&\"_read\",MDB,5,0)*($S76/2)+VLOOKUP($A76&\"_\"&\"vdd_dyn\"&\"_\"&$R76&\"_write\",MDB,5,0)*($S76/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0.02,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","N16FFC_POK_PMIC_IN_OV"]
["N16FFC_POK","_VDD_CORE_OV",1,5,"VDD_CORE","N/A","VDDA_MCU","N/A","LU","GP_Core_CTL","POK","10/30/2021","5 Analog","Power",0.02,"ON",0,"on",1,0,{"$f":"IFERROR(IF($I77=\"SI\",AP77*$C77*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ77*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK77*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL77*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM77*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN77*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO77*'Power Scaling'!F$4)*IF(P77=\"OFF\",0.06,1),VLOOKUP($A77&\"_\"&U$3,MDB,5,0)*$C77*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P77=\"OFF\",0.06,1)),0)","v":0},{"$f":"C77*IFERROR(IF($I77=\"SI\",(AE77*IF(S77=0,0,1)+(AF77-AE77)*S77)*IF(R77>0,R77,Q77)/Q77*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ77*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK77*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL77*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM77*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN77*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO77*'Power Scaling'!I$4)*AQ77,IF(OR($I77=\"AO\",$I77=\"LU\"),VLOOKUP($A77&\"_\"&\"vdd_dyn\"&\"_\"&$R77&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I77=\"LUUA\",$I77=\"LUUB\"),VLOOKUP($A77&\"_\"&\"vdd_dyn\"&\"_\"&$R77&\"\",MDB,5,0)*$C77*$S77*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A77&\"_\"&\"vdd_dyn\"&\"_\"&$R77&\"_idle\",MDB,5,0)*(1-$S77)+VLOOKUP($A77&\"_\"&\"vdd_dyn\"&\"_\"&$R77&\"_read\",MDB,5,0)*($S77/2)+VLOOKUP($A77&\"_\"&\"vdd_dyn\"&\"_\"&$R77&\"_write\",MDB,5,0)*($S77/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0.02,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","N16FFC_POK_VDD_CORE_OV"]
["N16FFC_POK","_VDD_CORE_UV",1,5,"VDD_CORE","N/A","VDDA_MCU","N/A","LU","GP_Core_CTL","POK","10/30/2021","5 Analog","Power",0.02,"ON",0,"on",1,0,{"$f":"IFERROR(IF($I78=\"SI\",AP78*$C78*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ78*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK78*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL78*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM78*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN78*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO78*'Power Scaling'!F$4)*IF(P78=\"OFF\",0.06,1),VLOOKUP($A78&\"_\"&U$3,MDB,5,0)*$C78*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P78=\"OFF\",0.06,1)),0)","v":0},{"$f":"C78*IFERROR(IF($I78=\"SI\",(AE78*IF(S78=0,0,1)+(AF78-AE78)*S78)*IF(R78>0,R78,Q78)/Q78*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ78*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK78*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL78*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM78*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN78*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO78*'Power Scaling'!I$4)*AQ78,IF(OR($I78=\"AO\",$I78=\"LU\"),VLOOKUP($A78&\"_\"&\"vdd_dyn\"&\"_\"&$R78&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I78=\"LUUA\",$I78=\"LUUB\"),VLOOKUP($A78&\"_\"&\"vdd_dyn\"&\"_\"&$R78&\"\",MDB,5,0)*$C78*$S78*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A78&\"_\"&\"vdd_dyn\"&\"_\"&$R78&\"_idle\",MDB,5,0)*(1-$S78)+VLOOKUP($A78&\"_\"&\"vdd_dyn\"&\"_\"&$R78&\"_read\",MDB,5,0)*($S78/2)+VLOOKUP($A78&\"_\"&\"vdd_dyn\"&\"_\"&$R78&\"_write\",MDB,5,0)*($S78/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0.02,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","N16FFC_POK_VDD_CORE_UV"]
["N16FFC_POK","_VDDR_CORE_OV",1,5,"VDD_CORE","N/A","VDDA_MCU","N/A","LU","GP_Core_CTL","POK","10/30/2021","5 Analog","Power",0.02,"ON",0,"on",1,0,{"$f":"IFERROR(IF($I79=\"SI\",AP79*$C79*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ79*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK79*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL79*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM79*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN79*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO79*'Power Scaling'!F$4)*IF(P79=\"OFF\",0.06,1),VLOOKUP($A79&\"_\"&U$3,MDB,5,0)*$C79*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P79=\"OFF\",0.06,1)),0)","v":0},{"$f":"C79*IFERROR(IF($I79=\"SI\",(AE79*IF(S79=0,0,1)+(AF79-AE79)*S79)*IF(R79>0,R79,Q79)/Q79*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ79*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK79*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL79*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM79*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN79*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO79*'Power Scaling'!I$4)*AQ79,IF(OR($I79=\"AO\",$I79=\"LU\"),VLOOKUP($A79&\"_\"&\"vdd_dyn\"&\"_\"&$R79&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I79=\"LUUA\",$I79=\"LUUB\"),VLOOKUP($A79&\"_\"&\"vdd_dyn\"&\"_\"&$R79&\"\",MDB,5,0)*$C79*$S79*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A79&\"_\"&\"vdd_dyn\"&\"_\"&$R79&\"_idle\",MDB,5,0)*(1-$S79)+VLOOKUP($A79&\"_\"&\"vdd_dyn\"&\"_\"&$R79&\"_read\",MDB,5,0)*($S79/2)+VLOOKUP($A79&\"_\"&\"vdd_dyn\"&\"_\"&$R79&\"_write\",MDB,5,0)*($S79/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0.02,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","N16FFC_POK_VDDR_CORE_OV"]
["N16FFC_POK","_VDDR_CORE_UV",1,5,"VDD_CORE","N/A","VDDA_MCU","N/A","LU","GP_Core_CTL","POK","10/30/2021","5 Analog","Power",0.02,"ON",0,"on",1,0,{"$f":"IFERROR(IF($I80=\"SI\",AP80*$C80*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ80*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK80*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL80*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM80*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN80*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO80*'Power Scaling'!F$4)*IF(P80=\"OFF\",0.06,1),VLOOKUP($A80&\"_\"&U$3,MDB,5,0)*$C80*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P80=\"OFF\",0.06,1)),0)","v":0},{"$f":"C80*IFERROR(IF($I80=\"SI\",(AE80*IF(S80=0,0,1)+(AF80-AE80)*S80)*IF(R80>0,R80,Q80)/Q80*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ80*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK80*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL80*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM80*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN80*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO80*'Power Scaling'!I$4)*AQ80,IF(OR($I80=\"AO\",$I80=\"LU\"),VLOOKUP($A80&\"_\"&\"vdd_dyn\"&\"_\"&$R80&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I80=\"LUUA\",$I80=\"LUUB\"),VLOOKUP($A80&\"_\"&\"vdd_dyn\"&\"_\"&$R80&\"\",MDB,5,0)*$C80*$S80*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A80&\"_\"&\"vdd_dyn\"&\"_\"&$R80&\"_idle\",MDB,5,0)*(1-$S80)+VLOOKUP($A80&\"_\"&\"vdd_dyn\"&\"_\"&$R80&\"_read\",MDB,5,0)*($S80/2)+VLOOKUP($A80&\"_\"&\"vdd_dyn\"&\"_\"&$R80&\"_write\",MDB,5,0)*($S80/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0.02,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","N16FFC_POK_VDDR_CORE_UV"]
["N16FFC_POK","_VMON_EXT_OV",1,5,"VDD_CORE","N/A","VDDA_MCU","N/A","LU","GP_Core_CTL","POK","10/30/2021","5 Analog","Power",0.02,"ON",0,"on",1,0,{"$f":"IFERROR(IF($I81=\"SI\",AP81*$C81*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ81*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK81*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL81*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM81*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN81*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO81*'Power Scaling'!F$4)*IF(P81=\"OFF\",0.06,1),VLOOKUP($A81&\"_\"&U$3,MDB,5,0)*$C81*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P81=\"OFF\",0.06,1)),0)","v":0},{"$f":"C81*IFERROR(IF($I81=\"SI\",(AE81*IF(S81=0,0,1)+(AF81-AE81)*S81)*IF(R81>0,R81,Q81)/Q81*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ81*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK81*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL81*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM81*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN81*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO81*'Power Scaling'!I$4)*AQ81,IF(OR($I81=\"AO\",$I81=\"LU\"),VLOOKUP($A81&\"_\"&\"vdd_dyn\"&\"_\"&$R81&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I81=\"LUUA\",$I81=\"LUUB\"),VLOOKUP($A81&\"_\"&\"vdd_dyn\"&\"_\"&$R81&\"\",MDB,5,0)*$C81*$S81*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A81&\"_\"&\"vdd_dyn\"&\"_\"&$R81&\"_idle\",MDB,5,0)*(1-$S81)+VLOOKUP($A81&\"_\"&\"vdd_dyn\"&\"_\"&$R81&\"_read\",MDB,5,0)*($S81/2)+VLOOKUP($A81&\"_\"&\"vdd_dyn\"&\"_\"&$R81&\"_write\",MDB,5,0)*($S81/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0.02,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","N16FFC_POK_VMON_EXT_OV"]
["N16FFC_POK","_VMON_EXT_UV",1,5,"VDD_CORE","N/A","VDDA_MCU","N/A","LU","GP_Core_CTL","POK","10/30/2021","5 Analog","Power",0.02,"ON",0,"on",1,0,{"$f":"IFERROR(IF($I82=\"SI\",AP82*$C82*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ82*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK82*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL82*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM82*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN82*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO82*'Power Scaling'!F$4)*IF(P82=\"OFF\",0.06,1),VLOOKUP($A82&\"_\"&U$3,MDB,5,0)*$C82*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P82=\"OFF\",0.06,1)),0)","v":0},{"$f":"C82*IFERROR(IF($I82=\"SI\",(AE82*IF(S82=0,0,1)+(AF82-AE82)*S82)*IF(R82>0,R82,Q82)/Q82*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ82*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK82*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL82*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM82*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN82*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO82*'Power Scaling'!I$4)*AQ82,IF(OR($I82=\"AO\",$I82=\"LU\"),VLOOKUP($A82&\"_\"&\"vdd_dyn\"&\"_\"&$R82&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I82=\"LUUA\",$I82=\"LUUB\"),VLOOKUP($A82&\"_\"&\"vdd_dyn\"&\"_\"&$R82&\"\",MDB,5,0)*$C82*$S82*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A82&\"_\"&\"vdd_dyn\"&\"_\"&$R82&\"_idle\",MDB,5,0)*(1-$S82)+VLOOKUP($A82&\"_\"&\"vdd_dyn\"&\"_\"&$R82&\"_read\",MDB,5,0)*($S82/2)+VLOOKUP($A82&\"_\"&\"vdd_dyn\"&\"_\"&$R82&\"_write\",MDB,5,0)*($S82/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0.02,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","N16FFC_POK_VMON_EXT_UV"]
["PGD","_MAIN_CORE",1,5,"VDD_CORE","VDD_CORE","N/A","N/A","LU","GP_Core_CTL","PGD","10/30/2021","5 Analog","Power",0,"ON",0,"on",1,0,{"$f":"IFERROR(IF($I83=\"SI\",AP83*$C83*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ83*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK83*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL83*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM83*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN83*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO83*'Power Scaling'!F$4)*IF(P83=\"OFF\",0.06,1),VLOOKUP($A83&\"_\"&U$3,MDB,5,0)*$C83*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P83=\"OFF\",0.06,1)),0)","v":0},{"$f":"C83*IFERROR(IF($I83=\"SI\",(AE83*IF(S83=0,0,1)+(AF83-AE83)*S83)*IF(R83>0,R83,Q83)/Q83*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ83*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK83*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL83*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM83*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN83*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO83*'Power Scaling'!I$4)*AQ83,IF(OR($I83=\"AO\",$I83=\"LU\"),VLOOKUP($A83&\"_\"&\"vdd_dyn\"&\"_\"&$R83&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I83=\"LUUA\",$I83=\"LUUB\"),VLOOKUP($A83&\"_\"&\"vdd_dyn\"&\"_\"&$R83&\"\",MDB,5,0)*$C83*$S83*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A83&\"_\"&\"vdd_dyn\"&\"_\"&$R83&\"_idle\",MDB,5,0)*(1-$S83)+VLOOKUP($A83&\"_\"&\"vdd_dyn\"&\"_\"&$R83&\"_read\",MDB,5,0)*($S83/2)+VLOOKUP($A83&\"_\"&\"vdd_dyn\"&\"_\"&$R83&\"_write\",MDB,5,0)*($S83/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","PGD_MAIN_CORE"]
["ddr32_3733_ios","_0",1,3,"VDD_CORE","N/A","VDDS_DDR","VDDS_DDR_C","LUUD","PD_DDR","LP/DDR4-32 IO 3733","10/30/2021","6 IO","DDR-PHY",215.16,"ON",0,{"$f":"IF(ISBLANK(BD84),0,INDIRECT(BD84))","v":"lpddr4_2400_32"},{"$f":"S39","v":1.1000000000000001},0,{"$f":"IFERROR(IF($I84=\"SI\",AP84*$C84*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ84*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK84*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL84*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM84*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN84*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO84*'Power Scaling'!F$4)*IF(P84=\"OFF\",0.06,1),VLOOKUP($A84&\"_\"&U$3,MDB,5,0)*$C84*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P84=\"OFF\",0.06,1)),0)","v":0},{"$f":"C84*IFERROR(IF($I84=\"SI\",(AE84*IF(S84=0,0,1)+(AF84-AE84)*S84)*IF(R84>0,R84,Q84)/Q84*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ84*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK84*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL84*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM84*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN84*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO84*'Power Scaling'!I$4)*AQ84,IF(OR($I84=\"AO\",$I84=\"LU\"),VLOOKUP($A84&\"_\"&\"vdd_dyn\"&\"_\"&$R84&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I84=\"LUUA\",$I84=\"LUUB\"),VLOOKUP($A84&\"_\"&\"vdd_dyn\"&\"_\"&$R84&\"\",MDB,5,0)*$C84*$S84*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A84&\"_\"&\"vdd_dyn\"&\"_\"&$R84&\"_idle\",MDB,5,0)*(1-$S84)+VLOOKUP($A84&\"_\"&\"vdd_dyn\"&\"_\"&$R84&\"_read\",MDB,5,0)*($S84/2)+VLOOKUP($A84&\"_\"&\"vdd_dyn\"&\"_\"&$R84&\"_write\",MDB,5,0)*($S84/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,215.16,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","ddr32_3733_ios_0","CG$25",null,null,null,null,null,null,null,null,null,"CF$25",null,null,"DDR"]
["ABJSTBL5","_multiple",1,5,"VDD_CORE","N/A","VDDA_TEMP0","N/A","LU","GP_Core_CTL","PVT Sensor","10/30/2021","6 IO","Monitor",0.60000271699999996,"ON",0,"on",1,0,{"$f":"IFERROR(IF($I85=\"SI\",AP85*$C85*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ85*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK85*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL85*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM85*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN85*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO85*'Power Scaling'!F$4)*IF(P85=\"OFF\",0.06,1),VLOOKUP($A85&\"_\"&U$3,MDB,5,0)*$C85*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P85=\"OFF\",0.06,1)),0)","v":0},{"$f":"C85*IFERROR(IF($I85=\"SI\",(AE85*IF(S85=0,0,1)+(AF85-AE85)*S85)*IF(R85>0,R85,Q85)/Q85*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ85*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK85*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL85*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM85*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN85*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO85*'Power Scaling'!I$4)*AQ85,IF(OR($I85=\"AO\",$I85=\"LU\"),VLOOKUP($A85&\"_\"&\"vdd_dyn\"&\"_\"&$R85&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I85=\"LUUA\",$I85=\"LUUB\"),VLOOKUP($A85&\"_\"&\"vdd_dyn\"&\"_\"&$R85&\"\",MDB,5,0)*$C85*$S85*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A85&\"_\"&\"vdd_dyn\"&\"_\"&$R85&\"_idle\",MDB,5,0)*(1-$S85)+VLOOKUP($A85&\"_\"&\"vdd_dyn\"&\"_\"&$R85&\"_read\",MDB,5,0)*($S85/2)+VLOOKUP($A85&\"_\"&\"vdd_dyn\"&\"_\"&$R85&\"_write\",MDB,5,0)*($S85/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0.60000271699999996,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","ABJSTBL5_multiple"]
["ABJSTBL5","_multiple",1,5,"VDD_CORE","N/A","VDDA_TEMP1","N/A","LU","GP_Core_CTL","PVT Sensor","10/30/2021","6 IO","Monitor",0.60000271699999996,"ON",0,"on",1,0,{"$f":"IFERROR(IF($I86=\"SI\",AP86*$C86*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ86*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK86*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL86*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM86*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN86*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO86*'Power Scaling'!F$4)*IF(P86=\"OFF\",0.06,1),VLOOKUP($A86&\"_\"&U$3,MDB,5,0)*$C86*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P86=\"OFF\",0.06,1)),0)","v":0},{"$f":"C86*IFERROR(IF($I86=\"SI\",(AE86*IF(S86=0,0,1)+(AF86-AE86)*S86)*IF(R86>0,R86,Q86)/Q86*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ86*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK86*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL86*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM86*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN86*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO86*'Power Scaling'!I$4)*AQ86,IF(OR($I86=\"AO\",$I86=\"LU\"),VLOOKUP($A86&\"_\"&\"vdd_dyn\"&\"_\"&$R86&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I86=\"LUUA\",$I86=\"LUUB\"),VLOOKUP($A86&\"_\"&\"vdd_dyn\"&\"_\"&$R86&\"\",MDB,5,0)*$C86*$S86*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A86&\"_\"&\"vdd_dyn\"&\"_\"&$R86&\"_idle\",MDB,5,0)*(1-$S86)+VLOOKUP($A86&\"_\"&\"vdd_dyn\"&\"_\"&$R86&\"_read\",MDB,5,0)*($S86/2)+VLOOKUP($A86&\"_\"&\"vdd_dyn\"&\"_\"&$R86&\"_write\",MDB,5,0)*($S86/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0.60000271699999996,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","ABJSTBL5_multiple"]
["ABJSTBL5","_multiple",1,5,"VDD_CORE","N/A","VDDA_TEMP2","N/A","LU","GP_Core_CTL","PVT Sensor","10/30/2021","6 IO","Monitor",0.60000271699999996,"ON",0,"on",1,0,{"$f":"IFERROR(IF($I87=\"SI\",AP87*$C87*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ87*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK87*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL87*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM87*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN87*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO87*'Power Scaling'!F$4)*IF(P87=\"OFF\",0.06,1),VLOOKUP($A87&\"_\"&U$3,MDB,5,0)*$C87*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P87=\"OFF\",0.06,1)),0)","v":0},{"$f":"C87*IFERROR(IF($I87=\"SI\",(AE87*IF(S87=0,0,1)+(AF87-AE87)*S87)*IF(R87>0,R87,Q87)/Q87*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ87*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK87*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL87*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM87*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN87*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO87*'Power Scaling'!I$4)*AQ87,IF(OR($I87=\"AO\",$I87=\"LU\"),VLOOKUP($A87&\"_\"&\"vdd_dyn\"&\"_\"&$R87&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I87=\"LUUA\",$I87=\"LUUB\"),VLOOKUP($A87&\"_\"&\"vdd_dyn\"&\"_\"&$R87&\"\",MDB,5,0)*$C87*$S87*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A87&\"_\"&\"vdd_dyn\"&\"_\"&$R87&\"_idle\",MDB,5,0)*(1-$S87)+VLOOKUP($A87&\"_\"&\"vdd_dyn\"&\"_\"&$R87&\"_read\",MDB,5,0)*($S87/2)+VLOOKUP($A87&\"_\"&\"vdd_dyn\"&\"_\"&$R87&\"_write\",MDB,5,0)*($S87/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0.60000271699999996,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","ABJSTBL5_multiple"]
["N16FFC_HFXOSC","_0",1,5,"VDD_CORE","N/A","VDDS_OSC0","N/A","LU","GP_Core_CTL","HFOSC","10/30/2021","6 IO","OSC",5.58,"ON",0,"on",1,0,{"$f":"IFERROR(IF($I88=\"SI\",AP88*$C88*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ88*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK88*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL88*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM88*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN88*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO88*'Power Scaling'!F$4)*IF(P88=\"OFF\",0.06,1),VLOOKUP($A88&\"_\"&U$3,MDB,5,0)*$C88*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P88=\"OFF\",0.06,1)),0)","v":0},{"$f":"C88*IFERROR(IF($I88=\"SI\",(AE88*IF(S88=0,0,1)+(AF88-AE88)*S88)*IF(R88>0,R88,Q88)/Q88*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ88*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK88*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL88*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM88*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN88*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO88*'Power Scaling'!I$4)*AQ88,IF(OR($I88=\"AO\",$I88=\"LU\"),VLOOKUP($A88&\"_\"&\"vdd_dyn\"&\"_\"&$R88&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I88=\"LUUA\",$I88=\"LUUB\"),VLOOKUP($A88&\"_\"&\"vdd_dyn\"&\"_\"&$R88&\"\",MDB,5,0)*$C88*$S88*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A88&\"_\"&\"vdd_dyn\"&\"_\"&$R88&\"_idle\",MDB,5,0)*(1-$S88)+VLOOKUP($A88&\"_\"&\"vdd_dyn\"&\"_\"&$R88&\"_read\",MDB,5,0)*($S88/2)+VLOOKUP($A88&\"_\"&\"vdd_dyn\"&\"_\"&$R88&\"_write\",MDB,5,0)*($S88/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,5.58,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","N16FFC_HFXOSC_0"]
["N16FFC_LFXOSC","_0",1,5,"VDD_CORE","N/A","VDDS_OSC0","N/A","LU","GP_Core_CTL","LFOSC","10/30/2021","6 IO","OSC",2.6280000000000001E-3,"ON",0,"on",1,0,{"$f":"IFERROR(IF($I89=\"SI\",AP89*$C89*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ89*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK89*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL89*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM89*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN89*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO89*'Power Scaling'!F$4)*IF(P89=\"OFF\",0.06,1),VLOOKUP($A89&\"_\"&U$3,MDB,5,0)*$C89*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P89=\"OFF\",0.06,1)),0)","v":0},{"$f":"C89*IFERROR(IF($I89=\"SI\",(AE89*IF(S89=0,0,1)+(AF89-AE89)*S89)*IF(R89>0,R89,Q89)/Q89*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ89*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK89*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL89*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM89*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN89*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO89*'Power Scaling'!I$4)*AQ89,IF(OR($I89=\"AO\",$I89=\"LU\"),VLOOKUP($A89&\"_\"&\"vdd_dyn\"&\"_\"&$R89&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I89=\"LUUA\",$I89=\"LUUB\"),VLOOKUP($A89&\"_\"&\"vdd_dyn\"&\"_\"&$R89&\"\",MDB,5,0)*$C89*$S89*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A89&\"_\"&\"vdd_dyn\"&\"_\"&$R89&\"_idle\",MDB,5,0)*(1-$S89)+VLOOKUP($A89&\"_\"&\"vdd_dyn\"&\"_\"&$R89&\"_read\",MDB,5,0)*($S89/2)+VLOOKUP($A89&\"_\"&\"vdd_dyn\"&\"_\"&$R89&\"_write\",MDB,5,0)*($S89/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,2.6280000000000001E-3,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","N16FFC_LFXOSC_0"]
["N16FFC_RCOSC","_0",1,5,"VDD_CORE","N/A","VDDS_OSC0","N/A","LU","GP_Core_CTL","RCOSC","10/30/2021","6 IO","OSC",8.7300000000000003E-2,"ON",0,"on",1,0,{"$f":"IFERROR(IF($I90=\"SI\",AP90*$C90*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ90*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK90*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL90*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM90*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN90*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO90*'Power Scaling'!F$4)*IF(P90=\"OFF\",0.06,1),VLOOKUP($A90&\"_\"&U$3,MDB,5,0)*$C90*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P90=\"OFF\",0.06,1)),0)","v":0},{"$f":"C90*IFERROR(IF($I90=\"SI\",(AE90*IF(S90=0,0,1)+(AF90-AE90)*S90)*IF(R90>0,R90,Q90)/Q90*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ90*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK90*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL90*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM90*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN90*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO90*'Power Scaling'!I$4)*AQ90,IF(OR($I90=\"AO\",$I90=\"LU\"),VLOOKUP($A90&\"_\"&\"vdd_dyn\"&\"_\"&$R90&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I90=\"LUUA\",$I90=\"LUUB\"),VLOOKUP($A90&\"_\"&\"vdd_dyn\"&\"_\"&$R90&\"\",MDB,5,0)*$C90*$S90*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A90&\"_\"&\"vdd_dyn\"&\"_\"&$R90&\"_idle\",MDB,5,0)*(1-$S90)+VLOOKUP($A90&\"_\"&\"vdd_dyn\"&\"_\"&$R90&\"_read\",MDB,5,0)*($S90/2)+VLOOKUP($A90&\"_\"&\"vdd_dyn\"&\"_\"&$R90&\"_write\",MDB,5,0)*($S90/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,8.7300000000000003E-2,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","N16FFC_RCOSC_0"]
[{"$error":"#N/A"},{"$error":"#N/A"},0,{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},0,{"$error":"#N/A"},0,{"$f":"IF(R93=\"disable\",\"disable\",\"1PLL\")","v":{"$error":"#VALUE!"}},{"$f":"IF(R91=\"disable\",0%,100%)","v":{"$error":"#VALUE!"}},0,{"$f":"IFERROR(IF($I91=\"SI\",AP91*$C91*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ91*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK91*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL91*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM91*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN91*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO91*'Power Scaling'!F$4)*IF(P91=\"OFF\",0.06,1),VLOOKUP($A91&\"_\"&U$3,MDB,5,0)*$C91*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P91=\"OFF\",0.06,1)),0)","v":0},{"$f":"C91*IFERROR(IF($I91=\"SI\",(AE91*IF(S91=0,0,1)+(AF91-AE91)*S91)*IF(R91>0,R91,Q91)/Q91*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ91*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK91*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL91*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM91*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN91*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO91*'Power Scaling'!I$4)*AQ91,IF(OR($I91=\"AO\",$I91=\"LU\"),VLOOKUP($A91&\"_\"&\"vdd_dyn\"&\"_\"&$R91&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I91=\"LUUA\",$I91=\"LUUB\"),VLOOKUP($A91&\"_\"&\"vdd_dyn\"&\"_\"&$R91&\"\",MDB,5,0)*$C91*$S91*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A91&\"_\"&\"vdd_dyn\"&\"_\"&$R91&\"_idle\",MDB,5,0)*(1-$S91)+VLOOKUP($A91&\"_\"&\"vdd_dyn\"&\"_\"&$R91&\"_read\",MDB,5,0)*($S91/2)+VLOOKUP($A91&\"_\"&\"vdd_dyn\"&\"_\"&$R91&\"_write\",MDB,5,0)*($S91/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,{"$error":"#N/A"},{"$error":"#N/A"},"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.",{"$error":"#N/A"},null,null,null,null,null,null,null,null,null,null,"CF$37"]
[{"$error":"#N/A"},{"$error":"#N/A"},0,{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},0,{"$error":"#N/A"},0,{"$f":"IF(OR(R94=\"unused\",R94=\"suspend\"),\"disable\",\"1PLL\")","v":{"$error":"#VALUE!"}},{"$f":"IF(R92=\"disable\",0%,100%)","v":{"$error":"#VALUE!"}},0,{"$f":"IFERROR(IF($I92=\"SI\",AP92*$C92*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ92*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK92*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL92*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM92*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN92*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO92*'Power Scaling'!F$4)*IF(P92=\"OFF\",0.06,1),VLOOKUP($A92&\"_\"&U$3,MDB,5,0)*$C92*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P92=\"OFF\",0.06,1)),0)","v":0},{"$f":"C92*IFERROR(IF($I92=\"SI\",(AE92*IF(S92=0,0,1)+(AF92-AE92)*S92)*IF(R92>0,R92,Q92)/Q92*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ92*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK92*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL92*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM92*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN92*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO92*'Power Scaling'!I$4)*AQ92,IF(OR($I92=\"AO\",$I92=\"LU\"),VLOOKUP($A92&\"_\"&\"vdd_dyn\"&\"_\"&$R92&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I92=\"LUUA\",$I92=\"LUUB\"),VLOOKUP($A92&\"_\"&\"vdd_dyn\"&\"_\"&$R92&\"\",MDB,5,0)*$C92*$S92*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A92&\"_\"&\"vdd_dyn\"&\"_\"&$R92&\"_idle\",MDB,5,0)*(1-$S92)+VLOOKUP($A92&\"_\"&\"vdd_dyn\"&\"_\"&$R92&\"_read\",MDB,5,0)*($S92/2)+VLOOKUP($A92&\"_\"&\"vdd_dyn\"&\"_\"&$R92&\"_write\",MDB,5,0)*($S92/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,{"$error":"#N/A"},{"$error":"#N/A"},"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.",{"$error":"#N/A"},null,null,null,null,null,null,null,null,null,null,"CF$39"]
[{"$error":"#N/A"},{"$error":"#N/A"},0,{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},0,{"$error":"#N/A"},0,{"$f":"IF(AZ93=\"unused\",BA93,AZ93)","v":{"$error":"#VALUE!"}},{"$f":"IF(R93=\"disable\",0%,100%)","v":{"$error":"#VALUE!"}},0,{"$f":"IFERROR(IF($I93=\"SI\",AP93*$C93*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ93*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK93*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL93*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM93*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN93*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO93*'Power Scaling'!F$4)*IF(P93=\"OFF\",0.06,1),VLOOKUP($A93&\"_\"&U$3,MDB,5,0)*$C93*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P93=\"OFF\",0.06,1)),0)","v":0},{"$f":"C93*IFERROR(IF($I93=\"SI\",(AE93*IF(S93=0,0,1)+(AF93-AE93)*S93)*IF(R93>0,R93,Q93)/Q93*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ93*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK93*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL93*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM93*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN93*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO93*'Power Scaling'!I$4)*AQ93,IF(OR($I93=\"AO\",$I93=\"LU\"),VLOOKUP($A93&\"_\"&\"vdd_dyn\"&\"_\"&$R93&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I93=\"LUUA\",$I93=\"LUUB\"),VLOOKUP($A93&\"_\"&\"vdd_dyn\"&\"_\"&$R93&\"\",MDB,5,0)*$C93*$S93*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A93&\"_\"&\"vdd_dyn\"&\"_\"&$R93&\"_idle\",MDB,5,0)*(1-$S93)+VLOOKUP($A93&\"_\"&\"vdd_dyn\"&\"_\"&$R93&\"_read\",MDB,5,0)*($S93/2)+VLOOKUP($A93&\"_\"&\"vdd_dyn\"&\"_\"&$R93&\"_write\",MDB,5,0)*($S93/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,{"$error":"#N/A"},{"$error":"#N/A"},"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.",{"$error":"#N/A"},"CB$38","CC$38","CD$38","CB$32","CC$32","CD$32",{"$f":"IF(AND(IF(ISBLANK(AT93),\"unused\",INDIRECT(AT93))<>\"unused\",IF(ISBLANK(AU93),0,INDIRECT(AU93))*IF(ISBLANK(AV93),0,INDIRECT(AV93))),INDIRECT(AT93),\"unused\")","v":{"$error":"#VALUE!"}},{"$f":"IF(AND(IF(ISBLANK(AW93),\"unused\",INDIRECT(AW93))<>\"unused\",IF(ISBLANK(AX93),0,INDIRECT(AX93))*IF(ISBLANK(AY93),0,INDIRECT(AY93))),INDIRECT(AW93),\"unused\")","v":"unused"},null,null,"CF$37"]
[{"$error":"#N/A"},{"$error":"#N/A"},0,{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},0,{"$error":"#N/A"},0,{"$f":"IF(IF(IF(AZ94=\"suspend\",BA94,AZ94)=\"1g\",1,0)+IF(S93=\"1g\",1,0)>INDIRECT(AY94),\"unused\",IF(AZ94=\"suspend\",BA94,AZ94))","v":{"$error":"#VALUE!"}},{"$f":"IF(OR(R94=\"suspend\",R94=\"disable\"),0%,100%)","v":{"$error":"#VALUE!"}},0,{"$f":"IFERROR(IF($I94=\"SI\",AP94*$C94*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ94*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK94*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL94*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM94*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN94*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO94*'Power Scaling'!F$4)*IF(P94=\"OFF\",0.06,1),VLOOKUP($A94&\"_\"&U$3,MDB,5,0)*$C94*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P94=\"OFF\",0.06,1)),0)","v":0},{"$f":"C94*IFERROR(IF($I94=\"SI\",(AE94*IF(S94=0,0,1)+(AF94-AE94)*S94)*IF(R94>0,R94,Q94)/Q94*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ94*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK94*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL94*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM94*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN94*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO94*'Power Scaling'!I$4)*AQ94,IF(OR($I94=\"AO\",$I94=\"LU\"),VLOOKUP($A94&\"_\"&\"vdd_dyn\"&\"_\"&$R94&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I94=\"LUUA\",$I94=\"LUUB\"),VLOOKUP($A94&\"_\"&\"vdd_dyn\"&\"_\"&$R94&\"\",MDB,5,0)*$C94*$S94*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A94&\"_\"&\"vdd_dyn\"&\"_\"&$R94&\"_idle\",MDB,5,0)*(1-$S94)+VLOOKUP($A94&\"_\"&\"vdd_dyn\"&\"_\"&$R94&\"_read\",MDB,5,0)*($S94/2)+VLOOKUP($A94&\"_\"&\"vdd_dyn\"&\"_\"&$R94&\"_write\",MDB,5,0)*($S94/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,{"$error":"#N/A"},{"$error":"#N/A"},"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.",{"$error":"#N/A"},"CB$40","CC$40","CD$40","CB$32","CC$32","CD$32",{"$f":"IF(AND(IF(ISBLANK(AT94),\"suspend\",INDIRECT(AT94))<>\"suspend\",IF(ISBLANK(AU94),0,INDIRECT(AU94))*IF(ISBLANK(AV94),0,INDIRECT(AV94))),INDIRECT(AT94),\"suspend\")","v":{"$error":"#VALUE!"}},{"$f":"IF(AND(IF(ISBLANK(AW94),\"unused\",INDIRECT(AW94))<>\"unused\",IF(ISBLANK(AX94),0,INDIRECT(AX94))*IF(ISBLANK(AY94),0,INDIRECT(AY94))),INDIRECT(AW94),\"unused\")","v":"unused"},null,null,"CF$39"]
["sd0901_rx4","_0",1,1,"VDD_CORE","VDDA_CORE_CSIRX0","VDDA_1P8_CSIRX0","N/A","LU","GP_Core_CTL","DPHY 1.2 RX - 4L","10/30/2021","6 IO","SerDes",18.619,"ON",0,{"$f":"IF(ISBLANK(BD95),\"ulps\",IF(INDIRECT(BE95)>BF95,INDIRECT(BD95),\"ulps\"))","v":"1p5g4l"},{"$f":"IF(R95=\"ulps\",0,INDIRECT(AU95))","v":0.1},0,{"$f":"IFERROR(IF($I95=\"SI\",AP95*$C95*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ95*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK95*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL95*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM95*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN95*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO95*'Power Scaling'!F$4)*IF(P95=\"OFF\",0.06,1),VLOOKUP($A95&\"_\"&U$3,MDB,5,0)*$C95*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P95=\"OFF\",0.06,1)),0)","v":0},{"$f":"C95*IFERROR(IF($I95=\"SI\",(AE95*IF(S95=0,0,1)+(AF95-AE95)*S95)*IF(R95>0,R95,Q95)/Q95*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ95*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK95*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL95*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM95*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN95*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO95*'Power Scaling'!I$4)*AQ95,IF(OR($I95=\"AO\",$I95=\"LU\"),VLOOKUP($A95&\"_\"&\"vdd_dyn\"&\"_\"&$R95&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I95=\"LUUA\",$I95=\"LUUB\"),VLOOKUP($A95&\"_\"&\"vdd_dyn\"&\"_\"&$R95&\"\",MDB,5,0)*$C95*$S95*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A95&\"_\"&\"vdd_dyn\"&\"_\"&$R95&\"_idle\",MDB,5,0)*(1-$S95)+VLOOKUP($A95&\"_\"&\"vdd_dyn\"&\"_\"&$R95&\"_read\",MDB,5,0)*($S95/2)+VLOOKUP($A95&\"_\"&\"vdd_dyn\"&\"_\"&$R95&\"_write\",MDB,5,0)*($S95/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,18.619,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","sd0901_rx4_0","CF$29","CG$29","CH$29",0,null,null,null,null,null,null,"CF$29","CH$29",0]
[{"$error":"#N/A"},{"$error":"#N/A"},0,{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},0,{"$error":"#N/A"},0,{"$f":"IF(ISBLANK(BD96),\"ulps\",IF(INDIRECT(BE96)>BF96,INDIRECT(BD96),\"ulps\"))","v":"ulps"},{"$f":"IF(R96=\"ulps\",0,INDIRECT(AU96))","v":0},0,{"$f":"IFERROR(IF($I96=\"SI\",AP96*$C96*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ96*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK96*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL96*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM96*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN96*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO96*'Power Scaling'!F$4)*IF(P96=\"OFF\",0.06,1),VLOOKUP($A96&\"_\"&U$3,MDB,5,0)*$C96*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P96=\"OFF\",0.06,1)),0)","v":0},{"$f":"C96*IFERROR(IF($I96=\"SI\",(AE96*IF(S96=0,0,1)+(AF96-AE96)*S96)*IF(R96>0,R96,Q96)/Q96*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ96*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK96*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL96*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM96*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN96*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO96*'Power Scaling'!I$4)*AQ96,IF(OR($I96=\"AO\",$I96=\"LU\"),VLOOKUP($A96&\"_\"&\"vdd_dyn\"&\"_\"&$R96&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I96=\"LUUA\",$I96=\"LUUB\"),VLOOKUP($A96&\"_\"&\"vdd_dyn\"&\"_\"&$R96&\"\",MDB,5,0)*$C96*$S96*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A96&\"_\"&\"vdd_dyn\"&\"_\"&$R96&\"_idle\",MDB,5,0)*(1-$S96)+VLOOKUP($A96&\"_\"&\"vdd_dyn\"&\"_\"&$R96&\"_read\",MDB,5,0)*($S96/2)+VLOOKUP($A96&\"_\"&\"vdd_dyn\"&\"_\"&$R96&\"_write\",MDB,5,0)*($S96/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,{"$error":"#N/A"},{"$error":"#N/A"},"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.",{"$error":"#N/A"},"CF$29","CG$29","CH$29",1,null,null,null,null,null,null,"CF$29","CH$29",1]
[{"$error":"#N/A"},{"$error":"#N/A"},0,{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},0,{"$error":"#N/A"},0,{"$f":"IF(ISBLANK(BD97),\"ulps\",IF(INDIRECT(BE97)>BF97,INDIRECT(BD97),\"ulps\"))","v":"ulps"},{"$f":"IF(R97=\"ulps\",0,INDIRECT(AU97))","v":0},0,{"$f":"IFERROR(IF($I97=\"SI\",AP97*$C97*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ97*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK97*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL97*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM97*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN97*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO97*'Power Scaling'!F$4)*IF(P97=\"OFF\",0.06,1),VLOOKUP($A97&\"_\"&U$3,MDB,5,0)*$C97*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P97=\"OFF\",0.06,1)),0)","v":0},{"$f":"C97*IFERROR(IF($I97=\"SI\",(AE97*IF(S97=0,0,1)+(AF97-AE97)*S97)*IF(R97>0,R97,Q97)/Q97*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ97*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK97*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL97*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM97*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN97*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO97*'Power Scaling'!I$4)*AQ97,IF(OR($I97=\"AO\",$I97=\"LU\"),VLOOKUP($A97&\"_\"&\"vdd_dyn\"&\"_\"&$R97&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I97=\"LUUA\",$I97=\"LUUB\"),VLOOKUP($A97&\"_\"&\"vdd_dyn\"&\"_\"&$R97&\"\",MDB,5,0)*$C97*$S97*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A97&\"_\"&\"vdd_dyn\"&\"_\"&$R97&\"_idle\",MDB,5,0)*(1-$S97)+VLOOKUP($A97&\"_\"&\"vdd_dyn\"&\"_\"&$R97&\"_read\",MDB,5,0)*($S97/2)+VLOOKUP($A97&\"_\"&\"vdd_dyn\"&\"_\"&$R97&\"_write\",MDB,5,0)*($S97/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,{"$error":"#N/A"},{"$error":"#N/A"},"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.",{"$error":"#N/A"},"CF$29","CG$29","CH$29",2,null,null,null,null,null,null,"CF$29","CH$29",2]
[{"$error":"#N/A"},{"$error":"#N/A"},0,{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},0,{"$error":"#N/A"},0,{"$f":"IF(ISBLANK(BD98),\"ulps\",IF(INDIRECT(BE98)>BF98,INDIRECT(BD98),\"ulps\"))","v":"ulps"},{"$f":"IF(R98=\"ulps\",0,INDIRECT(AU98))","v":0},0,{"$f":"IFERROR(IF($I98=\"SI\",AP98*$C98*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ98*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK98*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL98*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM98*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN98*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO98*'Power Scaling'!F$4)*IF(P98=\"OFF\",0.06,1),VLOOKUP($A98&\"_\"&U$3,MDB,5,0)*$C98*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P98=\"OFF\",0.06,1)),0)","v":0},{"$f":"C98*IFERROR(IF($I98=\"SI\",(AE98*IF(S98=0,0,1)+(AF98-AE98)*S98)*IF(R98>0,R98,Q98)/Q98*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ98*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK98*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL98*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM98*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN98*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO98*'Power Scaling'!I$4)*AQ98,IF(OR($I98=\"AO\",$I98=\"LU\"),VLOOKUP($A98&\"_\"&\"vdd_dyn\"&\"_\"&$R98&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I98=\"LUUA\",$I98=\"LUUB\"),VLOOKUP($A98&\"_\"&\"vdd_dyn\"&\"_\"&$R98&\"\",MDB,5,0)*$C98*$S98*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A98&\"_\"&\"vdd_dyn\"&\"_\"&$R98&\"_idle\",MDB,5,0)*(1-$S98)+VLOOKUP($A98&\"_\"&\"vdd_dyn\"&\"_\"&$R98&\"_read\",MDB,5,0)*($S98/2)+VLOOKUP($A98&\"_\"&\"vdd_dyn\"&\"_\"&$R98&\"_write\",MDB,5,0)*($S98/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,{"$error":"#N/A"},{"$error":"#N/A"},"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.",{"$error":"#N/A"},"CF$29","CG$29","CH$29",3,null,null,null,null,null,null,"CF$29","CH$29",3]
["sd0901_tx4","_0",1,3,"VDD_CORE","VDDA_0P8_DSITX_C","VDDA_0P8_DSITX","VDDA_1P8_DSITX","LU","GP_Core_CTL","DPHY 1.2 TX - 4L","10/30/2021","6 IO","SerDes",3.0880000000000001,"ON",0,{"$f":"IF(ISBLANK(BD99),\"ulps\",IF(INDIRECT(BE99)>BF99,INDIRECT(BD99),\"ulps\"))","v":"ulps"},{"$f":"IF(R99=\"ulps\",0,INDIRECT(AU99))","v":0},0,{"$f":"IFERROR(IF($I99=\"SI\",AP99*$C99*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ99*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK99*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL99*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM99*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN99*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO99*'Power Scaling'!F$4)*IF(P99=\"OFF\",0.06,1),VLOOKUP($A99&\"_\"&U$3,MDB,5,0)*$C99*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P99=\"OFF\",0.06,1)),0)","v":0},{"$f":"C99*IFERROR(IF($I99=\"SI\",(AE99*IF(S99=0,0,1)+(AF99-AE99)*S99)*IF(R99>0,R99,Q99)/Q99*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ99*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK99*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL99*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM99*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN99*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO99*'Power Scaling'!I$4)*AQ99,IF(OR($I99=\"AO\",$I99=\"LU\"),VLOOKUP($A99&\"_\"&\"vdd_dyn\"&\"_\"&$R99&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I99=\"LUUA\",$I99=\"LUUB\"),VLOOKUP($A99&\"_\"&\"vdd_dyn\"&\"_\"&$R99&\"\",MDB,5,0)*$C99*$S99*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A99&\"_\"&\"vdd_dyn\"&\"_\"&$R99&\"_idle\",MDB,5,0)*(1-$S99)+VLOOKUP($A99&\"_\"&\"vdd_dyn\"&\"_\"&$R99&\"_read\",MDB,5,0)*($S99/2)+VLOOKUP($A99&\"_\"&\"vdd_dyn\"&\"_\"&$R99&\"_write\",MDB,5,0)*($S99/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,2.9279999999999999,0,0.16,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","sd0901_tx4_0","CF$30","CG$30","CH$30",0,null,null,null,null,null,null,"CF$30","CH$30",0]
["LVDSTS16LLBI1E","_multiple",10,5,"VDD_CORE","N/A","VDDA_1P8_OLDI0","N/A","LU","GP_Core_CTL","LVDS IO","10/30/2021","6 IO","Special",{"$f":"SUM(U100:AD100)","v":148.1},{"$f":"INDEX(PD_State_Table,MATCH(J100,PD_Table_Row_Header,0),2)","v":"ON"},0,{"$f":"IF(ISBLANK(BD100),\"disabled\",INDIRECT(BD100))","v":"oldi_dual_24b_modes"},{"$f":"IF(R100=\"disabled\",0,INDIRECT(AT100))","v":1},0,{"$f":"IFERROR(IF($I100=\"SI\",AP100*$C100*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ100*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK100*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL100*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM100*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN100*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO100*'Power Scaling'!F$4)*IF(P100=\"OFF\",0.06,1),VLOOKUP($A100&\"_\"&U$3,MDB,5,0)*$C100*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P100=\"OFF\",0.06,1)),0)","v":0},{"$f":"C100*IFERROR(IF($I100=\"SI\",(AE100*IF(S100=0,0,1)+(AF100-AE100)*S100)*IF(R100>0,R100,Q100)/Q100*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ100*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK100*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL100*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM100*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN100*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO100*'Power Scaling'!I$4)*AQ100,IF(OR($I100=\"AO\",$I100=\"LU\"),VLOOKUP($A100&\"_\"&\"vdd_dyn\"&\"_\"&$R100&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I100=\"LUUA\",$I100=\"LUUB\"),VLOOKUP($A100&\"_\"&\"vdd_dyn\"&\"_\"&$R100&\"\",MDB,5,0)*$C100*$S100*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A100&\"_\"&\"vdd_dyn\"&\"_\"&$R100&\"_idle\",MDB,5,0)*(1-$S100)+VLOOKUP($A100&\"_\"&\"vdd_dyn\"&\"_\"&$R100&\"_read\",MDB,5,0)*($S100/2)+VLOOKUP($A100&\"_\"&\"vdd_dyn\"&\"_\"&$R100&\"_write\",MDB,5,0)*($S100/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,{"$f":"IFERROR(VLOOKUP($A100&\"_\"&X$3,MDB,5,0)*$C100*VLOOKUP(\"vddr_lkg\",pwr_scale_table,2,0)*IF(P100=\"OFF\",0.06,1),0)","v":0},{"$f":"IFERROR(VLOOKUP($A100&\"_\"&Y$3,MDB,5,0)*$C100*(VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*0.5+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*0.5),0)","v":0},{"$f":"IFERROR(IF(I100=\"LUUB\",VLOOKUP($A100&\"_\"&Z$3&\"_\"&$R100&\"\",MDB,5,0)*$C100*$S100*((VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)/4+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)/4+VLOOKUP(\"vdd_sw\",pwr_scale_table,2,0)/2)),VLOOKUP($A100&\"_\"&Z$3&\"_\"&$R100&\"\",MDB,5,0)*$C100*((VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)/4+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)/4+VLOOKUP(\"vdd_sw\",pwr_scale_table,2,0)/2))),0)","v":0},{"$f":"IFERROR(VLOOKUP($A100&\"_\"&AA$3,MDB,5,0)*$C100*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0),0)","v":0},{"$f":"IFERROR(IF(OR($I100=\"LUUA\",$I100=\"LUUB\"),VLOOKUP($A100&\"_\"&AB$3&\"_\"&$R100&\"\",MDB,5,0)*$C100*$S100,IF(I100=\"LUUD\",VLOOKUP($A100&\"_\"&AB$3&\"_\"&$R100&\"_idle\",MDB,5,0)*(1-$S100)+VLOOKUP($A100&\"_\"&AB$3&\"_\"&$R100&\"_read\",MDB,5,0)*($S100/2)+VLOOKUP($A100&\"_\"&AB$3&\"_\"&$R100&\"_write\",MDB,5,0)*($S100/2),VLOOKUP($A100&\"_\"&AB$3&\"_\"&$R100&\"\",MDB,5,0)*$C100)),0)","v":148.1},{"$f":"IFERROR(VLOOKUP($A100&\"_\"&AC$3,MDB,5,0)*$C100*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0),0)","v":0},{"$f":"IFERROR(IF(OR($I100=\"LUUA\",$I100=\"LUUB\"),VLOOKUP($A100&\"_\"&AD$3&\"_\"&$R100&\"\",MDB,5,0)*$C100*$S100,IF(I100=\"LUUD\",VLOOKUP($A100&\"_\"&AD$3&\"_\"&$R100&\"_idle\",MDB,5,0)*(1-$S100)+VLOOKUP($A100&\"_\"&AD$3&\"_\"&$R100&\"_read\",MDB,5,0)*($S100/2)+VLOOKUP($A100&\"_\"&AD$3&\"_\"&$R100&\"_write\",MDB,5,0)*($S100/2),VLOOKUP($A100&\"_\"&AD$3&\"_\"&$R100&\"\",MDB,5,0)*$C100)),0)","v":0},0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.",{"$f":"A100&B100","v":"LVDSTS16LLBI1E_multiple"},"CG$32",null,null,null,null,null,null,null,null,null,"CF$32"]
["N16FFC_POR","_0",1,5,"VDD_CORE","N/A","VDDA_MCU","N/A","LU","GP_Core_CTL","POR","10/30/2021","6 IO","Special",0.48599999999999999,"ON",0,"on",1,0,{"$f":"IFERROR(IF($I101=\"SI\",AP101*$C101*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ101*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK101*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL101*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM101*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN101*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO101*'Power Scaling'!F$4)*IF(P101=\"OFF\",0.06,1),VLOOKUP($A101&\"_\"&U$3,MDB,5,0)*$C101*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P101=\"OFF\",0.06,1)),0)","v":0},{"$f":"C101*IFERROR(IF($I101=\"SI\",(AE101*IF(S101=0,0,1)+(AF101-AE101)*S101)*IF(R101>0,R101,Q101)/Q101*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ101*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK101*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL101*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM101*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN101*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO101*'Power Scaling'!I$4)*AQ101,IF(OR($I101=\"AO\",$I101=\"LU\"),VLOOKUP($A101&\"_\"&\"vdd_dyn\"&\"_\"&$R101&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I101=\"LUUA\",$I101=\"LUUB\"),VLOOKUP($A101&\"_\"&\"vdd_dyn\"&\"_\"&$R101&\"\",MDB,5,0)*$C101*$S101*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A101&\"_\"&\"vdd_dyn\"&\"_\"&$R101&\"_idle\",MDB,5,0)*(1-$S101)+VLOOKUP($A101&\"_\"&\"vdd_dyn\"&\"_\"&$R101&\"_read\",MDB,5,0)*($S101/2)+VLOOKUP($A101&\"_\"&\"vdd_dyn\"&\"_\"&$R101&\"_write\",MDB,5,0)*($S101/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0.48599999999999999,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","N16FFC_POR_0"]
["N16FFC_TEMP_DIODE_TOP","_0",1,5,"VDD_CORE","N/A","VDDA_TEMP0","N/A","LU","GP_Core_CTL","Temp Sensing Diode","10/30/2021","6 IO","Special",2,"ON",0,"on",1,0,{"$f":"IFERROR(IF($I102=\"SI\",AP102*$C102*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ102*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK102*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL102*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM102*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN102*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO102*'Power Scaling'!F$4)*IF(P102=\"OFF\",0.06,1),VLOOKUP($A102&\"_\"&U$3,MDB,5,0)*$C102*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P102=\"OFF\",0.06,1)),0)","v":0},{"$f":"C102*IFERROR(IF($I102=\"SI\",(AE102*IF(S102=0,0,1)+(AF102-AE102)*S102)*IF(R102>0,R102,Q102)/Q102*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ102*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK102*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL102*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM102*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN102*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO102*'Power Scaling'!I$4)*AQ102,IF(OR($I102=\"AO\",$I102=\"LU\"),VLOOKUP($A102&\"_\"&\"vdd_dyn\"&\"_\"&$R102&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I102=\"LUUA\",$I102=\"LUUB\"),VLOOKUP($A102&\"_\"&\"vdd_dyn\"&\"_\"&$R102&\"\",MDB,5,0)*$C102*$S102*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A102&\"_\"&\"vdd_dyn\"&\"_\"&$R102&\"_idle\",MDB,5,0)*(1-$S102)+VLOOKUP($A102&\"_\"&\"vdd_dyn\"&\"_\"&$R102&\"_read\",MDB,5,0)*($S102/2)+VLOOKUP($A102&\"_\"&\"vdd_dyn\"&\"_\"&$R102&\"_write\",MDB,5,0)*($S102/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,2,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","N16FFC_TEMP_DIODE_TOP_0"]
["PDBODPMACRO","_0",1,5,"VDD_CORE","N/A","N/A","N/A","AO","GP_Core_CTL","ODP IO","10/30/2021","6 IO","Special",0,"ON",0,"on",1,0,{"$f":"IFERROR(IF($I103=\"SI\",AP103*$C103*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ103*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK103*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL103*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM103*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN103*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO103*'Power Scaling'!F$4)*IF(P103=\"OFF\",0.06,1),VLOOKUP($A103&\"_\"&U$3,MDB,5,0)*$C103*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P103=\"OFF\",0.06,1)),0)","v":0},{"$f":"C103*IFERROR(IF($I103=\"SI\",(AE103*IF(S103=0,0,1)+(AF103-AE103)*S103)*IF(R103>0,R103,Q103)/Q103*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ103*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK103*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL103*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM103*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN103*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO103*'Power Scaling'!I$4)*AQ103,IF(OR($I103=\"AO\",$I103=\"LU\"),VLOOKUP($A103&\"_\"&\"vdd_dyn\"&\"_\"&$R103&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I103=\"LUUA\",$I103=\"LUUB\"),VLOOKUP($A103&\"_\"&\"vdd_dyn\"&\"_\"&$R103&\"\",MDB,5,0)*$C103*$S103*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A103&\"_\"&\"vdd_dyn\"&\"_\"&$R103&\"_idle\",MDB,5,0)*(1-$S103)+VLOOKUP($A103&\"_\"&\"vdd_dyn\"&\"_\"&$R103&\"_read\",MDB,5,0)*($S103/2)+VLOOKUP($A103&\"_\"&\"vdd_dyn\"&\"_\"&$R103&\"_write\",MDB,5,0)*($S103/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","PDBODPMACRO_0"]
["emmc51phy_top","_emmc_0",1,2,"VDD_CORE","VDDA_0P8_DLL_MMC0","VDDS_MMC0","VDDA_3P3_SDIO","LU","GP_Core_CTL","Arasan HS400 8 bit","10/30/2021","6 IO","Special",99,"ON",0,{"$f":"IF(ISBLANK(BD104),\"ulps\",IF(INDIRECT(BE104)>BF104,INDIRECT(BD104),\"ulps\"))","v":"hs400"},{"$f":"IF(R104=\"ulps\",0,INDIRECT(AU104))","v":1},0,{"$f":"IFERROR(IF($I104=\"SI\",AP104*$C104*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ104*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK104*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL104*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM104*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN104*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO104*'Power Scaling'!F$4)*IF(P104=\"OFF\",0.06,1),VLOOKUP($A104&\"_\"&U$3,MDB,5,0)*$C104*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P104=\"OFF\",0.06,1)),0)","v":0},{"$f":"C104*IFERROR(IF($I104=\"SI\",(AE104*IF(S104=0,0,1)+(AF104-AE104)*S104)*IF(R104>0,R104,Q104)/Q104*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ104*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK104*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL104*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM104*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN104*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO104*'Power Scaling'!I$4)*AQ104,IF(OR($I104=\"AO\",$I104=\"LU\"),VLOOKUP($A104&\"_\"&\"vdd_dyn\"&\"_\"&$R104&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I104=\"LUUA\",$I104=\"LUUB\"),VLOOKUP($A104&\"_\"&\"vdd_dyn\"&\"_\"&$R104&\"\",MDB,5,0)*$C104*$S104*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A104&\"_\"&\"vdd_dyn\"&\"_\"&$R104&\"_idle\",MDB,5,0)*(1-$S104)+VLOOKUP($A104&\"_\"&\"vdd_dyn\"&\"_\"&$R104&\"_read\",MDB,5,0)*($S104/2)+VLOOKUP($A104&\"_\"&\"vdd_dyn\"&\"_\"&$R104&\"_write\",MDB,5,0)*($S104/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,99,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","emmc51phy_top_emmc_0","CF$31","CG$31","CH$31",null,null,null,null,null,null,null,"CF$31","CH$31"]
["PRWDWUWSWEWCDGSDIO","_mmc_1",7,5,"VDD_CORE","N/A","VDDSHV1P8","N/A","LUUB","GP_Core_CTL","SDIO - 1 bit","10/30/2021","6 IO","Special",9.0300000000000011,"ON",0,{"$f":"IF(ISBLANK(BD105),\"unused\",IF(INDIRECT(BE105)>BF105,INDIRECT(BD105),\"unused\"))","v":"hs200_200mbs"},{"$f":"IF(R105=\"unused\",0,INDIRECT(AU105))","v":1},0,{"$f":"IFERROR(IF($I105=\"SI\",AP105*$C105*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ105*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK105*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL105*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM105*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN105*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO105*'Power Scaling'!F$4)*IF(P105=\"OFF\",0.06,1),VLOOKUP($A105&\"_\"&U$3,MDB,5,0)*$C105*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P105=\"OFF\",0.06,1)),0)","v":0},{"$f":"C105*IFERROR(IF($I105=\"SI\",(AE105*IF(S105=0,0,1)+(AF105-AE105)*S105)*IF(R105>0,R105,Q105)/Q105*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ105*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK105*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL105*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM105*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN105*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO105*'Power Scaling'!I$4)*AQ105,IF(OR($I105=\"AO\",$I105=\"LU\"),VLOOKUP($A105&\"_\"&\"vdd_dyn\"&\"_\"&$R105&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I105=\"LUUA\",$I105=\"LUUB\"),VLOOKUP($A105&\"_\"&\"vdd_dyn\"&\"_\"&$R105&\"\",MDB,5,0)*$C105*$S105*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A105&\"_\"&\"vdd_dyn\"&\"_\"&$R105&\"_idle\",MDB,5,0)*(1-$S105)+VLOOKUP($A105&\"_\"&\"vdd_dyn\"&\"_\"&$R105&\"_read\",MDB,5,0)*($S105/2)+VLOOKUP($A105&\"_\"&\"vdd_dyn\"&\"_\"&$R105&\"_write\",MDB,5,0)*($S105/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,9.0300000000000011,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","PRWDWUWSWEWCDGSDIO_mmc_1","CB$62","CC$62","CD$62",0,null,null,null,null,null,null,"CB$62","CD$62",0]
["PRWDWUWSWEWCDGSDIO","_mmc_2",7,5,"VDD_CORE","N/A","VDDSHV1P8","N/A","LUUB","GP_Core_CTL","SDIO - 1 bit","10/30/2021","6 IO","Special",9.0300000000000011,"ON",0,{"$f":"IF(ISBLANK(BD106),\"unused\",IF(INDIRECT(BE106)>BF106,INDIRECT(BD106),\"unused\"))","v":"hs200_200mbs"},{"$f":"IF(R106=\"unused\",0,INDIRECT(AU106))","v":1},0,{"$f":"IFERROR(IF($I106=\"SI\",AP106*$C106*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ106*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK106*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL106*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM106*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN106*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO106*'Power Scaling'!F$4)*IF(P106=\"OFF\",0.06,1),VLOOKUP($A106&\"_\"&U$3,MDB,5,0)*$C106*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P106=\"OFF\",0.06,1)),0)","v":0},{"$f":"C106*IFERROR(IF($I106=\"SI\",(AE106*IF(S106=0,0,1)+(AF106-AE106)*S106)*IF(R106>0,R106,Q106)/Q106*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ106*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK106*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL106*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM106*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN106*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO106*'Power Scaling'!I$4)*AQ106,IF(OR($I106=\"AO\",$I106=\"LU\"),VLOOKUP($A106&\"_\"&\"vdd_dyn\"&\"_\"&$R106&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I106=\"LUUA\",$I106=\"LUUB\"),VLOOKUP($A106&\"_\"&\"vdd_dyn\"&\"_\"&$R106&\"\",MDB,5,0)*$C106*$S106*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A106&\"_\"&\"vdd_dyn\"&\"_\"&$R106&\"_idle\",MDB,5,0)*(1-$S106)+VLOOKUP($A106&\"_\"&\"vdd_dyn\"&\"_\"&$R106&\"_read\",MDB,5,0)*($S106/2)+VLOOKUP($A106&\"_\"&\"vdd_dyn\"&\"_\"&$R106&\"_write\",MDB,5,0)*($S106/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,9.0300000000000011,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","PRWDWUWSWEWCDGSDIO_mmc_2","CB$62","CC$62","CD$62",1,null,null,null,null,null,null,"CB$62","CD$62",1]
["sd1000","_0",1,4,"VDD_CORE","VDDA_CORE_USB","VDDA_1P8_USB","VDDA_3P3_USB","LU","GP_Core_CTL","USB2 - PHY","10/30/2021","6 IO","Special",14.790000000000001,"ON",0,{"$f":"IF(ISBLANK(AT107),\"sleep\",IF(OR(INDIRECT(AT107)=\"sleep\",INDIRECT(AV107)<=AW107),\"sleep\",INDIRECT(AT107)))","v":"host_hs"},{"$f":"IF(R107=\"sleep\",0,INDIRECT(AU107))","v":1},0,{"$f":"IFERROR(IF($I107=\"SI\",AP107*$C107*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ107*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK107*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL107*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM107*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN107*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO107*'Power Scaling'!F$4)*IF(P107=\"OFF\",0.06,1),VLOOKUP($A107&\"_\"&U$3,MDB,5,0)*$C107*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P107=\"OFF\",0.06,1)),0)","v":0},{"$f":"C107*IFERROR(IF($I107=\"SI\",(AE107*IF(S107=0,0,1)+(AF107-AE107)*S107)*IF(R107>0,R107,Q107)/Q107*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ107*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK107*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL107*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM107*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN107*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO107*'Power Scaling'!I$4)*AQ107,IF(OR($I107=\"AO\",$I107=\"LU\"),VLOOKUP($A107&\"_\"&\"vdd_dyn\"&\"_\"&$R107&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I107=\"LUUA\",$I107=\"LUUB\"),VLOOKUP($A107&\"_\"&\"vdd_dyn\"&\"_\"&$R107&\"\",MDB,5,0)*$C107*$S107*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A107&\"_\"&\"vdd_dyn\"&\"_\"&$R107&\"_idle\",MDB,5,0)*(1-$S107)+VLOOKUP($A107&\"_\"&\"vdd_dyn\"&\"_\"&$R107&\"_read\",MDB,5,0)*($S107/2)+VLOOKUP($A107&\"_\"&\"vdd_dyn\"&\"_\"&$R107&\"_write\",MDB,5,0)*($S107/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},{"$f":"C107*IFERROR(IF($I107=\"SI\",(AE107*IF(S107=0,0,1)+(AF107-AE107)*S107)*VLOOKUP(\"vdd_sw\",pwr_scale_table,2,0)*AI107,0),0)","v":0},0,0,0,0,12.88,0,1.91,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","sd1000_0","CB$41","CC$41","CD$41",0,null,null,null,null,null,null,"CB$40","CD$41",0]
["sd1000","_1",1,4,"VDD_CORE","VDDA_CORE_USB","VDDA_1P8_USB","VDDA_3P3_USB","LU","GP_Core_CTL","USB2 - PHY","10/30/2021","6 IO","Special",14.790000000000001,"ON",0,{"$f":"IF(ISBLANK(AT108),\"sleep\",IF(OR(INDIRECT(AT108)=\"sleep\",INDIRECT(AV108)<=AW108),\"sleep\",INDIRECT(AT108)))","v":"host_hs"},{"$f":"IF(R108=\"sleep\",0,INDIRECT(AU108))","v":1},0,{"$f":"IFERROR(IF($I108=\"SI\",AP108*$C108*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ108*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK108*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL108*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM108*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN108*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO108*'Power Scaling'!F$4)*IF(P108=\"OFF\",0.06,1),VLOOKUP($A108&\"_\"&U$3,MDB,5,0)*$C108*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P108=\"OFF\",0.06,1)),0)","v":0},{"$f":"C108*IFERROR(IF($I108=\"SI\",(AE108*IF(S108=0,0,1)+(AF108-AE108)*S108)*IF(R108>0,R108,Q108)/Q108*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ108*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK108*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL108*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM108*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN108*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO108*'Power Scaling'!I$4)*AQ108,IF(OR($I108=\"AO\",$I108=\"LU\"),VLOOKUP($A108&\"_\"&\"vdd_dyn\"&\"_\"&$R108&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I108=\"LUUA\",$I108=\"LUUB\"),VLOOKUP($A108&\"_\"&\"vdd_dyn\"&\"_\"&$R108&\"\",MDB,5,0)*$C108*$S108*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A108&\"_\"&\"vdd_dyn\"&\"_\"&$R108&\"_idle\",MDB,5,0)*(1-$S108)+VLOOKUP($A108&\"_\"&\"vdd_dyn\"&\"_\"&$R108&\"_read\",MDB,5,0)*($S108/2)+VLOOKUP($A108&\"_\"&\"vdd_dyn\"&\"_\"&$R108&\"_write\",MDB,5,0)*($S108/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,12.88,0,1.91,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","sd1000_1","CB$41","CC$41","CD$41",1,null,null,null,null,null,null,"CB$41","CD$41",0]
["TODP16FFC18_C170915","_0",1,5,"VDD_CORE","N/A","N/A","N/A","LU","GP_Core_CTL","ODP","10/30/2021","6 IO","Special",0,"ON",0,"on",1,0,{"$f":"IFERROR(IF($I109=\"SI\",AP109*$C109*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ109*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK109*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL109*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM109*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN109*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO109*'Power Scaling'!F$4)*IF(P109=\"OFF\",0.06,1),VLOOKUP($A109&\"_\"&U$3,MDB,5,0)*$C109*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P109=\"OFF\",0.06,1)),0)","v":0},{"$f":"C109*IFERROR(IF($I109=\"SI\",(AE109*IF(S109=0,0,1)+(AF109-AE109)*S109)*IF(R109>0,R109,Q109)/Q109*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ109*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK109*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL109*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM109*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN109*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO109*'Power Scaling'!I$4)*AQ109,IF(OR($I109=\"AO\",$I109=\"LU\"),VLOOKUP($A109&\"_\"&\"vdd_dyn\"&\"_\"&$R109&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I109=\"LUUA\",$I109=\"LUUB\"),VLOOKUP($A109&\"_\"&\"vdd_dyn\"&\"_\"&$R109&\"\",MDB,5,0)*$C109*$S109*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A109&\"_\"&\"vdd_dyn\"&\"_\"&$R109&\"_idle\",MDB,5,0)*(1-$S109)+VLOOKUP($A109&\"_\"&\"vdd_dyn\"&\"_\"&$R109&\"_read\",MDB,5,0)*($S109/2)+VLOOKUP($A109&\"_\"&\"vdd_dyn\"&\"_\"&$R109&\"_write\",MDB,5,0)*($S109/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","TODP16FFC18_C170915_0"]
["PVDD18MODEDET","_Main",8,5,"VDD_CORE","N/A","VDDSHV1P8","VDDSHV3P3","AO","GP_Core_CTL","LVCMOS SD","10/30/2021","6 IO","LVCMOS",0,"ON",0,"on",1,0,{"$f":"IFERROR(IF($I110=\"SI\",AP110*$C110*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ110*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK110*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL110*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM110*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN110*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO110*'Power Scaling'!F$4)*IF(P110=\"OFF\",0.06,1),VLOOKUP($A110&\"_\"&U$3,MDB,5,0)*$C110*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P110=\"OFF\",0.06,1)),0)","v":0},{"$f":"C110*IFERROR(IF($I110=\"SI\",(AE110*IF(S110=0,0,1)+(AF110-AE110)*S110)*IF(R110>0,R110,Q110)/Q110*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ110*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK110*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL110*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM110*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN110*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO110*'Power Scaling'!I$4)*AQ110,IF(OR($I110=\"AO\",$I110=\"LU\"),VLOOKUP($A110&\"_\"&\"vdd_dyn\"&\"_\"&$R110&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I110=\"LUUA\",$I110=\"LUUB\"),VLOOKUP($A110&\"_\"&\"vdd_dyn\"&\"_\"&$R110&\"\",MDB,5,0)*$C110*$S110*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A110&\"_\"&\"vdd_dyn\"&\"_\"&$R110&\"_idle\",MDB,5,0)*(1-$S110)+VLOOKUP($A110&\"_\"&\"vdd_dyn\"&\"_\"&$R110&\"_read\",MDB,5,0)*($S110/2)+VLOOKUP($A110&\"_\"&\"vdd_dyn\"&\"_\"&$R110&\"_write\",MDB,5,0)*($S110/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","PVDD18MODEDET_Main"]
["n16_core_apd_esd","_multiple",1,5,"VDD_CORE","N/A","N/A","N/A","AO","GP_Core_CTL","APD ESD","10/30/2021","5 Analog","Passives",0,"ON",0,"on",1,0,{"$f":"IFERROR(IF($I111=\"SI\",AP111*$C111*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ111*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK111*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL111*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM111*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN111*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO111*'Power Scaling'!F$4)*IF(P111=\"OFF\",0.06,1),VLOOKUP($A111&\"_\"&U$3,MDB,5,0)*$C111*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P111=\"OFF\",0.06,1)),0)","v":0},{"$f":"C111*IFERROR(IF($I111=\"SI\",(AE111*IF(S111=0,0,1)+(AF111-AE111)*S111)*IF(R111>0,R111,Q111)/Q111*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ111*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK111*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL111*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM111*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN111*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO111*'Power Scaling'!I$4)*AQ111,IF(OR($I111=\"AO\",$I111=\"LU\"),VLOOKUP($A111&\"_\"&\"vdd_dyn\"&\"_\"&$R111&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I111=\"LUUA\",$I111=\"LUUB\"),VLOOKUP($A111&\"_\"&\"vdd_dyn\"&\"_\"&$R111&\"\",MDB,5,0)*$C111*$S111*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A111&\"_\"&\"vdd_dyn\"&\"_\"&$R111&\"_idle\",MDB,5,0)*(1-$S111)+VLOOKUP($A111&\"_\"&\"vdd_dyn\"&\"_\"&$R111&\"_read\",MDB,5,0)*($S111/2)+VLOOKUP($A111&\"_\"&\"vdd_dyn\"&\"_\"&$R111&\"_write\",MDB,5,0)*($S111/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","n16_core_apd_esd_multiple"]
["n16_core_sig_esd_secondary","_multiple",26,5,"VDD_CORE","N/A","N/A","N/A","AO","GP_Core_CTL","SIG ESD","10/30/2021","5 Analog","Passives",0,"ON",0,"on",1,0,{"$f":"IFERROR(IF($I112=\"SI\",AP112*$C112*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ112*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK112*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL112*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM112*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN112*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO112*'Power Scaling'!F$4)*IF(P112=\"OFF\",0.06,1),VLOOKUP($A112&\"_\"&U$3,MDB,5,0)*$C112*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P112=\"OFF\",0.06,1)),0)","v":0},{"$f":"C112*IFERROR(IF($I112=\"SI\",(AE112*IF(S112=0,0,1)+(AF112-AE112)*S112)*IF(R112>0,R112,Q112)/Q112*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ112*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK112*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL112*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM112*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN112*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO112*'Power Scaling'!I$4)*AQ112,IF(OR($I112=\"AO\",$I112=\"LU\"),VLOOKUP($A112&\"_\"&\"vdd_dyn\"&\"_\"&$R112&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I112=\"LUUA\",$I112=\"LUUB\"),VLOOKUP($A112&\"_\"&\"vdd_dyn\"&\"_\"&$R112&\"\",MDB,5,0)*$C112*$S112*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A112&\"_\"&\"vdd_dyn\"&\"_\"&$R112&\"_idle\",MDB,5,0)*(1-$S112)+VLOOKUP($A112&\"_\"&\"vdd_dyn\"&\"_\"&$R112&\"_read\",MDB,5,0)*($S112/2)+VLOOKUP($A112&\"_\"&\"vdd_dyn\"&\"_\"&$R112&\"_write\",MDB,5,0)*($S112/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","n16_core_sig_esd_secondary_multiple"]
["n16_core_vdd_clamp","_multiple",13,5,"VDD_CORE","N/A","N/A","N/A","AO","GP_Core_CTL","0.8V POWER ESD","10/30/2021","5 Analog","Passives",0,"ON",0,"on",1,0,{"$f":"IFERROR(IF($I113=\"SI\",AP113*$C113*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ113*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK113*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL113*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM113*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN113*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO113*'Power Scaling'!F$4)*IF(P113=\"OFF\",0.06,1),VLOOKUP($A113&\"_\"&U$3,MDB,5,0)*$C113*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P113=\"OFF\",0.06,1)),0)","v":0},{"$f":"C113*IFERROR(IF($I113=\"SI\",(AE113*IF(S113=0,0,1)+(AF113-AE113)*S113)*IF(R113>0,R113,Q113)/Q113*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ113*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK113*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL113*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM113*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN113*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO113*'Power Scaling'!I$4)*AQ113,IF(OR($I113=\"AO\",$I113=\"LU\"),VLOOKUP($A113&\"_\"&\"vdd_dyn\"&\"_\"&$R113&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I113=\"LUUA\",$I113=\"LUUB\"),VLOOKUP($A113&\"_\"&\"vdd_dyn\"&\"_\"&$R113&\"\",MDB,5,0)*$C113*$S113*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A113&\"_\"&\"vdd_dyn\"&\"_\"&$R113&\"_idle\",MDB,5,0)*(1-$S113)+VLOOKUP($A113&\"_\"&\"vdd_dyn\"&\"_\"&$R113&\"_read\",MDB,5,0)*($S113/2)+VLOOKUP($A113&\"_\"&\"vdd_dyn\"&\"_\"&$R113&\"_write\",MDB,5,0)*($S113/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","n16_core_vdd_clamp_multiple"]
["n16_core_vdd3p3_clamp","_multiple",1,5,"VDD_CORE","N/A","N/A","N/A","AO","GP_Core_CTL","3.3V POWER ESD","10/30/2021","5 Analog","Passives",0,"ON",0,"on",1,0,{"$f":"IFERROR(IF($I114=\"SI\",AP114*$C114*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ114*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK114*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL114*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM114*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN114*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO114*'Power Scaling'!F$4)*IF(P114=\"OFF\",0.06,1),VLOOKUP($A114&\"_\"&U$3,MDB,5,0)*$C114*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P114=\"OFF\",0.06,1)),0)","v":0},{"$f":"C114*IFERROR(IF($I114=\"SI\",(AE114*IF(S114=0,0,1)+(AF114-AE114)*S114)*IF(R114>0,R114,Q114)/Q114*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ114*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK114*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL114*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM114*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN114*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO114*'Power Scaling'!I$4)*AQ114,IF(OR($I114=\"AO\",$I114=\"LU\"),VLOOKUP($A114&\"_\"&\"vdd_dyn\"&\"_\"&$R114&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I114=\"LUUA\",$I114=\"LUUB\"),VLOOKUP($A114&\"_\"&\"vdd_dyn\"&\"_\"&$R114&\"\",MDB,5,0)*$C114*$S114*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A114&\"_\"&\"vdd_dyn\"&\"_\"&$R114&\"_idle\",MDB,5,0)*(1-$S114)+VLOOKUP($A114&\"_\"&\"vdd_dyn\"&\"_\"&$R114&\"_read\",MDB,5,0)*($S114/2)+VLOOKUP($A114&\"_\"&\"vdd_dyn\"&\"_\"&$R114&\"_write\",MDB,5,0)*($S114/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","n16_core_vdd3p3_clamp_multiple"]
["n16_core_vdda_clamp","_multiple",25,5,"VDD_CORE","N/A","N/A","N/A","AO","GP_Core_CTL","1.8V POWER ESD","10/30/2021","5 Analog","Passives",0,"ON",0,"on",1,0,{"$f":"IFERROR(IF($I115=\"SI\",AP115*$C115*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ115*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK115*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL115*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM115*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN115*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO115*'Power Scaling'!F$4)*IF(P115=\"OFF\",0.06,1),VLOOKUP($A115&\"_\"&U$3,MDB,5,0)*$C115*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P115=\"OFF\",0.06,1)),0)","v":0},{"$f":"C115*IFERROR(IF($I115=\"SI\",(AE115*IF(S115=0,0,1)+(AF115-AE115)*S115)*IF(R115>0,R115,Q115)/Q115*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ115*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK115*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL115*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM115*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN115*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO115*'Power Scaling'!I$4)*AQ115,IF(OR($I115=\"AO\",$I115=\"LU\"),VLOOKUP($A115&\"_\"&\"vdd_dyn\"&\"_\"&$R115&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I115=\"LUUA\",$I115=\"LUUB\"),VLOOKUP($A115&\"_\"&\"vdd_dyn\"&\"_\"&$R115&\"\",MDB,5,0)*$C115*$S115*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A115&\"_\"&\"vdd_dyn\"&\"_\"&$R115&\"_idle\",MDB,5,0)*(1-$S115)+VLOOKUP($A115&\"_\"&\"vdd_dyn\"&\"_\"&$R115&\"_read\",MDB,5,0)*($S115/2)+VLOOKUP($A115&\"_\"&\"vdd_dyn\"&\"_\"&$R115&\"_write\",MDB,5,0)*($S115/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","n16_core_vdda_clamp_multiple"]
[{"$error":"#N/A"},{"$error":"#N/A"},0,{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},0,{"$error":"#N/A"},0,"on",1,0,{"$f":"IFERROR(IF($I116=\"SI\",AP116*$C116*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ116*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK116*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL116*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM116*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN116*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO116*'Power Scaling'!F$4)*IF(P116=\"OFF\",0.06,1),VLOOKUP($A116&\"_\"&U$3,MDB,5,0)*$C116*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P116=\"OFF\",0.06,1)),0)","v":0},{"$f":"C116*IFERROR(IF($I116=\"SI\",(AE116*IF(S116=0,0,1)+(AF116-AE116)*S116)*IF(R116>0,R116,Q116)/Q116*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ116*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK116*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL116*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM116*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN116*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO116*'Power Scaling'!I$4)*AQ116,IF(OR($I116=\"AO\",$I116=\"LU\"),VLOOKUP($A116&\"_\"&\"vdd_dyn\"&\"_\"&$R116&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I116=\"LUUA\",$I116=\"LUUB\"),VLOOKUP($A116&\"_\"&\"vdd_dyn\"&\"_\"&$R116&\"\",MDB,5,0)*$C116*$S116*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A116&\"_\"&\"vdd_dyn\"&\"_\"&$R116&\"_idle\",MDB,5,0)*(1-$S116)+VLOOKUP($A116&\"_\"&\"vdd_dyn\"&\"_\"&$R116&\"_read\",MDB,5,0)*($S116/2)+VLOOKUP($A116&\"_\"&\"vdd_dyn\"&\"_\"&$R116&\"_write\",MDB,5,0)*($S116/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,{"$error":"#N/A"},{"$error":"#N/A"},"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.",{"$error":"#N/A"}]
["PCBRTEPOCODIO","_Main",8,5,"VDD_CORE","N/A","VDDSHV1P8","VDDSHV3P3","AO","GP_Core_CTL","LVCMOS POC","10/30/2021","6 IO","LVCMOS",0,"ON",0,"on",1,0,{"$f":"IFERROR(IF($I117=\"SI\",AP117*$C117*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ117*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK117*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL117*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM117*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN117*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO117*'Power Scaling'!F$4)*IF(P117=\"OFF\",0.06,1),VLOOKUP($A117&\"_\"&U$3,MDB,5,0)*$C117*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P117=\"OFF\",0.06,1)),0)","v":0},{"$f":"C117*IFERROR(IF($I117=\"SI\",(AE117*IF(S117=0,0,1)+(AF117-AE117)*S117)*IF(R117>0,R117,Q117)/Q117*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ117*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK117*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL117*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM117*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN117*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO117*'Power Scaling'!I$4)*AQ117,IF(OR($I117=\"AO\",$I117=\"LU\"),VLOOKUP($A117&\"_\"&\"vdd_dyn\"&\"_\"&$R117&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I117=\"LUUA\",$I117=\"LUUB\"),VLOOKUP($A117&\"_\"&\"vdd_dyn\"&\"_\"&$R117&\"\",MDB,5,0)*$C117*$S117*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A117&\"_\"&\"vdd_dyn\"&\"_\"&$R117&\"_idle\",MDB,5,0)*(1-$S117)+VLOOKUP($A117&\"_\"&\"vdd_dyn\"&\"_\"&$R117&\"_read\",MDB,5,0)*($S117/2)+VLOOKUP($A117&\"_\"&\"vdd_dyn\"&\"_\"&$R117&\"_write\",MDB,5,0)*($S117/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","PCBRTEPOCODIO_Main"]
["PDIDGZRESET_C161202","_0",1,5,"VDD_CORE","N/A","VDDSHV1P8","VDDSHV3P3","AO","GP_Core_CTL","DDR Reset Input","10/30/2021","6 IO","LVCMOS",0,"ON",0,"on",1,0,{"$f":"IFERROR(IF($I118=\"SI\",AP118*$C118*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ118*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK118*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL118*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM118*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN118*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO118*'Power Scaling'!F$4)*IF(P118=\"OFF\",0.06,1),VLOOKUP($A118&\"_\"&U$3,MDB,5,0)*$C118*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P118=\"OFF\",0.06,1)),0)","v":0},{"$f":"C118*IFERROR(IF($I118=\"SI\",(AE118*IF(S118=0,0,1)+(AF118-AE118)*S118)*IF(R118>0,R118,Q118)/Q118*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ118*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK118*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL118*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM118*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN118*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO118*'Power Scaling'!I$4)*AQ118,IF(OR($I118=\"AO\",$I118=\"LU\"),VLOOKUP($A118&\"_\"&\"vdd_dyn\"&\"_\"&$R118&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I118=\"LUUA\",$I118=\"LUUB\"),VLOOKUP($A118&\"_\"&\"vdd_dyn\"&\"_\"&$R118&\"\",MDB,5,0)*$C118*$S118*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A118&\"_\"&\"vdd_dyn\"&\"_\"&$R118&\"_idle\",MDB,5,0)*(1-$S118)+VLOOKUP($A118&\"_\"&\"vdd_dyn\"&\"_\"&$R118&\"_read\",MDB,5,0)*($S118/2)+VLOOKUP($A118&\"_\"&\"vdd_dyn\"&\"_\"&$R118&\"_write\",MDB,5,0)*($S118/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","PDIDGZRESET_C161202_0"]
["PRBOPDDGZIIC","_Main",5,5,"VDD_CORE","N/A","VDDSHV1P8","VDDSHV3P3","AO","GP_Core_CTL","Open Drain - 1 bit","10/30/2021","6 IO","LVCMOS",0,"ON",0,"on",1,0,{"$f":"IFERROR(IF($I119=\"SI\",AP119*$C119*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ119*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK119*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL119*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM119*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN119*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO119*'Power Scaling'!F$4)*IF(P119=\"OFF\",0.06,1),VLOOKUP($A119&\"_\"&U$3,MDB,5,0)*$C119*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P119=\"OFF\",0.06,1)),0)","v":0},{"$f":"C119*IFERROR(IF($I119=\"SI\",(AE119*IF(S119=0,0,1)+(AF119-AE119)*S119)*IF(R119>0,R119,Q119)/Q119*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ119*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK119*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL119*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM119*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN119*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO119*'Power Scaling'!I$4)*AQ119,IF(OR($I119=\"AO\",$I119=\"LU\"),VLOOKUP($A119&\"_\"&\"vdd_dyn\"&\"_\"&$R119&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I119=\"LUUA\",$I119=\"LUUB\"),VLOOKUP($A119&\"_\"&\"vdd_dyn\"&\"_\"&$R119&\"\",MDB,5,0)*$C119*$S119*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A119&\"_\"&\"vdd_dyn\"&\"_\"&$R119&\"_idle\",MDB,5,0)*(1-$S119)+VLOOKUP($A119&\"_\"&\"vdd_dyn\"&\"_\"&$R119&\"_read\",MDB,5,0)*($S119/2)+VLOOKUP($A119&\"_\"&\"vdd_dyn\"&\"_\"&$R119&\"_write\",MDB,5,0)*($S119/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","PRBOPDDGZIIC_Main"]
["PRWDWUWSWEWCDGLVCMOS","_Main",154,5,"VDD_CORE","N/A","VDDSHV1P8","VDDSHV3P3","AO","GP_Core_CTL","LVCMOS IO","10/30/2021","6 IO","LVCMOS",0,"ON",0,"on",1,0,{"$f":"IFERROR(IF($I120=\"SI\",AP120*$C120*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ120*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK120*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL120*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM120*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN120*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO120*'Power Scaling'!F$4)*IF(P120=\"OFF\",0.06,1),VLOOKUP($A120&\"_\"&U$3,MDB,5,0)*$C120*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P120=\"OFF\",0.06,1)),0)","v":0},{"$f":"C120*IFERROR(IF($I120=\"SI\",(AE120*IF(S120=0,0,1)+(AF120-AE120)*S120)*IF(R120>0,R120,Q120)/Q120*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ120*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK120*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL120*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM120*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN120*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO120*'Power Scaling'!I$4)*AQ120,IF(OR($I120=\"AO\",$I120=\"LU\"),VLOOKUP($A120&\"_\"&\"vdd_dyn\"&\"_\"&$R120&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I120=\"LUUA\",$I120=\"LUUB\"),VLOOKUP($A120&\"_\"&\"vdd_dyn\"&\"_\"&$R120&\"\",MDB,5,0)*$C120*$S120*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A120&\"_\"&\"vdd_dyn\"&\"_\"&$R120&\"_idle\",MDB,5,0)*(1-$S120)+VLOOKUP($A120&\"_\"&\"vdd_dyn\"&\"_\"&$R120&\"_read\",MDB,5,0)*($S120/2)+VLOOKUP($A120&\"_\"&\"vdd_dyn\"&\"_\"&$R120&\"_write\",MDB,5,0)*($S120/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","PRWDWUWSWEWCDGLVCMOS_Main"]
["PVDD1LVCMOSM","_Main",15,5,"VDD_CORE","N/A","VDDSHV1P8","VDDSHV3P3","AO","GP_Core_CTL","LVCMOS PVDD1","10/30/2021","6 IO","LVCMOS",0,"ON",0,"on",1,0,{"$f":"IFERROR(IF($I121=\"SI\",AP121*$C121*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ121*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK121*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL121*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM121*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN121*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO121*'Power Scaling'!F$4)*IF(P121=\"OFF\",0.06,1),VLOOKUP($A121&\"_\"&U$3,MDB,5,0)*$C121*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P121=\"OFF\",0.06,1)),0)","v":0},{"$f":"C121*IFERROR(IF($I121=\"SI\",(AE121*IF(S121=0,0,1)+(AF121-AE121)*S121)*IF(R121>0,R121,Q121)/Q121*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ121*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK121*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL121*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM121*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN121*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO121*'Power Scaling'!I$4)*AQ121,IF(OR($I121=\"AO\",$I121=\"LU\"),VLOOKUP($A121&\"_\"&\"vdd_dyn\"&\"_\"&$R121&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I121=\"LUUA\",$I121=\"LUUB\"),VLOOKUP($A121&\"_\"&\"vdd_dyn\"&\"_\"&$R121&\"\",MDB,5,0)*$C121*$S121*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A121&\"_\"&\"vdd_dyn\"&\"_\"&$R121&\"_idle\",MDB,5,0)*(1-$S121)+VLOOKUP($A121&\"_\"&\"vdd_dyn\"&\"_\"&$R121&\"_read\",MDB,5,0)*($S121/2)+VLOOKUP($A121&\"_\"&\"vdd_dyn\"&\"_\"&$R121&\"_write\",MDB,5,0)*($S121/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","PVDD1LVCMOSM_Main"]
["PVDD2CDGM_C161202","_main",4,5,"VDD_CORE","N/A","VDDSHV1P8","VDDSHV3P3","AO","GP_Core_CTL","IO Cell VDDS PAD cell","10/30/2021","6 IO","LVCMOS",0,"ON",0,"on",1,0,{"$f":"IFERROR(IF($I122=\"SI\",AP122*$C122*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ122*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK122*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL122*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM122*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN122*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO122*'Power Scaling'!F$4)*IF(P122=\"OFF\",0.06,1),VLOOKUP($A122&\"_\"&U$3,MDB,5,0)*$C122*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P122=\"OFF\",0.06,1)),0)","v":0},{"$f":"C122*IFERROR(IF($I122=\"SI\",(AE122*IF(S122=0,0,1)+(AF122-AE122)*S122)*IF(R122>0,R122,Q122)/Q122*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ122*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK122*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL122*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM122*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN122*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO122*'Power Scaling'!I$4)*AQ122,IF(OR($I122=\"AO\",$I122=\"LU\"),VLOOKUP($A122&\"_\"&\"vdd_dyn\"&\"_\"&$R122&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I122=\"LUUA\",$I122=\"LUUB\"),VLOOKUP($A122&\"_\"&\"vdd_dyn\"&\"_\"&$R122&\"\",MDB,5,0)*$C122*$S122*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A122&\"_\"&\"vdd_dyn\"&\"_\"&$R122&\"_idle\",MDB,5,0)*(1-$S122)+VLOOKUP($A122&\"_\"&\"vdd_dyn\"&\"_\"&$R122&\"_read\",MDB,5,0)*($S122/2)+VLOOKUP($A122&\"_\"&\"vdd_dyn\"&\"_\"&$R122&\"_write\",MDB,5,0)*($S122/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","PVDD2CDGM_C161202_main"]
["PVDD3LDOLVCMOS","_Main",8,5,"VDD_CORE","N/A","VDDSHV1P8","VDDSHV3P3","AO","GP_Core_CTL","LVCMOS PVDD3LDO","10/30/2021","6 IO","LVCMOS",0,"ON",0,"on",1,0,{"$f":"IFERROR(IF($I123=\"SI\",AP123*$C123*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ123*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK123*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL123*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM123*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN123*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO123*'Power Scaling'!F$4)*IF(P123=\"OFF\",0.06,1),VLOOKUP($A123&\"_\"&U$3,MDB,5,0)*$C123*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P123=\"OFF\",0.06,1)),0)","v":0},{"$f":"C123*IFERROR(IF($I123=\"SI\",(AE123*IF(S123=0,0,1)+(AF123-AE123)*S123)*IF(R123>0,R123,Q123)/Q123*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ123*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK123*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL123*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM123*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN123*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO123*'Power Scaling'!I$4)*AQ123,IF(OR($I123=\"AO\",$I123=\"LU\"),VLOOKUP($A123&\"_\"&\"vdd_dyn\"&\"_\"&$R123&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I123=\"LUUA\",$I123=\"LUUB\"),VLOOKUP($A123&\"_\"&\"vdd_dyn\"&\"_\"&$R123&\"\",MDB,5,0)*$C123*$S123*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A123&\"_\"&\"vdd_dyn\"&\"_\"&$R123&\"_idle\",MDB,5,0)*(1-$S123)+VLOOKUP($A123&\"_\"&\"vdd_dyn\"&\"_\"&$R123&\"_read\",MDB,5,0)*($S123/2)+VLOOKUP($A123&\"_\"&\"vdd_dyn\"&\"_\"&$R123&\"_write\",MDB,5,0)*($S123/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","PVDD3LDOLVCMOS_Main"]
["PVDD3LVCMOSM","_main",10,5,"VDD_CORE","N/A","VDDSHV1P8","VDDSHV3P3","AO","GP_Core_CTL","LVCMOS PVDD3 power cell","10/30/2021","6 IO","LVCMOS",0,"ON",0,"on",1,0,{"$f":"IFERROR(IF($I124=\"SI\",AP124*$C124*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ124*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK124*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL124*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM124*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN124*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO124*'Power Scaling'!F$4)*IF(P124=\"OFF\",0.06,1),VLOOKUP($A124&\"_\"&U$3,MDB,5,0)*$C124*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P124=\"OFF\",0.06,1)),0)","v":0},{"$f":"C124*IFERROR(IF($I124=\"SI\",(AE124*IF(S124=0,0,1)+(AF124-AE124)*S124)*IF(R124>0,R124,Q124)/Q124*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ124*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK124*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL124*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM124*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN124*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO124*'Power Scaling'!I$4)*AQ124,IF(OR($I124=\"AO\",$I124=\"LU\"),VLOOKUP($A124&\"_\"&\"vdd_dyn\"&\"_\"&$R124&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I124=\"LUUA\",$I124=\"LUUB\"),VLOOKUP($A124&\"_\"&\"vdd_dyn\"&\"_\"&$R124&\"\",MDB,5,0)*$C124*$S124*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A124&\"_\"&\"vdd_dyn\"&\"_\"&$R124&\"_idle\",MDB,5,0)*(1-$S124)+VLOOKUP($A124&\"_\"&\"vdd_dyn\"&\"_\"&$R124&\"_read\",MDB,5,0)*($S124/2)+VLOOKUP($A124&\"_\"&\"vdd_dyn\"&\"_\"&$R124&\"_write\",MDB,5,0)*($S124/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","PVDD3LVCMOSM_main"]
["canfd","_0",1,0,"VDD_CORE","N/A","VDDSHV1P8","VDDSHV3P3","LUUA","GP_Core_Ctl","CANFD LVCMOS IO","10/30/2021","7 LVCMOS IO","CANFD",6.5339999999999995E-2,"ON",0,{"$f":"IF(ISBLANK(BD125),\"unused\",IF(INDIRECT(BE125)>BF125,INDIRECT(BD125),\"unused\"))","v":"1mbs_3p3v"},{"$f":"IF(R125=\"unused\",0,INDIRECT(AT125))","v":1},2,{"$f":"IFERROR(IF($I125=\"SI\",AP125*$C125*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ125*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK125*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL125*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM125*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN125*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO125*'Power Scaling'!F$4)*IF(P125=\"OFF\",0.06,1),VLOOKUP($A125&\"_\"&U$3,MDB,5,0)*$C125*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P125=\"OFF\",0.06,1)),0)","v":0},{"$f":"C125*IFERROR(IF($I125=\"SI\",(AE125*IF(S125=0,0,1)+(AF125-AE125)*S125)*IF(R125>0,R125,Q125)/Q125*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ125*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK125*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL125*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM125*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN125*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO125*'Power Scaling'!I$4)*AQ125,IF(OR($I125=\"AO\",$I125=\"LU\"),VLOOKUP($A125&\"_\"&\"vdd_dyn\"&\"_\"&$R125&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I125=\"LUUA\",$I125=\"LUUB\"),VLOOKUP($A125&\"_\"&\"vdd_dyn\"&\"_\"&$R125&\"\",MDB,5,0)*$C125*$S125*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A125&\"_\"&\"vdd_dyn\"&\"_\"&$R125&\"_idle\",MDB,5,0)*(1-$S125)+VLOOKUP($A125&\"_\"&\"vdd_dyn\"&\"_\"&$R125&\"_read\",MDB,5,0)*($S125/2)+VLOOKUP($A125&\"_\"&\"vdd_dyn\"&\"_\"&$R125&\"_write\",MDB,5,0)*($S125/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,6.5339999999999995E-2,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","canfd_0","CC$61",null,null,null,null,null,null,null,null,null,"CB$61","CD$61",0,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,43,{"$f":"CA43","v":"LVCMOS IO"},"Mode","Utilization","Instances"]
["canfd","_1",1,0,"VDD_CORE","N/A","VDDSHV1P8","VDDSHV3P3","LUUA","GP_Core_Ctl","CANFD LVCMOS IO","10/30/2021","7 LVCMOS IO","CANFD",0,"ON",0,"unused",0,2,{"$f":"IFERROR(IF($I126=\"SI\",AP126*$C126*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ126*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK126*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL126*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM126*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN126*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO126*'Power Scaling'!F$4)*IF(P126=\"OFF\",0.06,1),VLOOKUP($A126&\"_\"&U$3,MDB,5,0)*$C126*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P126=\"OFF\",0.06,1)),0)","v":0},{"$f":"C126*IFERROR(IF($I126=\"SI\",(AE126*IF(S126=0,0,1)+(AF126-AE126)*S126)*IF(R126>0,R126,Q126)/Q126*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ126*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK126*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL126*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM126*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN126*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO126*'Power Scaling'!I$4)*AQ126,IF(OR($I126=\"AO\",$I126=\"LU\"),VLOOKUP($A126&\"_\"&\"vdd_dyn\"&\"_\"&$R126&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I126=\"LUUA\",$I126=\"LUUB\"),VLOOKUP($A126&\"_\"&\"vdd_dyn\"&\"_\"&$R126&\"\",MDB,5,0)*$C126*$S126*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A126&\"_\"&\"vdd_dyn\"&\"_\"&$R126&\"_idle\",MDB,5,0)*(1-$S126)+VLOOKUP($A126&\"_\"&\"vdd_dyn\"&\"_\"&$R126&\"_read\",MDB,5,0)*($S126/2)+VLOOKUP($A126&\"_\"&\"vdd_dyn\"&\"_\"&$R126&\"_write\",MDB,5,0)*($S126/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","canfd_1","CC$61",null,null,null,null,null,null,null,null,null,"CB$61","CD$61",1,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,44,"WKUP I2C","i2c_400k_3p3v",1,1]
["canfd","_mcu_0",1,0,"VDD_CORE","N/A","VDDSHV1P8_MCU","VDDSHV3P3_MCU","LUUA","GP_Core_Ctl","CANFD LVCMOS IO","10/30/2021","7 LVCMOS IO","CANFD",0.32669999999999999,"ON",0,"5mbs_3p3v",1,2,{"$f":"IFERROR(IF($I127=\"SI\",AP127*$C127*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ127*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK127*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL127*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM127*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN127*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO127*'Power Scaling'!F$4)*IF(P127=\"OFF\",0.06,1),VLOOKUP($A127&\"_\"&U$3,MDB,5,0)*$C127*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P127=\"OFF\",0.06,1)),0)","v":0},{"$f":"C127*IFERROR(IF($I127=\"SI\",(AE127*IF(S127=0,0,1)+(AF127-AE127)*S127)*IF(R127>0,R127,Q127)/Q127*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ127*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK127*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL127*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM127*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN127*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO127*'Power Scaling'!I$4)*AQ127,IF(OR($I127=\"AO\",$I127=\"LU\"),VLOOKUP($A127&\"_\"&\"vdd_dyn\"&\"_\"&$R127&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I127=\"LUUA\",$I127=\"LUUB\"),VLOOKUP($A127&\"_\"&\"vdd_dyn\"&\"_\"&$R127&\"\",MDB,5,0)*$C127*$S127*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A127&\"_\"&\"vdd_dyn\"&\"_\"&$R127&\"_idle\",MDB,5,0)*(1-$S127)+VLOOKUP($A127&\"_\"&\"vdd_dyn\"&\"_\"&$R127&\"_read\",MDB,5,0)*($S127/2)+VLOOKUP($A127&\"_\"&\"vdd_dyn\"&\"_\"&$R127&\"_write\",MDB,5,0)*($S127/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0.32669999999999999,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","canfd_mcu_0","CC$49",null,null,null,null,null,null,null,null,null,"CB$49","CD$49",0,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,45,"WKUP UART","1m_3p3v",1,1]
["canfd","_mcu_1",1,0,"VDD_CORE","N/A","VDDSHV1P8_MCU","VDDSHV3P3_MCU","LUUA","GP_Core_Ctl","CANFD LVCMOS IO","10/30/2021","7 LVCMOS IO","CANFD",0,"ON",0,"unused",0,2,{"$f":"IFERROR(IF($I128=\"SI\",AP128*$C128*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ128*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK128*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL128*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM128*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN128*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO128*'Power Scaling'!F$4)*IF(P128=\"OFF\",0.06,1),VLOOKUP($A128&\"_\"&U$3,MDB,5,0)*$C128*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P128=\"OFF\",0.06,1)),0)","v":0},{"$f":"C128*IFERROR(IF($I128=\"SI\",(AE128*IF(S128=0,0,1)+(AF128-AE128)*S128)*IF(R128>0,R128,Q128)/Q128*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ128*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK128*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL128*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM128*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN128*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO128*'Power Scaling'!I$4)*AQ128,IF(OR($I128=\"AO\",$I128=\"LU\"),VLOOKUP($A128&\"_\"&\"vdd_dyn\"&\"_\"&$R128&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I128=\"LUUA\",$I128=\"LUUB\"),VLOOKUP($A128&\"_\"&\"vdd_dyn\"&\"_\"&$R128&\"\",MDB,5,0)*$C128*$S128*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A128&\"_\"&\"vdd_dyn\"&\"_\"&$R128&\"_idle\",MDB,5,0)*(1-$S128)+VLOOKUP($A128&\"_\"&\"vdd_dyn\"&\"_\"&$R128&\"_read\",MDB,5,0)*($S128/2)+VLOOKUP($A128&\"_\"&\"vdd_dyn\"&\"_\"&$R128&\"_write\",MDB,5,0)*($S128/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","canfd_mcu_1","CC$49",null,null,null,null,null,null,null,null,null,"CB$49","CD$49",1,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,46,"MCU I2C","i2c_400k_3p3v",1,1]
["dpi","_0",1,0,"VDD_CORE","N/A","VDDSHV1P8","VDDSHV3P3","LUUA","GP_Core_Ctl","DPI LVCMOS IO","10/30/2021","7 LVCMOS IO","DPI Display",59.628859970000001,"ON",0,"HD_|_1280x720x60_fps_24b_|_3p3V",1,28,{"$f":"IFERROR(IF($I129=\"SI\",AP129*$C129*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ129*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK129*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL129*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM129*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN129*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO129*'Power Scaling'!F$4)*IF(P129=\"OFF\",0.06,1),VLOOKUP($A129&\"_\"&U$3,MDB,5,0)*$C129*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P129=\"OFF\",0.06,1)),0)","v":0},{"$f":"C129*IFERROR(IF($I129=\"SI\",(AE129*IF(S129=0,0,1)+(AF129-AE129)*S129)*IF(R129>0,R129,Q129)/Q129*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ129*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK129*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL129*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM129*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN129*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO129*'Power Scaling'!I$4)*AQ129,IF(OR($I129=\"AO\",$I129=\"LU\"),VLOOKUP($A129&\"_\"&\"vdd_dyn\"&\"_\"&$R129&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I129=\"LUUA\",$I129=\"LUUB\"),VLOOKUP($A129&\"_\"&\"vdd_dyn\"&\"_\"&$R129&\"\",MDB,5,0)*$C129*$S129*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A129&\"_\"&\"vdd_dyn\"&\"_\"&$R129&\"_idle\",MDB,5,0)*(1-$S129)+VLOOKUP($A129&\"_\"&\"vdd_dyn\"&\"_\"&$R129&\"_read\",MDB,5,0)*($S129/2)+VLOOKUP($A129&\"_\"&\"vdd_dyn\"&\"_\"&$R129&\"_write\",MDB,5,0)*($S129/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,59.628859970000001,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","dpi_0","CC$63",null,null,null,null,null,null,null,null,null,"CB$63","CD$63",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,47,"MCU UART","112k_3p3v",1,1]
["ecap","_0",1,0,"VDD_CORE","N/A","VDDSHV1P8","VDDSHV3P3","LUUA","GP_Core_Ctl","eCAP LVCMOS IO","10/30/2021","7 LVCMOS IO","eCAP",0,"ON",0,"unused",0,1,{"$f":"IFERROR(IF($I130=\"SI\",AP130*$C130*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ130*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK130*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL130*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM130*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN130*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO130*'Power Scaling'!F$4)*IF(P130=\"OFF\",0.06,1),VLOOKUP($A130&\"_\"&U$3,MDB,5,0)*$C130*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P130=\"OFF\",0.06,1)),0)","v":0},{"$f":"C130*IFERROR(IF($I130=\"SI\",(AE130*IF(S130=0,0,1)+(AF130-AE130)*S130)*IF(R130>0,R130,Q130)/Q130*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ130*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK130*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL130*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM130*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN130*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO130*'Power Scaling'!I$4)*AQ130,IF(OR($I130=\"AO\",$I130=\"LU\"),VLOOKUP($A130&\"_\"&\"vdd_dyn\"&\"_\"&$R130&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I130=\"LUUA\",$I130=\"LUUB\"),VLOOKUP($A130&\"_\"&\"vdd_dyn\"&\"_\"&$R130&\"\",MDB,5,0)*$C130*$S130*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A130&\"_\"&\"vdd_dyn\"&\"_\"&$R130&\"_idle\",MDB,5,0)*(1-$S130)+VLOOKUP($A130&\"_\"&\"vdd_dyn\"&\"_\"&$R130&\"_read\",MDB,5,0)*($S130/2)+VLOOKUP($A130&\"_\"&\"vdd_dyn\"&\"_\"&$R130&\"_write\",MDB,5,0)*($S130/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","ecap_0","CC$58",null,null,null,null,null,null,null,null,null,"CB$58","CD$58",0,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,48,"MCU McSPI","Controller_2.083_Mbaud_3p3v",1,1]
["ecap","_1",1,0,"VDD_CORE","N/A","VDDSHV1P8","VDDSHV3P3","LUUA","GP_Core_Ctl","eCAP LVCMOS IO","10/30/2021","7 LVCMOS IO","eCAP",0,"ON",0,"unused",0,1,{"$f":"IFERROR(IF($I131=\"SI\",AP131*$C131*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ131*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK131*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL131*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM131*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN131*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO131*'Power Scaling'!F$4)*IF(P131=\"OFF\",0.06,1),VLOOKUP($A131&\"_\"&U$3,MDB,5,0)*$C131*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P131=\"OFF\",0.06,1)),0)","v":0},{"$f":"C131*IFERROR(IF($I131=\"SI\",(AE131*IF(S131=0,0,1)+(AF131-AE131)*S131)*IF(R131>0,R131,Q131)/Q131*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ131*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK131*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL131*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM131*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN131*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO131*'Power Scaling'!I$4)*AQ131,IF(OR($I131=\"AO\",$I131=\"LU\"),VLOOKUP($A131&\"_\"&\"vdd_dyn\"&\"_\"&$R131&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I131=\"LUUA\",$I131=\"LUUB\"),VLOOKUP($A131&\"_\"&\"vdd_dyn\"&\"_\"&$R131&\"\",MDB,5,0)*$C131*$S131*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A131&\"_\"&\"vdd_dyn\"&\"_\"&$R131&\"_idle\",MDB,5,0)*(1-$S131)+VLOOKUP($A131&\"_\"&\"vdd_dyn\"&\"_\"&$R131&\"_read\",MDB,5,0)*($S131/2)+VLOOKUP($A131&\"_\"&\"vdd_dyn\"&\"_\"&$R131&\"_write\",MDB,5,0)*($S131/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","ecap_1","CC$58",null,null,null,null,null,null,null,null,null,"CB$58","CD$58",1,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,49,"MCU MCAN","5mbs_3p3v",1,1]
["ecap","_2",1,0,"VDD_CORE","N/A","VDDSHV1P8","VDDSHV3P3","LUUA","GP_Core_Ctl","eCAP LVCMOS IO","10/30/2021","7 LVCMOS IO","eCAP",{"$f":"SUM(U132:AD132)","v":0},{"$f":"INDEX(PD_State_Table,MATCH(J132,PD_Table_Row_Header,0),2)","v":"ON"},0,"unused",0,1,{"$f":"IFERROR(IF($I132=\"SI\",AP132*$C132*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ132*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK132*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL132*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM132*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN132*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO132*'Power Scaling'!F$4)*IF(P132=\"OFF\",0.06,1),VLOOKUP($A132&\"_\"&U$3,MDB,5,0)*$C132*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P132=\"OFF\",0.06,1)),0)","v":0},{"$f":"C132*IFERROR(IF($I132=\"SI\",(AE132*IF(S132=0,0,1)+(AF132-AE132)*S132)*IF(R132>0,R132,Q132)/Q132*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ132*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK132*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL132*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM132*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN132*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO132*'Power Scaling'!I$4)*AQ132,IF(OR($I132=\"AO\",$I132=\"LU\"),VLOOKUP($A132&\"_\"&\"vdd_dyn\"&\"_\"&$R132&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I132=\"LUUA\",$I132=\"LUUB\"),VLOOKUP($A132&\"_\"&\"vdd_dyn\"&\"_\"&$R132&\"\",MDB,5,0)*$C132*$S132*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A132&\"_\"&\"vdd_dyn\"&\"_\"&$R132&\"_idle\",MDB,5,0)*(1-$S132)+VLOOKUP($A132&\"_\"&\"vdd_dyn\"&\"_\"&$R132&\"_read\",MDB,5,0)*($S132/2)+VLOOKUP($A132&\"_\"&\"vdd_dyn\"&\"_\"&$R132&\"_write\",MDB,5,0)*($S132/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,{"$f":"IFERROR(VLOOKUP($A132&\"_\"&X$3,MDB,5,0)*$C132*VLOOKUP(\"vddr_lkg\",pwr_scale_table,2,0)*IF(P132=\"OFF\",0.06,1),0)","v":0},{"$f":"IFERROR(VLOOKUP($A132&\"_\"&Y$3,MDB,5,0)*$C132*(VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*0.5+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*0.5),0)","v":0},{"$f":"IFERROR(IF(I132=\"LUUB\",VLOOKUP($A132&\"_\"&Z$3&\"_\"&$R132&\"\",MDB,5,0)*$C132*$S132*((VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)/4+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)/4+VLOOKUP(\"vdd_sw\",pwr_scale_table,2,0)/2)),VLOOKUP($A132&\"_\"&Z$3&\"_\"&$R132&\"\",MDB,5,0)*$C132*((VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)/4+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)/4+VLOOKUP(\"vdd_sw\",pwr_scale_table,2,0)/2))),0)","v":0},{"$f":"IFERROR(VLOOKUP($A132&\"_\"&AA$3,MDB,5,0)*$C132*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0),0)","v":0},{"$f":"IFERROR(IF(OR($I132=\"LUUA\",$I132=\"LUUB\"),VLOOKUP($A132&\"_\"&AB$3&\"_\"&$R132&\"\",MDB,5,0)*$C132*$S132,IF(I132=\"LUUD\",VLOOKUP($A132&\"_\"&AB$3&\"_\"&$R132&\"_idle\",MDB,5,0)*(1-$S132)+VLOOKUP($A132&\"_\"&AB$3&\"_\"&$R132&\"_read\",MDB,5,0)*($S132/2)+VLOOKUP($A132&\"_\"&AB$3&\"_\"&$R132&\"_write\",MDB,5,0)*($S132/2),VLOOKUP($A132&\"_\"&AB$3&\"_\"&$R132&\"\",MDB,5,0)*$C132)),0)","v":0},{"$f":"IFERROR(VLOOKUP($A132&\"_\"&AC$3,MDB,5,0)*$C132*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0),0)","v":0},{"$f":"IFERROR(IF(OR($I132=\"LUUA\",$I132=\"LUUB\"),VLOOKUP($A132&\"_\"&AD$3&\"_\"&$R132&\"\",MDB,5,0)*$C132*$S132,IF(I132=\"LUUD\",VLOOKUP($A132&\"_\"&AD$3&\"_\"&$R132&\"_idle\",MDB,5,0)*(1-$S132)+VLOOKUP($A132&\"_\"&AD$3&\"_\"&$R132&\"_read\",MDB,5,0)*($S132/2)+VLOOKUP($A132&\"_\"&AD$3&\"_\"&$R132&\"_write\",MDB,5,0)*($S132/2),VLOOKUP($A132&\"_\"&AD$3&\"_\"&$R132&\"\",MDB,5,0)*$C132)),0)","v":0},0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.",{"$f":"A132&B132","v":"ecap_2"},"CC$58",null,null,null,null,null,null,null,null,null,"CB$58","CD$58",2,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,50,"MCU GPIO","1mbs_3p3v_20pf",1,5]
["epwm","_0",1,0,"VDD_CORE","N/A","VDDSHV1P8","VDDSHV3P3","LUUA","GP_Core_Ctl","ePWM LVCMOS IO","10/30/2021","7 LVCMOS IO","ePWM",0.50738399999999995,"ON",0,"on_1p8v",1,3,{"$f":"IFERROR(IF($I133=\"SI\",AP133*$C133*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ133*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK133*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL133*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM133*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN133*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO133*'Power Scaling'!F$4)*IF(P133=\"OFF\",0.06,1),VLOOKUP($A133&\"_\"&U$3,MDB,5,0)*$C133*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P133=\"OFF\",0.06,1)),0)","v":0},{"$f":"C133*IFERROR(IF($I133=\"SI\",(AE133*IF(S133=0,0,1)+(AF133-AE133)*S133)*IF(R133>0,R133,Q133)/Q133*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ133*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK133*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL133*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM133*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN133*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO133*'Power Scaling'!I$4)*AQ133,IF(OR($I133=\"AO\",$I133=\"LU\"),VLOOKUP($A133&\"_\"&\"vdd_dyn\"&\"_\"&$R133&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I133=\"LUUA\",$I133=\"LUUB\"),VLOOKUP($A133&\"_\"&\"vdd_dyn\"&\"_\"&$R133&\"\",MDB,5,0)*$C133*$S133*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A133&\"_\"&\"vdd_dyn\"&\"_\"&$R133&\"_idle\",MDB,5,0)*(1-$S133)+VLOOKUP($A133&\"_\"&\"vdd_dyn\"&\"_\"&$R133&\"_read\",MDB,5,0)*($S133/2)+VLOOKUP($A133&\"_\"&\"vdd_dyn\"&\"_\"&$R133&\"_write\",MDB,5,0)*($S133/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0.50738399999999995,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","epwm_0","CC$59",null,null,null,null,null,null,null,null,null,"CB$59","CD$59",0]
["epwm","_1",1,0,"VDD_CORE","N/A","VDDSHV1P8","VDDSHV3P3","LUUA","GP_Core_Ctl","ePWM LVCMOS IO","10/30/2021","7 LVCMOS IO","ePWM",0.50738399999999995,"ON",0,"on_1p8v",1,3,{"$f":"IFERROR(IF($I134=\"SI\",AP134*$C134*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ134*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK134*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL134*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM134*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN134*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO134*'Power Scaling'!F$4)*IF(P134=\"OFF\",0.06,1),VLOOKUP($A134&\"_\"&U$3,MDB,5,0)*$C134*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P134=\"OFF\",0.06,1)),0)","v":0},{"$f":"C134*IFERROR(IF($I134=\"SI\",(AE134*IF(S134=0,0,1)+(AF134-AE134)*S134)*IF(R134>0,R134,Q134)/Q134*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ134*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK134*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL134*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM134*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN134*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO134*'Power Scaling'!I$4)*AQ134,IF(OR($I134=\"AO\",$I134=\"LU\"),VLOOKUP($A134&\"_\"&\"vdd_dyn\"&\"_\"&$R134&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I134=\"LUUA\",$I134=\"LUUB\"),VLOOKUP($A134&\"_\"&\"vdd_dyn\"&\"_\"&$R134&\"\",MDB,5,0)*$C134*$S134*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A134&\"_\"&\"vdd_dyn\"&\"_\"&$R134&\"_idle\",MDB,5,0)*(1-$S134)+VLOOKUP($A134&\"_\"&\"vdd_dyn\"&\"_\"&$R134&\"_read\",MDB,5,0)*($S134/2)+VLOOKUP($A134&\"_\"&\"vdd_dyn\"&\"_\"&$R134&\"_write\",MDB,5,0)*($S134/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0.50738399999999995,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","epwm_1","CC$59",null,null,null,null,null,null,null,null,null,"CB$59","CD$59",1,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,52,{"$f":"CA52","v":"LVCMOS IO"},"Mode","Utilization","Instances"]
["epwm","_2",1,0,"VDD_CORE","N/A","VDDSHV1P8","VDDSHV3P3","LUUA","GP_Core_Ctl","ePWM LVCMOS IO","10/30/2021","7 LVCMOS IO","ePWM",0.50738399999999995,"ON",0,"on_1p8v",1,3,{"$f":"IFERROR(IF($I135=\"SI\",AP135*$C135*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ135*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK135*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL135*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM135*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN135*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO135*'Power Scaling'!F$4)*IF(P135=\"OFF\",0.06,1),VLOOKUP($A135&\"_\"&U$3,MDB,5,0)*$C135*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P135=\"OFF\",0.06,1)),0)","v":0},{"$f":"C135*IFERROR(IF($I135=\"SI\",(AE135*IF(S135=0,0,1)+(AF135-AE135)*S135)*IF(R135>0,R135,Q135)/Q135*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ135*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK135*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL135*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM135*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN135*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO135*'Power Scaling'!I$4)*AQ135,IF(OR($I135=\"AO\",$I135=\"LU\"),VLOOKUP($A135&\"_\"&\"vdd_dyn\"&\"_\"&$R135&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I135=\"LUUA\",$I135=\"LUUB\"),VLOOKUP($A135&\"_\"&\"vdd_dyn\"&\"_\"&$R135&\"\",MDB,5,0)*$C135*$S135*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A135&\"_\"&\"vdd_dyn\"&\"_\"&$R135&\"_idle\",MDB,5,0)*(1-$S135)+VLOOKUP($A135&\"_\"&\"vdd_dyn\"&\"_\"&$R135&\"_read\",MDB,5,0)*($S135/2)+VLOOKUP($A135&\"_\"&\"vdd_dyn\"&\"_\"&$R135&\"_write\",MDB,5,0)*($S135/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0.50738399999999995,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","epwm_2","CC$59",null,null,null,null,null,null,null,null,null,"CB$59","CD$59",2,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,53,"MAIN GPIO","1mbs_1p8v_20pf",1,30]
["eqep","_0",1,0,"VDD_CORE","N/A","VDDSHV1P8","VDDSHV3P3","LUUA","GP_Core_Ctl","eQEP LVCMOS IO","10/30/2021","7 LVCMOS IO","eQEP",0,"ON",0,"unused",0,4,{"$f":"IFERROR(IF($I136=\"SI\",AP136*$C136*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ136*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK136*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL136*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM136*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN136*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO136*'Power Scaling'!F$4)*IF(P136=\"OFF\",0.06,1),VLOOKUP($A136&\"_\"&U$3,MDB,5,0)*$C136*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P136=\"OFF\",0.06,1)),0)","v":0},{"$f":"C136*IFERROR(IF($I136=\"SI\",(AE136*IF(S136=0,0,1)+(AF136-AE136)*S136)*IF(R136>0,R136,Q136)/Q136*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ136*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK136*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL136*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM136*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN136*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO136*'Power Scaling'!I$4)*AQ136,IF(OR($I136=\"AO\",$I136=\"LU\"),VLOOKUP($A136&\"_\"&\"vdd_dyn\"&\"_\"&$R136&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I136=\"LUUA\",$I136=\"LUUB\"),VLOOKUP($A136&\"_\"&\"vdd_dyn\"&\"_\"&$R136&\"\",MDB,5,0)*$C136*$S136*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A136&\"_\"&\"vdd_dyn\"&\"_\"&$R136&\"_idle\",MDB,5,0)*(1-$S136)+VLOOKUP($A136&\"_\"&\"vdd_dyn\"&\"_\"&$R136&\"_read\",MDB,5,0)*($S136/2)+VLOOKUP($A136&\"_\"&\"vdd_dyn\"&\"_\"&$R136&\"_write\",MDB,5,0)*($S136/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","eqep_0","CC$60",null,null,null,null,null,null,null,null,null,"CB$60","CD$60",0,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,54,"MAIN I2C","i2c_400k_3p3v",1,3.0000000000000004]
["eqep","_1",1,0,"VDD_CORE","N/A","VDDSHV1P8","VDDSHV3P3","LUUA","GP_Core_Ctl","eQEP LVCMOS IO","10/30/2021","7 LVCMOS IO","eQEP",0,"ON",0,"unused",0,4,{"$f":"IFERROR(IF($I137=\"SI\",AP137*$C137*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ137*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK137*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL137*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM137*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN137*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO137*'Power Scaling'!F$4)*IF(P137=\"OFF\",0.06,1),VLOOKUP($A137&\"_\"&U$3,MDB,5,0)*$C137*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P137=\"OFF\",0.06,1)),0)","v":0},{"$f":"C137*IFERROR(IF($I137=\"SI\",(AE137*IF(S137=0,0,1)+(AF137-AE137)*S137)*IF(R137>0,R137,Q137)/Q137*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ137*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK137*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL137*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM137*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN137*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO137*'Power Scaling'!I$4)*AQ137,IF(OR($I137=\"AO\",$I137=\"LU\"),VLOOKUP($A137&\"_\"&\"vdd_dyn\"&\"_\"&$R137&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I137=\"LUUA\",$I137=\"LUUB\"),VLOOKUP($A137&\"_\"&\"vdd_dyn\"&\"_\"&$R137&\"\",MDB,5,0)*$C137*$S137*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A137&\"_\"&\"vdd_dyn\"&\"_\"&$R137&\"_idle\",MDB,5,0)*(1-$S137)+VLOOKUP($A137&\"_\"&\"vdd_dyn\"&\"_\"&$R137&\"_read\",MDB,5,0)*($S137/2)+VLOOKUP($A137&\"_\"&\"vdd_dyn\"&\"_\"&$R137&\"_write\",MDB,5,0)*($S137/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","eqep_1","CC$60",null,null,null,null,null,null,null,null,null,"CB$60","CD$60",1,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,55,"MAIN UART","3p6m_1p8v",1,5]
["eqep","_2",1,0,"VDD_CORE","N/A","VDDSHV1P8","VDDSHV3P3","LUUA","GP_Core_Ctl","eQEP LVCMOS IO","10/30/2021","7 LVCMOS IO","eQEP",0,"ON",0,"unused",0,4,{"$f":"IFERROR(IF($I138=\"SI\",AP138*$C138*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ138*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK138*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL138*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM138*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN138*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO138*'Power Scaling'!F$4)*IF(P138=\"OFF\",0.06,1),VLOOKUP($A138&\"_\"&U$3,MDB,5,0)*$C138*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P138=\"OFF\",0.06,1)),0)","v":0},{"$f":"C138*IFERROR(IF($I138=\"SI\",(AE138*IF(S138=0,0,1)+(AF138-AE138)*S138)*IF(R138>0,R138,Q138)/Q138*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ138*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK138*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL138*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM138*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN138*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO138*'Power Scaling'!I$4)*AQ138,IF(OR($I138=\"AO\",$I138=\"LU\"),VLOOKUP($A138&\"_\"&\"vdd_dyn\"&\"_\"&$R138&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I138=\"LUUA\",$I138=\"LUUB\"),VLOOKUP($A138&\"_\"&\"vdd_dyn\"&\"_\"&$R138&\"\",MDB,5,0)*$C138*$S138*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A138&\"_\"&\"vdd_dyn\"&\"_\"&$R138&\"_idle\",MDB,5,0)*(1-$S138)+VLOOKUP($A138&\"_\"&\"vdd_dyn\"&\"_\"&$R138&\"_read\",MDB,5,0)*($S138/2)+VLOOKUP($A138&\"_\"&\"vdd_dyn\"&\"_\"&$R138&\"_write\",MDB,5,0)*($S138/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","eqep_2","CC$60",null,null,null,null,null,null,null,null,null,"CB$60","CD$60",2,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,56,"MAIN McSPI","Controller_3.125_Mbaud_3p3v",1,3]
["ethernet","_port_0",1,0,"VDD_CORE","N/A","VDDSHV1P8","VDDSHV3P3","LUUA","GP_Core_Ctl","Ethernet LVCMOS IO","10/30/2021","7 LVCMOS IO","Ethernet",25.37,"ON",0,"rgmii_1000_1p8v",1,14,{"$f":"IFERROR(IF($I139=\"SI\",AP139*$C139*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ139*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK139*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL139*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM139*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN139*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO139*'Power Scaling'!F$4)*IF(P139=\"OFF\",0.06,1),VLOOKUP($A139&\"_\"&U$3,MDB,5,0)*$C139*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P139=\"OFF\",0.06,1)),0)","v":0},{"$f":"C139*IFERROR(IF($I139=\"SI\",(AE139*IF(S139=0,0,1)+(AF139-AE139)*S139)*IF(R139>0,R139,Q139)/Q139*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ139*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK139*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL139*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM139*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN139*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO139*'Power Scaling'!I$4)*AQ139,IF(OR($I139=\"AO\",$I139=\"LU\"),VLOOKUP($A139&\"_\"&\"vdd_dyn\"&\"_\"&$R139&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I139=\"LUUA\",$I139=\"LUUB\"),VLOOKUP($A139&\"_\"&\"vdd_dyn\"&\"_\"&$R139&\"\",MDB,5,0)*$C139*$S139*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A139&\"_\"&\"vdd_dyn\"&\"_\"&$R139&\"_idle\",MDB,5,0)*(1-$S139)+VLOOKUP($A139&\"_\"&\"vdd_dyn\"&\"_\"&$R139&\"_read\",MDB,5,0)*($S139/2)+VLOOKUP($A139&\"_\"&\"vdd_dyn\"&\"_\"&$R139&\"_write\",MDB,5,0)*($S139/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},{"$f":"C139*IFERROR(IF($I139=\"SI\",(AE139*IF(S139=0,0,1)+(AF139-AE139)*S139)*VLOOKUP(\"vdd_sw\",pwr_scale_table,2,0)*AI139,0),0)","v":0},0,0,0,0,25.37,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","ethernet_port_0","CC$65",null,null,null,null,null,null,null,null,null,"CB$65","CD$65",0,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,57,"MAIN McASP","16Ch_TX_48_ksps_24b_3p3v",1,3]
["ethernet","_port_1",1,0,"VDD_CORE","N/A","VDDSHV1P8","VDDSHV3P3","LUUA","GP_Core_Ctl","Ethernet LVCMOS IO","10/30/2021","7 LVCMOS IO","Ethernet",25.37,"ON",0,"rgmii_1000_1p8v",1,14,{"$f":"IFERROR(IF($I140=\"SI\",AP140*$C140*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ140*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK140*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL140*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM140*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN140*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO140*'Power Scaling'!F$4)*IF(P140=\"OFF\",0.06,1),VLOOKUP($A140&\"_\"&U$3,MDB,5,0)*$C140*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P140=\"OFF\",0.06,1)),0)","v":0},{"$f":"C140*IFERROR(IF($I140=\"SI\",(AE140*IF(S140=0,0,1)+(AF140-AE140)*S140)*IF(R140>0,R140,Q140)/Q140*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ140*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK140*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL140*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM140*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN140*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO140*'Power Scaling'!I$4)*AQ140,IF(OR($I140=\"AO\",$I140=\"LU\"),VLOOKUP($A140&\"_\"&\"vdd_dyn\"&\"_\"&$R140&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I140=\"LUUA\",$I140=\"LUUB\"),VLOOKUP($A140&\"_\"&\"vdd_dyn\"&\"_\"&$R140&\"\",MDB,5,0)*$C140*$S140*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A140&\"_\"&\"vdd_dyn\"&\"_\"&$R140&\"_idle\",MDB,5,0)*(1-$S140)+VLOOKUP($A140&\"_\"&\"vdd_dyn\"&\"_\"&$R140&\"_read\",MDB,5,0)*($S140/2)+VLOOKUP($A140&\"_\"&\"vdd_dyn\"&\"_\"&$R140&\"_write\",MDB,5,0)*($S140/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,25.37,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","ethernet_port_1","CC$65",null,null,null,null,null,null,null,null,null,"CB$65","CD$65",1,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,58,"MAIN ECAP","unused",1,0]
["gpio","_0",240,0,"VDD_CORE","N/A","VDDSHV1P8","VDDSHV3P3","LUUA","GP_Core_Ctl","GPIO LVCMOS IO","10/30/2021","7 LVCMOS IO","GPIO",12.177216000000001,"ON",0,"1mbs_1p8v_20pf",1,1,{"$f":"IFERROR(IF($I141=\"SI\",AP141*$C141*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ141*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK141*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL141*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM141*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN141*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO141*'Power Scaling'!F$4)*IF(P141=\"OFF\",0.06,1),VLOOKUP($A141&\"_\"&U$3,MDB,5,0)*$C141*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P141=\"OFF\",0.06,1)),0)","v":0},{"$f":"C141*IFERROR(IF($I141=\"SI\",(AE141*IF(S141=0,0,1)+(AF141-AE141)*S141)*IF(R141>0,R141,Q141)/Q141*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ141*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK141*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL141*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM141*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN141*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO141*'Power Scaling'!I$4)*AQ141,IF(OR($I141=\"AO\",$I141=\"LU\"),VLOOKUP($A141&\"_\"&\"vdd_dyn\"&\"_\"&$R141&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I141=\"LUUA\",$I141=\"LUUB\"),VLOOKUP($A141&\"_\"&\"vdd_dyn\"&\"_\"&$R141&\"\",MDB,5,0)*$C141*$S141*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A141&\"_\"&\"vdd_dyn\"&\"_\"&$R141&\"_idle\",MDB,5,0)*(1-$S141)+VLOOKUP($A141&\"_\"&\"vdd_dyn\"&\"_\"&$R141&\"_read\",MDB,5,0)*($S141/2)+VLOOKUP($A141&\"_\"&\"vdd_dyn\"&\"_\"&$R141&\"_write\",MDB,5,0)*($S141/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,12.177216000000001,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","gpio_0","CC$53",null,null,null,null,null,null,null,null,null,"CB$53","CD$53",0,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,59,"MAIN EPWM","on_1p8v",1,3.0000000000000004]
["gpio","_1",240,0,"VDD_CORE","N/A","VDDSHV1P8","VDDSHV3P3","LUUA","GP_Core_Ctl","GPIO LVCMOS IO","10/30/2021","7 LVCMOS IO","GPIO",12.177216000000001,"ON",0,"1mbs_1p8v_20pf",1,1,{"$f":"IFERROR(IF($I142=\"SI\",AP142*$C142*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ142*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK142*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL142*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM142*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN142*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO142*'Power Scaling'!F$4)*IF(P142=\"OFF\",0.06,1),VLOOKUP($A142&\"_\"&U$3,MDB,5,0)*$C142*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P142=\"OFF\",0.06,1)),0)","v":0},{"$f":"C142*IFERROR(IF($I142=\"SI\",(AE142*IF(S142=0,0,1)+(AF142-AE142)*S142)*IF(R142>0,R142,Q142)/Q142*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ142*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK142*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL142*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM142*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN142*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO142*'Power Scaling'!I$4)*AQ142,IF(OR($I142=\"AO\",$I142=\"LU\"),VLOOKUP($A142&\"_\"&\"vdd_dyn\"&\"_\"&$R142&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I142=\"LUUA\",$I142=\"LUUB\"),VLOOKUP($A142&\"_\"&\"vdd_dyn\"&\"_\"&$R142&\"\",MDB,5,0)*$C142*$S142*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A142&\"_\"&\"vdd_dyn\"&\"_\"&$R142&\"_idle\",MDB,5,0)*(1-$S142)+VLOOKUP($A142&\"_\"&\"vdd_dyn\"&\"_\"&$R142&\"_read\",MDB,5,0)*($S142/2)+VLOOKUP($A142&\"_\"&\"vdd_dyn\"&\"_\"&$R142&\"_write\",MDB,5,0)*($S142/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,12.177216000000001,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","gpio_1","CC$53",null,null,null,null,null,null,null,null,null,"CB$53","CD$53",1,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,60,"MAIN EQEP","off",1,0]
["gpio","_mcu",150,0,"VDD_CORE","N/A","VDDSHV1P8","VDDSHV3P3","LUUA","GP_Core_Ctl","GPIO LVCMOS IO","10/30/2021","7 LVCMOS IO","GPIO",392.03999999999996,"ON",0,"1mbs_3p3v_20pf",1,1,{"$f":"IFERROR(IF($I143=\"SI\",AP143*$C143*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ143*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK143*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL143*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM143*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN143*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO143*'Power Scaling'!F$4)*IF(P143=\"OFF\",0.06,1),VLOOKUP($A143&\"_\"&U$3,MDB,5,0)*$C143*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P143=\"OFF\",0.06,1)),0)","v":0},{"$f":"C143*IFERROR(IF($I143=\"SI\",(AE143*IF(S143=0,0,1)+(AF143-AE143)*S143)*IF(R143>0,R143,Q143)/Q143*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ143*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK143*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL143*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM143*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN143*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO143*'Power Scaling'!I$4)*AQ143,IF(OR($I143=\"AO\",$I143=\"LU\"),VLOOKUP($A143&\"_\"&\"vdd_dyn\"&\"_\"&$R143&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I143=\"LUUA\",$I143=\"LUUB\"),VLOOKUP($A143&\"_\"&\"vdd_dyn\"&\"_\"&$R143&\"\",MDB,5,0)*$C143*$S143*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A143&\"_\"&\"vdd_dyn\"&\"_\"&$R143&\"_idle\",MDB,5,0)*(1-$S143)+VLOOKUP($A143&\"_\"&\"vdd_dyn\"&\"_\"&$R143&\"_read\",MDB,5,0)*($S143/2)+VLOOKUP($A143&\"_\"&\"vdd_dyn\"&\"_\"&$R143&\"_write\",MDB,5,0)*($S143/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,392.03999999999996,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","gpio_mcu","CC$50",null,null,null,null,null,null,null,null,null,"CB$50","CD$50",0,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,61,"MAIN MCAN","1mbs_3p3v",1,1]
["gpmc","_0",1,0,"VDD_CORE","N/A","VDDSHV1P8","VDDSHV3P3","LUUA","GP_Core_Ctl","GPMC LVCMOS IO","10/30/2021","7 LVCMOS IO","GPMC",0,"ON",0,{"$f":"IF(ISBLANK(BD144),\"unused\",INDIRECT(BD144))","v":"unused"},0,34,{"$f":"IFERROR(IF($I144=\"SI\",AP144*$C144*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ144*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK144*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL144*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM144*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN144*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO144*'Power Scaling'!F$4)*IF(P144=\"OFF\",0.06,1),VLOOKUP($A144&\"_\"&U$3,MDB,5,0)*$C144*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P144=\"OFF\",0.06,1)),0)","v":0},{"$f":"C144*IFERROR(IF($I144=\"SI\",(AE144*IF(S144=0,0,1)+(AF144-AE144)*S144)*IF(R144>0,R144,Q144)/Q144*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ144*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK144*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL144*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM144*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN144*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO144*'Power Scaling'!I$4)*AQ144,IF(OR($I144=\"AO\",$I144=\"LU\"),VLOOKUP($A144&\"_\"&\"vdd_dyn\"&\"_\"&$R144&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I144=\"LUUA\",$I144=\"LUUB\"),VLOOKUP($A144&\"_\"&\"vdd_dyn\"&\"_\"&$R144&\"\",MDB,5,0)*$C144*$S144*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A144&\"_\"&\"vdd_dyn\"&\"_\"&$R144&\"_idle\",MDB,5,0)*(1-$S144)+VLOOKUP($A144&\"_\"&\"vdd_dyn\"&\"_\"&$R144&\"_read\",MDB,5,0)*($S144/2)+VLOOKUP($A144&\"_\"&\"vdd_dyn\"&\"_\"&$R144&\"_write\",MDB,5,0)*($S144/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","gpmc_0","CG$26",null,null,null,null,null,null,null,null,null,"CF$26",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,62,"MAIN MMCSD1","hs200_200mbs",1,3]
["i2c","_0",1,0,"VDD_CORE","N/A","VDDSHV1P8","VDDSHV3P3","LUUA","GP_Core_Ctl","I2C LVCMOS IO","10/30/2021","7 LVCMOS IO","I2C",0.48107664,"ON",0,{"$f":"IF(ISBLANK(BD145),\"unused\",IF(INDIRECT(BE145)>BF145,INDIRECT(BD145),\"unused\"))","v":"i2c_400k_3p3v"},1,2,{"$f":"IFERROR(IF($I145=\"SI\",AP145*$C145*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ145*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK145*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL145*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM145*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN145*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO145*'Power Scaling'!F$4)*IF(P145=\"OFF\",0.06,1),VLOOKUP($A145&\"_\"&U$3,MDB,5,0)*$C145*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P145=\"OFF\",0.06,1)),0)","v":0},{"$f":"C145*IFERROR(IF($I145=\"SI\",(AE145*IF(S145=0,0,1)+(AF145-AE145)*S145)*IF(R145>0,R145,Q145)/Q145*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ145*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK145*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL145*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM145*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN145*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO145*'Power Scaling'!I$4)*AQ145,IF(OR($I145=\"AO\",$I145=\"LU\"),VLOOKUP($A145&\"_\"&\"vdd_dyn\"&\"_\"&$R145&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I145=\"LUUA\",$I145=\"LUUB\"),VLOOKUP($A145&\"_\"&\"vdd_dyn\"&\"_\"&$R145&\"\",MDB,5,0)*$C145*$S145*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A145&\"_\"&\"vdd_dyn\"&\"_\"&$R145&\"_idle\",MDB,5,0)*(1-$S145)+VLOOKUP($A145&\"_\"&\"vdd_dyn\"&\"_\"&$R145&\"_read\",MDB,5,0)*($S145/2)+VLOOKUP($A145&\"_\"&\"vdd_dyn\"&\"_\"&$R145&\"_write\",MDB,5,0)*($S145/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0.48107664,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","i2c_0","CC$54",null,null,null,null,null,null,null,null,null,"CB$54","CD$54",0,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,63,"MAIN DSS 0: DPI","HD_|_1280x720x60_fps_24b_|_3p3V",1,1]
["i2c","_1",1,0,"VDD_CORE","N/A","VDDSHV1P8","VDDSHV3P3","LUUA","GP_Core_Ctl","I2C LVCMOS IO","10/30/2021","7 LVCMOS IO","I2C",0.48107664,"ON",0,"i2c_400k_3p3v",1,2,{"$f":"IFERROR(IF($I146=\"SI\",AP146*$C146*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ146*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK146*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL146*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM146*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN146*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO146*'Power Scaling'!F$4)*IF(P146=\"OFF\",0.06,1),VLOOKUP($A146&\"_\"&U$3,MDB,5,0)*$C146*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P146=\"OFF\",0.06,1)),0)","v":0},{"$f":"C146*IFERROR(IF($I146=\"SI\",(AE146*IF(S146=0,0,1)+(AF146-AE146)*S146)*IF(R146>0,R146,Q146)/Q146*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ146*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK146*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL146*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM146*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN146*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO146*'Power Scaling'!I$4)*AQ146,IF(OR($I146=\"AO\",$I146=\"LU\"),VLOOKUP($A146&\"_\"&\"vdd_dyn\"&\"_\"&$R146&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I146=\"LUUA\",$I146=\"LUUB\"),VLOOKUP($A146&\"_\"&\"vdd_dyn\"&\"_\"&$R146&\"\",MDB,5,0)*$C146*$S146*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A146&\"_\"&\"vdd_dyn\"&\"_\"&$R146&\"_idle\",MDB,5,0)*(1-$S146)+VLOOKUP($A146&\"_\"&\"vdd_dyn\"&\"_\"&$R146&\"_read\",MDB,5,0)*($S146/2)+VLOOKUP($A146&\"_\"&\"vdd_dyn\"&\"_\"&$R146&\"_write\",MDB,5,0)*($S146/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0.48107664,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","i2c_1","CC$54",null,null,null,null,null,null,null,null,null,"CB$54","CD$54",1,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,64,"MAIN FSS OSPI1 (QSPI)","ospi_ddr_controller_133_3p3v",1,1]
["i2c","_2",1,0,"VDD_CORE","N/A","VDDSHV1P8","VDDSHV3P3","LUUA","GP_Core_Ctl","I2C LVCMOS IO","10/30/2021","7 LVCMOS IO","I2C",0.48107664,"ON",0,"i2c_400k_3p3v",1,2,{"$f":"IFERROR(IF($I147=\"SI\",AP147*$C147*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ147*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK147*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL147*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM147*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN147*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO147*'Power Scaling'!F$4)*IF(P147=\"OFF\",0.06,1),VLOOKUP($A147&\"_\"&U$3,MDB,5,0)*$C147*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P147=\"OFF\",0.06,1)),0)","v":0},{"$f":"C147*IFERROR(IF($I147=\"SI\",(AE147*IF(S147=0,0,1)+(AF147-AE147)*S147)*IF(R147>0,R147,Q147)/Q147*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ147*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK147*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL147*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM147*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN147*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO147*'Power Scaling'!I$4)*AQ147,IF(OR($I147=\"AO\",$I147=\"LU\"),VLOOKUP($A147&\"_\"&\"vdd_dyn\"&\"_\"&$R147&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I147=\"LUUA\",$I147=\"LUUB\"),VLOOKUP($A147&\"_\"&\"vdd_dyn\"&\"_\"&$R147&\"\",MDB,5,0)*$C147*$S147*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A147&\"_\"&\"vdd_dyn\"&\"_\"&$R147&\"_idle\",MDB,5,0)*(1-$S147)+VLOOKUP($A147&\"_\"&\"vdd_dyn\"&\"_\"&$R147&\"_read\",MDB,5,0)*($S147/2)+VLOOKUP($A147&\"_\"&\"vdd_dyn\"&\"_\"&$R147&\"_write\",MDB,5,0)*($S147/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0.48107664,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","i2c_2","CC$54",null,null,null,null,null,null,null,null,null,"CB$54","CD$54",2,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,65,"MAIN Ethernet","rgmii_1000_1p8v",1,2]
["i2c","_3",1,0,"VDD_CORE","N/A","VDDSHV1P8","VDDSHV3P3","LUUA","GP_Core_Ctl","I2C LVCMOS IO","10/30/2021","7 LVCMOS IO","I2C",0,"ON",0,"unused",0,2,{"$f":"IFERROR(IF($I148=\"SI\",AP148*$C148*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ148*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK148*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL148*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM148*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN148*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO148*'Power Scaling'!F$4)*IF(P148=\"OFF\",0.06,1),VLOOKUP($A148&\"_\"&U$3,MDB,5,0)*$C148*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P148=\"OFF\",0.06,1)),0)","v":0},{"$f":"C148*IFERROR(IF($I148=\"SI\",(AE148*IF(S148=0,0,1)+(AF148-AE148)*S148)*IF(R148>0,R148,Q148)/Q148*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ148*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK148*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL148*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM148*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN148*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO148*'Power Scaling'!I$4)*AQ148,IF(OR($I148=\"AO\",$I148=\"LU\"),VLOOKUP($A148&\"_\"&\"vdd_dyn\"&\"_\"&$R148&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I148=\"LUUA\",$I148=\"LUUB\"),VLOOKUP($A148&\"_\"&\"vdd_dyn\"&\"_\"&$R148&\"\",MDB,5,0)*$C148*$S148*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A148&\"_\"&\"vdd_dyn\"&\"_\"&$R148&\"_idle\",MDB,5,0)*(1-$S148)+VLOOKUP($A148&\"_\"&\"vdd_dyn\"&\"_\"&$R148&\"_read\",MDB,5,0)*($S148/2)+VLOOKUP($A148&\"_\"&\"vdd_dyn\"&\"_\"&$R148&\"_write\",MDB,5,0)*($S148/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","i2c_3","CC$54",null,null,null,null,null,null,null,null,null,"CB$54","CD$54",3]
[{"$error":"#N/A"},{"$error":"#N/A"},0,{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},0,{"$error":"#N/A"},0,"unused",0,2,{"$f":"IFERROR(IF($I149=\"SI\",AP149*$C149*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ149*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK149*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL149*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM149*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN149*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO149*'Power Scaling'!F$4)*IF(P149=\"OFF\",0.06,1),VLOOKUP($A149&\"_\"&U$3,MDB,5,0)*$C149*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P149=\"OFF\",0.06,1)),0)","v":0},{"$f":"C149*IFERROR(IF($I149=\"SI\",(AE149*IF(S149=0,0,1)+(AF149-AE149)*S149)*IF(R149>0,R149,Q149)/Q149*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ149*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK149*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL149*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM149*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN149*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO149*'Power Scaling'!I$4)*AQ149,IF(OR($I149=\"AO\",$I149=\"LU\"),VLOOKUP($A149&\"_\"&\"vdd_dyn\"&\"_\"&$R149&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I149=\"LUUA\",$I149=\"LUUB\"),VLOOKUP($A149&\"_\"&\"vdd_dyn\"&\"_\"&$R149&\"\",MDB,5,0)*$C149*$S149*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A149&\"_\"&\"vdd_dyn\"&\"_\"&$R149&\"_idle\",MDB,5,0)*(1-$S149)+VLOOKUP($A149&\"_\"&\"vdd_dyn\"&\"_\"&$R149&\"_read\",MDB,5,0)*($S149/2)+VLOOKUP($A149&\"_\"&\"vdd_dyn\"&\"_\"&$R149&\"_write\",MDB,5,0)*($S149/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,{"$error":"#N/A"},{"$error":"#N/A"},"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.",{"$error":"#N/A"},"CC$54",null,null,null,null,null,null,null,null,null,"CB$54","CD$54",4]
["i2c_od","_mcu_0",1,0,"VDD_CORE","N/A","VDDSHV1P8_MCU","VDDSHV3P3_MCU","LUUA","GP_Core_Ctl","I2C_OD LVCMOS IO","10/30/2021","7 LVCMOS IO","I2C with OD",0.23957999999999999,"ON",0,"i2c_400k_3p3v",1,2,{"$f":"IFERROR(IF($I150=\"SI\",AP150*$C150*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ150*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK150*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL150*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM150*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN150*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO150*'Power Scaling'!F$4)*IF(P150=\"OFF\",0.06,1),VLOOKUP($A150&\"_\"&U$3,MDB,5,0)*$C150*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P150=\"OFF\",0.06,1)),0)","v":0},{"$f":"C150*IFERROR(IF($I150=\"SI\",(AE150*IF(S150=0,0,1)+(AF150-AE150)*S150)*IF(R150>0,R150,Q150)/Q150*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ150*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK150*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL150*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM150*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN150*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO150*'Power Scaling'!I$4)*AQ150,IF(OR($I150=\"AO\",$I150=\"LU\"),VLOOKUP($A150&\"_\"&\"vdd_dyn\"&\"_\"&$R150&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I150=\"LUUA\",$I150=\"LUUB\"),VLOOKUP($A150&\"_\"&\"vdd_dyn\"&\"_\"&$R150&\"\",MDB,5,0)*$C150*$S150*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A150&\"_\"&\"vdd_dyn\"&\"_\"&$R150&\"_idle\",MDB,5,0)*(1-$S150)+VLOOKUP($A150&\"_\"&\"vdd_dyn\"&\"_\"&$R150&\"_read\",MDB,5,0)*($S150/2)+VLOOKUP($A150&\"_\"&\"vdd_dyn\"&\"_\"&$R150&\"_write\",MDB,5,0)*($S150/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0.23957999999999999,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","i2c_od_mcu_0","CC$46",null,null,null,null,null,null,null,null,null,"CB$46","CD$46",0]
["i2c_od","_wkp_0",1,0,"VDD_CORE","N/A","VDDSHV1P8_MCU","VDDSHV3P3_MCU","LUUA","GP_Core_Ctl","I2C_OD LVCMOS IO","10/30/2021","7 LVCMOS IO","I2C with OD",0.23957999999999999,"ON",0,"i2c_400k_3p3v",1,2,{"$f":"IFERROR(IF($I151=\"SI\",AP151*$C151*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ151*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK151*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL151*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM151*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN151*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO151*'Power Scaling'!F$4)*IF(P151=\"OFF\",0.06,1),VLOOKUP($A151&\"_\"&U$3,MDB,5,0)*$C151*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P151=\"OFF\",0.06,1)),0)","v":0},{"$f":"C151*IFERROR(IF($I151=\"SI\",(AE151*IF(S151=0,0,1)+(AF151-AE151)*S151)*IF(R151>0,R151,Q151)/Q151*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ151*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK151*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL151*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM151*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN151*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO151*'Power Scaling'!I$4)*AQ151,IF(OR($I151=\"AO\",$I151=\"LU\"),VLOOKUP($A151&\"_\"&\"vdd_dyn\"&\"_\"&$R151&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I151=\"LUUA\",$I151=\"LUUB\"),VLOOKUP($A151&\"_\"&\"vdd_dyn\"&\"_\"&$R151&\"\",MDB,5,0)*$C151*$S151*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A151&\"_\"&\"vdd_dyn\"&\"_\"&$R151&\"_idle\",MDB,5,0)*(1-$S151)+VLOOKUP($A151&\"_\"&\"vdd_dyn\"&\"_\"&$R151&\"_read\",MDB,5,0)*($S151/2)+VLOOKUP($A151&\"_\"&\"vdd_dyn\"&\"_\"&$R151&\"_write\",MDB,5,0)*($S151/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0.23957999999999999,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","i2c_od_wkp_0","CC$44",null,null,null,null,null,null,null,null,null,"CB$44","CD$44",0]
["mcasp","_0",1,0,"VDD_CORE","N/A","VDDSHV1P8","VDDSHV3P3","LUUA","GP_Core_Ctl","McASP LVCMOS IO","10/30/2021","7 LVCMOS IO","McASP",5.5226831619999999,"ON",0,"16Ch_TX_48_ksps_24b_3p3v",1,10,{"$f":"IFERROR(IF($I152=\"SI\",AP152*$C152*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ152*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK152*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL152*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM152*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN152*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO152*'Power Scaling'!F$4)*IF(P152=\"OFF\",0.06,1),VLOOKUP($A152&\"_\"&U$3,MDB,5,0)*$C152*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P152=\"OFF\",0.06,1)),0)","v":0},{"$f":"C152*IFERROR(IF($I152=\"SI\",(AE152*IF(S152=0,0,1)+(AF152-AE152)*S152)*IF(R152>0,R152,Q152)/Q152*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ152*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK152*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL152*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM152*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN152*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO152*'Power Scaling'!I$4)*AQ152,IF(OR($I152=\"AO\",$I152=\"LU\"),VLOOKUP($A152&\"_\"&\"vdd_dyn\"&\"_\"&$R152&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I152=\"LUUA\",$I152=\"LUUB\"),VLOOKUP($A152&\"_\"&\"vdd_dyn\"&\"_\"&$R152&\"\",MDB,5,0)*$C152*$S152*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A152&\"_\"&\"vdd_dyn\"&\"_\"&$R152&\"_idle\",MDB,5,0)*(1-$S152)+VLOOKUP($A152&\"_\"&\"vdd_dyn\"&\"_\"&$R152&\"_read\",MDB,5,0)*($S152/2)+VLOOKUP($A152&\"_\"&\"vdd_dyn\"&\"_\"&$R152&\"_write\",MDB,5,0)*($S152/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,5.5226831619999999,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","mcasp_0","CC$57",null,null,null,null,null,null,null,null,null,"CB$57","CD$57",0]
["mcasp","_1",1,0,"VDD_CORE","N/A","VDDSHV1P8","VDDSHV3P3","LUUA","GP_Core_Ctl","McASP LVCMOS IO","10/30/2021","7 LVCMOS IO","McASP",5.5226831619999999,"ON",0,"16Ch_TX_48_ksps_24b_3p3v",1,10,{"$f":"IFERROR(IF($I153=\"SI\",AP153*$C153*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ153*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK153*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL153*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM153*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN153*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO153*'Power Scaling'!F$4)*IF(P153=\"OFF\",0.06,1),VLOOKUP($A153&\"_\"&U$3,MDB,5,0)*$C153*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P153=\"OFF\",0.06,1)),0)","v":0},{"$f":"C153*IFERROR(IF($I153=\"SI\",(AE153*IF(S153=0,0,1)+(AF153-AE153)*S153)*IF(R153>0,R153,Q153)/Q153*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ153*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK153*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL153*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM153*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN153*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO153*'Power Scaling'!I$4)*AQ153,IF(OR($I153=\"AO\",$I153=\"LU\"),VLOOKUP($A153&\"_\"&\"vdd_dyn\"&\"_\"&$R153&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I153=\"LUUA\",$I153=\"LUUB\"),VLOOKUP($A153&\"_\"&\"vdd_dyn\"&\"_\"&$R153&\"\",MDB,5,0)*$C153*$S153*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A153&\"_\"&\"vdd_dyn\"&\"_\"&$R153&\"_idle\",MDB,5,0)*(1-$S153)+VLOOKUP($A153&\"_\"&\"vdd_dyn\"&\"_\"&$R153&\"_read\",MDB,5,0)*($S153/2)+VLOOKUP($A153&\"_\"&\"vdd_dyn\"&\"_\"&$R153&\"_write\",MDB,5,0)*($S153/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,5.5226831619999999,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","mcasp_1","CC$57",null,null,null,null,null,null,null,null,null,"CB$57","CD$57",1]
["mcasp","_2",1,0,"VDD_CORE","N/A","VDDSHV1P8","VDDSHV3P3","LUUA","GP_Core_Ctl","McASP LVCMOS IO","10/30/2021","7 LVCMOS IO","McASP",5.5226831619999999,"ON",0,"16Ch_TX_48_ksps_24b_3p3v",1,10,{"$f":"IFERROR(IF($I154=\"SI\",AP154*$C154*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ154*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK154*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL154*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM154*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN154*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO154*'Power Scaling'!F$4)*IF(P154=\"OFF\",0.06,1),VLOOKUP($A154&\"_\"&U$3,MDB,5,0)*$C154*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P154=\"OFF\",0.06,1)),0)","v":0},{"$f":"C154*IFERROR(IF($I154=\"SI\",(AE154*IF(S154=0,0,1)+(AF154-AE154)*S154)*IF(R154>0,R154,Q154)/Q154*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ154*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK154*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL154*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM154*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN154*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO154*'Power Scaling'!I$4)*AQ154,IF(OR($I154=\"AO\",$I154=\"LU\"),VLOOKUP($A154&\"_\"&\"vdd_dyn\"&\"_\"&$R154&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I154=\"LUUA\",$I154=\"LUUB\"),VLOOKUP($A154&\"_\"&\"vdd_dyn\"&\"_\"&$R154&\"\",MDB,5,0)*$C154*$S154*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A154&\"_\"&\"vdd_dyn\"&\"_\"&$R154&\"_idle\",MDB,5,0)*(1-$S154)+VLOOKUP($A154&\"_\"&\"vdd_dyn\"&\"_\"&$R154&\"_read\",MDB,5,0)*($S154/2)+VLOOKUP($A154&\"_\"&\"vdd_dyn\"&\"_\"&$R154&\"_write\",MDB,5,0)*($S154/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,5.5226831619999999,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","mcasp_2","CC$57",null,null,null,null,null,null,null,null,null,"CB$57","CD$57",2]
[{"$error":"#N/A"},{"$error":"#N/A"},0,{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},0,{"$error":"#N/A"},0,"unused",0,10,{"$f":"IFERROR(IF($I155=\"SI\",AP155*$C155*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ155*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK155*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL155*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM155*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN155*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO155*'Power Scaling'!F$4)*IF(P155=\"OFF\",0.06,1),VLOOKUP($A155&\"_\"&U$3,MDB,5,0)*$C155*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P155=\"OFF\",0.06,1)),0)","v":0},{"$f":"C155*IFERROR(IF($I155=\"SI\",(AE155*IF(S155=0,0,1)+(AF155-AE155)*S155)*IF(R155>0,R155,Q155)/Q155*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ155*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK155*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL155*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM155*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN155*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO155*'Power Scaling'!I$4)*AQ155,IF(OR($I155=\"AO\",$I155=\"LU\"),VLOOKUP($A155&\"_\"&\"vdd_dyn\"&\"_\"&$R155&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I155=\"LUUA\",$I155=\"LUUB\"),VLOOKUP($A155&\"_\"&\"vdd_dyn\"&\"_\"&$R155&\"\",MDB,5,0)*$C155*$S155*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A155&\"_\"&\"vdd_dyn\"&\"_\"&$R155&\"_idle\",MDB,5,0)*(1-$S155)+VLOOKUP($A155&\"_\"&\"vdd_dyn\"&\"_\"&$R155&\"_read\",MDB,5,0)*($S155/2)+VLOOKUP($A155&\"_\"&\"vdd_dyn\"&\"_\"&$R155&\"_write\",MDB,5,0)*($S155/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,{"$error":"#N/A"},{"$error":"#N/A"},"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.",{"$error":"#N/A"},"CC$57",null,null,null,null,null,null,null,null,null,"CB$57","CD$57",3]
[{"$error":"#N/A"},{"$error":"#N/A"},0,{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},{"$error":"#N/A"},0,{"$error":"#N/A"},0,"unused",0,10,{"$f":"IFERROR(IF($I156=\"SI\",AP156*$C156*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ156*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK156*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL156*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM156*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN156*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO156*'Power Scaling'!F$4)*IF(P156=\"OFF\",0.06,1),VLOOKUP($A156&\"_\"&U$3,MDB,5,0)*$C156*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P156=\"OFF\",0.06,1)),0)","v":0},{"$f":"C156*IFERROR(IF($I156=\"SI\",(AE156*IF(S156=0,0,1)+(AF156-AE156)*S156)*IF(R156>0,R156,Q156)/Q156*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ156*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK156*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL156*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM156*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN156*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO156*'Power Scaling'!I$4)*AQ156,IF(OR($I156=\"AO\",$I156=\"LU\"),VLOOKUP($A156&\"_\"&\"vdd_dyn\"&\"_\"&$R156&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I156=\"LUUA\",$I156=\"LUUB\"),VLOOKUP($A156&\"_\"&\"vdd_dyn\"&\"_\"&$R156&\"\",MDB,5,0)*$C156*$S156*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A156&\"_\"&\"vdd_dyn\"&\"_\"&$R156&\"_idle\",MDB,5,0)*(1-$S156)+VLOOKUP($A156&\"_\"&\"vdd_dyn\"&\"_\"&$R156&\"_read\",MDB,5,0)*($S156/2)+VLOOKUP($A156&\"_\"&\"vdd_dyn\"&\"_\"&$R156&\"_write\",MDB,5,0)*($S156/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,{"$error":"#N/A"},{"$error":"#N/A"},"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.",{"$error":"#N/A"},"CC$57",null,null,null,null,null,null,null,null,null,"CB$57","CD$57",4]
["fssul","_0",1,0,"VDD_CORE","N/A","VDDSHV1P8","VDDSHV3P3","LUUA","GP_Core_Ctl","FSSUL LVCMOS IO","10/30/2021","7 LVCMOS IO","OSPI/QSPI",52.150879240000002,"ON",0,"ospi_ddr_controller_133_3p3v",1,10,{"$f":"IFERROR(IF($I157=\"SI\",AP157*$C157*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ157*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK157*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL157*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM157*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN157*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO157*'Power Scaling'!F$4)*IF(P157=\"OFF\",0.06,1),VLOOKUP($A157&\"_\"&U$3,MDB,5,0)*$C157*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P157=\"OFF\",0.06,1)),0)","v":0},{"$f":"C157*IFERROR(IF($I157=\"SI\",(AE157*IF(S157=0,0,1)+(AF157-AE157)*S157)*IF(R157>0,R157,Q157)/Q157*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ157*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK157*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL157*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM157*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN157*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO157*'Power Scaling'!I$4)*AQ157,IF(OR($I157=\"AO\",$I157=\"LU\"),VLOOKUP($A157&\"_\"&\"vdd_dyn\"&\"_\"&$R157&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I157=\"LUUA\",$I157=\"LUUB\"),VLOOKUP($A157&\"_\"&\"vdd_dyn\"&\"_\"&$R157&\"\",MDB,5,0)*$C157*$S157*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A157&\"_\"&\"vdd_dyn\"&\"_\"&$R157&\"_idle\",MDB,5,0)*(1-$S157)+VLOOKUP($A157&\"_\"&\"vdd_dyn\"&\"_\"&$R157&\"_read\",MDB,5,0)*($S157/2)+VLOOKUP($A157&\"_\"&\"vdd_dyn\"&\"_\"&$R157&\"_write\",MDB,5,0)*($S157/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,52.150879240000002,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","fssul_0","CC$64",null,null,null,null,null,null,null,null,null,"CB$64","CD$64",0]
["spi","_0",1,0,"VDD_CORE","N/A","VDDSHV1P8","VDDSHV3P3","LUUA","GP_Core_Ctl","SPI LVCMOS IO","10/30/2021","7 LVCMOS IO","SPI",3.7435872379999999,"ON",0,"Controller_3.125_Mbaud_3p3v",1,4,{"$f":"IFERROR(IF($I158=\"SI\",AP158*$C158*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ158*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK158*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL158*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM158*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN158*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO158*'Power Scaling'!F$4)*IF(P158=\"OFF\",0.06,1),VLOOKUP($A158&\"_\"&U$3,MDB,5,0)*$C158*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P158=\"OFF\",0.06,1)),0)","v":0},{"$f":"C158*IFERROR(IF($I158=\"SI\",(AE158*IF(S158=0,0,1)+(AF158-AE158)*S158)*IF(R158>0,R158,Q158)/Q158*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ158*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK158*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL158*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM158*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN158*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO158*'Power Scaling'!I$4)*AQ158,IF(OR($I158=\"AO\",$I158=\"LU\"),VLOOKUP($A158&\"_\"&\"vdd_dyn\"&\"_\"&$R158&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I158=\"LUUA\",$I158=\"LUUB\"),VLOOKUP($A158&\"_\"&\"vdd_dyn\"&\"_\"&$R158&\"\",MDB,5,0)*$C158*$S158*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A158&\"_\"&\"vdd_dyn\"&\"_\"&$R158&\"_idle\",MDB,5,0)*(1-$S158)+VLOOKUP($A158&\"_\"&\"vdd_dyn\"&\"_\"&$R158&\"_read\",MDB,5,0)*($S158/2)+VLOOKUP($A158&\"_\"&\"vdd_dyn\"&\"_\"&$R158&\"_write\",MDB,5,0)*($S158/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,3.7435872379999999,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","spi_0","CC$56",null,null,null,null,null,null,null,null,null,"CB$56","CD$56",0]
["spi","_1",1,0,"VDD_CORE","N/A","VDDSHV1P8","VDDSHV3P3","LUUA","GP_Core_Ctl","SPI LVCMOS IO","10/30/2021","7 LVCMOS IO","SPI",3.7435872379999999,"ON",0,"Controller_3.125_Mbaud_3p3v",1,4,{"$f":"IFERROR(IF($I159=\"SI\",AP159*$C159*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ159*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK159*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL159*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM159*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN159*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO159*'Power Scaling'!F$4)*IF(P159=\"OFF\",0.06,1),VLOOKUP($A159&\"_\"&U$3,MDB,5,0)*$C159*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P159=\"OFF\",0.06,1)),0)","v":0},{"$f":"C159*IFERROR(IF($I159=\"SI\",(AE159*IF(S159=0,0,1)+(AF159-AE159)*S159)*IF(R159>0,R159,Q159)/Q159*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ159*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK159*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL159*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM159*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN159*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO159*'Power Scaling'!I$4)*AQ159,IF(OR($I159=\"AO\",$I159=\"LU\"),VLOOKUP($A159&\"_\"&\"vdd_dyn\"&\"_\"&$R159&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I159=\"LUUA\",$I159=\"LUUB\"),VLOOKUP($A159&\"_\"&\"vdd_dyn\"&\"_\"&$R159&\"\",MDB,5,0)*$C159*$S159*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A159&\"_\"&\"vdd_dyn\"&\"_\"&$R159&\"_idle\",MDB,5,0)*(1-$S159)+VLOOKUP($A159&\"_\"&\"vdd_dyn\"&\"_\"&$R159&\"_read\",MDB,5,0)*($S159/2)+VLOOKUP($A159&\"_\"&\"vdd_dyn\"&\"_\"&$R159&\"_write\",MDB,5,0)*($S159/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,3.7435872379999999,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","spi_1","CC$56",null,null,null,null,null,null,null,null,null,"CB$56","CD$56",1]
["spi","_2",1,0,"VDD_CORE","N/A","VDDSHV1P8","VDDSHV3P3","LUUA","GP_Core_Ctl","SPI LVCMOS IO","10/30/2021","7 LVCMOS IO","SPI",3.7435872379999999,"ON",0,"Controller_3.125_Mbaud_3p3v",1,4,{"$f":"IFERROR(IF($I160=\"SI\",AP160*$C160*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ160*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK160*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL160*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM160*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN160*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO160*'Power Scaling'!F$4)*IF(P160=\"OFF\",0.06,1),VLOOKUP($A160&\"_\"&U$3,MDB,5,0)*$C160*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P160=\"OFF\",0.06,1)),0)","v":0},{"$f":"C160*IFERROR(IF($I160=\"SI\",(AE160*IF(S160=0,0,1)+(AF160-AE160)*S160)*IF(R160>0,R160,Q160)/Q160*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ160*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK160*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL160*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM160*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN160*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO160*'Power Scaling'!I$4)*AQ160,IF(OR($I160=\"AO\",$I160=\"LU\"),VLOOKUP($A160&\"_\"&\"vdd_dyn\"&\"_\"&$R160&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I160=\"LUUA\",$I160=\"LUUB\"),VLOOKUP($A160&\"_\"&\"vdd_dyn\"&\"_\"&$R160&\"\",MDB,5,0)*$C160*$S160*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A160&\"_\"&\"vdd_dyn\"&\"_\"&$R160&\"_idle\",MDB,5,0)*(1-$S160)+VLOOKUP($A160&\"_\"&\"vdd_dyn\"&\"_\"&$R160&\"_read\",MDB,5,0)*($S160/2)+VLOOKUP($A160&\"_\"&\"vdd_dyn\"&\"_\"&$R160&\"_write\",MDB,5,0)*($S160/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,3.7435872379999999,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","spi_2","CC$56",null,null,null,null,null,null,null,null,null,"CB$56","CD$56",2]
["spi","_mcu_0",1,0,"VDD_CORE","N/A","VDDSHV1P8_MCU","VDDSHV3P3_MCU","LUUA","GP_Core_Ctl","SPI LVCMOS IO","10/30/2021","7 LVCMOS IO","SPI",2.4953255090000002,"ON",0,"Controller_2.083_Mbaud_3p3v",1,4,{"$f":"IFERROR(IF($I161=\"SI\",AP161*$C161*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ161*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK161*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL161*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM161*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN161*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO161*'Power Scaling'!F$4)*IF(P161=\"OFF\",0.06,1),VLOOKUP($A161&\"_\"&U$3,MDB,5,0)*$C161*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P161=\"OFF\",0.06,1)),0)","v":0},{"$f":"C161*IFERROR(IF($I161=\"SI\",(AE161*IF(S161=0,0,1)+(AF161-AE161)*S161)*IF(R161>0,R161,Q161)/Q161*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ161*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK161*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL161*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM161*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN161*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO161*'Power Scaling'!I$4)*AQ161,IF(OR($I161=\"AO\",$I161=\"LU\"),VLOOKUP($A161&\"_\"&\"vdd_dyn\"&\"_\"&$R161&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I161=\"LUUA\",$I161=\"LUUB\"),VLOOKUP($A161&\"_\"&\"vdd_dyn\"&\"_\"&$R161&\"\",MDB,5,0)*$C161*$S161*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A161&\"_\"&\"vdd_dyn\"&\"_\"&$R161&\"_idle\",MDB,5,0)*(1-$S161)+VLOOKUP($A161&\"_\"&\"vdd_dyn\"&\"_\"&$R161&\"_read\",MDB,5,0)*($S161/2)+VLOOKUP($A161&\"_\"&\"vdd_dyn\"&\"_\"&$R161&\"_write\",MDB,5,0)*($S161/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,2.4953255090000002,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","spi_mcu_0","CC$48",null,null,null,null,null,null,null,null,null,"CB$48","CD$48",0]
["spi","_mcu_1",1,0,"VDD_CORE","N/A","VDDSHV1P8_MCU","VDDSHV3P3_MCU","LUUA","GP_Core_Ctl","SPI LVCMOS IO","10/30/2021","7 LVCMOS IO","SPI",0,"ON",0,"unused",0,4,{"$f":"IFERROR(IF($I162=\"SI\",AP162*$C162*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ162*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK162*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL162*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM162*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN162*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO162*'Power Scaling'!F$4)*IF(P162=\"OFF\",0.06,1),VLOOKUP($A162&\"_\"&U$3,MDB,5,0)*$C162*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P162=\"OFF\",0.06,1)),0)","v":0},{"$f":"C162*IFERROR(IF($I162=\"SI\",(AE162*IF(S162=0,0,1)+(AF162-AE162)*S162)*IF(R162>0,R162,Q162)/Q162*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ162*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK162*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL162*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM162*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN162*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO162*'Power Scaling'!I$4)*AQ162,IF(OR($I162=\"AO\",$I162=\"LU\"),VLOOKUP($A162&\"_\"&\"vdd_dyn\"&\"_\"&$R162&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I162=\"LUUA\",$I162=\"LUUB\"),VLOOKUP($A162&\"_\"&\"vdd_dyn\"&\"_\"&$R162&\"\",MDB,5,0)*$C162*$S162*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A162&\"_\"&\"vdd_dyn\"&\"_\"&$R162&\"_idle\",MDB,5,0)*(1-$S162)+VLOOKUP($A162&\"_\"&\"vdd_dyn\"&\"_\"&$R162&\"_read\",MDB,5,0)*($S162/2)+VLOOKUP($A162&\"_\"&\"vdd_dyn\"&\"_\"&$R162&\"_write\",MDB,5,0)*($S162/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","spi_mcu_1","CC$48",null,null,null,null,null,null,null,null,null,"CB$48","CD$48",1]
["uart","_1",1,0,"VDD_CORE","N/A","VDDSHV1P8","VDDSHV3P3","LUUA","GP_Core_Ctl","UART LVCMOS IO","10/30/2021","7 LVCMOS IO","uart",0.15008418700000001,"ON",0,"3p6m_1p8v",1,4,{"$f":"IFERROR(IF($I163=\"SI\",AP163*$C163*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ163*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK163*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL163*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM163*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN163*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO163*'Power Scaling'!F$4)*IF(P163=\"OFF\",0.06,1),VLOOKUP($A163&\"_\"&U$3,MDB,5,0)*$C163*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P163=\"OFF\",0.06,1)),0)","v":0},{"$f":"C163*IFERROR(IF($I163=\"SI\",(AE163*IF(S163=0,0,1)+(AF163-AE163)*S163)*IF(R163>0,R163,Q163)/Q163*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ163*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK163*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL163*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM163*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN163*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO163*'Power Scaling'!I$4)*AQ163,IF(OR($I163=\"AO\",$I163=\"LU\"),VLOOKUP($A163&\"_\"&\"vdd_dyn\"&\"_\"&$R163&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I163=\"LUUA\",$I163=\"LUUB\"),VLOOKUP($A163&\"_\"&\"vdd_dyn\"&\"_\"&$R163&\"\",MDB,5,0)*$C163*$S163*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A163&\"_\"&\"vdd_dyn\"&\"_\"&$R163&\"_idle\",MDB,5,0)*(1-$S163)+VLOOKUP($A163&\"_\"&\"vdd_dyn\"&\"_\"&$R163&\"_read\",MDB,5,0)*($S163/2)+VLOOKUP($A163&\"_\"&\"vdd_dyn\"&\"_\"&$R163&\"_write\",MDB,5,0)*($S163/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0.15008418700000001,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","uart_1","CC$55",null,null,null,null,null,null,null,null,null,"CB$55","CD$55",1]
["uart","_2",1,0,"VDD_CORE","N/A","VDDSHV1P8","VDDSHV3P3","LUUA","GP_Core_Ctl","UART LVCMOS IO","10/30/2021","7 LVCMOS IO","uart",{"$f":"SUM(U164:AD164)","v":0.15008418700000001},{"$f":"INDEX(PD_State_Table,MATCH(J164,PD_Table_Row_Header,0),2)","v":"ON"},0,"3p6m_1p8v",1,4,{"$f":"IFERROR(IF($I164=\"SI\",AP164*$C164*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ164*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK164*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL164*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM164*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN164*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO164*'Power Scaling'!F$4)*IF(P164=\"OFF\",0.06,1),VLOOKUP($A164&\"_\"&U$3,MDB,5,0)*$C164*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P164=\"OFF\",0.06,1)),0)","v":0},{"$f":"C164*IFERROR(IF($I164=\"SI\",(AE164*IF(S164=0,0,1)+(AF164-AE164)*S164)*IF(R164>0,R164,Q164)/Q164*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ164*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK164*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL164*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM164*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN164*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO164*'Power Scaling'!I$4)*AQ164,IF(OR($I164=\"AO\",$I164=\"LU\"),VLOOKUP($A164&\"_\"&\"vdd_dyn\"&\"_\"&$R164&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I164=\"LUUA\",$I164=\"LUUB\"),VLOOKUP($A164&\"_\"&\"vdd_dyn\"&\"_\"&$R164&\"\",MDB,5,0)*$C164*$S164*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A164&\"_\"&\"vdd_dyn\"&\"_\"&$R164&\"_idle\",MDB,5,0)*(1-$S164)+VLOOKUP($A164&\"_\"&\"vdd_dyn\"&\"_\"&$R164&\"_read\",MDB,5,0)*($S164/2)+VLOOKUP($A164&\"_\"&\"vdd_dyn\"&\"_\"&$R164&\"_write\",MDB,5,0)*($S164/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,{"$f":"IFERROR(VLOOKUP($A164&\"_\"&X$3,MDB,5,0)*$C164*VLOOKUP(\"vddr_lkg\",pwr_scale_table,2,0)*IF(P164=\"OFF\",0.06,1),0)","v":0},{"$f":"IFERROR(VLOOKUP($A164&\"_\"&Y$3,MDB,5,0)*$C164*(VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*0.5+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*0.5),0)","v":0},{"$f":"IFERROR(IF(I164=\"LUUB\",VLOOKUP($A164&\"_\"&Z$3&\"_\"&$R164&\"\",MDB,5,0)*$C164*$S164*((VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)/4+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)/4+VLOOKUP(\"vdd_sw\",pwr_scale_table,2,0)/2)),VLOOKUP($A164&\"_\"&Z$3&\"_\"&$R164&\"\",MDB,5,0)*$C164*((VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)/4+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)/4+VLOOKUP(\"vdd_sw\",pwr_scale_table,2,0)/2))),0)","v":0},{"$f":"IFERROR(VLOOKUP($A164&\"_\"&AA$3,MDB,5,0)*$C164*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0),0)","v":0},{"$f":"IFERROR(IF(OR($I164=\"LUUA\",$I164=\"LUUB\"),VLOOKUP($A164&\"_\"&AB$3&\"_\"&$R164&\"\",MDB,5,0)*$C164*$S164,IF(I164=\"LUUD\",VLOOKUP($A164&\"_\"&AB$3&\"_\"&$R164&\"_idle\",MDB,5,0)*(1-$S164)+VLOOKUP($A164&\"_\"&AB$3&\"_\"&$R164&\"_read\",MDB,5,0)*($S164/2)+VLOOKUP($A164&\"_\"&AB$3&\"_\"&$R164&\"_write\",MDB,5,0)*($S164/2),VLOOKUP($A164&\"_\"&AB$3&\"_\"&$R164&\"\",MDB,5,0)*$C164)),0)","v":0.15008418700000001},{"$f":"IFERROR(VLOOKUP($A164&\"_\"&AC$3,MDB,5,0)*$C164*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0),0)","v":0},{"$f":"IFERROR(IF(OR($I164=\"LUUA\",$I164=\"LUUB\"),VLOOKUP($A164&\"_\"&AD$3&\"_\"&$R164&\"\",MDB,5,0)*$C164*$S164,IF(I164=\"LUUD\",VLOOKUP($A164&\"_\"&AD$3&\"_\"&$R164&\"_idle\",MDB,5,0)*(1-$S164)+VLOOKUP($A164&\"_\"&AD$3&\"_\"&$R164&\"_read\",MDB,5,0)*($S164/2)+VLOOKUP($A164&\"_\"&AD$3&\"_\"&$R164&\"_write\",MDB,5,0)*($S164/2),VLOOKUP($A164&\"_\"&AD$3&\"_\"&$R164&\"\",MDB,5,0)*$C164)),0)","v":0},0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.",{"$f":"A164&B164","v":"uart_2"},"CC$55",null,null,null,null,null,null,null,null,null,"CB$55","CD$55",2]
["uart","_3",1,0,"VDD_CORE","N/A","VDDSHV1P8","VDDSHV3P3","LUUA","GP_Core_Ctl","UART LVCMOS IO","10/30/2021","7 LVCMOS IO","uart",0.15008418700000001,"ON",0,"3p6m_1p8v",1,4,{"$f":"IFERROR(IF($I165=\"SI\",AP165*$C165*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ165*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK165*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL165*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM165*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN165*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO165*'Power Scaling'!F$4)*IF(P165=\"OFF\",0.06,1),VLOOKUP($A165&\"_\"&U$3,MDB,5,0)*$C165*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P165=\"OFF\",0.06,1)),0)","v":0},{"$f":"C165*IFERROR(IF($I165=\"SI\",(AE165*IF(S165=0,0,1)+(AF165-AE165)*S165)*IF(R165>0,R165,Q165)/Q165*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ165*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK165*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL165*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM165*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN165*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO165*'Power Scaling'!I$4)*AQ165,IF(OR($I165=\"AO\",$I165=\"LU\"),VLOOKUP($A165&\"_\"&\"vdd_dyn\"&\"_\"&$R165&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I165=\"LUUA\",$I165=\"LUUB\"),VLOOKUP($A165&\"_\"&\"vdd_dyn\"&\"_\"&$R165&\"\",MDB,5,0)*$C165*$S165*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A165&\"_\"&\"vdd_dyn\"&\"_\"&$R165&\"_idle\",MDB,5,0)*(1-$S165)+VLOOKUP($A165&\"_\"&\"vdd_dyn\"&\"_\"&$R165&\"_read\",MDB,5,0)*($S165/2)+VLOOKUP($A165&\"_\"&\"vdd_dyn\"&\"_\"&$R165&\"_write\",MDB,5,0)*($S165/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0.15008418700000001,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","uart_3","CC$55",null,null,null,null,null,null,null,null,null,"CB$55","CD$55",3]
["uart","_4",1,0,"VDD_CORE","N/A","VDDSHV1P8","VDDSHV3P3","LUUA","GP_Core_Ctl","UART LVCMOS IO","10/30/2021","7 LVCMOS IO","uart",0.15008418700000001,"ON",0,"3p6m_1p8v",1,4,{"$f":"IFERROR(IF($I166=\"SI\",AP166*$C166*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ166*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK166*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL166*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM166*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN166*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO166*'Power Scaling'!F$4)*IF(P166=\"OFF\",0.06,1),VLOOKUP($A166&\"_\"&U$3,MDB,5,0)*$C166*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P166=\"OFF\",0.06,1)),0)","v":0},{"$f":"C166*IFERROR(IF($I166=\"SI\",(AE166*IF(S166=0,0,1)+(AF166-AE166)*S166)*IF(R166>0,R166,Q166)/Q166*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ166*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK166*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL166*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM166*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN166*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO166*'Power Scaling'!I$4)*AQ166,IF(OR($I166=\"AO\",$I166=\"LU\"),VLOOKUP($A166&\"_\"&\"vdd_dyn\"&\"_\"&$R166&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I166=\"LUUA\",$I166=\"LUUB\"),VLOOKUP($A166&\"_\"&\"vdd_dyn\"&\"_\"&$R166&\"\",MDB,5,0)*$C166*$S166*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A166&\"_\"&\"vdd_dyn\"&\"_\"&$R166&\"_idle\",MDB,5,0)*(1-$S166)+VLOOKUP($A166&\"_\"&\"vdd_dyn\"&\"_\"&$R166&\"_read\",MDB,5,0)*($S166/2)+VLOOKUP($A166&\"_\"&\"vdd_dyn\"&\"_\"&$R166&\"_write\",MDB,5,0)*($S166/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0.15008418700000001,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","uart_4","CC$55",null,null,null,null,null,null,null,null,null,"CB$55","CD$55",4]
["uart","_5",1,0,"VDD_CORE","N/A","VDDSHV1P8","VDDSHV3P3","LUUA","GP_Core_Ctl","UART LVCMOS IO","10/30/2021","7 LVCMOS IO","uart",0,"ON",0,"unused",0,4,{"$f":"IFERROR(IF($I167=\"SI\",AP167*$C167*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ167*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK167*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL167*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM167*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN167*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO167*'Power Scaling'!F$4)*IF(P167=\"OFF\",0.06,1),VLOOKUP($A167&\"_\"&U$3,MDB,5,0)*$C167*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P167=\"OFF\",0.06,1)),0)","v":0},{"$f":"C167*IFERROR(IF($I167=\"SI\",(AE167*IF(S167=0,0,1)+(AF167-AE167)*S167)*IF(R167>0,R167,Q167)/Q167*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ167*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK167*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL167*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM167*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN167*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO167*'Power Scaling'!I$4)*AQ167,IF(OR($I167=\"AO\",$I167=\"LU\"),VLOOKUP($A167&\"_\"&\"vdd_dyn\"&\"_\"&$R167&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I167=\"LUUA\",$I167=\"LUUB\"),VLOOKUP($A167&\"_\"&\"vdd_dyn\"&\"_\"&$R167&\"\",MDB,5,0)*$C167*$S167*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A167&\"_\"&\"vdd_dyn\"&\"_\"&$R167&\"_idle\",MDB,5,0)*(1-$S167)+VLOOKUP($A167&\"_\"&\"vdd_dyn\"&\"_\"&$R167&\"_read\",MDB,5,0)*($S167/2)+VLOOKUP($A167&\"_\"&\"vdd_dyn\"&\"_\"&$R167&\"_write\",MDB,5,0)*($S167/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","uart_5","CC$55",null,null,null,null,null,null,null,null,null,"CB$55","CD$55",5]
["uart","_6",1,0,"VDD_CORE","N/A","VDDSHV1P8","VDDSHV3P3","LUUA","GP_Core_Ctl","UART LVCMOS IO","10/30/2021","7 LVCMOS IO","uart",0,"ON",0,"unused",0,4,{"$f":"IFERROR(IF($I168=\"SI\",AP168*$C168*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ168*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK168*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL168*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM168*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN168*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO168*'Power Scaling'!F$4)*IF(P168=\"OFF\",0.06,1),VLOOKUP($A168&\"_\"&U$3,MDB,5,0)*$C168*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P168=\"OFF\",0.06,1)),0)","v":0},{"$f":"C168*IFERROR(IF($I168=\"SI\",(AE168*IF(S168=0,0,1)+(AF168-AE168)*S168)*IF(R168>0,R168,Q168)/Q168*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ168*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK168*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL168*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM168*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN168*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO168*'Power Scaling'!I$4)*AQ168,IF(OR($I168=\"AO\",$I168=\"LU\"),VLOOKUP($A168&\"_\"&\"vdd_dyn\"&\"_\"&$R168&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I168=\"LUUA\",$I168=\"LUUB\"),VLOOKUP($A168&\"_\"&\"vdd_dyn\"&\"_\"&$R168&\"\",MDB,5,0)*$C168*$S168*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A168&\"_\"&\"vdd_dyn\"&\"_\"&$R168&\"_idle\",MDB,5,0)*(1-$S168)+VLOOKUP($A168&\"_\"&\"vdd_dyn\"&\"_\"&$R168&\"_read\",MDB,5,0)*($S168/2)+VLOOKUP($A168&\"_\"&\"vdd_dyn\"&\"_\"&$R168&\"_write\",MDB,5,0)*($S168/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","uart_6","CC$55",null,null,null,null,null,null,null,null,null,"CB$55","CD$55",6]
["uart","mcu_0",1,0,"VDD_CORE","N/A","VDDSHV1P8_MCU","VDDSHV3P3_MCU","LUUA","GP_Core_Ctl","UART LVCMOS IO","10/30/2021","7 LVCMOS IO","uart",2.7369619000000001E-2,"ON",0,"112k_3p3v",1,4,{"$f":"IFERROR(IF($I169=\"SI\",AP169*$C169*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ169*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK169*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL169*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM169*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN169*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO169*'Power Scaling'!F$4)*IF(P169=\"OFF\",0.06,1),VLOOKUP($A169&\"_\"&U$3,MDB,5,0)*$C169*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P169=\"OFF\",0.06,1)),0)","v":0},{"$f":"C169*IFERROR(IF($I169=\"SI\",(AE169*IF(S169=0,0,1)+(AF169-AE169)*S169)*IF(R169>0,R169,Q169)/Q169*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ169*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK169*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL169*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM169*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN169*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO169*'Power Scaling'!I$4)*AQ169,IF(OR($I169=\"AO\",$I169=\"LU\"),VLOOKUP($A169&\"_\"&\"vdd_dyn\"&\"_\"&$R169&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I169=\"LUUA\",$I169=\"LUUB\"),VLOOKUP($A169&\"_\"&\"vdd_dyn\"&\"_\"&$R169&\"\",MDB,5,0)*$C169*$S169*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A169&\"_\"&\"vdd_dyn\"&\"_\"&$R169&\"_idle\",MDB,5,0)*(1-$S169)+VLOOKUP($A169&\"_\"&\"vdd_dyn\"&\"_\"&$R169&\"_read\",MDB,5,0)*($S169/2)+VLOOKUP($A169&\"_\"&\"vdd_dyn\"&\"_\"&$R169&\"_write\",MDB,5,0)*($S169/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,2.7369619000000001E-2,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","uartmcu_0","CC$47",null,null,null,null,null,null,null,null,null,"CB$47","CD$47",0]
["uart","wkp_0",1,0,"VDD_CORE","N/A","VDDSHV1P8_MCU","VDDSHV3P3_MCU","LUUA","GP_Core_Ctl","UART LVCMOS IO","10/30/2021","7 LVCMOS IO","uart",0.24437159999999999,"ON",0,"1m_3p3v",1,4,{"$f":"IFERROR(IF($I170=\"SI\",AP170*$C170*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ170*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK170*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL170*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM170*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN170*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO170*'Power Scaling'!F$4)*IF(P170=\"OFF\",0.06,1),VLOOKUP($A170&\"_\"&U$3,MDB,5,0)*$C170*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P170=\"OFF\",0.06,1)),0)","v":0},{"$f":"C170*IFERROR(IF($I170=\"SI\",(AE170*IF(S170=0,0,1)+(AF170-AE170)*S170)*IF(R170>0,R170,Q170)/Q170*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ170*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK170*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL170*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM170*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN170*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO170*'Power Scaling'!I$4)*AQ170,IF(OR($I170=\"AO\",$I170=\"LU\"),VLOOKUP($A170&\"_\"&\"vdd_dyn\"&\"_\"&$R170&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I170=\"LUUA\",$I170=\"LUUB\"),VLOOKUP($A170&\"_\"&\"vdd_dyn\"&\"_\"&$R170&\"\",MDB,5,0)*$C170*$S170*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A170&\"_\"&\"vdd_dyn\"&\"_\"&$R170&\"_idle\",MDB,5,0)*(1-$S170)+VLOOKUP($A170&\"_\"&\"vdd_dyn\"&\"_\"&$R170&\"_read\",MDB,5,0)*($S170/2)+VLOOKUP($A170&\"_\"&\"vdd_dyn\"&\"_\"&$R170&\"_write\",MDB,5,0)*($S170/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0.24437159999999999,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","uartwkp_0","CC$45",null,null,null,null,null,null,null,null,null,"CB$45","CD$45",0]
["uart_modem","_0",1,0,"VDD_CORE","N/A","VDDSHV1P8","VDDSHV3P3","LUUA","GP_Core_Ctl","UART Modem LVCMOS IO","10/30/2021","7 LVCMOS IO","uart_modem",0.15008418700000001,"ON",0,"3p6m_1p8v",1,8,{"$f":"IFERROR(IF($I171=\"SI\",AP171*$C171*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ171*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK171*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL171*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM171*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN171*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO171*'Power Scaling'!F$4)*IF(P171=\"OFF\",0.06,1),VLOOKUP($A171&\"_\"&U$3,MDB,5,0)*$C171*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P171=\"OFF\",0.06,1)),0)","v":0},{"$f":"C171*IFERROR(IF($I171=\"SI\",(AE171*IF(S171=0,0,1)+(AF171-AE171)*S171)*IF(R171>0,R171,Q171)/Q171*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ171*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK171*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL171*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM171*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN171*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO171*'Power Scaling'!I$4)*AQ171,IF(OR($I171=\"AO\",$I171=\"LU\"),VLOOKUP($A171&\"_\"&\"vdd_dyn\"&\"_\"&$R171&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I171=\"LUUA\",$I171=\"LUUB\"),VLOOKUP($A171&\"_\"&\"vdd_dyn\"&\"_\"&$R171&\"\",MDB,5,0)*$C171*$S171*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A171&\"_\"&\"vdd_dyn\"&\"_\"&$R171&\"_idle\",MDB,5,0)*(1-$S171)+VLOOKUP($A171&\"_\"&\"vdd_dyn\"&\"_\"&$R171&\"_read\",MDB,5,0)*($S171/2)+VLOOKUP($A171&\"_\"&\"vdd_dyn\"&\"_\"&$R171&\"_write\",MDB,5,0)*($S171/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0.15008418700000001,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","uart_modem_0","CC$55",null,null,null,null,null,null,null,null,null,"CB$55","CD$55",0]
["sam67_usb2_wrap","_1",1,4,"VDD_CORE","N/A","N/A","N/A","SI","GP_Core_CTL","USB2 Controller","sam62p_dec_power","3 Periph","HS_Serial",5.9743833935950414,"ON",125,{"$f":"IF(ISBLANK(BD172),0,INDIRECT(BD172))","v":0},{"$f":"IF(AND(IF(ISBLANK(AT172),\"unused\",INDIRECT(AT172))<>\"suspend\",IF(ISBLANK(AU172),0,INDIRECT(AU172))*IF(ISBLANK(AV172),0,IF(INDIRECT(AV172)>1,1,0))),INDIRECT(AU172),0%)","v":1},8,{"$f":"IFERROR(IF($I172=\"SI\",AP172*$C172*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ172*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK172*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL172*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM172*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN172*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO172*'Power Scaling'!F$4)*IF(P172=\"OFF\",0.06,1),VLOOKUP($A172&\"_\"&U$3,MDB,5,0)*$C172*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P172=\"OFF\",0.06,1)),0)","v":0},{"$f":"C172*IFERROR(IF($I172=\"SI\",(AE172*IF(S172=0,0,1)+(AF172-AE172)*S172)*IF(R172>0,R172,Q172)/Q172*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ172*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK172*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL172*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM172*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN172*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO172*'Power Scaling'!I$4)*AQ172,IF(OR($I172=\"AO\",$I172=\"LU\"),VLOOKUP($A172&\"_\"&\"vdd_dyn\"&\"_\"&$R172&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I172=\"LUUA\",$I172=\"LUUB\"),VLOOKUP($A172&\"_\"&\"vdd_dyn\"&\"_\"&$R172&\"\",MDB,5,0)*$C172*$S172*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A172&\"_\"&\"vdd_dyn\"&\"_\"&$R172&\"_idle\",MDB,5,0)*(1-$S172)+VLOOKUP($A172&\"_\"&\"vdd_dyn\"&\"_\"&$R172&\"_read\",MDB,5,0)*($S172/2)+VLOOKUP($A172&\"_\"&\"vdd_dyn\"&\"_\"&$R172&\"_write\",MDB,5,0)*($S172/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},5.9743833935950414,0,0,0,0,0,0,0,0.27600000000000002,0.35,0.28999999999999998,21,23.5,0,0,0.02,0.06,0.84,0.08,1.869545542456585,20.631420498058993,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","sam67_usb2_wrap_1","CB$41","CC$41","CD$41"]
["sam67_wiz16b8m4cdt3_wrap","_0",1,3,"VDD_CORE","N/A","N/A","N/A","SI","GP_Core_CTL","PCS_MUX 4L DPHY TX","sam62p_dec_power","3 Periph","HS_Serial",0,"ON",500,{"$f":"IF(ISBLANK(AT173),\"ulps\",INDIRECT(AT173))","v":"ulps"},{"$f":"IF(R173=\"ulps\",0,IF(ISBLANK(AV173),0,IF(INDIRECT(AV173)>0,IF(ISBLANK(AU173),0,INDIRECT(AU173)),0)))","v":0},8,{"$f":"IFERROR(IF($I173=\"SI\",AP173*$C173*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ173*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK173*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL173*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM173*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN173*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO173*'Power Scaling'!F$4)*IF(P173=\"OFF\",0.06,1),VLOOKUP($A173&\"_\"&U$3,MDB,5,0)*$C173*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P173=\"OFF\",0.06,1)),0)","v":0},{"$f":"C173*IFERROR(IF($I173=\"SI\",(AE173*IF(S173=0,0,1)+(AF173-AE173)*S173)*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ173*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK173*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL173*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM173*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN173*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO173*'Power Scaling'!I$4)*AQ173,IF(OR($I173=\"AO\",$I173=\"LU\"),VLOOKUP($A173&\"_\"&\"vdd_dyn\"&\"_\"&$R173&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I173=\"LUUA\",$I173=\"LUUB\"),VLOOKUP($A173&\"_\"&\"vdd_dyn\"&\"_\"&$R173&\"\",MDB,5,0)*$C173*$S173*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A173&\"_\"&\"vdd_dyn\"&\"_\"&$R173&\"_idle\",MDB,5,0)*(1-$S173)+VLOOKUP($A173&\"_\"&\"vdd_dyn\"&\"_\"&$R173&\"_read\",MDB,5,0)*($S173/2)+VLOOKUP($A173&\"_\"&\"vdd_dyn\"&\"_\"&$R173&\"_write\",MDB,5,0)*($S173/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},0,0,0,0,0,0,0,0,0.373,0.48,0.57999999999999996,2.1,4.5999999999999996,0,0,0.05,0.17,0.72,0.06,0.12470073382640834,1.9951610314420087,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","sam67_wiz16b8m4cdt3_wrap_0","CB$36","CC$36","CD$36"]
["N16FFC_POKSA","_0",1,5,"VDD_CORE","N/A","VDDA_MCU","N/A","LU","GP_Core_CTL","POKSA","10/30/2021","5 Analog","Power",4.6440000000000002E-2,"ON",0,"on",1,0,{"$f":"IFERROR(IF($I174=\"SI\",AP174*$C174*(VLOOKUP(\"vdd_lkg (ulvt20)\",pwr_scale_table,2,0)*$AJ174*'Power Scaling'!F$7+VLOOKUP(\"vdd_lkg (ulvt16)\",pwr_scale_table,2,0)*$AK174*'Power Scaling'!F$8+VLOOKUP(\"vdd_lkg (lvt20)\",pwr_scale_table,2,0)*$AL174*'Power Scaling'!F$5+VLOOKUP(\"vdd_lkg (lvt16)\",pwr_scale_table,2,0)*AM174*'Power Scaling'!F$6+VLOOKUP(\"vdd_lkg (svt20)\",pwr_scale_table,2,0)*$AN174*'Power Scaling'!F$3+VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*$AO174*'Power Scaling'!F$4)*IF(P174=\"OFF\",0.06,1),VLOOKUP($A174&\"_\"&U$3,MDB,5,0)*$C174*VLOOKUP(\"vdd_lkg (svt16)\",pwr_scale_table,2,0)*IF(P174=\"OFF\",0.06,1)),0)","v":0},{"$f":"C174*IFERROR(IF($I174=\"SI\",(AE174*IF(S174=0,0,1)+(AF174-AE174)*S174)*IF(R174>0,R174,Q174)/Q174*(VLOOKUP(\"vdd_int (ulvt20)\",pwr_scale_table,2,0)*$AJ174*'Power Scaling'!I$7+VLOOKUP(\"vdd_int (ulvt16)\",pwr_scale_table,2,0)*$AK174*'Power Scaling'!I$8+VLOOKUP(\"vdd_int (lvt20)\",pwr_scale_table,2,0)*$AL174*'Power Scaling'!I$5+VLOOKUP(\"vdd_int (lvt16)\",pwr_scale_table,2,0)*AM174*'Power Scaling'!I$6+VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)*$AN174*'Power Scaling'!I$3+VLOOKUP(\"vdd_int (svt16)\",pwr_scale_table,2,0)*$AO174*'Power Scaling'!I$4)*AQ174,IF(OR($I174=\"AO\",$I174=\"LU\"),VLOOKUP($A174&\"_\"&\"vdd_dyn\"&\"_\"&$R174&\"\",MDB,5,0)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),IF(OR($I174=\"LUUA\",$I174=\"LUUB\"),VLOOKUP($A174&\"_\"&\"vdd_dyn\"&\"_\"&$R174&\"\",MDB,5,0)*$C174*$S174*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0),VLOOKUP($A174&\"_\"&\"vdd_dyn\"&\"_\"&$R174&\"_idle\",MDB,5,0)*(1-$S174)+VLOOKUP($A174&\"_\"&\"vdd_dyn\"&\"_\"&$R174&\"_read\",MDB,5,0)*($S174/2)+VLOOKUP($A174&\"_\"&\"vdd_dyn\"&\"_\"&$R174&\"_write\",MDB,5,0)*($S174/2)*VLOOKUP(\"vdd_int (svt20)\",pwr_scale_table,2,0)))),0)","v":0},{"$f":"C174*IFERROR(IF($I174=\"SI\",(AE174*IF(S174=0,0,1)+(AF174-AE174)*S174)*(IF(R174>0,R174,Q174)/Q174)*VLOOKUP(\"vdd_sw\",pwr_scale_table,2,0)*AI174,0),0)","v":0},0,0,0,0,4.6440000000000002E-2,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,"The Vx1 macro is a display data standard used on the DLPC8430.  It is a receiver only and it's under development.  Power is estimated at this time.","N16FFC_POKSA_0"]
[null,"Voltage Groups"]
[null,"V_G1"]
[null,"V_G2"]
[null,"V_G3"]
[null,"V_G4"]
[null,"V_G5"]
[null,"V_G6"]
[null,"V_G7"]
[null,"V_G8"]
[null,"V_G9"]
[null,"V_G10"]
[null,"V_G11"]
[]
[]
[]
[]
[]
[]
[]
[null,"Margin",{"$f":"IF($CE$3=\"PDN\",1.05,1)","v":1},{"$f":"IF($CE$3=\"PDN\",1.1,1)","v":1}]
[null,{"$f":"\"Tj = \"&Tj&\"C\"","v":"Tj = 150C"},null,{"$f":"IF($CE$3=\"Thermal\",\"\", \"Step Current (Total) = \"&SUM(L198:L200)&\"mA\")","v":""}]
[null,{"$f":"IF($CE$3=\"Thermal\",\"Thermal Power\", \"PDN (Peak) Power\")","v":"Thermal Power"},null,{"$f":"IF($CE$3=\"Thermal\",\"not suitable for designing a PDN\", \"Peak power is intended for PDN resourcing\")","v":"not suitable for designing a PDN"},null,null,null,"Cumulative Power"]
[null,null,"Leakage Power [mW]","Dynamic Power [mW]","Total Power [mW]","Voltage [V]","Total Current [mA]","Leakage","Dynamic","Power round factor",null,"Step Current [mA]"]
[{"$f":"B198","v":"VDD_CORE"},"VDD_CORE",{"$f":"ROUNDUP(H198*C$194/J198,0)*J198","v":0},{"$f":"ROUNDUP(I198*D$194/J198,0)*J198","v":1024},{"$f":"SUM(C198:D198)","v":1024},{"$f":"VDD_Core","v":0.75},{"$f":"ROUNDUP(E198/F198,0)","v":1366},{"$f":"SUMIF($E$4:$E$174,$A198,$U$4:$U$174)+SUMIF($F$4:$F$174,$A198,$Y$4:$Y$174)+SUMIF($G$4:$G$174,$A198,$AA$4:$AA$174)+SUMIF($H$4:$H$174,$A198,$AC$4:$AC$174)","v":0},{"$f":"SUMIF($E$4:$E$174,$A198,$V$4:$V$174)+SUMIF($E$4:$E$174,$A198,$W$4:$W$174)+SUMIF($F$4:$F$174,$A198,$Z$4:$Z$174)","v":1023.0675798945607},1,null,{"$f":"ROUNDUP(D198/2/(F198*J198),0)*J198","v":683},"V_G1"]
[{"$f":"A198","v":"VDD_CORE"},"VDDR_CORE",{"$f":"ROUNDUP(H199*C$194/J199,0)*J199","v":0},{"$f":"ROUNDUP(I199*D$194/J199,0)*J199","v":0},{"$f":"SUM(C199:D199)","v":0},0.85,{"$f":"ROUNDUP(E199/F199,0)","v":0},{"$f":"SUMIF($E$4:$E$174,$A199,$X$4:$X$174)+SUMIF($F$4:$F$174,$A199,$Y$4:$Y$174)+SUMIF($G$4:$G$174,$A199,$AA$4:$AA$174)+SUMIF($H$4:$H$174,$A199,$AC$4:$AC$174)","v":0},0,1,null,{"$f":"ROUNDUP(D199/(F199*J199)*0.8,0)*J199","v":0},"V_G2"]
["VDD_CANUART","VDD_CANUART",0,0,0,0.75,0,{"$f":"SUMIF($E$4:$E$174,$A200,$U$4:$U$174)+SUMIF($F$4:$F$174,$A200,$Y$4:$Y$174)+SUMIF($G$4:$G$174,$A200,$AA$4:$AA$174)+SUMIF($H$4:$H$174,$A200,$AC$4:$AC$174)","v":0},{"$f":"SUMIF($E$4:$E$174,$A200,$V$4:$V$174)+SUMIF($E$4:$E$174,$A200,$W$4:$W$174)+SUMIF($F$4:$F$174,$A200,$Z$4:$Z$174)","v":0},{"$f":"IF(OR(H200>=100,I200>=100),10,1)","v":1},null,{"$f":"ROUNDUP(D200/2/(F200*J200),0)*J200","v":0},"V_G4"]
[]
["VDDS_DDR","VDDS_DDR/VDDS_DDR_C",0,216,216,1.1000000000000001,197,{"$f":"SUMIF($F$4:$F$174,$A202,$Y$4:$Y$174)+SUMIF($G$4:$G$174,$A202,$AA$4:$AA$174)+SUMIF($H$4:$H$174,$A202,$AC$4:$AC$174)","v":0},{"$f":"SUMIF($F$4:$F$174,$A202,$Z$4:$Z$174)+SUMIF($G$4:$G$174,$A202,$AB$4:$AB$174)+SUMIF($H$4:$H$174,$A202,$AD$4:$AD$174)","v":215.16},1,null,null,"V_G3"]
[]
[null,"VDDA_1P8_CSI_DSI",0,19,19,1.8,11,{"$f":"SUMIF($F$4:$F$174,$A249,$Y$4:$Y$174)+SUMIF($G$4:$G$174,$A249,$AA$4:$AA$174)+SUMIF($H$4:$H$174,$A249,$AC$4:$AC$174)+SUMIF($F$4:$F$174,$A250,$Y$4:$Y$174)+SUMIF($G$4:$G$174,$A250,$AA$4:$AA$174)+SUMIF($H$4:$H$174,$A250,$AC$4:$AC$174)","v":0},{"$f":"SUMIF($F$4:$F$174,$A249,$Z$4:$Z$174)+SUMIF($G$4:$G$174,$A249,$AB$4:$AB$174)+SUMIF($H$4:$H$174,$A249,$AD$4:$AD$174)+SUMIF($F$4:$F$174,$A250,$Z$4:$Z$174)+SUMIF($G$4:$G$174,$A250,$AB$4:$AB$174)+SUMIF($H$4:$H$174,$A250,$AD$4:$AD$174)","v":18.779},1,null,null,"V_G5"]
[null,"VDDA_CORE_CSI_DSI",0,3,3,{"$f":"VDD_Core","v":0.75},4,{"$f":"SUMIF($F$4:$F$174,$A251,$Y$4:$Y$174)+SUMIF($G$4:$G$174,$A251,$AA$4:$AA$174)+SUMIF($H$4:$H$174,$A251,$AC$4:$AC$174)+SUMIF($F$4:$F$174,$A252,$Y$4:$Y$174)+SUMIF($G$4:$G$174,$A252,$AA$4:$AA$174)+SUMIF($H$4:$H$174,$A252,$AC$4:$AC$174)","v":0},{"$f":"SUMIF($F$4:$F$174,$A251,$Z$4:$Z$174)+SUMIF($G$4:$G$174,$A251,$AB$4:$AB$174)+SUMIF($H$4:$H$174,$A251,$AD$4:$AD$174)+SUMIF($F$4:$F$174,$A252,$Z$4:$Z$174)+SUMIF($G$4:$G$174,$A252,$AB$4:$AB$174)+SUMIF($H$4:$H$174,$A252,$AD$4:$AD$174)","v":2.9279999999999999},1,null,null,"V_G1"]
["VDDA_0P8_DSITX_C","VDDA_CORE_DSI_CLK",0,0,0,{"$f":"VDD_Core","v":0.75},0,{"$f":"SUMIF($F$4:$F$174,$A206,$Y$4:$Y$174)+SUMIF($G$4:$G$174,$A206,$AA$4:$AA$174)+SUMIF($H$4:$H$174,$A206,$AC$4:$AC$174)","v":0},{"$f":"SUMIF($F$4:$F$174,$A206,$Z$4:$Z$174)+SUMIF($G$4:$G$174,$A206,$AB$4:$AB$174)+SUMIF($H$4:$H$174,$A206,$AD$4:$AD$174)","v":0},1,null,null,"V_G1"]
[]
["VDDA_3P3_USB","VDDA_3P3_USB",0,4,4,3.3,2,0,3.82,1,null,null,"V_G6"]
["VDDA_1P8_USB","VDDA_1P8_USB",0,26,26,1.8,15,0,25.76,1,null,null,"V_G7"]
["VDDA_CORE_USB","VDDA_CORE_USB",0,0,0,{"$f":"VDD_Core","v":0.75},0,0,0,1,null,null,"V_G1"]
[]
["VDDA_1P8_OLDI0","VDDA_1P8_OLDI0",0,149,149,1.8,83,0,148.1,1,null,null,"V_G5"]
[]
["VDDA_PLL0","VDDA_PLL0",0,19,19,1.8,11,0,18.303658383000002,1,null,null,"V_G9"]
["VDDA_PLL1","VDDA_PLL1",0,29,29,1.8,17,0,28.262082694,1,null,null,"V_G9"]
["VDDA_PLL2","VDDA_PLL2",0,8,8,1.8,5,0,7.2802355409999997,1,null,null,"V_G9"]
["VDDA_PLL3","VDDA_PLL3",0,7,7,1.8,4,0,6.1012194610000003,1,null,null,"V_G9"]
["VDDA_PLL4","VDDA_PLL4",0,20,20,1.8,12,0,19.735369282000001,1,null,null,"V_G9"]
[]
["VDDA_TEMP0","VDDA_TEMP0",0,3,3,1.8,2,0,2.6000027169999997,1,null,null,"V_G7"]
["VDDA_TEMP1","VDDA_TEMP1",0,1,1,1.8,1,0,0.60000271699999996,1,null,null,"V_G7"]
["VDDA_TEMP2","VDDA_TEMP2",0,1,1,1.8,1,0,0.60000271699999996,1,null,null,"V_G7"]
["VDDS_OSC0","VDDS_OSC0",0,6,6,1.8,4,0,5.6699279999999996,1,null,null,"V_G8"]
[]
["VDDA_MCU","VDDA_MCU",0,10,10,1.8,6,0,9.1991534119999976,1,null,null,"V_G9"]
[]
["VDDA_DDR_PLL0","VDDA_DDR_PLL0",1,4,5,{"$f":"VDD_Core","v":0.75},7,0,0,1,null,null,"V_G1"]
[]
["VDDS_MMC0","VDDS_MMC0",0,99,99,1.8,55,0,99,1,null,null,"V_G10"]
["VDD_MMC0","VDD_MMC0",0,0,0,0.85,0,0,0,1,null,null,"V_G2"]
["VDDA_0P85_DLL_MMC0","VDDA_0P85_DLL_MMC0",1,4,5,0.85,6,0,0,1,null,null,"V_G2"]
[]
["VDDSHV3P3","VDDSHV3P3",0,534,534,3.3,162,{"$f":"SUMIF($F$4:$F$174,$A233,$Y$4:$Y$174)+SUMIF($G$4:$G$174,$A233,$AA$4:$AA$174)+SUMIF($H$4:$H$174,$A233,$AC$4:$AC$174)","v":0},{"$f":"SUMIF($F$4:$F$174,$A233,$Z$4:$Z$174)+SUMIF($G$4:$G$174,$A233,$AB$4:$AB$174)+SUMIF($H$4:$H$174,$A233,$AD$4:$AD$174)","v":533.12712033000025},1]
["VDDSHV1P8","VDDSHV1P8",0,96,96,1.8,54,{"$f":"SUMIF($F$4:$F$174,$A234,$Y$4:$Y$174)+SUMIF($G$4:$G$174,$A234,$AA$4:$AA$174)+SUMIF($H$4:$H$174,$A234,$AC$4:$AC$174)","v":0},{"$f":"SUMIF($F$4:$F$174,$A234,$Z$4:$Z$174)+SUMIF($G$4:$G$174,$A234,$AB$4:$AB$174)+SUMIF($H$4:$H$174,$A234,$AD$4:$AD$174)","v":95.427004935000028},1]
["VDDSHV3P3_MCU","VDDSHV3P3_MCU",{"$f":"ROUNDUP(H235*C$194/J235,0)*J235","v":0},{"$f":"ROUNDUP(I235*D$194/J235,0)*J235","v":4},{"$f":"SUM(C235:D235)","v":4},3.3,{"$f":"ROUNDUP(E235/F235,0)","v":2},0,3.5729267280000001,1]
["VDDSHV1P8_MCU","VDDSHV1P8_MCU",0,0,0,1.8,0,0,0,1]
["VDDSHV_CANUART","VDDSHV_CANUART",0,0,0,null,null,0,0,1]
[]
[null,"VPP",0,400,720,1.8,400,400,null,null,null,null,"V_G11"]
[]
[]
[null,"Thermal Power"]
[null,"Tj [C]","Leakage Power [mW]","Dynamic Power [mW]","Total Power [mW]"]
[null,{"$f":"Tj","v":150},{"$f":"SUM(C198:C239)","v":2},{"$f":"SUM(D198:D237)","v":2286},{"$f":"SUM(E198:E237)","v":2288},{"$f":"SUM(C244:D244)","v":2288}]
[]
[]
[]
[]
["VDDA_1P8_CSIRX0"]
["VDDA_1P8_DSITX"]
["VDDA_0P8_DSITX"]
["VDDA_CORE_CSIRX0"]

{"sheet":"MDB","index":4,"n_rows":2422,"n_cols":7,"rows_kept":2422,"cut":false,"hidden":true,"merged":[]}
["Model Database (MDB)"]
[]
["Lookup_string","Cell_Name","Attribute","mode","Value","comment","Previous Value"]
[]
[]
[]
[]
[]
[]
[]
[]
[]
["ABJSTBL5_vdd_dyn_on","ABJSTBL5","vdd_dyn","on",0.08,"",""]
["ABJSTBL5_vdd_lkg","ABJSTBL5","vdd_lkg","on",0.08,"",""]
["ABJSTBL5_vddh1_dyn_on","ABJSTBL5","vddh1_dyn","on",0.60000271699999996,"",""]
["ABJSTBL5_vddh1_lkg","ABJSTBL5","vddh1_lkg","on",0.120000543,"",""]
[]
[]
[]
[]
[]
[]
["canfd_vdd_dyn_12mbs_1p8v","canfd","vdd_dyn","12mbs_1p8v",6.5067600000000005E-7,"",""]
["canfd_vdd_dyn_12mbs_3p3v","canfd","vdd_dyn","12mbs_3p3v",6.5067600000000005E-7,"",""]
["canfd_vdd_dyn_1mbs_1p8v","canfd","vdd_dyn","1mbs_1p8v",5.4223000000000002E-8,"",""]
["canfd_vdd_dyn_1mbs_3p3v","canfd","vdd_dyn","1mbs_3p3v",5.4223000000000002E-8,"",""]
["canfd_vdd_dyn_250kbs_1p8v","canfd","vdd_dyn","250kbs_1p8v",1.3555699999999999E-8,"",""]
["canfd_vdd_dyn_250kbs_3p3v","canfd","vdd_dyn","250kbs_3p3v",1.3555699999999999E-8,"",""]
["canfd_vdd_dyn_5mbs_1p8v","canfd","vdd_dyn","5mbs_1p8v",2.7111499999999998E-7,"",""]
["canfd_vdd_dyn_5mbs_3p3v","canfd","vdd_dyn","5mbs_3p3v",2.7111499999999998E-7,"",""]
["canfd_vdd_dyn_8mbs_1p8v","canfd","vdd_dyn","8mbs_1p8v",4.3378400000000001E-7,"",""]
["canfd_vdd_dyn_8mbs_3p3v","canfd","vdd_dyn","8mbs_3p3v",4.3378400000000001E-7,"",""]
["canfd_vdd_dyn_off","canfd","vdd_dyn","off",0,"",""]
["canfd_vddh1_dyn_12mbs_1p8v","canfd","vddh1_dyn","12mbs_1p8v",0.15221519999999999,"",""]
["canfd_vddh1_dyn_1mbs_1p8v","canfd","vddh1_dyn","1mbs_1p8v",1.2684600000000001E-2,"",""]
["canfd_vddh1_dyn_1mbs_8p8v","canfd","vddh1_dyn","1mbs_8p8v",0.10147680000000001,"",""]
["canfd_vddh1_dyn_250kbs_1p8v","canfd","vddh1_dyn","250kbs_1p8v",3.1711500000000002E-3,"",""]
["canfd_vddh1_dyn_5mbs_1p8v","canfd","vddh1_dyn","5mbs_1p8v",6.3422999999999993E-2,"",""]
["canfd_vddh1_dyn_off","canfd","vddh1_dyn","off",0,"",""]
["canfd_vddh2_dyn_12mbs_3p3v","canfd","vddh2_dyn","12mbs_3p3v",0.78408,"",""]
["canfd_vddh2_dyn_1mbs_3p3v","canfd","vddh2_dyn","1mbs_3p3v",6.5339999999999995E-2,"",""]
["canfd_vddh2_dyn_250kbs_3p3v","canfd","vddh2_dyn","250kbs_3p3v",1.6334999999999999E-2,"",""]
["canfd_vddh2_dyn_5mbs_3p3v","canfd","vddh2_dyn","5mbs_3p3v",0.32669999999999999,"",""]
["canfd_vddh2_dyn_8mbs_3p3v","canfd","vddh2_dyn","8mbs_3p3v",0.52271999999999996,"",""]
["canfd_vddh2_dyn_off","canfd","vddh2_dyn","off",0,"",""]
[]
[]
[]
[]
[]
[]
[]
[]
[]
["ddr32_3733_ios_vdd_dyn_ddr4_1067_32_idle","ddr32_3733_ios","vdd_dyn","ddr4_1067_32_idle",2.3140000000000001,"Updated on 3-11",0.77157437500000003]
["ddr32_3733_ios_vdd_dyn_ddr4_1067_32_read","ddr32_3733_ios","vdd_dyn","ddr4_1067_32_read",36.768153124999998,"Updated on 3-11",38.10690469]
["ddr32_3733_ios_vdd_dyn_ddr4_1067_32_write","ddr32_3733_ios","vdd_dyn","ddr4_1067_32_write",43.416896874999999,"Updated on 3-11",44.774187560000001]
["ddr32_3733_ios_vdd_dyn_ddr4_1333_32_idle","ddr32_3733_ios","vdd_dyn","ddr4_1333_32_idle",2.3140000000000001,"Updated on 3-11",0.96392562500000001]
["ddr32_3733_ios_vdd_dyn_ddr4_1333_32_read","ddr32_3733_ios","vdd_dyn","ddr4_1333_32_read",45.934346875000003,"Updated on 3-11",47.606845309999997]
["ddr32_3733_ios_vdd_dyn_ddr4_1333_32_write","ddr32_3733_ios","vdd_dyn","ddr4_1333_32_write",54.240603125000007,"Updated on 3-11",55.93626244]
["ddr32_3733_ios_vdd_dyn_ddr4_1600_32_idle","ddr32_3733_ios","vdd_dyn","ddr4_1600_32_idle",2.3140000000000001,"Updated on 3-11",1.157]
["ddr32_3733_ios_vdd_dyn_ddr4_1600_32_read","ddr32_3733_ios","vdd_dyn","ddr4_1600_32_read",55.134999999999998,"Updated on 3-11",57.142499999999998]
["ddr32_3733_ios_vdd_dyn_ddr4_1600_32_write","ddr32_3733_ios","vdd_dyn","ddr4_1600_32_write",65.105000000000004,"Updated on 3-11",67.140299999999996]
["ddr32_3733_ios_vdd_dyn_ddr4_1867_32_idle","ddr32_3733_ios","vdd_dyn","ddr4_1867_32_idle",2.3140000000000001,"Updated on 3-11",1.3500743749999999]
["ddr32_3733_ios_vdd_dyn_ddr4_1867_32_read","ddr32_3733_ios","vdd_dyn","ddr4_1867_32_read",64.335653124999993,"Updated on 3-11",66.67815469]
["ddr32_3733_ios_vdd_dyn_ddr4_1867_32_write","ddr32_3733_ios","vdd_dyn","ddr4_1867_32_write",75.969396875000001,"Updated on 3-11",78.34433756]
["ddr32_3733_ios_vdd_dyn_ddr4_2133_32_idle","ddr32_3733_ios","vdd_dyn","ddr4_2133_32_idle",2.3140000000000001,"Updated on 3-11",1.5424256249999999]
["ddr32_3733_ios_vdd_dyn_ddr4_2133_32_read","ddr32_3733_ios","vdd_dyn","ddr4_2133_32_read",73.501846874999998,"Updated on 3-11",76.178095310000003]
["ddr32_3733_ios_vdd_dyn_ddr4_2133_32_write","ddr32_3733_ios","vdd_dyn","ddr4_2133_32_write",86.793103125000002,"Updated on 3-11",89.506412440000005]
["ddr32_3733_ios_vdd_dyn_ddr4_2400_32_idle","ddr32_3733_ios","vdd_dyn","ddr4_2400_32_idle",2.3140000000000001,"Updated on 3-11",1.7355]
["ddr32_3733_ios_vdd_dyn_ddr4_2400_32_read","ddr32_3733_ios","vdd_dyn","ddr4_2400_32_read",82.702500000000001,"Updated on 3-11",85.713750000000005]
["ddr32_3733_ios_vdd_dyn_ddr4_2400_32_write","ddr32_3733_ios","vdd_dyn","ddr4_2400_32_write",97.657499999999999,"Updated on 3-11",100.71044999999999]
["ddr32_3733_ios_vdd_dyn_ddr4_2667_32_idle","ddr32_3733_ios","vdd_dyn","ddr4_2667_32_idle",2.3140000000000001,"Updated on 3-11",1.928574375]
["ddr32_3733_ios_vdd_dyn_ddr4_2667_32_read","ddr32_3733_ios","vdd_dyn","ddr4_2667_32_read",91.903153124999989,"Updated on 3-11",95.249404690000006]
["ddr32_3733_ios_vdd_dyn_ddr4_2667_32_write","ddr32_3733_ios","vdd_dyn","ddr4_2667_32_write",108.521896875,"Updated on 3-11",111.9144876]
["ddr32_3733_ios_vdd_dyn_ddr4_2933_32_idle","ddr32_3733_ios","vdd_dyn","ddr4_2933_32_idle",2.3140000000000001,"Updated on 3-11",2.1209256249999999]
["ddr32_3733_ios_vdd_dyn_ddr4_2933_32_read","ddr32_3733_ios","vdd_dyn","ddr4_2933_32_read",101.06934687499999,"Updated on 3-11",104.7493453]
["ddr32_3733_ios_vdd_dyn_ddr4_2933_32_write","ddr32_3733_ios","vdd_dyn","ddr4_2933_32_write",119.34560312500001,"Updated on 3-11",123.0765624]
["ddr32_3733_ios_vdd_dyn_ddr4_3200_32_idle","ddr32_3733_ios","vdd_dyn","ddr4_3200_32_idle",2.3140000000000001,"Updated on 3-11",2.3140000000000001]
["ddr32_3733_ios_vdd_dyn_ddr4_3200_32_read","ddr32_3733_ios","vdd_dyn","ddr4_3200_32_read",110.27,"Updated on 3-11",114.285]
["ddr32_3733_ios_vdd_dyn_ddr4_3200_32_write","ddr32_3733_ios","vdd_dyn","ddr4_3200_32_write",130.21,"Updated on 3-11",134.28059999999999]
["ddr32_3733_ios_vdd_dyn_ddr4_3467_32_idle","ddr32_3733_ios","vdd_dyn","ddr4_3467_32_idle",2.3140000000000001,"Updated on 3-11",2.5070743750000002]
["ddr32_3733_ios_vdd_dyn_ddr4_3467_32_read","ddr32_3733_ios","vdd_dyn","ddr4_3467_32_read",119.47065312499998,"Updated on 3-11",123.82065470000001]
["ddr32_3733_ios_vdd_dyn_ddr4_3467_32_write","ddr32_3733_ios","vdd_dyn","ddr4_3467_32_write",141.07439687499999,"Updated on 3-11",145.48463760000001]
["ddr32_3733_ios_vdd_dyn_ddr4_3733_32_idle","ddr32_3733_ios","vdd_dyn","ddr4_3733_32_idle",2.3140000000000001,"Updated on 3-11",2.6994256249999999]
["ddr32_3733_ios_vdd_dyn_ddr4_3733_32_read","ddr32_3733_ios","vdd_dyn","ddr4_3733_32_read",128.636846875,"Updated on 3-11",133.32059530000001]
["ddr32_3733_ios_vdd_dyn_ddr4_3733_32_write","ddr32_3733_ios","vdd_dyn","ddr4_3733_32_write",151.89810312500001,"Updated on 3-11",156.64671240000001]
["ddr32_3733_ios_vdd_dyn_ddr4_533_32_idle","ddr32_3733_ios","vdd_dyn","ddr4_533_32_idle",2.3140000000000001,"Updated on 3-11",0.38542562499999999]
["ddr32_3733_ios_vdd_dyn_ddr4_533_32_read","ddr32_3733_ios","vdd_dyn","ddr4_533_32_read",18.366846875,"Updated on 3-11",19.035595310000001]
["ddr32_3733_ios_vdd_dyn_ddr4_533_32_write","ddr32_3733_ios","vdd_dyn","ddr4_533_32_write",21.688103125000001,"Updated on 3-11",22.366112439999998]
["ddr32_3733_ios_vdd_dyn_ddr4_800_32_idle","ddr32_3733_ios","vdd_dyn","ddr4_800_32_idle",2.3140000000000001,"Updated on 3-11",0.57850000000000001]
["ddr32_3733_ios_vdd_dyn_ddr4_800_32_read","ddr32_3733_ios","vdd_dyn","ddr4_800_32_read",27.567499999999999,"Updated on 3-11",28.571249999999999]
["ddr32_3733_ios_vdd_dyn_ddr4_800_32_write","ddr32_3733_ios","vdd_dyn","ddr4_800_32_write",32.552500000000002,"Updated on 3-11",33.570149999999998]
["ddr32_3733_ios_vdd_dyn_deep_sleep","ddr32_3733_ios","vdd_dyn","deep_sleep",1.31,"Updated on 3-11",7.2312500000000002E-2]
["ddr32_3733_ios_vdd_dyn_lpddr4_100_32_idle","ddr32_3733_ios","vdd_dyn","lpddr4_100_32_idle",2.5400482185909454,"Updated on 3-11",3.9662500000000001]
["ddr32_3733_ios_vdd_dyn_lpddr4_100_32_read","ddr32_3733_ios","vdd_dyn","lpddr4_100_32_read",2.2740423252076076,"Updated on 3-11",3.65671875]
["ddr32_3733_ios_vdd_dyn_lpddr4_100_32_write","ddr32_3733_ios","vdd_dyn","lpddr4_100_32_write",1.31,"Updated on 3-11",0.77085124999999999]
["ddr32_3733_ios_vdd_dyn_lpddr4_1067_32_idle","ddr32_3733_ios","vdd_dyn","lpddr4_1067_32_idle",27.102314492365387,"Updated on 3-11",42.280225000000002]
["ddr32_3733_ios_vdd_dyn_lpddr4_1067_32_read","ddr32_3733_ios","vdd_dyn","lpddr4_1067_32_read",24.264031609965176,"Updated on 3-11",38.980621880000001]
["ddr32_3733_ios_vdd_dyn_lpddr4_1067_32_write","ddr32_3733_ios","vdd_dyn","lpddr4_1067_32_write",1.31,"Updated on 3-11",0.96392562500000001]
["ddr32_3733_ios_vdd_dyn_lpddr4_1333_32_idle","ddr32_3733_ios","vdd_dyn","lpddr4_1333_32_idle",33.858842753817306,"Updated on 3-11",52.870112499999998]
["ddr32_3733_ios_vdd_dyn_lpddr4_1333_32_read","ddr32_3733_ios","vdd_dyn","lpddr4_1333_32_read",30.31298419501741,"Updated on 3-11",48.744060939999997]
["ddr32_3733_ios_vdd_dyn_lpddr4_1333_32_write","ddr32_3733_ios","vdd_dyn","lpddr4_1333_32_write",1.31,"Updated on 3-11",1.157]
["ddr32_3733_ios_vdd_dyn_lpddr4_1600_32_idle","ddr32_3733_ios","vdd_dyn","lpddr4_1600_32_idle",40.640771497455127,"Updated on 3-11",63.46]
["ddr32_3733_ios_vdd_dyn_lpddr4_1600_32_read","ddr32_3733_ios","vdd_dyn","lpddr4_1600_32_read",36.384677203321722,"Updated on 3-11",58.5075]
["ddr32_3733_ios_vdd_dyn_lpddr4_1600_32_write","ddr32_3733_ios","vdd_dyn","lpddr4_1600_32_write",1.31,"Updated on 3-11",1.3500743749999999]
["ddr32_3733_ios_vdd_dyn_lpddr4_1867_32_idle","ddr32_3733_ios","vdd_dyn","lpddr4_1867_32_idle",47.422700241092947,"Updated on 3-11",74.049887499999997]
["ddr32_3733_ios_vdd_dyn_lpddr4_1867_32_read","ddr32_3733_ios","vdd_dyn","lpddr4_1867_32_read",42.456370211626037,"Updated on 3-11",68.270939060000003]
["ddr32_3733_ios_vdd_dyn_lpddr4_1867_32_write","ddr32_3733_ios","vdd_dyn","lpddr4_1867_32_write",1.31,"Updated on 3-11",1.5424256249999999]
["ddr32_3733_ios_vdd_dyn_lpddr4_2133_32_idle","ddr32_3733_ios","vdd_dyn","lpddr4_2133_32_idle",54.179228502544866,"Updated on 3-11",84.600112499999994]
["ddr32_3733_ios_vdd_dyn_lpddr4_2133_32_read","ddr32_3733_ios","vdd_dyn","lpddr4_2133_32_read",48.505322796678271,"Updated on 3-11",77.997810939999994]
["ddr32_3733_ios_vdd_dyn_lpddr4_2133_32_write","ddr32_3733_ios","vdd_dyn","lpddr4_2133_32_write",1.31,"Updated on 3-11",1.7355]
["ddr32_3733_ios_vdd_dyn_lpddr4_2400_32_idle","ddr32_3733_ios","vdd_dyn","lpddr4_2400_32_idle",60.961157246182687,"Updated on 3-11",95.19]
["ddr32_3733_ios_vdd_dyn_lpddr4_2400_32_read","ddr32_3733_ios","vdd_dyn","lpddr4_2400_32_read",54.577015804982587,"Updated on 3-11",87.761250000000004]
["ddr32_3733_ios_vdd_dyn_lpddr4_2400_32_write","ddr32_3733_ios","vdd_dyn","lpddr4_2400_32_write",1.31,"Updated on 3-11",1.928574375]
["ddr32_3733_ios_vdd_dyn_lpddr4_2667_32_idle","ddr32_3733_ios","vdd_dyn","lpddr4_2667_32_idle",67.743085989820514,"Updated on 3-11",105.7798875]
["ddr32_3733_ios_vdd_dyn_lpddr4_2667_32_read","ddr32_3733_ios","vdd_dyn","lpddr4_2667_32_read",60.648708813286902,"Updated on 3-11",97.52468906]
["ddr32_3733_ios_vdd_dyn_lpddr4_2667_32_write","ddr32_3733_ios","vdd_dyn","lpddr4_2667_32_write",1.31,"Updated on 3-11",2.1209256249999999]
["ddr32_3733_ios_vdd_dyn_lpddr4_2933_32_idle","ddr32_3733_ios","vdd_dyn","lpddr4_2933_32_idle",74.499614251272433,"Updated on 3-11",116.3301125]
["ddr32_3733_ios_vdd_dyn_lpddr4_2933_32_read","ddr32_3733_ios","vdd_dyn","lpddr4_2933_32_read",66.697661398339136,"Updated on 3-11",107.2515609]
["ddr32_3733_ios_vdd_dyn_lpddr4_2933_32_write","ddr32_3733_ios","vdd_dyn","lpddr4_2933_32_write",1.31,"Updated on 3-11",2.3140000000000001]
["ddr32_3733_ios_vdd_dyn_lpddr4_3200_32_idle","ddr32_3733_ios","vdd_dyn","lpddr4_3200_32_idle",81.281542994910254,"Updated on 3-11",126.92]
["ddr32_3733_ios_vdd_dyn_lpddr4_3200_32_read","ddr32_3733_ios","vdd_dyn","lpddr4_3200_32_read",72.769354406643444,"Updated on 3-11",117.015]
["ddr32_3733_ios_vdd_dyn_lpddr4_3200_32_write","ddr32_3733_ios","vdd_dyn","lpddr4_3200_32_write",1.31,"Updated on 3-11",2.5070743750000002]
["ddr32_3733_ios_vdd_dyn_lpddr4_3467_32_idle","ddr32_3733_ios","vdd_dyn","lpddr4_3467_32_idle",88.063471738548088,"Updated on 3-11",137.50988749999999]
["ddr32_3733_ios_vdd_dyn_lpddr4_3467_32_read","ddr32_3733_ios","vdd_dyn","lpddr4_3467_32_read",78.841047414947766,"Updated on 3-11",126.7784391]
["ddr32_3733_ios_vdd_dyn_lpddr4_3467_32_write","ddr32_3733_ios","vdd_dyn","lpddr4_3467_32_write",1.31,"Updated on 3-11",2.6994256249999999]
["ddr32_3733_ios_vdd_dyn_lpddr4_3733_32_idle","ddr32_3733_ios","vdd_dyn","lpddr4_3733_32_idle",94.82,"Updated on 3-11",148.0601125]
["ddr32_3733_ios_vdd_dyn_lpddr4_3733_32_read","ddr32_3733_ios","vdd_dyn","lpddr4_3733_32_read",84.89,"Updated on 3-11",136.50531090000001]
["ddr32_3733_ios_vdd_dyn_lpddr4_3733_32_write","ddr32_3733_ios","vdd_dyn","lpddr4_3733_32_write",1.31,"Updated on 3-11",2.8925000000000001]
["ddr32_3733_ios_vdd_dyn_lpddr4_4000_32_idle","ddr32_3733_ios","vdd_dyn","lpddr4_4000_32_idle",101.60192874363783,"Updated on 3-11",158.65]
["ddr32_3733_ios_vdd_dyn_lpddr4_4000_32_read","ddr32_3733_ios","vdd_dyn","lpddr4_4000_32_read",90.961693008304309,"Updated on 3-11",146.26875000000001]
["ddr32_3733_ios_vdd_dyn_lpddr4_4000_32_write","ddr32_3733_ios","vdd_dyn","lpddr4_4000_32_write",1.31,"Updated on 3-11",3.0855743750000002]
["ddr32_3733_ios_vdd_dyn_lpddr4_4267_32_idle","ddr32_3733_ios","vdd_dyn","lpddr4_4267_32_idle",108.38385748727563,"Updated on 3-11",169.23988750000001]
["ddr32_3733_ios_vdd_dyn_lpddr4_4267_32_read","ddr32_3733_ios","vdd_dyn","lpddr4_4267_32_read",97.033386016608631,"Updated on 3-11",156.03218910000001]
["ddr32_3733_ios_vdd_dyn_lpddr4_4267_32_write","ddr32_3733_ios","vdd_dyn","lpddr4_4267_32_write",1.31,"Updated on 3-11",3.6156250000000001E-2]
["ddr32_3733_ios_vdd_dyn_lpddr4_50_32_idle","ddr32_3733_ios","vdd_dyn","lpddr4_50_32_idle",1.2700241092954727,"Updated on 3-11",1.983125]
["ddr32_3733_ios_vdd_dyn_lpddr4_50_32_read","ddr32_3733_ios","vdd_dyn","lpddr4_50_32_read",1.1370211626038038,"Updated on 3-11",1.828359375]
["ddr32_3733_ios_vdd_dyn_lpddr4_50_32_write","ddr32_3733_ios","vdd_dyn","lpddr4_50_32_write",1.31,"Updated on 3-11",0.38542562499999999]
["ddr32_3733_ios_vdd_dyn_lpddr4_533_32_idle","ddr32_3733_ios","vdd_dyn","lpddr4_533_32_idle",13.538457005089739,"Updated on 3-11",21.140112500000001]
["ddr32_3733_ios_vdd_dyn_lpddr4_533_32_read","ddr32_3733_ios","vdd_dyn","lpddr4_533_32_read",12.120645593356551,"Updated on 3-11",19.490310940000001]
["ddr32_3733_ios_vdd_dyn_lpddr4_533_32_write","ddr32_3733_ios","vdd_dyn","lpddr4_533_32_write",1.31,"Updated on 3-11",0.57850000000000001]
["ddr32_3733_ios_vdd_dyn_lpddr4_800_32_idle","ddr32_3733_ios","vdd_dyn","lpddr4_800_32_idle",20.320385748727563,"Updated on 3-11",31.73]
["ddr32_3733_ios_vdd_dyn_lpddr4_800_32_read","ddr32_3733_ios","vdd_dyn","lpddr4_800_32_read",18.192338601660861,"Updated on 3-11",29.25375]
["ddr32_3733_ios_vdd_dyn_lpddr4_800_32_write","ddr32_3733_ios","vdd_dyn","lpddr4_800_32_write",0,"",""]
["ddr32_3733_ios_vdd_dyn_sleep_idle","ddr32_3733_ios","vdd_dyn","sleep_idle",0,"",""]
["ddr32_3733_ios_vdd_dyn_sleep_read","ddr32_3733_ios","vdd_dyn","sleep_read",0.5]
["ddr32_3733_ios_vdd_lkg","ddr32_3733_ios","vdd_lkg","",12.46,"Updated on 3-11",10.81]
["ddr32_3733_ios_vddh1_dyn_ddr4_1067_32_idle","ddr32_3733_ios","vddh1_dyn","ddr4_1067_32_idle",33,"",""]
["ddr32_3733_ios_vddh1_dyn_ddr4_1067_32_read","ddr32_3733_ios","vddh1_dyn","ddr4_1067_32_read",72.134,"",""]
["ddr32_3733_ios_vddh1_dyn_ddr4_1067_32_write","ddr32_3733_ios","vddh1_dyn","ddr4_1067_32_write",287.74200000000002,"",""]
["ddr32_3733_ios_vddh1_dyn_ddr4_1333_32_idle","ddr32_3733_ios","vddh1_dyn","ddr4_1333_32_idle",33,"",""]
["ddr32_3733_ios_vddh1_dyn_ddr4_1333_32_read","ddr32_3733_ios","vddh1_dyn","ddr4_1333_32_read",72.665999999999997,"",""]
["ddr32_3733_ios_vddh1_dyn_ddr4_1333_32_write","ddr32_3733_ios","vddh1_dyn","ddr4_1333_32_write",294.65800000000002,"",""]
["ddr32_3733_ios_vddh1_dyn_ddr4_1600_32_idle","ddr32_3733_ios","vddh1_dyn","ddr4_1600_32_idle",33,"",""]
["ddr32_3733_ios_vddh1_dyn_ddr4_1600_32_read","ddr32_3733_ios","vddh1_dyn","ddr4_1600_32_read",73.2,"",""]
["ddr32_3733_ios_vddh1_dyn_ddr4_1600_32_write","ddr32_3733_ios","vddh1_dyn","ddr4_1600_32_write",301.60000000000002,"",""]
["ddr32_3733_ios_vddh1_dyn_ddr4_1867_32_idle","ddr32_3733_ios","vddh1_dyn","ddr4_1867_32_idle",33,"",""]
["ddr32_3733_ios_vddh1_dyn_ddr4_1867_32_read","ddr32_3733_ios","vddh1_dyn","ddr4_1867_32_read",73.731999999999999,"",""]
["ddr32_3733_ios_vddh1_dyn_ddr4_1867_32_write","ddr32_3733_ios","vddh1_dyn","ddr4_1867_32_write",308.51600000000002,"",""]
["ddr32_3733_ios_vddh1_dyn_ddr4_2133_32_idle","ddr32_3733_ios","vddh1_dyn","ddr4_2133_32_idle",33,"",""]
["ddr32_3733_ios_vddh1_dyn_ddr4_2133_32_read","ddr32_3733_ios","vddh1_dyn","ddr4_2133_32_read",74.266000000000005,"",""]
["ddr32_3733_ios_vddh1_dyn_ddr4_2133_32_write","ddr32_3733_ios","vddh1_dyn","ddr4_2133_32_write",315.45800000000003,"",""]
["ddr32_3733_ios_vddh1_dyn_ddr4_2400_32_idle","ddr32_3733_ios","vddh1_dyn","ddr4_2400_32_idle",33,"",""]
["ddr32_3733_ios_vddh1_dyn_ddr4_2400_32_read","ddr32_3733_ios","vddh1_dyn","ddr4_2400_32_read",74.8,"",""]
["ddr32_3733_ios_vddh1_dyn_ddr4_2400_32_write","ddr32_3733_ios","vddh1_dyn","ddr4_2400_32_write",322.39999999999998,"",""]
["ddr32_3733_ios_vddh1_dyn_ddr4_2667_32_idle","ddr32_3733_ios","vddh1_dyn","ddr4_2667_32_idle",33,"",""]
["ddr32_3733_ios_vddh1_dyn_ddr4_2667_32_read","ddr32_3733_ios","vddh1_dyn","ddr4_2667_32_read",75.334000000000003,"",""]
["ddr32_3733_ios_vddh1_dyn_ddr4_2667_32_write","ddr32_3733_ios","vddh1_dyn","ddr4_2667_32_write",329.34199999999998,"",""]
["ddr32_3733_ios_vddh1_dyn_ddr4_2933_32_idle","ddr32_3733_ios","vddh1_dyn","ddr4_2933_32_idle",33,"",""]
["ddr32_3733_ios_vddh1_dyn_ddr4_2933_32_read","ddr32_3733_ios","vddh1_dyn","ddr4_2933_32_read",75.866,"",""]
["ddr32_3733_ios_vddh1_dyn_ddr4_2933_32_write","ddr32_3733_ios","vddh1_dyn","ddr4_2933_32_write",336.25799999999998,"",""]
["ddr32_3733_ios_vddh1_dyn_ddr4_3200_32_idle","ddr32_3733_ios","vddh1_dyn","ddr4_3200_32_idle",33,"",""]
["ddr32_3733_ios_vddh1_dyn_ddr4_3200_32_read","ddr32_3733_ios","vddh1_dyn","ddr4_3200_32_read",76.400000000000006,"",""]
["ddr32_3733_ios_vddh1_dyn_ddr4_3200_32_write","ddr32_3733_ios","vddh1_dyn","ddr4_3200_32_write",343.2,"",""]
["ddr32_3733_ios_vddh1_dyn_ddr4_3467_32_idle","ddr32_3733_ios","vddh1_dyn","ddr4_3467_32_idle",33,"",""]
["ddr32_3733_ios_vddh1_dyn_ddr4_3467_32_read","ddr32_3733_ios","vddh1_dyn","ddr4_3467_32_read",76.933999999999997,"",""]
["ddr32_3733_ios_vddh1_dyn_ddr4_3467_32_write","ddr32_3733_ios","vddh1_dyn","ddr4_3467_32_write",350.142,"",""]
["ddr32_3733_ios_vddh1_dyn_ddr4_3733_32_idle","ddr32_3733_ios","vddh1_dyn","ddr4_3733_32_idle",33,"",""]
["ddr32_3733_ios_vddh1_dyn_ddr4_3733_32_read","ddr32_3733_ios","vddh1_dyn","ddr4_3733_32_read",77.465999999999994,"",""]
["ddr32_3733_ios_vddh1_dyn_ddr4_3733_32_write","ddr32_3733_ios","vddh1_dyn","ddr4_3733_32_write",357.05799999999999,"",""]
["ddr32_3733_ios_vddh1_dyn_ddr4_533_32_idle","ddr32_3733_ios","vddh1_dyn","ddr4_533_32_idle",33,"",""]
["ddr32_3733_ios_vddh1_dyn_ddr4_533_32_read","ddr32_3733_ios","vddh1_dyn","ddr4_533_32_read",71.066000000000003,"",""]
["ddr32_3733_ios_vddh1_dyn_ddr4_533_32_write","ddr32_3733_ios","vddh1_dyn","ddr4_533_32_write",273.858,"",""]
["ddr32_3733_ios_vddh1_dyn_ddr4_800_32_idle","ddr32_3733_ios","vddh1_dyn","ddr4_800_32_idle",33,"",""]
["ddr32_3733_ios_vddh1_dyn_ddr4_800_32_read","ddr32_3733_ios","vddh1_dyn","ddr4_800_32_read",71.599999999999994,"",""]
["ddr32_3733_ios_vddh1_dyn_ddr4_800_32_write","ddr32_3733_ios","vddh1_dyn","ddr4_800_32_write",280.8,"",""]
["ddr32_3733_ios_vddh1_dyn_deep_sleep","ddr32_3733_ios","vddh1_dyn","deep_sleep",0.41699999999999998,"",""]
["ddr32_3733_ios_vddh1_dyn_lpddr4_100_32_idle","ddr32_3733_ios","vddh1_dyn","lpddr4_100_32_idle",33,"",""]
["ddr32_3733_ios_vddh1_dyn_lpddr4_100_32_read","ddr32_3733_ios","vddh1_dyn","lpddr4_100_32_read",70.2,"",""]
["ddr32_3733_ios_vddh1_dyn_lpddr4_100_32_write","ddr32_3733_ios","vddh1_dyn","lpddr4_100_32_write",262.60000000000002,"",""]
["ddr32_3733_ios_vddh1_dyn_lpddr4_1067_32_idle","ddr32_3733_ios","vddh1_dyn","lpddr4_1067_32_idle",33,"",""]
["ddr32_3733_ios_vddh1_dyn_lpddr4_1067_32_read","ddr32_3733_ios","vddh1_dyn","lpddr4_1067_32_read",72.134,"",""]
["ddr32_3733_ios_vddh1_dyn_lpddr4_1067_32_write","ddr32_3733_ios","vddh1_dyn","lpddr4_1067_32_write",287.74200000000002,"",""]
["ddr32_3733_ios_vddh1_dyn_lpddr4_1333_32_idle","ddr32_3733_ios","vddh1_dyn","lpddr4_1333_32_idle",33,"",""]
["ddr32_3733_ios_vddh1_dyn_lpddr4_1333_32_read","ddr32_3733_ios","vddh1_dyn","lpddr4_1333_32_read",72.665999999999997,"",""]
["ddr32_3733_ios_vddh1_dyn_lpddr4_1333_32_write","ddr32_3733_ios","vddh1_dyn","lpddr4_1333_32_write",294.65800000000002,"",""]
["ddr32_3733_ios_vddh1_dyn_lpddr4_1600_32_idle","ddr32_3733_ios","vddh1_dyn","lpddr4_1600_32_idle",33,"",""]
["ddr32_3733_ios_vddh1_dyn_lpddr4_1600_32_read","ddr32_3733_ios","vddh1_dyn","lpddr4_1600_32_read",73.2,"",""]
["ddr32_3733_ios_vddh1_dyn_lpddr4_1600_32_write","ddr32_3733_ios","vddh1_dyn","lpddr4_1600_32_write",301.60000000000002,"",""]
["ddr32_3733_ios_vddh1_dyn_lpddr4_1867_32_idle","ddr32_3733_ios","vddh1_dyn","lpddr4_1867_32_idle",33,"",""]
["ddr32_3733_ios_vddh1_dyn_lpddr4_1867_32_read","ddr32_3733_ios","vddh1_dyn","lpddr4_1867_32_read",73.731999999999999,"",""]
["ddr32_3733_ios_vddh1_dyn_lpddr4_1867_32_write","ddr32_3733_ios","vddh1_dyn","lpddr4_1867_32_write",308.51600000000002,"",""]
["ddr32_3733_ios_vddh1_dyn_lpddr4_2133_32_idle","ddr32_3733_ios","vddh1_dyn","lpddr4_2133_32_idle",33,"",""]
["ddr32_3733_ios_vddh1_dyn_lpddr4_2133_32_read","ddr32_3733_ios","vddh1_dyn","lpddr4_2133_32_read",74.266000000000005,"",""]
["ddr32_3733_ios_vddh1_dyn_lpddr4_2133_32_write","ddr32_3733_ios","vddh1_dyn","lpddr4_2133_32_write",315.45800000000003,"",""]
["ddr32_3733_ios_vddh1_dyn_lpddr4_2400_32_idle","ddr32_3733_ios","vddh1_dyn","lpddr4_2400_32_idle",33,"",""]
["ddr32_3733_ios_vddh1_dyn_lpddr4_2400_32_read","ddr32_3733_ios","vddh1_dyn","lpddr4_2400_32_read",74.8,"",""]
["ddr32_3733_ios_vddh1_dyn_lpddr4_2400_32_write","ddr32_3733_ios","vddh1_dyn","lpddr4_2400_32_write",322.39999999999998,"",""]
["ddr32_3733_ios_vddh1_dyn_lpddr4_2667_32_idle","ddr32_3733_ios","vddh1_dyn","lpddr4_2667_32_idle",33,"",""]
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["ddr32_3733_ios_vddh1_dyn_lpddr4_50_32_idle","ddr32_3733_ios","vddh1_dyn","lpddr4_50_32_idle",33,"",""]
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["ddr32_3733_ios_vddh1_dyn_lpddr4_533_32_idle","ddr32_3733_ios","vddh1_dyn","lpddr4_533_32_idle",33,"",""]
["ddr32_3733_ios_vddh1_dyn_lpddr4_533_32_read","ddr32_3733_ios","vddh1_dyn","lpddr4_533_32_read",71.066000000000003,"",""]
["ddr32_3733_ios_vddh1_dyn_lpddr4_533_32_write","ddr32_3733_ios","vddh1_dyn","lpddr4_533_32_write",273.858,"",""]
["ddr32_3733_ios_vddh1_dyn_lpddr4_800_32_idle","ddr32_3733_ios","vddh1_dyn","lpddr4_800_32_idle",33,"",""]
["ddr32_3733_ios_vddh1_dyn_lpddr4_800_32_read","ddr32_3733_ios","vddh1_dyn","lpddr4_800_32_read",71.599999999999994,"",""]
["ddr32_3733_ios_vddh1_dyn_lpddr4_800_32_write","ddr32_3733_ios","vddh1_dyn","lpddr4_800_32_write",280.8,"",""]
["ddr32_3733_ios_vddh1_dyn_sleep_idle","ddr32_3733_ios","vddh1_dyn","sleep_idle",0,"",""]
["ddr32_3733_ios_vddh1_dyn_sleep_read","ddr32_3733_ios","vddh1_dyn","sleep_read",0,"",""]
["ddr32_3733_ios_vddh1_dyn_sleep_write","ddr32_3733_ios","vddh1_dyn","sleep_write",0,"",""]
["ddr32_3733_ios_vddh1_lkg","ddr32_3733_ios","vddh1_lkg","",108.82,"Updated on 3-11",8.8709999999999997E-2]
["ddr32_3733_ios_vddh2_dyn_ddr4_1067_32_idle","ddr32_3733_ios","vddh2_dyn","ddr4_1067_32_idle",0,"",""]
["ddr32_3733_ios_vddh2_dyn_ddr4_1067_32_read","ddr32_3733_ios","vddh2_dyn","ddr4_1067_32_read",0,"",""]
["ddr32_3733_ios_vddh2_dyn_ddr4_1067_32_write","ddr32_3733_ios","vddh2_dyn","ddr4_1067_32_write",0,"",""]
["ddr32_3733_ios_vddh2_dyn_ddr4_1333_32_idle","ddr32_3733_ios","vddh2_dyn","ddr4_1333_32_idle",0,"",""]
["ddr32_3733_ios_vddh2_dyn_ddr4_1333_32_read","ddr32_3733_ios","vddh2_dyn","ddr4_1333_32_read",0,"",""]
["ddr32_3733_ios_vddh2_dyn_ddr4_1333_32_write","ddr32_3733_ios","vddh2_dyn","ddr4_1333_32_write",0,"",""]
["ddr32_3733_ios_vddh2_dyn_ddr4_1600_32_idle","ddr32_3733_ios","vddh2_dyn","ddr4_1600_32_idle",0,"",""]
["ddr32_3733_ios_vddh2_dyn_ddr4_1600_32_read","ddr32_3733_ios","vddh2_dyn","ddr4_1600_32_read",0,"",""]
["ddr32_3733_ios_vddh2_dyn_ddr4_1600_32_write","ddr32_3733_ios","vddh2_dyn","ddr4_1600_32_write",0,"",""]
["ddr32_3733_ios_vddh2_dyn_ddr4_1867_32_idle","ddr32_3733_ios","vddh2_dyn","ddr4_1867_32_idle",0,"",""]
["ddr32_3733_ios_vddh2_dyn_ddr4_1867_32_read","ddr32_3733_ios","vddh2_dyn","ddr4_1867_32_read",0,"",""]
["ddr32_3733_ios_vddh2_dyn_ddr4_1867_32_write","ddr32_3733_ios","vddh2_dyn","ddr4_1867_32_write",0,"",""]
["ddr32_3733_ios_vddh2_dyn_ddr4_2133_32_idle","ddr32_3733_ios","vddh2_dyn","ddr4_2133_32_idle",0,"",""]
["ddr32_3733_ios_vddh2_dyn_ddr4_2133_32_read","ddr32_3733_ios","vddh2_dyn","ddr4_2133_32_read",0,"",""]
["ddr32_3733_ios_vddh2_dyn_ddr4_2133_32_write","ddr32_3733_ios","vddh2_dyn","ddr4_2133_32_write",0,"",""]
["ddr32_3733_ios_vddh2_dyn_ddr4_2400_32_idle","ddr32_3733_ios","vddh2_dyn","ddr4_2400_32_idle",0,"",""]
["ddr32_3733_ios_vddh2_dyn_ddr4_2400_32_read","ddr32_3733_ios","vddh2_dyn","ddr4_2400_32_read",0,"",""]
["ddr32_3733_ios_vddh2_dyn_ddr4_2400_32_write","ddr32_3733_ios","vddh2_dyn","ddr4_2400_32_write",0,"",""]
["ddr32_3733_ios_vddh2_dyn_ddr4_2667_32_idle","ddr32_3733_ios","vddh2_dyn","ddr4_2667_32_idle",0,"",""]
["ddr32_3733_ios_vddh2_dyn_ddr4_2667_32_read","ddr32_3733_ios","vddh2_dyn","ddr4_2667_32_read",0,"",""]
["ddr32_3733_ios_vddh2_dyn_ddr4_2667_32_write","ddr32_3733_ios","vddh2_dyn","ddr4_2667_32_write",0,"",""]
["ddr32_3733_ios_vddh2_dyn_ddr4_2933_32_idle","ddr32_3733_ios","vddh2_dyn","ddr4_2933_32_idle",0,"",""]
["ddr32_3733_ios_vddh2_dyn_ddr4_2933_32_read","ddr32_3733_ios","vddh2_dyn","ddr4_2933_32_read",0,"",""]
["ddr32_3733_ios_vddh2_dyn_ddr4_2933_32_write","ddr32_3733_ios","vddh2_dyn","ddr4_2933_32_write",0,"",""]
["ddr32_3733_ios_vddh2_dyn_ddr4_3200_32_idle","ddr32_3733_ios","vddh2_dyn","ddr4_3200_32_idle",0,"",""]
["ddr32_3733_ios_vddh2_dyn_ddr4_3200_32_read","ddr32_3733_ios","vddh2_dyn","ddr4_3200_32_read",0,"",""]
["ddr32_3733_ios_vddh2_dyn_ddr4_3200_32_write","ddr32_3733_ios","vddh2_dyn","ddr4_3200_32_write",0,"",""]
["ddr32_3733_ios_vddh2_dyn_ddr4_3467_32_idle","ddr32_3733_ios","vddh2_dyn","ddr4_3467_32_idle",0,"",""]
["ddr32_3733_ios_vddh2_dyn_ddr4_3467_32_read","ddr32_3733_ios","vddh2_dyn","ddr4_3467_32_read",0,"",""]
["ddr32_3733_ios_vddh2_dyn_ddr4_3467_32_write","ddr32_3733_ios","vddh2_dyn","ddr4_3467_32_write",0,"",""]
["ddr32_3733_ios_vddh2_dyn_ddr4_3733_32_idle","ddr32_3733_ios","vddh2_dyn","ddr4_3733_32_idle",0,"",""]
["ddr32_3733_ios_vddh2_dyn_ddr4_3733_32_read","ddr32_3733_ios","vddh2_dyn","ddr4_3733_32_read",0,"",""]
["ddr32_3733_ios_vddh2_dyn_ddr4_3733_32_write","ddr32_3733_ios","vddh2_dyn","ddr4_3733_32_write",0,"",""]
["ddr32_3733_ios_vddh2_dyn_ddr4_533_32_idle","ddr32_3733_ios","vddh2_dyn","ddr4_533_32_idle",0,"",""]
["ddr32_3733_ios_vddh2_dyn_ddr4_533_32_read","ddr32_3733_ios","vddh2_dyn","ddr4_533_32_read",0,"",""]
["ddr32_3733_ios_vddh2_dyn_ddr4_533_32_write","ddr32_3733_ios","vddh2_dyn","ddr4_533_32_write",0,"",""]
["ddr32_3733_ios_vddh2_dyn_ddr4_800_32_idle","ddr32_3733_ios","vddh2_dyn","ddr4_800_32_idle",0,"",""]
["ddr32_3733_ios_vddh2_dyn_ddr4_800_32_read","ddr32_3733_ios","vddh2_dyn","ddr4_800_32_read",0,"",""]
["ddr32_3733_ios_vddh2_dyn_ddr4_800_32_write","ddr32_3733_ios","vddh2_dyn","ddr4_800_32_write",0,"",""]
["ddr32_3733_ios_vddh2_dyn_deep_sleep","ddr32_3733_ios","vddh2_dyn","deep_sleep",0.41699999999999998,"",""]
["ddr32_3733_ios_vddh2_dyn_lpddr4_100_32_idle","ddr32_3733_ios","vddh2_dyn","lpddr4_100_32_idle",0,"Updated on 3-11",50]
["ddr32_3733_ios_vddh2_dyn_lpddr4_100_32_read","ddr32_3733_ios","vddh2_dyn","lpddr4_100_32_read",0,"Updated on 3-11",50]
["ddr32_3733_ios_vddh2_dyn_lpddr4_100_32_write","ddr32_3733_ios","vddh2_dyn","lpddr4_100_32_write",0,"Updated on 3-11",50]
["ddr32_3733_ios_vddh2_dyn_lpddr4_1067_32_idle","ddr32_3733_ios","vddh2_dyn","lpddr4_1067_32_idle",0,"Updated on 3-11",50]
["ddr32_3733_ios_vddh2_dyn_lpddr4_1067_32_read","ddr32_3733_ios","vddh2_dyn","lpddr4_1067_32_read",0,"Updated on 3-11",50]
["ddr32_3733_ios_vddh2_dyn_lpddr4_1067_32_write","ddr32_3733_ios","vddh2_dyn","lpddr4_1067_32_write",0,"Updated on 3-11",50]
["ddr32_3733_ios_vddh2_dyn_lpddr4_1333_32_idle","ddr32_3733_ios","vddh2_dyn","lpddr4_1333_32_idle",0,"Updated on 3-11",50]
["ddr32_3733_ios_vddh2_dyn_lpddr4_1333_32_read","ddr32_3733_ios","vddh2_dyn","lpddr4_1333_32_read",0,"Updated on 3-11",50]
["ddr32_3733_ios_vddh2_dyn_lpddr4_1333_32_write","ddr32_3733_ios","vddh2_dyn","lpddr4_1333_32_write",0,"Updated on 3-11",50]
["ddr32_3733_ios_vddh2_dyn_lpddr4_1600_32_idle","ddr32_3733_ios","vddh2_dyn","lpddr4_1600_32_idle",0,"Updated on 3-11",50]
["ddr32_3733_ios_vddh2_dyn_lpddr4_1600_32_read","ddr32_3733_ios","vddh2_dyn","lpddr4_1600_32_read",0,"Updated on 3-11",50]
["ddr32_3733_ios_vddh2_dyn_lpddr4_1600_32_write","ddr32_3733_ios","vddh2_dyn","lpddr4_1600_32_write",0,"Updated on 3-11",50]
["ddr32_3733_ios_vddh2_dyn_lpddr4_1867_32_idle","ddr32_3733_ios","vddh2_dyn","lpddr4_1867_32_idle",0,"Updated on 3-11",50]
["ddr32_3733_ios_vddh2_dyn_lpddr4_1867_32_read","ddr32_3733_ios","vddh2_dyn","lpddr4_1867_32_read",0,"Updated on 3-11",50]
["ddr32_3733_ios_vddh2_dyn_lpddr4_1867_32_write","ddr32_3733_ios","vddh2_dyn","lpddr4_1867_32_write",0,"Updated on 3-11",50]
["ddr32_3733_ios_vddh2_dyn_lpddr4_2133_32_idle","ddr32_3733_ios","vddh2_dyn","lpddr4_2133_32_idle",0,"Updated on 3-11",50]
["ddr32_3733_ios_vddh2_dyn_lpddr4_2133_32_read","ddr32_3733_ios","vddh2_dyn","lpddr4_2133_32_read",0,"Updated on 3-11",50]
["ddr32_3733_ios_vddh2_dyn_lpddr4_2133_32_write","ddr32_3733_ios","vddh2_dyn","lpddr4_2133_32_write",0,"Updated on 3-11",50]
["ddr32_3733_ios_vddh2_dyn_lpddr4_2400_32_idle","ddr32_3733_ios","vddh2_dyn","lpddr4_2400_32_idle",0,"Updated on 3-11",50]
["ddr32_3733_ios_vddh2_dyn_lpddr4_2400_32_read","ddr32_3733_ios","vddh2_dyn","lpddr4_2400_32_read",0,"Updated on 3-11",50]
["ddr32_3733_ios_vddh2_dyn_lpddr4_2400_32_write","ddr32_3733_ios","vddh2_dyn","lpddr4_2400_32_write",0,"Updated on 3-11",50]
["ddr32_3733_ios_vddh2_dyn_lpddr4_2667_32_idle","ddr32_3733_ios","vddh2_dyn","lpddr4_2667_32_idle",0,"Updated on 3-11",50]
["ddr32_3733_ios_vddh2_dyn_lpddr4_2667_32_read","ddr32_3733_ios","vddh2_dyn","lpddr4_2667_32_read",0,"Updated on 3-11",50]
["ddr32_3733_ios_vddh2_dyn_lpddr4_2667_32_write","ddr32_3733_ios","vddh2_dyn","lpddr4_2667_32_write",0,"Updated on 3-11",50]
["ddr32_3733_ios_vddh2_dyn_lpddr4_2933_32_idle","ddr32_3733_ios","vddh2_dyn","lpddr4_2933_32_idle",0,"Updated on 3-11",50]
["ddr32_3733_ios_vddh2_dyn_lpddr4_2933_32_read","ddr32_3733_ios","vddh2_dyn","lpddr4_2933_32_read",0,"Updated on 3-11",50]
["ddr32_3733_ios_vddh2_dyn_lpddr4_2933_32_write","ddr32_3733_ios","vddh2_dyn","lpddr4_2933_32_write",0,"Updated on 3-11",50]
["ddr32_3733_ios_vddh2_dyn_lpddr4_3200_32_idle","ddr32_3733_ios","vddh2_dyn","lpddr4_3200_32_idle",0,"Updated on 3-11",50]
["ddr32_3733_ios_vddh2_dyn_lpddr4_3200_32_read","ddr32_3733_ios","vddh2_dyn","lpddr4_3200_32_read",0,"Updated on 3-11",50]
["ddr32_3733_ios_vddh2_dyn_lpddr4_3200_32_write","ddr32_3733_ios","vddh2_dyn","lpddr4_3200_32_write",0,"Updated on 3-11",50]
["ddr32_3733_ios_vddh2_dyn_lpddr4_3467_32_idle","ddr32_3733_ios","vddh2_dyn","lpddr4_3467_32_idle",0,"Updated on 3-11",50]
["ddr32_3733_ios_vddh2_dyn_lpddr4_3467_32_read","ddr32_3733_ios","vddh2_dyn","lpddr4_3467_32_read",0,"Updated on 3-11",50]
["ddr32_3733_ios_vddh2_dyn_lpddr4_3467_32_write","ddr32_3733_ios","vddh2_dyn","lpddr4_3467_32_write",0,"Updated on 3-11",50]
["ddr32_3733_ios_vddh2_dyn_lpddr4_3733_32_idle","ddr32_3733_ios","vddh2_dyn","lpddr4_3733_32_idle",0,"Updated on 3-11",50]
["ddr32_3733_ios_vddh2_dyn_lpddr4_3733_32_read","ddr32_3733_ios","vddh2_dyn","lpddr4_3733_32_read",0,"Updated on 3-11",50]
["ddr32_3733_ios_vddh2_dyn_lpddr4_3733_32_write","ddr32_3733_ios","vddh2_dyn","lpddr4_3733_32_write",0,"Updated on 3-11",50]
["ddr32_3733_ios_vddh2_dyn_lpddr4_4000_32_idle","ddr32_3733_ios","vddh2_dyn","lpddr4_4000_32_idle",0,"Updated on 3-11",50]
["ddr32_3733_ios_vddh2_dyn_lpddr4_4000_32_read","ddr32_3733_ios","vddh2_dyn","lpddr4_4000_32_read",0,"Updated on 3-11",50]
["ddr32_3733_ios_vddh2_dyn_lpddr4_4000_32_write","ddr32_3733_ios","vddh2_dyn","lpddr4_4000_32_write",0,"Updated on 3-11",50]
["ddr32_3733_ios_vddh2_dyn_lpddr4_4267_32_idle","ddr32_3733_ios","vddh2_dyn","lpddr4_4267_32_idle",0,"Updated on 3-11",50]
["ddr32_3733_ios_vddh2_dyn_lpddr4_4267_32_read","ddr32_3733_ios","vddh2_dyn","lpddr4_4267_32_read",0,"Updated on 3-11",50]
["ddr32_3733_ios_vddh2_dyn_lpddr4_4267_32_write","ddr32_3733_ios","vddh2_dyn","lpddr4_4267_32_write",0,"Updated on 3-11",50]
["ddr32_3733_ios_vddh2_dyn_lpddr4_50_32_idle","ddr32_3733_ios","vddh2_dyn","lpddr4_50_32_idle",0,"Updated on 3-11",50]
["ddr32_3733_ios_vddh2_dyn_lpddr4_50_32_read","ddr32_3733_ios","vddh2_dyn","lpddr4_50_32_read",0,"Updated on 3-11",50]
["ddr32_3733_ios_vddh2_dyn_lpddr4_50_32_write","ddr32_3733_ios","vddh2_dyn","lpddr4_50_32_write",0,"Updated on 3-11",50]
["ddr32_3733_ios_vddh2_dyn_lpddr4_533_32_idle","ddr32_3733_ios","vddh2_dyn","lpddr4_533_32_idle",0,"Updated on 3-11",50]
["ddr32_3733_ios_vddh2_dyn_lpddr4_533_32_read","ddr32_3733_ios","vddh2_dyn","lpddr4_533_32_read",0,"Updated on 3-11",50]
["ddr32_3733_ios_vddh2_dyn_lpddr4_533_32_write","ddr32_3733_ios","vddh2_dyn","lpddr4_533_32_write",0,"Updated on 3-11",50]
["ddr32_3733_ios_vddh2_dyn_lpddr4_800_32_idle","ddr32_3733_ios","vddh2_dyn","lpddr4_800_32_idle",0,"Updated on 3-11",50]
["ddr32_3733_ios_vddh2_dyn_lpddr4_800_32_read","ddr32_3733_ios","vddh2_dyn","lpddr4_800_32_read",0,"Updated on 3-11",50]
["ddr32_3733_ios_vddh2_dyn_lpddr4_800_32_write","ddr32_3733_ios","vddh2_dyn","lpddr4_800_32_write",0,"Updated on 3-11",50]
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["ddr32_3733_ios_vddh2_dyn_sleep_read","ddr32_3733_ios","vddh2_dyn","sleep_read",0,"",""]
["ddr32_3733_ios_vddh2_dyn_sleep_write","ddr32_3733_ios","vddh2_dyn","sleep_write",0,"",""]
["ddr32_3733_ios_vddh2_lkg","ddr32_3733_ios","vddh2_lkg","",0,"Updated on 3-11",0.11412]
[]
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[]
[]
[]
[]
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[]
["ddr32_3733_phy_vdd_dyn_idle","ddr32_3733_phy","vdd_dyn_idle","",0.11,"Updated on 3-11",0.15]
["ddr32_3733_phy_vdd_dyn_int_trk","ddr32_3733_phy","vdd_dyn_int_trk","",281,"Updated on 3-11",338.7]
["ddr32_3733_phy_vdd_dyn_max","ddr32_3733_phy","vdd_dyn_max","",0.95,"Updated on 3-11",0.95]
["ddr32_3733_phy_vdd_dyn_peak","ddr32_3733_phy","vdd_dyn_peak","",1,"Updated on 3-11",1]
["ddr32_3733_phy_vdd_dyn_sw_trk","ddr32_3733_phy","vdd_dyn_sw_trk","",281,"Updated on 3-11",338.7]
["ddr32_3733_phy_vdd_lkg","ddr32_3733_phy","vdd_lkg","",365.1,"Updated on 3-11",431.6]
["ddr32_3733_phy_vddr_lkg","ddr32_3733_phy","vddr_lkg","",0,"Updated on 3-11",0]
[]
[]
[]
[]
[]
[]
[]
[]
[]
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["DIVTS16FFC1TO128A_vdd_dyn_100","DIVTS16FFC1TO128A","vdd_dyn","100",0.14080000000000001,"",""]
["DIVTS16FFC1TO128A_vdd_dyn_1000","DIVTS16FFC1TO128A","vdd_dyn","1000",1.4079999999999999,"",""]
["DIVTS16FFC1TO128A_vdd_dyn_200","DIVTS16FFC1TO128A","vdd_dyn","200",0.28160000000000002,"",""]
["DIVTS16FFC1TO128A_vdd_dyn_25","DIVTS16FFC1TO128A","vdd_dyn","25",3.5000000000000003E-2,"",""]
["DIVTS16FFC1TO128A_vdd_dyn_300","DIVTS16FFC1TO128A","vdd_dyn","300",0.4224,"",""]
["DIVTS16FFC1TO128A_vdd_dyn_400","DIVTS16FFC1TO128A","vdd_dyn","400",0.56320000000000003,"",""]
["DIVTS16FFC1TO128A_vdd_dyn_50","DIVTS16FFC1TO128A","vdd_dyn","50",7.0000000000000007E-2,"",""]
["DIVTS16FFC1TO128A_vdd_dyn_500","DIVTS16FFC1TO128A","vdd_dyn","500",0.70399999999999996,"",""]
["DIVTS16FFC1TO128A_vdd_dyn_600","DIVTS16FFC1TO128A","vdd_dyn","600",0.8448,"",""]
["DIVTS16FFC1TO128A_vdd_dyn_700","DIVTS16FFC1TO128A","vdd_dyn","700",0.98560000000000003,"",""]
["DIVTS16FFC1TO128A_vdd_dyn_800","DIVTS16FFC1TO128A","vdd_dyn","800",1.1264000000000001,"",""]
["DIVTS16FFC1TO128A_vdd_dyn_900","DIVTS16FFC1TO128A","vdd_dyn","900",1.2672000000000001,"",""]
[]
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[]
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[]
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[]
[]
[]
[]
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["ecap_vdd_dyn_pwm_out_1m_1p8v","ecap","vdd_dyn","pwm_out_1m_1p8v",1.15368E-7,"",""]
["ecap_vdd_dyn_pwm_out_1m_3p3v","ecap","vdd_dyn","pwm_out_1m_3p3v",1.15368E-7,"",""]
["ecap_vdd_dyn_pwm_out_5m_1p8v","ecap","vdd_dyn","pwm_out_5m_1p8v",5.7683999999999997E-7,"",""]
["ecap_vdd_dyn_pwm_out_5m_3p3v","ecap","vdd_dyn","pwm_out_5m_3p3v",5.7683999999999997E-7,"",""]
["ecap_vddh1_dyn_capture_in_5m_1p8v","ecap","vddh1_dyn","capture_in_5m_1p8v",0,"",""]
["ecap_vddh1_dyn_pwm_out_1m_1p8v","ecap","vddh1_dyn","pwm_out_1m_1p8v",5.0738400000000003E-2,"",""]
["ecap_vddh1_dyn_pwm_out_5m_1p8v","ecap","vddh1_dyn","pwm_out_5m_1p8v",0.25369199999999997,"",""]
["ecap_vddh2_dyn_capture_in_1m_3p3v","ecap","vddh2_dyn","capture_in_1m_3p3v",0,"",""]
["ecap_vddh2_dyn_capture_in_5m_3p3v","ecap","vddh2_dyn","capture_in_5m_3p3v",0,"",""]
["ecap_vddh2_dyn_pwm_out_1m_3p3v","ecap","vddh2_dyn","pwm_out_1m_3p3v",0.26135999999999998,"",""]
["ecap_vddh2_dyn_pwm_out_5m_3p3v","ecap","vddh2_dyn","pwm_out_5m_3p3v",1.3068,"",""]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
["emmc51phy_top_ls_VCORE_vdd_dyn_int_trk","emmc51phy_top_ls_VCORE","vdd_dyn_int_trk","",0.2,"AM62P tracker update 03-31-23",""]
["emmc51phy_top_ls_VCORE_vdd_dyn_sw_trk","emmc51phy_top_ls_VCORE","vdd_dyn_sw_trk","",0.3,"AM62P tracker update 03-31-23",""]
["emmc51phy_top_ls_VCORE_vdd_lkg","emmc51phy_top_ls_VCORE","vdd_lkg","",0.1,"AM62P tracker update 03-31-23",""]
["emmc51phy_top_ls_VCORE_vddr_lkg","emmc51phy_top_ls_VCORE","vddr_lkg","",0,"AM62P tracker update 03-31-23",""]
[]
[]
[]
[]
[]
["emmc51phy_top_vdd_dyn_ddr_100mbs","emmc51phy_top","vdd_dyn","ddr_100mbs",8.4114799999999993E-6,"SDIO VDDS power estimation - bundle power converted into average power per bit.",""]
["emmc51phy_top_vdd_dyn_ddr_200mbs","emmc51phy_top","vdd_dyn","ddr_200mbs",1.6823000000000001E-5,"SDIO VDDS power estimation - bundle power converted into average power per bit.",""]
["emmc51phy_top_vdd_dyn_hs200","emmc51phy_top","vdd_dyn","hs200",4.2240000000000002,"Arasan PHY - 8 ma full operation at hs400 (so lower for hs200)",""]
["emmc51phy_top_vdd_dyn_hs400","emmc51phy_top","vdd_dyn","hs400",7.04,"Arasan PHY",""]
["emmc51phy_top_vdd_dyn_off","emmc51phy_top","vdd_dyn","off",0,"Arasan PHY",""]
["emmc51phy_top_vdd_dyn_sdr_100mbs","emmc51phy_top","vdd_dyn","sdr_100mbs",1.1297100000000001E-5,"SDIO VDDS power estimation - bundle power converted into average power per bit.",""]
["emmc51phy_top_vdd_dyn_sdr_25mbs","emmc51phy_top","vdd_dyn","sdr_25mbs",2.8242800000000001E-6,"SDIO VDDS power estimation - bundle power converted into average power per bit.",""]
["emmc51phy_top_vdd_dyn_sdr_50mbs","emmc51phy_top","vdd_dyn","sdr_50mbs",5.6485600000000002E-6,"SDIO VDDS power estimation - bundle power converted into average power per bit.",""]
["emmc51phy_top_vdd_lkg","emmc51phy_top","vdd_lkg","",0.17599999999999999,"Arasan PHY 200 uA leakage max",""]
["emmc51phy_top_vdda_dyn_ddr_100mbs","emmc51phy_top","vdda_dyn","ddr_100mbs",5.8079999999999998,"Arasan PHY",""]
["emmc51phy_top_vdda_dyn_ddr_200mbs","emmc51phy_top","vdda_dyn","ddr_200mbs",5.8079999999999998,"Arasan PHY",""]
["emmc51phy_top_vdda_dyn_hs200","emmc51phy_top","vdda_dyn","hs200",5.8079999999999998,"Arasan PHY - 6.6 mA normal operation for DLL - assuming same regardless of mode.",""]
["emmc51phy_top_vdda_dyn_hs400","emmc51phy_top","vdda_dyn","hs400",5.8079999999999998,"Arasan PHY",""]
["emmc51phy_top_vdda_dyn_off","emmc51phy_top","vdda_dyn","off",0,"Arasan PHY",""]
["emmc51phy_top_vdda_dyn_sdr_100mbs","emmc51phy_top","vdda_dyn","sdr_100mbs",5.8079999999999998,"Arasan PHY",""]
["emmc51phy_top_vdda_dyn_sdr_25mbs","emmc51phy_top","vdda_dyn","sdr_25mbs",5.8079999999999998,"Arasan PHY",""]
["emmc51phy_top_vdda_dyn_sdr_50mbs","emmc51phy_top","vdda_dyn","sdr_50mbs",5.8079999999999998,"Arasan PHY",""]
["emmc51phy_top_vdda_lkg","emmc51phy_top","vdda_lkg","",8.7999999999999995E-2,"Arasan PHY 100 ua leakage dll",""]
["emmc51phy_top_vddh1_dyn_ddr_100mbs","emmc51phy_top","vddh1_dyn","ddr_100mbs",0.8,"5-10 pf 50% WR 50% data toggle bundle is 0.5-0.8 mw/bit into 1.8V across emmc4-8.",""]
["emmc51phy_top_vddh1_dyn_ddr_200mbs","emmc51phy_top","vddh1_dyn","ddr_200mbs",1.6,"5-10 pf 50% WR 50% data toggle bundle is 0.8-1.0 mw/bit into 1.8V across emmc4-8.",""]
["emmc51phy_top_vddh1_dyn_hs200","emmc51phy_top","vddh1_dyn","hs200",59.4,"Arasan PHY - half rate should be 60% since the clock does not change and is 20% of the power.",""]
["emmc51phy_top_vddh1_dyn_hs400","emmc51phy_top","vddh1_dyn","hs400",99,"Arasan PHY datasheet specified 50 mA normal operation at 1.98V at 200 Mhz",""]
["emmc51phy_top_vddh1_dyn_off","emmc51phy_top","vddh1_dyn","off",0,"Arasan PHY",""]
["emmc51phy_top_vddh1_dyn_sdr_100mbs","emmc51phy_top","vddh1_dyn","sdr_100mbs",1,"5-10 pf 50% WR 50% data toggle bundle is 0.8-1 mw/bit into 1.8V across emmc4-8.",""]
["emmc51phy_top_vddh1_dyn_sdr_25mbs","emmc51phy_top","vddh1_dyn","sdr_25mbs",0.3,"5-10 pf 50% WR 50% data toggle bundle is 0.2-0.3 mw/bit into 1.8V across emmc4-8.",""]
["emmc51phy_top_vddh1_dyn_sdr_50mbs","emmc51phy_top","vddh1_dyn","sdr_50mbs",0.5,"5-10 pf 50% WR 50% data toggle bundle is 0.4-0.5 mw/bit into 1.8V across emmc4-8.",""]
["emmc51phy_top_vddh1_lkg","emmc51phy_top","vddh1_lkg","",0.59399999999999997,"Arasan PHY 300 uA leakage on 1.98V supply",""]
[]
[]
[]
[]
[]
[]
[]
["epwm_vdd_dyn_on_1p8v","epwm","vdd_dyn","on_1p8v",9.9999999999999995E-7,"",""]
["epwm_vdd_dyn_on_3p3v","epwm","vdd_dyn","on_3p3v",9.9999999999999995E-7,"",""]
["epwm_vddh1_dyn_on_1p8v","epwm","vddh1_dyn","on_1p8v",0.50738399999999995,"",""]
["epwm_vddh2_dyn_on_3p3v","epwm","vddh2_dyn","on_3p3v",2.6135999999999999,"",""]
[]
[]
[]
[]
[]
[]
[]
["eqep_vdd_dyn_on_1p8v","eqep","vdd_dyn","on_1p8v",1.03116E-7,"",""]
["eqep_vdd_dyn_on_3p3v","eqep","vdd_dyn","on_3p3v",1.03116E-7,"",""]
["eqep_vddh1_dyn_on_1p8v","eqep","vddh1_dyn","on_1p8v",4.6510200000000001E-4,"",""]
["eqep_vddh2_dyn_on_3p3v","eqep","vddh2_dyn","on_3p3v",2.6136000000000002E-3,"",""]
[]
[]
[]
[]
[]
[]
["ethernet_vdd_dyn_off","ethernet","vdd_dyn","off","","",""]
["ethernet_vdd_dyn_rgmii_10_1p8v","ethernet","vdd_dyn","rgmii_10_1p8v",0,"",""]
["ethernet_vdd_dyn_rgmii_10_3p3v","ethernet","vdd_dyn","rgmii_10_3p3v",0,"",""]
["ethernet_vdd_dyn_rgmii_100_1p8v","ethernet","vdd_dyn","rgmii_100_1p8v",0,"",""]
["ethernet_vdd_dyn_rgmii_100_3p3v","ethernet","vdd_dyn","rgmii_100_3p3v",0,"",""]
["ethernet_vdd_dyn_rgmii_1000_1p8v","ethernet","vdd_dyn","rgmii_1000_1p8v",0,"",""]
["ethernet_vdd_dyn_rgmii_1000_3p3v","ethernet","vdd_dyn","rgmii_1000_3p3v",0,"",""]
["ethernet_vdd_dyn_rmii_10_1p8v","ethernet","vdd_dyn","rmii_10_1p8v",0,"",""]
["ethernet_vdd_dyn_rmii_10_3p3v","ethernet","vdd_dyn","rmii_10_3p3v",0,"",""]
["ethernet_vdd_dyn_rmii_100_1p8v","ethernet","vdd_dyn","rmii_100_1p8v",0,"",""]
["ethernet_vdd_dyn_rmii_100_3p3v","ethernet","vdd_dyn","rmii_100_3p3v",0,"",""]
["ethernet_vddh1_dyn_off","ethernet","vddh1_dyn","off","0 ","",""]
["ethernet_vddh1_dyn_rgmii_10_1p8v","ethernet","vddh1_dyn","rgmii_10_1p8v",0.59,"",""]
["ethernet_vddh1_dyn_rgmii_10_3p3v","ethernet","vddh1_dyn","rgmii_10_3p3v","0 ","",""]
["ethernet_vddh1_dyn_rgmii_100_1p8v","ethernet","vddh1_dyn","rgmii_100_1p8v",5.12,"",""]
["ethernet_vddh1_dyn_rgmii_100_3p3v","ethernet","vddh1_dyn","rgmii_100_3p3v","0 ","",""]
["ethernet_vddh1_dyn_rgmii_1000_1p8v","ethernet","vddh1_dyn","rgmii_1000_1p8v",25.37,"",""]
["ethernet_vddh1_dyn_rgmii_1000_3p3v","ethernet","vddh1_dyn","rgmii_1000_3p3v","0 ","",""]
["ethernet_vddh1_dyn_rmii_10_1p8v","ethernet","vddh1_dyn","rmii_10_1p8v",0.65,"",""]
["ethernet_vddh1_dyn_rmii_10_3p3v","ethernet","vddh1_dyn","rmii_10_3p3v","0 ","",""]
["ethernet_vddh1_dyn_rmii_100_1p8v","ethernet","vddh1_dyn","rmii_100_1p8v",5.0599999999999996,"",""]
["ethernet_vddh1_dyn_rmii_100_3p3v","ethernet","vddh1_dyn","rmii_100_3p3v","0 ","",""]
["ethernet_vddh2_dyn_off","ethernet","vddh2_dyn","off","0 ","",""]
["ethernet_vddh2_dyn_rgmii_10_1p8v","ethernet","vddh2_dyn","rgmii_10_1p8v","0 ","",""]
["ethernet_vddh2_dyn_rgmii_10_3p3v","ethernet","vddh2_dyn","rgmii_10_3p3v",3.15,"",""]
["ethernet_vddh2_dyn_rgmii_100_1p8v","ethernet","vddh2_dyn","rgmii_100_1p8v","0 ","",""]
["ethernet_vddh2_dyn_rgmii_100_3p3v","ethernet","vddh2_dyn","rgmii_100_3p3v",27.53,"",""]
["ethernet_vddh2_dyn_rgmii_1000_1p8v","ethernet","vddh2_dyn","rgmii_1000_1p8v","0 ","",""]
["ethernet_vddh2_dyn_rgmii_1000_3p3v","ethernet","vddh2_dyn","rgmii_1000_3p3v",136.34,"",""]
["ethernet_vddh2_dyn_rmii_10_1p8v","ethernet","vddh2_dyn","rmii_10_1p8v","0 ","",""]
["ethernet_vddh2_dyn_rmii_10_3p3v","ethernet","vddh2_dyn","rmii_10_3p3v",3.5,"",""]
["ethernet_vddh2_dyn_rmii_100_1p8v","ethernet","vddh2_dyn","rmii_100_1p8v","0 ","",""]
["ethernet_vddh2_dyn_rmii_100_3p3v","ethernet","vddh2_dyn","rmii_100_3p3v",27.18,"",""]
[]
[]
[]
[]
[]
[]
["fssul_vdd_dyn_off","fssul","vdd_dyn","off",0,"",""]
["fssul_vdd_dyn_ospi_ddr_controller_133_1p8v","fssul","vdd_dyn","ospi_ddr_controller_133_1p8v",3.6522800000000002E-5,"",""]
["fssul_vdd_dyn_ospi_ddr_controller_133_3p3v","fssul","vdd_dyn","ospi_ddr_controller_133_3p3v",3.6522800000000002E-5,"",""]
["fssul_vdd_dyn_ospi_ddr_controller_160_1p8v","fssul","vdd_dyn","ospi_ddr_controller_160_1p8v",4.3937199999999997E-5,"",""]
["fssul_vdd_dyn_ospi_ddr_controller_160_3p3v","fssul","vdd_dyn","ospi_ddr_controller_160_3p3v",4.3937199999999997E-5,"",""]
["fssul_vdd_dyn_ospi_sdr_controller_108_1p8v","fssul","vdd_dyn","ospi_sdr_controller_108_1p8v",3.5887499999999998E-5,"",""]
["fssul_vdd_dyn_ospi_sdr_controller_108_3p3v","fssul","vdd_dyn","ospi_sdr_controller_108_3p3v",3.5887499999999998E-5,"",""]
["fssul_vdd_dyn_ospi_sdr_controller_133_1p8v","fssul","vdd_dyn","ospi_sdr_controller_133_1p8v",4.4194799999999999E-5,"",""]
["fssul_vdd_dyn_ospi_sdr_controller_133_3p3v","fssul","vdd_dyn","ospi_sdr_controller_133_3p3v",4.4194799999999999E-5,"",""]
["fssul_vdd_dyn_qspi_ddr_controller_133_1p8v","fssul","vdd_dyn","qspi_ddr_controller_133_1p8v",2.2099500000000001E-5,"",""]
["fssul_vdd_dyn_qspi_ddr_controller_133_3p3v","fssul","vdd_dyn","qspi_ddr_controller_133_3p3v",2.2099500000000001E-5,"",""]
["fssul_vdd_dyn_qspi_ddr_controller_160_1p8v","fssul","vdd_dyn","qspi_ddr_controller_160_1p8v",2.6585899999999999E-5,"",""]
["fssul_vdd_dyn_qspi_ddr_controller_160_3p3v","fssul","vdd_dyn","qspi_ddr_controller_160_3p3v",2.6585899999999999E-5,"",""]
["fssul_vdd_dyn_qspi_sdr_controller_108_1p8v","fssul","vdd_dyn","qspi_sdr_controller_108_1p8v",2.4175299999999999E-5,"",""]
["fssul_vdd_dyn_qspi_sdr_controller_108_3p3v","fssul","vdd_dyn","qspi_sdr_controller_108_3p3v",2.4175299999999999E-5,"",""]
["fssul_vdd_dyn_qspi_sdr_controller_133_1p8v","fssul","vdd_dyn","qspi_sdr_controller_133_1p8v",2.9771500000000001E-5,"",""]
["fssul_vdd_dyn_qspi_sdr_controller_133_3p3v","fssul","vdd_dyn","qspi_sdr_controller_133_3p3v",2.9771500000000001E-5,"",""]
["fssul_vddh1_dyn_ospi_ddr_controller_133_1p8v","fssul","vddh1_dyn","ospi_ddr_controller_133_1p8v",10.124166560000001,"",""]
["fssul_vddh1_dyn_ospi_ddr_controller_160_1p8v","fssul","vddh1_dyn","ospi_ddr_controller_160_1p8v",8.7962683540000004,"",""]
["fssul_vddh1_dyn_ospi_sdr_controller_108_1p8v","fssul","vddh1_dyn","ospi_sdr_controller_108_1p8v",10.96100133,"",""]
["fssul_vddh1_dyn_ospi_sdr_controller_133_1p8v","fssul","vddh1_dyn","ospi_sdr_controller_133_1p8v",13.498270160000001,"",""]
["fssul_vddh1_dyn_qspi_ddr_controller_133_1p8v","fssul","vddh1_dyn","qspi_ddr_controller_133_1p8v",6.7500629569999999,"",""]
["fssul_vddh1_dyn_qspi_ddr_controller_160_1p8v","fssul","vddh1_dyn","qspi_ddr_controller_160_1p8v",5.8647163539999996,"",""]
["fssul_vddh1_dyn_qspi_sdr_controller_108_1p8v","fssul","vddh1_dyn","qspi_sdr_controller_108_1p8v",8.2211277299999992,"",""]
["fssul_vddh1_dyn_qspi_sdr_controller_133_1p8v","fssul","vddh1_dyn","qspi_sdr_controller_133_1p8v",10.124166560000001,"",""]
["fssul_vddh2_dyn_off","fssul","vddh2_dyn","off",0,"",""]
["fssul_vddh2_dyn_ospi_ddr_controller_133_3p3v","fssul","vddh2_dyn","ospi_ddr_controller_133_3p3v",52.150879240000002,"",""]
["fssul_vddh2_dyn_ospi_ddr_controller_160_3p3v","fssul","vddh2_dyn","ospi_ddr_controller_160_3p3v",41.825266560000003,"",""]
["fssul_vddh2_dyn_ospi_sdr_controller_108_3p3v","fssul","vddh2_dyn","ospi_sdr_controller_108_3p3v",56.461522389999999,"",""]
["fssul_vddh2_dyn_ospi_sdr_controller_133_3p3v","fssul","vddh2_dyn","ospi_sdr_controller_133_3p3v",69.531319240000002,"",""]
["fssul_vddh2_dyn_qspi_ddr_controller_133_3p3v","fssul","vddh2_dyn","qspi_ddr_controller_133_3p3v",34.770439240000002,"",""]
["fssul_vddh2_dyn_qspi_ddr_controller_160_3p3v","fssul","vddh2_dyn","qspi_ddr_controller_160_3p3v",27.88606656,"",""]
["fssul_vddh2_dyn_qspi_sdr_controller_108_3p3v","fssul","vddh2_dyn","qspi_sdr_controller_108_3p3v",42.348082390000002,"",""]
["fssul_vddh2_dyn_qspi_sdr_controller_133_3p3v","fssul","vddh2_dyn","qspi_sdr_controller_133_3p3v",52.150879240000002,"",""]
[]
[]
[]
[]
[]
[]
[]
["gpio_vdd_dyn_1mbs_1p8v_20pf","gpio","vdd_dyn","1mbs_1p8v_20pf",1.15368E-7,"",""]
["gpio_vdd_dyn_1mbs_3p3v_20pf","gpio","vdd_dyn","1mbs_3p3v_20pf",1.15368E-7,"",""]
["gpio_vddh1_dyn_1mbs_1p8v_20pf","gpio","vddh1_dyn","1mbs_1p8v_20pf",5.0738400000000003E-2,"",""]
["gpio_vddh2_dyn_1mbs_3p3v_20pf","gpio","vddh2_dyn","1mbs_3p3v_20pf",2.6135999999999999,"",""]
[]
[]
[]
[]
[]
[]
["gpmc_vdd_dyn_16b_100_MHz_1p8V","gpmc","vdd_dyn","16b_100_MHz_1p8V",0,"",""]
["gpmc_vdd_dyn_16b_100_MHz_3p3V","gpmc","vdd_dyn","16b_100_MHz_3p3V",0,"",""]
["gpmc_vdd_dyn_16b_133_MHz_1p8V","gpmc","vdd_dyn","16b_133_MHz_1p8V",0,"",""]
["gpmc_vdd_dyn_16b_133_MHz_3p3V","gpmc","vdd_dyn","16b_133_MHz_3p3V",0,"",""]
["gpmc_vdd_dyn_16b_80_MHz_1p8V","gpmc","vdd_dyn","16b_80_MHz_1p8V",0,"",""]
["gpmc_vdd_dyn_16b_80_MHz_3p3V","gpmc","vdd_dyn","16b_80_MHz_3p3V",0,"",""]
["gpmc_vdd_dyn_off","gpmc","vdd_dyn","off","0 ","",""]
["gpmc_vddh1_dyn_16b_100_MHz_1p8V","gpmc","vddh1_dyn","16b_100_MHz_1p8V",49.06,"",""]
["gpmc_vddh1_dyn_16b_133_MHz_1p8V","gpmc","vddh1_dyn","16b_133_MHz_1p8V",37.119999999999997,"",""]
["gpmc_vddh1_dyn_16b_80_MHz_1p8V","gpmc","vddh1_dyn","16b_80_MHz_1p8V",15.56,"",""]
["gpmc_vddh1_dyn_off","gpmc","vddh1_dyn","off","0 ","",""]
["gpmc_vddh2_dyn_16b_100_MHz_3p3V","gpmc","vddh2_dyn","16b_100_MHz_3p3V",104.57,"",""]
["gpmc_vddh2_dyn_16b_133_MHz_3p3V","gpmc","vddh2_dyn","16b_133_MHz_3p3V",104.31,"",""]
["gpmc_vddh2_dyn_16b_80_MHz_3p3V","gpmc","vddh2_dyn","16b_80_MHz_3p3V",83.65,"",""]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
["i2c_od_vdd_dyn_i2c_100k_1p8v","i2c_od","vdd_dyn","i2c_100k_1p8v",2.07662E-8,"",""]
["i2c_od_vdd_dyn_i2c_100k_3p3v","i2c_od","vdd_dyn","i2c_100k_3p3v",2.07662E-8,"",""]
["i2c_od_vdd_dyn_i2c_1m_1p8v","i2c_od","vdd_dyn","i2c_1m_1p8v",1.35557E-7,"",""]
["i2c_od_vdd_dyn_i2c_3p4m_1p8v","i2c_od","vdd_dyn","i2c_3p4m_1p8v",4.6089500000000003E-7,"",""]
["i2c_od_vdd_dyn_i2c_400k_1p8v","i2c_od","vdd_dyn","i2c_400k_1p8v",5.4223000000000002E-8,"",""]
["i2c_od_vdd_dyn_i2c_400k_3p3v","i2c_od","vdd_dyn","i2c_400k_3p3v",5.4223000000000002E-8,"",""]
["i2c_od_vddh1_dyn_i2c_100k_1p8v","i2c_od","vddh1_dyn","i2c_100k_1p8v",2.0436300000000001E-2,"",""]
["i2c_od_vddh1_dyn_i2c_1m_1p8v","i2c_od","vddh1_dyn","i2c_1m_1p8v",0.10218149999999999,"",""]
["i2c_od_vddh1_dyn_i2c_3p4m_1p8v","i2c_od","vddh1_dyn","i2c_3p4m_1p8v",0.34741709999999998,"",""]
["i2c_od_vddh1_dyn_i2c_400k_1p8v","i2c_od","vddh1_dyn","i2c_400k_1p8v",4.0872600000000002E-2,"",""]
["i2c_od_vddh2_dyn_i2c_100k_3p3v","i2c_od","vddh2_dyn","i2c_100k_3p3v",0.11978999999999999,"",""]
["i2c_od_vddh2_dyn_i2c_400k_3p3v","i2c_od","vddh2_dyn","i2c_400k_3p3v",0.23957999999999999,"",""]
[]
[]
[]
[]
["i2c_vdd_dyn_i2c_100k_1p8v","i2c","vdd_dyn","i2c_100k_1p8v",1.44787E-8,"",""]
["i2c_vdd_dyn_i2c_400k_1p8v","i2c","vdd_dyn","i2c_400k_1p8v",5.7914700000000003E-8,"",""]
["i2c_vddh1_dyn_i2c_100k_1p8v","i2c","vddh1_dyn","i2c_100k_1p8v",2.0518044999999999E-2,"",""]
["i2c_vddh1_dyn_i2c_400k_1p8v","i2c","vddh1_dyn","i2c_400k_1p8v",8.2072180999999994E-2,"",""]
["i2c_vddh2_dyn_i2c_100k_3p3v","i2c","vddh2_dyn","i2c_100k_3p3v",0.12026916,"",""]
["i2c_vddh2_dyn_i2c_400k_3p3v","i2c","vddh2_dyn","i2c_400k_3p3v",0.48107664,"",""]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
["j7_n16_edg_lvl_iopm_vdd_dyn_idle","j7_n16_edg_lvl_iopm","vdd_dyn_idle","",0," J7AHP Update 12/20/21","0"]
["j7_n16_edg_lvl_iopm_vdd_dyn_max","j7_n16_edg_lvl_iopm","vdd_dyn_max","",0.4,"Subchip Vdd dynamic max power as a percent of Vdd tracker dyn power.",""]
["j7_n16_edg_lvl_iopm_vdd_dyn_peak","j7_n16_edg_lvl_iopm","vdd_dyn_peak","",0.48,"Subchip Vdd dynamic power peak as a % of tracker dyn power.  Max +20% for most Joules value if simulated.",""]
["j7_n16_edg_lvl_iopm_vdd_dyn_trk","j7_n16_edg_lvl_iopm","vdd_dyn_trk","",0,"Subchip Vdd dynamic power as provided by tracker (stdcell + SRAM perif 12.5% toggle)",""]
["j7_n16_edg_lvl_iopm_vdd_lkg","j7_n16_edg_lvl_iopm","vdd_lkg","",0,"Subchip routed mm2",""]
["j7_n16_edg_lvl_iopm_vddr_lkg","j7_n16_edg_lvl_iopm","vddr_lkg","",0,"Subchip SRAM Array Supply Leakage",""]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
["LVDSTS16LLBI1E_vdd_dyn_aurora","LVDSTS16LLBI1E","vdd_dyn","aurora",0.113,"",""]
["LVDSTS16LLBI1E_vdd_dyn_disabled","LVDSTS16LLBI1E","vdd_dyn","disabled",0,"",""]
["LVDSTS16LLBI1E_vdd_dyn_mlb","LVDSTS16LLBI1E","vdd_dyn","mlb",3.9E-2,"",""]
["LVDSTS16LLBI1E_vdd_dyn_oldi_dual_18b_modes","LVDSTS16LLBI1E","vdd_dyn","oldi_dual_18b_modes",0.113,"",""]
["LVDSTS16LLBI1E_vdd_dyn_oldi_dual_24b_modes","LVDSTS16LLBI1E","vdd_dyn","oldi_dual_24b_modes",0.13700000000000001,"",""]
["LVDSTS16LLBI1E_vdd_dyn_oldi_single_18b_modes","LVDSTS16LLBI1E","vdd_dyn","oldi_single_18b_modes",6.6000000000000003E-2,"",""]
["LVDSTS16LLBI1E_vdd_dyn_oldi_single_24b_modes","LVDSTS16LLBI1E","vdd_dyn","oldi_single_24b_modes",0.08,"",""]
["LVDSTS16LLBI1E_vdd_lkg","LVDSTS16LLBI1E","vdd_lkg","",4.3999999999999997E-2,"",""]
["LVDSTS16LLBI1E_vddh1_dyn_aurora","LVDSTS16LLBI1E","vddh1_dyn","aurora",11.848000000000001,"",""]
["LVDSTS16LLBI1E_vddh1_dyn_disabled","LVDSTS16LLBI1E","vddh1_dyn","disabled",0,"",""]
["LVDSTS16LLBI1E_vddh1_dyn_mlb","LVDSTS16LLBI1E","vddh1_dyn","mlb",4.4429999999999996,"",""]
["LVDSTS16LLBI1E_vddh1_dyn_oldi_dual_18b_modes","LVDSTS16LLBI1E","vddh1_dyn","oldi_dual_18b_modes",11.848000000000001,"",""]
["LVDSTS16LLBI1E_vddh1_dyn_oldi_dual_24b_modes","LVDSTS16LLBI1E","vddh1_dyn","oldi_dual_24b_modes",14.81,"",""]
["LVDSTS16LLBI1E_vddh1_dyn_oldi_single_18b_modes","LVDSTS16LLBI1E","vddh1_dyn","oldi_single_18b_modes",5.9240000000000004,"",""]
["LVDSTS16LLBI1E_vddh1_dyn_oldi_single_24b_modes","LVDSTS16LLBI1E","vddh1_dyn","oldi_single_24b_modes",7.4050000000000002,"",""]
["LVDSTS16LLBI1E_vddh1_lkg","LVDSTS16LLBI1E","vddh1_lkg","",3.9600000000000003E-2,"",""]
[]
[]
[]
[]
[]
[]
["mcasp_vdd_dyn_12Ch_RXTX_48_ksps_24b_1p8v","mcasp","vdd_dyn","12Ch_RXTX_48_ksps_24b_1p8v",6.1680700000000005E-7,"",""]
["mcasp_vdd_dyn_12Ch_RXTX_48_ksps_24b_3p3v","mcasp","vdd_dyn","12Ch_RXTX_48_ksps_24b_3p3v",6.1680700000000005E-7,"",""]
["mcasp_vdd_dyn_12Ch_TX_48_ksps_24b_1p8v","mcasp","vdd_dyn","12Ch_TX_48_ksps_24b_1p8v",5.3188199999999997E-7,"",""]
["mcasp_vdd_dyn_12Ch_TX_48_ksps_24b_3p3v","mcasp","vdd_dyn","12Ch_TX_48_ksps_24b_3p3v",5.3188199999999997E-7,"",""]
["mcasp_vdd_dyn_16Ch_RXTX_48ksps_24b_1p8v","mcasp","vdd_dyn","16Ch_RXTX_48ksps_24b_1p8v",7.33763E-7,"",""]
["mcasp_vdd_dyn_16Ch_RXTX_48ksps_24b_3p3v","mcasp","vdd_dyn","16Ch_RXTX_48ksps_24b_3p3v",7.33763E-7,"",""]
["mcasp_vdd_dyn_16Ch_TX_48_ksps_24b_1p8v","mcasp","vdd_dyn","16Ch_TX_48_ksps_24b_1p8v",6.6485200000000003E-7,"",""]
["mcasp_vdd_dyn_16Ch_TX_48_ksps_24b_3p3v","mcasp","vdd_dyn","16Ch_TX_48_ksps_24b_3p3v",6.6485200000000003E-7,"",""]
["mcasp_vdd_dyn_2Ch_RX_48_ksps_24b_1p8v","mcasp","vdd_dyn","2Ch_RX_48_ksps_24b_1p8v",1.6220899999999999E-7,"",""]
["mcasp_vdd_dyn_2Ch_RX_48_ksps_24b_3p3v","mcasp","vdd_dyn","2Ch_RX_48_ksps_24b_3p3v",1.6220899999999999E-7,"",""]
["mcasp_vdd_dyn_2Ch_RXTX_48_ksps_24b_1p8v","mcasp","vdd_dyn","2Ch_RXTX_48_ksps_24b_1p8v",3.2441900000000001E-7,"",""]
["mcasp_vdd_dyn_2Ch_RXTX_48_ksps_24b_3p3v","mcasp","vdd_dyn","2Ch_RXTX_48_ksps_24b_3p3v",3.2441900000000001E-7,"",""]
["mcasp_vdd_dyn_2Ch_TX_48_ksps_24b_1p8v","mcasp","vdd_dyn","2Ch_TX_48_ksps_24b_1p8v",3.9891099999999999E-7,"",""]
["mcasp_vdd_dyn_2Ch_TX_48_ksps_24b_3p3v","mcasp","vdd_dyn","2Ch_TX_48_ksps_24b_3p3v",3.9891099999999999E-7,"",""]
["mcasp_vdd_dyn_4Ch_RX_48_ksps_24b_1p8v","mcasp","vdd_dyn","4Ch_RX_48_ksps_24b_1p8v",1.9144800000000001E-7,"",""]
["mcasp_vdd_dyn_4Ch_RX_48_ksps_24b_3p3v","mcasp","vdd_dyn","4Ch_RX_48_ksps_24b_3p3v",1.9144800000000001E-7,"",""]
["mcasp_vdd_dyn_4Ch_RXTX_48_ksps_24b_1p8v","mcasp","vdd_dyn","4Ch_RXTX_48_ksps_24b_1p8v",3.8289600000000002E-7,"",""]
["mcasp_vdd_dyn_4Ch_RXTX_48_ksps_24b_3p3v","mcasp","vdd_dyn","4Ch_RXTX_48_ksps_24b_3p3v",3.8289600000000002E-7,"",""]
["mcasp_vdd_dyn_4Ch_TX_48_ksps_24b_1p8v","mcasp","vdd_dyn","4Ch_TX_48_ksps_24b_1p8v",5.3188199999999997E-7,"",""]
["mcasp_vdd_dyn_4Ch_TX_48_ksps_24b_3p3v","mcasp","vdd_dyn","4Ch_TX_48_ksps_24b_3p3v",5.3188199999999997E-7,"",""]
["mcasp_vdd_dyn_8Ch_RX_48_ksps_24b_1p8v","mcasp","vdd_dyn","8Ch_RX_48_ksps_24b_1p8v",2.4992600000000001E-7,"",""]
["mcasp_vdd_dyn_8Ch_RX_48_ksps_24b_3p3v","mcasp","vdd_dyn","8Ch_RX_48_ksps_24b_3p3v",2.4992600000000001E-7,"",""]
["mcasp_vdd_dyn_8Ch_RXTX_48_ksps_24b_1p8v","mcasp","vdd_dyn","8Ch_RXTX_48_ksps_24b_1p8v",4.9985200000000002E-7,"",""]
["mcasp_vdd_dyn_8Ch_RXTX_48_ksps_24b_3p3v","mcasp","vdd_dyn","8Ch_RXTX_48_ksps_24b_3p3v",4.9985200000000002E-7,"",""]
["mcasp_vdd_dyn_8Ch_TX_48_ksps_24b_1p8v","mcasp","vdd_dyn","8Ch_TX_48_ksps_24b_1p8v",3.9891099999999999E-7,"",""]
["mcasp_vdd_dyn_8Ch_TX_48_ksps_24b_3p3v","mcasp","vdd_dyn","8Ch_TX_48_ksps_24b_3p3v",3.9891099999999999E-7,"",""]
["mcasp_vdd_dyn_off","mcasp","vdd_dyn","off",0,"",""]
["mcasp_vddh1_dyn_12Ch_RXTX_48_ksps_24b_1p8v","mcasp","vddh1_dyn","12Ch_RXTX_48_ksps_24b_1p8v",0.376870223,"",""]
["mcasp_vddh1_dyn_12Ch_TX_48_ksps_24b_1p8v","mcasp","vddh1_dyn","12Ch_TX_48_ksps_24b_1p8v",0.75374044500000004,"",""]
["mcasp_vddh1_dyn_16Ch_RXTX_48ksps_24b_1p8v","mcasp","vddh1_dyn","16Ch_RXTX_48ksps_24b_1p8v",0.376870223,"",""]
["mcasp_vddh1_dyn_16Ch_TX_48_ksps_24b_1p8v","mcasp","vddh1_dyn","16Ch_TX_48_ksps_24b_1p8v",0.94217555600000003,"",""]
["mcasp_vddh1_dyn_2Ch_RX_48_ksps_24b_1p8v","mcasp","vddh1_dyn","2Ch_RX_48_ksps_24b_1p8v",0.18843511099999999,"",""]
["mcasp_vddh1_dyn_2Ch_RXTX_48_ksps_24b_1p8v","mcasp","vddh1_dyn","2Ch_RXTX_48_ksps_24b_1p8v",0.376870223,"",""]
["mcasp_vddh1_dyn_2Ch_TX_48_ksps_24b_1p8v","mcasp","vddh1_dyn","2Ch_TX_48_ksps_24b_1p8v",0.56530533400000005,"",""]
["mcasp_vddh1_dyn_4Ch_RX_48_ksps_24b_1p8v","mcasp","vddh1_dyn","4Ch_RX_48_ksps_24b_1p8v",0.18843511099999999,"",""]
["mcasp_vddh1_dyn_4Ch_RXTX_48_ksps_24b_1p8v","mcasp","vddh1_dyn","4Ch_RXTX_48_ksps_24b_1p8v",0.376870223,"",""]
["mcasp_vddh1_dyn_4Ch_TX_48_ksps_24b_1p8v","mcasp","vddh1_dyn","4Ch_TX_48_ksps_24b_1p8v",0.75374044500000004,"",""]
["mcasp_vddh1_dyn_8Ch_RX_48_ksps_24b_1p8v","mcasp","vddh1_dyn","8Ch_RX_48_ksps_24b_1p8v",0.18843511099999999,"",""]
["mcasp_vddh1_dyn_8Ch_RXTX_48_ksps_24b_1p8v","mcasp","vddh1_dyn","8Ch_RXTX_48_ksps_24b_1p8v",0.376870223,"",""]
["mcasp_vddh1_dyn_8Ch_TX_48_ksps_24b_1p8v","mcasp","vddh1_dyn","8Ch_TX_48_ksps_24b_1p8v",0.56530533400000005,"",""]
["mcasp_vddh2_dyn_12Ch_RXTX_48_ksps_24b_3p3v","mcasp","vddh2_dyn","12Ch_RXTX_48_ksps_24b_3p3v",2.2090732649999998,"",""]
["mcasp_vddh2_dyn_12Ch_TX_48_ksps_24b_3p3v","mcasp","vddh2_dyn","12Ch_TX_48_ksps_24b_3p3v",4.4181465290000004,"",""]
["mcasp_vddh2_dyn_16Ch_RXTX_48ksps_24b_3p3v","mcasp","vddh2_dyn","16Ch_RXTX_48ksps_24b_3p3v",2.2090732649999998,"",""]
["mcasp_vddh2_dyn_16Ch_TX_48_ksps_24b_3p3v","mcasp","vddh2_dyn","16Ch_TX_48_ksps_24b_3p3v",5.5226831619999999,"",""]
["mcasp_vddh2_dyn_2Ch_RX_48_ksps_24b_3p3v","mcasp","vddh2_dyn","2Ch_RX_48_ksps_24b_3p3v",1.1045366320000001,"",""]
["mcasp_vddh2_dyn_2Ch_RXTX_48_ksps_24b_3p3v","mcasp","vddh2_dyn","2Ch_RXTX_48_ksps_24b_3p3v",2.2090732649999998,"",""]
["mcasp_vddh2_dyn_2Ch_TX_48_ksps_24b_3p3v","mcasp","vddh2_dyn","2Ch_TX_48_ksps_24b_3p3v",3.3136098970000001,"",""]
["mcasp_vddh2_dyn_4Ch_RX_48_ksps_24b_3p3v","mcasp","vddh2_dyn","4Ch_RX_48_ksps_24b_3p3v",1.1045366320000001,"",""]
["mcasp_vddh2_dyn_4Ch_RXTX_48_ksps_24b_3p3v","mcasp","vddh2_dyn","4Ch_RXTX_48_ksps_24b_3p3v",2.2090732649999998,"",""]
["mcasp_vddh2_dyn_4Ch_TX_48_ksps_24b_3p3v","mcasp","vddh2_dyn","4Ch_TX_48_ksps_24b_3p3v",4.4181465290000004,"",""]
["mcasp_vddh2_dyn_8Ch_RX_48_ksps_24b_3p3v","mcasp","vddh2_dyn","8Ch_RX_48_ksps_24b_3p3v",1.1045366320000001,"",""]
["mcasp_vddh2_dyn_8Ch_RXTX_48_ksps_24b_3p3v","mcasp","vddh2_dyn","8Ch_RXTX_48_ksps_24b_3p3v",2.2090732649999998,"",""]
["mcasp_vddh2_dyn_8Ch_TX_48_ksps_24b_3p3v","mcasp","vddh2_dyn","8Ch_TX_48_ksps_24b_3p3v",3.3136098970000001,"",""]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
["N16FFC_HFXOSC_vddh1_dyn_on","N16FFC_HFXOSC","vddh1_dyn","on",5.58,"",""]
["N16FFC_HFXOSC_vddh1_lkg","N16FFC_HFXOSC","vddh1_lkg","on",1.7820081000000002E-2,"",""]
[]
[]
[]
[]
[]
[]
[]
[]
[]
["N16FFC_LFXOSC_vddh1_dyn_on","N16FFC_LFXOSC","vddh1_dyn","on",2.6280000000000001E-3,"",""]
["N16FFC_LFXOSC_vddh1_lkg","N16FFC_LFXOSC","vddh1_lkg","on",5.3460239999999996E-3,"",""]
[]
[]
[]
[]
[]
[]
[]
[]
[]
["N16FFC_POK_vdd_lkg","N16FFC_POK","vdd_lkg","on",1.6720000000000001E-3,"",""]
["N16FFC_POK_vddh1_dyn_on","N16FFC_POK","vddh1_dyn","on",0.02,"",""]
["N16FFC_POK_vddh1_lkg","N16FFC_POK","vddh1_lkg","on",4.0127999999999997E-2,"",""]
[]
[]
[]
[]
[]
[]
[]
[]
[]
["N16FFC_POKSA_vdd_lkg","N16FFC_POKSA","vdd_lkg","on",1.17766E-2,"",""]
["N16FFC_POKSA_vddh1_dyn_deep_sleep","N16FFC_POKSA","vddh1_dyn","deep_sleep",1,"",""]
["N16FFC_POKSA_vddh1_dyn_on","N16FFC_POKSA","vddh1_dyn","on",4.6440000000000002E-2,"",""]
["N16FFC_POKSA_vddh1_lkg","N16FFC_POKSA","vddh1_lkg","on",3.474E-2,"",""]
[]
[]
[]
[]
[]
[]
[]
[]
[]
["N16FFC_POR_vdd_dyn_on","N16FFC_POR","vdd_dyn","on",4.7999999999999996E-3,"",""]
["N16FFC_POR_vdd_lkg","N16FFC_POR","vdd_lkg","on",5.2800240000000003E-3,"",""]
["N16FFC_POR_vddh1_dyn_on","N16FFC_POR","vddh1_dyn","on",0.48599999999999999,"",""]
["N16FFC_POR_vddh1_lkg","N16FFC_POR","vddh1_lkg","on",0.2430011,"",""]
[]
[]
[]
[]
[]
[]
[]
[]
[]
["N16FFC_RCOSC_vddh1_dyn_on","N16FFC_RCOSC","vddh1_dyn","on",8.7300000000000003E-2,"",""]
["N16FFC_RCOSC_vddh1_lkg","N16FFC_RCOSC","vddh1_lkg","on",4.0140182000000003E-2,"",""]
[]
[]
[]
[]
[]
[]
[]
[]
[]
["N16FFC_TEMP_DIODE_TOP_vddh1_dyn_on","N16FFC_TEMP_DIODE_TOP","vddh1_dyn","on",2,"",""]
["N16FFC_TEMP_DIODE_TOP_vddh1_lkg","N16FFC_TEMP_DIODE_TOP","vddh1_lkg","on",0.18000081500000001,"",""]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
["PGD_vdda_dyn_off","PGD","vdda_dyn","off",0,"",""]
["PGD_vdda_dyn_on","PGD","vdda_dyn","on",4.4000000000000004,"",""]
["PGD_vdda_lkg","PGD","vdda_lkg","on",4.3999999999999997E-2,"",""]
[]
[]
[]
[]
[]
[]
[]
[]
[]
["PLLTS16FFCLAFRACF_vdd_dyn_0","PLLTS16FFCLAFRACF","vdd_dyn","0",0,"",""]
["PLLTS16FFCLAFRACF_vdd_dyn_1000","PLLTS16FFCLAFRACF","vdd_dyn","1000",0.95040000000000002,"",""]
["PLLTS16FFCLAFRACF_vdd_dyn_1250","PLLTS16FFCLAFRACF","vdd_dyn","1250",1.1879999999999999,"",""]
["PLLTS16FFCLAFRACF_vdd_dyn_1500","PLLTS16FFCLAFRACF","vdd_dyn","1500",1.4256,"",""]
["PLLTS16FFCLAFRACF_vdd_dyn_1750","PLLTS16FFCLAFRACF","vdd_dyn","1750",1.6632,"",""]
["PLLTS16FFCLAFRACF_vdd_dyn_2000","PLLTS16FFCLAFRACF","vdd_dyn","2000",1.9008,"",""]
["PLLTS16FFCLAFRACF_vdd_dyn_2250","PLLTS16FFCLAFRACF","vdd_dyn","2250",2.1383999999999999,"",""]
["PLLTS16FFCLAFRACF_vdd_dyn_250","PLLTS16FFCLAFRACF","vdd_dyn","250",0.3,"",""]
["PLLTS16FFCLAFRACF_vdd_dyn_2500","PLLTS16FFCLAFRACF","vdd_dyn","2500",2.3759999999999999,"",""]
["PLLTS16FFCLAFRACF_vdd_dyn_2750","PLLTS16FFCLAFRACF","vdd_dyn","2750",2.6135999999999999,"",""]
["PLLTS16FFCLAFRACF_vdd_dyn_3000","PLLTS16FFCLAFRACF","vdd_dyn","3000",2.8512,"",""]
["PLLTS16FFCLAFRACF_vdd_dyn_3250","PLLTS16FFCLAFRACF","vdd_dyn","3250",3.0888,"",""]
["PLLTS16FFCLAFRACF_vdd_dyn_3500","PLLTS16FFCLAFRACF","vdd_dyn","3500",3.3264,"",""]
["PLLTS16FFCLAFRACF_vdd_dyn_3750","PLLTS16FFCLAFRACF","vdd_dyn","3750",3.5640000000000001,"",""]
["PLLTS16FFCLAFRACF_vdd_dyn_500","PLLTS16FFCLAFRACF","vdd_dyn","500",0.47520000000000001,"",""]
["PLLTS16FFCLAFRACF_vdd_dyn_750","PLLTS16FFCLAFRACF","vdd_dyn","750",0.71279999999999999,"",""]
["PLLTS16FFCLAFRACF_vdd_lkg","PLLTS16FFCLAFRACF","vdd_lkg","0",3.8885176E-2,"",""]
["PLLTS16FFCLAFRACF_vddh1_dyn_","PLLTS16FFCLAFRACF","vddh1_dyn","","","",""]
["PLLTS16FFCLAFRACF_vddh1_dyn_0","PLLTS16FFCLAFRACF","vddh1_dyn","0",0,"",""]
["PLLTS16FFCLAFRACF_vddh1_dyn_1000","PLLTS16FFCLAFRACF","vddh1_dyn","1000",2.1571068269999998,"",""]
["PLLTS16FFCLAFRACF_vddh1_dyn_1250","PLLTS16FFCLAFRACF","vddh1_dyn","1250",3.014648438,"",""]
["PLLTS16FFCLAFRACF_vddh1_dyn_1500","PLLTS16FFCLAFRACF","vddh1_dyn","1500",3.9628582849999998,"",""]
["PLLTS16FFCLAFRACF_vddh1_dyn_1750","PLLTS16FFCLAFRACF","vddh1_dyn","1750",4.9937721890000004,"",""]
["PLLTS16FFCLAFRACF_vddh1_dyn_2000","PLLTS16FFCLAFRACF","vddh1_dyn","2000",6.1012194610000003,"",""]
["PLLTS16FFCLAFRACF_vddh1_dyn_2250","PLLTS16FFCLAFRACF","vddh1_dyn","2250",7.2802355409999997,"",""]
["PLLTS16FFCLAFRACF_vddh1_dyn_250","PLLTS16FFCLAFRACF","vddh1_dyn","250",0.3,"",""]
["PLLTS16FFCLAFRACF_vddh1_dyn_2500","PLLTS16FFCLAFRACF","vddh1_dyn","2500",8.5267134119999994,"",""]
["PLLTS16FFCLAFRACF_vddh1_dyn_2750","PLLTS16FFCLAFRACF","vddh1_dyn","2750",9.8371817099999994,"",""]
["PLLTS16FFCLAFRACF_vddh1_dyn_3000","PLLTS16FFCLAFRACF","vddh1_dyn","3000",11.208655869999999,"",""]
["PLLTS16FFCLAFRACF_vddh1_dyn_3250","PLLTS16FFCLAFRACF","vddh1_dyn","3250",12.638533819999999,"",""]
["PLLTS16FFCLAFRACF_vddh1_dyn_3500","PLLTS16FFCLAFRACF","vddh1_dyn","3500",14.124520710000001,"",""]
["PLLTS16FFCLAFRACF_vddh1_dyn_3750","PLLTS16FFCLAFRACF","vddh1_dyn","3750",15.66457278,"",""]
["PLLTS16FFCLAFRACF_vddh1_dyn_500","PLLTS16FFCLAFRACF","vddh1_dyn","500",0.76265243299999996,"",""]
["PLLTS16FFCLAFRACF_vddh1_dyn_750","PLLTS16FFCLAFRACF","vddh1_dyn","750",1.4010819830000001,"",""]
["PLLTS16FFCLAFRACF_vddh1_lkg","PLLTS16FFCLAFRACF","vddh1_lkg","0",4.5450200000000002E-6,"",""]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
["PRWDWUWSWEWCDGSDIO_vdd_dyn_ddr_100mbs","PRWDWUWSWEWCDGSDIO","vdd_dyn","ddr_100mbs",8.4114799999999993E-6,"",""]
["PRWDWUWSWEWCDGSDIO_vdd_dyn_hs200_200mbs","PRWDWUWSWEWCDGSDIO","vdd_dyn","hs200_200mbs",1.6823000000000001E-5,"",""]
["PRWDWUWSWEWCDGSDIO_vdd_dyn_off","PRWDWUWSWEWCDGSDIO","vdd_dyn","off",0,"",""]
["PRWDWUWSWEWCDGSDIO_vdd_dyn_sdr_25mbs","PRWDWUWSWEWCDGSDIO","vdd_dyn","sdr_25mbs",2.8242800000000001E-6,"",""]
["PRWDWUWSWEWCDGSDIO_vdd_dyn_sdr_50mbs","PRWDWUWSWEWCDGSDIO","vdd_dyn","sdr_50mbs",5.6485600000000002E-6,"",""]
["PRWDWUWSWEWCDGSDIO_vddh1_dyn_ddr_100mbs","PRWDWUWSWEWCDGSDIO","vddh1_dyn","ddr_100mbs",0.47,"",""]
["PRWDWUWSWEWCDGSDIO_vddh1_dyn_hs200_200mbs","PRWDWUWSWEWCDGSDIO","vddh1_dyn","hs200_200mbs",1.29,"",""]
["PRWDWUWSWEWCDGSDIO_vddh1_dyn_off","PRWDWUWSWEWCDGSDIO","vddh1_dyn","off",0,"",""]
["PRWDWUWSWEWCDGSDIO_vddh1_dyn_sdr_25mbs","PRWDWUWSWEWCDGSDIO","vddh1_dyn","sdr_25mbs",0.16,"",""]
["PRWDWUWSWEWCDGSDIO_vddh1_dyn_sdr_50mbs","PRWDWUWSWEWCDGSDIO","vddh1_dyn","sdr_50mbs",0.32,"",""]
[]
[]
[]
[]
[]
[]
[]
[]
[]
["PVDD18MODEDET_vdd_lkg","PVDD18MODEDET","vdd_lkg","on",0.30640000000000001,"",""]
["PVDD18MODEDET_vddh1_dyn_deep_sleep","PVDD18MODEDET","vddh1_dyn","deep_sleep",1.9699999999999999E-2,"",""]
["PVDD18MODEDET_vddh1_dyn_on","PVDD18MODEDET","vddh1_dyn","on",0,"",""]
["PVDD18MODEDET_vddh1_lkg","PVDD18MODEDET","vddh1_lkg","on",2.718,"",""]
["PVDD18MODEDET_vddh2_lkg","PVDD18MODEDET","vddh2_lkg","on",4.3890000000000002,"",""]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
["sam62_a53_dual_wrap_cba_cpu_phys_vdd_dyn_idle","sam62_a53_dual_wrap_cba_cpu_phys","vdd_dyn_idle","",1.2E-2,"","0.012"]
["sam62_a53_dual_wrap_cba_cpu_phys_vdd_dyn_int_trk","sam62_a53_dual_wrap_cba_cpu_phys","vdd_dyn_int_trk","",301.2,"AM62P tracker dump - 5-24-23","289.2"]
["sam62_a53_dual_wrap_cba_cpu_phys_vdd_dyn_max","sam62_a53_dual_wrap_cba_cpu_phys","vdd_dyn_max","",0.15,"",""]
["sam62_a53_dual_wrap_cba_cpu_phys_vdd_dyn_peak","sam62_a53_dual_wrap_cba_cpu_phys","vdd_dyn_peak","",0.18,""," Joules value if simulated."]
["sam62_a53_dual_wrap_cba_cpu_phys_vdd_dyn_sw_trk","sam62_a53_dual_wrap_cba_cpu_phys","vdd_dyn_sw_trk","",240.9,"AM62P tracker dump - 5-24-23","220.4"]
["sam62_a53_dual_wrap_cba_cpu_phys_vdd_lkg","sam62_a53_dual_wrap_cba_cpu_phys","vdd_lkg","",67.400000000000006,"AM62P tracker dump - 5-24-23","75.8"]
["sam62_a53_dual_wrap_cba_cpu_phys_vddr_lkg","sam62_a53_dual_wrap_cba_cpu_phys","vddr_lkg","",7.2,"AM62P tracker dump - 5-24-23","7"]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
["sam62_efuse_ctrl_wrap_vdd_dyn_idle","sam62_efuse_ctrl_wrap","vdd_dyn_idle","",0.155,"","0.131"]
["sam62_efuse_ctrl_wrap_vdd_dyn_int_trk","sam62_efuse_ctrl_wrap","vdd_dyn_int_trk","",3.7,"AM62P C1 tracker update","3.8"]
["sam62_efuse_ctrl_wrap_vdd_dyn_max","sam62_efuse_ctrl_wrap","vdd_dyn_max","",0.18,"",""]
["sam62_efuse_ctrl_wrap_vdd_dyn_peak","sam62_efuse_ctrl_wrap","vdd_dyn_peak","",0.22,""," Joules value if simulated."]
["sam62_efuse_ctrl_wrap_vdd_dyn_sw_trk","sam62_efuse_ctrl_wrap","vdd_dyn_sw_trk","",3.9,"AM62P C1 tracker update","3.8"]
["sam62_efuse_ctrl_wrap_vdd_lkg","sam62_efuse_ctrl_wrap","vdd_lkg","",0.7,"","0.7"]
["sam62_efuse_ctrl_wrap_vddr_lkg","sam62_efuse_ctrl_wrap","vddr_lkg","",0,"","0"]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
["sam62_emmc_4bit_wrap_vdd_dyn_idle","sam62_emmc_4bit_wrap","vdd_dyn_idle","",0.26800000000000002,"","0.224"]
["sam62_emmc_4bit_wrap_vdd_dyn_int_trk","sam62_emmc_4bit_wrap","vdd_dyn_int_trk","",8.5,"AM62P tracker update 03-31-23","8.7"]
["sam62_emmc_4bit_wrap_vdd_dyn_max","sam62_emmc_4bit_wrap","vdd_dyn_max","",0.48,"",""]
["sam62_emmc_4bit_wrap_vdd_dyn_peak","sam62_emmc_4bit_wrap","vdd_dyn_peak","",0.57999999999999996,""," Joules value if simulated."]
["sam62_emmc_4bit_wrap_vdd_dyn_sw_trk","sam62_emmc_4bit_wrap","vdd_dyn_sw_trk","",7.6,"AM62P tracker update 03-31-23","7.8"]
["sam62_emmc_4bit_wrap_vdd_lkg","sam62_emmc_4bit_wrap","vdd_lkg","",2,"","2"]
["sam62_emmc_4bit_wrap_vddr_lkg","sam62_emmc_4bit_wrap","vddr_lkg","",1.2,"","1.2"]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
["sam62_gpmc_elm_wrap_vdd_dyn_idle","sam62_gpmc_elm_wrap","vdd_dyn_idle","",0.20599999999999999,"","0.217"]
["sam62_gpmc_elm_wrap_vdd_dyn_int_trk","sam62_gpmc_elm_wrap","vdd_dyn_int_trk","",6.5,"AM62P C1 tracker update","6.7"]
["sam62_gpmc_elm_wrap_vdd_dyn_max","sam62_gpmc_elm_wrap","vdd_dyn_max","",0.48,"",""]
["sam62_gpmc_elm_wrap_vdd_dyn_peak","sam62_gpmc_elm_wrap","vdd_dyn_peak","",0.57999999999999996,""," Joules value if simulated."]
["sam62_gpmc_elm_wrap_vdd_dyn_sw_trk","sam62_gpmc_elm_wrap","vdd_dyn_sw_trk","",6.9,"AM62P C1 tracker update","6.7"]
["sam62_gpmc_elm_wrap_vdd_lkg","sam62_gpmc_elm_wrap","vdd_lkg","",1.3,"","1.3"]
["sam62_gpmc_elm_wrap_vddr_lkg","sam62_gpmc_elm_wrap","vddr_lkg","",0,"","0"]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
["sam62_mcasp_wrap_vdd_dyn_idle","sam62_mcasp_wrap","vdd_dyn_idle","",0.40200000000000002,"","0.403"]
["sam62_mcasp_wrap_vdd_dyn_int_trk","sam62_mcasp_wrap","vdd_dyn_int_trk","",2.9,"AM62P C1 tracker update","2.95"]
["sam62_mcasp_wrap_vdd_dyn_max","sam62_mcasp_wrap","vdd_dyn_max","",0.72,"",""]
["sam62_mcasp_wrap_vdd_dyn_peak","sam62_mcasp_wrap","vdd_dyn_peak","",0.86,""," Joules value if simulated."]
["sam62_mcasp_wrap_vdd_dyn_sw_trk","sam62_mcasp_wrap","vdd_dyn_sw_trk","",3,"AM62P C1 tracker update","2.95"]
["sam62_mcasp_wrap_vdd_lkg","sam62_mcasp_wrap","vdd_lkg","",0.6,"","0.6"]
["sam62_mcasp_wrap_vddr_lkg","sam62_mcasp_wrap","vddr_lkg","",0,"","0"]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
["sam62_odp_ctrl_wrap_vdd_dyn_idle","sam62_odp_ctrl_wrap","vdd_dyn_idle","",0.44,"","0.416"]
["sam62_odp_ctrl_wrap_vdd_dyn_int_trk","sam62_odp_ctrl_wrap","vdd_dyn_int_trk","",1,"","2"]
["sam62_odp_ctrl_wrap_vdd_dyn_max","sam62_odp_ctrl_wrap","vdd_dyn_max","",0.5,"Hack to fix max less than idle",0.43]
["sam62_odp_ctrl_wrap_vdd_dyn_peak","sam62_odp_ctrl_wrap","vdd_dyn_peak","",0.52,""," Joules value if simulated."]
["sam62_odp_ctrl_wrap_vdd_dyn_sw_trk","sam62_odp_ctrl_wrap","vdd_dyn_sw_trk","",1,"","2"]
["sam62_odp_ctrl_wrap_vdd_lkg","sam62_odp_ctrl_wrap","vdd_lkg","",0.2,"","0.2"]
["sam62_odp_ctrl_wrap_vddr_lkg","sam62_odp_ctrl_wrap","vddr_lkg","",0,"","0"]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
["sam62_pll_ctrl_wrap_vdd_dyn_idle","sam62_pll_ctrl_wrap","vdd_dyn_idle","",0.47499999999999998,"","0.2"]
["sam62_pll_ctrl_wrap_vdd_dyn_int_trk","sam62_pll_ctrl_wrap","vdd_dyn_int_trk","",3.4,"AM62P C1 tracker update","3.15"]
["sam62_pll_ctrl_wrap_vdd_dyn_max","sam62_pll_ctrl_wrap","vdd_dyn_max","",0.5,"Hack to fix max less than idle",0.26]
["sam62_pll_ctrl_wrap_vdd_dyn_peak","sam62_pll_ctrl_wrap","vdd_dyn_peak","",0.31,""," Joules value if simulated."]
["sam62_pll_ctrl_wrap_vdd_dyn_sw_trk","sam62_pll_ctrl_wrap","vdd_dyn_sw_trk","",2.9,"AM62P C1 tracker update","3.15"]
["sam62_pll_ctrl_wrap_vdd_lkg","sam62_pll_ctrl_wrap","vdd_lkg","",0.6,"AM62P C1 tracker update","0.5"]
["sam62_pll_ctrl_wrap_vddr_lkg","sam62_pll_ctrl_wrap","vddr_lkg","",0,"","0"]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
["sam62a_a53_512kb_wrap_vdd_dyn_idle","sam62a_a53_512kb_wrap","vdd_dyn_idle","",0.14599999999999999,"","0.103"]
["sam62a_a53_512kb_wrap_vdd_dyn_int_trk","sam62a_a53_512kb_wrap","vdd_dyn_int_trk","",302.60000000000002,"AM62P tracker dump - 5-24-23","273.3"]
["sam62a_a53_512kb_wrap_vdd_dyn_max","sam62a_a53_512kb_wrap","vdd_dyn_max","",0.25,"Hack to fix max less than idle",0.1]
["sam62a_a53_512kb_wrap_vdd_dyn_peak","sam62a_a53_512kb_wrap","vdd_dyn_peak","",0.15,""," Joules value if simulated."]
["sam62a_a53_512kb_wrap_vdd_dyn_sw_trk","sam62a_a53_512kb_wrap","vdd_dyn_sw_trk","",330.8,"AM62P tracker dump - 5-24-23","290.6"]
["sam62a_a53_512kb_wrap_vdd_lkg","sam62a_a53_512kb_wrap","vdd_lkg","",103.4,"AM62P tracker dump - 5-24-23","92.1"]
["sam62a_a53_512kb_wrap_vddr_lkg","sam62a_a53_512kb_wrap","vddr_lkg","",21.2,"","21.2"]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
["sam62a_can_io_domain_vdd_dyn_idle","sam62a_can_io_domain","vdd_dyn_idle","",0,"SAM62A 2-18-22 update","0.02"]
["sam62a_can_io_domain_vdd_dyn_int_trk","sam62a_can_io_domain","vdd_dyn_int_trk","",0.1,"AM62P tracker update 03-31-23",""]
["sam62a_can_io_domain_vdd_dyn_max","sam62a_can_io_domain","vdd_dyn_max","",0.4,"SAM62A 2-18-22 update",""]
["sam62a_can_io_domain_vdd_dyn_peak","sam62a_can_io_domain","vdd_dyn_peak","",0.48,"SAM62A 2-18-22 update",""]
["sam62a_can_io_domain_vdd_dyn_sw_trk","sam62a_can_io_domain","vdd_dyn_sw_trk","",0.3,"AM62P tracker update 03-31-23",""]
["sam62a_can_io_domain_vdd_dyn_trk","sam62a_can_io_domain","vdd_dyn_trk","",0.3,"SAM62A 2-18-22 update","0.3"]
["sam62a_can_io_domain_vdd_lkg","sam62a_can_io_domain","vdd_lkg","",0,"SAM62A 2-18-22 update","0"]
["sam62a_can_io_domain_vddr_lkg","sam62a_can_io_domain","vddr_lkg","",0,"SAM62A 2-18-22 update","0"]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
["sam62a_mcu_pulsar_ul_wrap_vdd_dyn_idle","sam62a_mcu_pulsar_ul_wrap","vdd_dyn_idle","",0.111,"","0.111"]
["sam62a_mcu_pulsar_ul_wrap_vdd_dyn_int_trk","sam62a_mcu_pulsar_ul_wrap","vdd_dyn_int_trk","",122.6,"AM62P tracker update 03-31-23","122.9"]
["sam62a_mcu_pulsar_ul_wrap_vdd_dyn_max","sam62a_mcu_pulsar_ul_wrap","vdd_dyn_max","",0.4,"Hack to fix max less than idle",0.3]
["sam62a_mcu_pulsar_ul_wrap_vdd_dyn_peak","sam62a_mcu_pulsar_ul_wrap","vdd_dyn_peak","",0.36,""," Joules value if simulated."]
["sam62a_mcu_pulsar_ul_wrap_vdd_dyn_sw_trk","sam62a_mcu_pulsar_ul_wrap","vdd_dyn_sw_trk","",106.6,"AM62P tracker update 03-31-23","106.7"]
["sam62a_mcu_pulsar_ul_wrap_vdd_lkg","sam62a_mcu_pulsar_ul_wrap","vdd_lkg","",20.5,"AM62P C1 tracker update","20.5"]
["sam62a_mcu_pulsar_ul_wrap_vddr_lkg","sam62a_mcu_pulsar_ul_wrap","vddr_lkg","",5.9,"AM62P C1 tracker update","5.9"]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
["sam62p_core_vdd_dyn_idle","sam62p_core","vdd_dyn_idle","",0.23300000000000001,null,"0.15"]
["sam62p_core_vdd_dyn_int_trk","sam62p_core","vdd_dyn_int_trk","",138,"","276"]
["sam62p_core_vdd_dyn_max","sam62p_core","vdd_dyn_max","",0.4,"",""]
["sam62p_core_vdd_dyn_peak","sam62p_core","vdd_dyn_peak","",0.48,"",""]
["sam62p_core_vdd_dyn_sw_trk","sam62p_core","vdd_dyn_sw_trk","",138,"","276"]
["sam62p_core_vdd_lkg","sam62p_core","vdd_lkg","",52.865000000000002,"AM62P tracker update - 05-24-23",33.9]
["sam62p_core_vddr_lkg","sam62p_core","vddr_lkg","",0,"",""]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
["sam62p_main_ip_wrap_vdd_dyn_idle","sam62p_main_ip_wrap","vdd_dyn_idle","",6.8000000000000005E-2,"","0.065"]
["sam62p_main_ip_wrap_vdd_dyn_int_trk","sam62p_main_ip_wrap","vdd_dyn_int_trk","",379.5,"AM62P tracker dump - 5-24-23","381.8"]
["sam62p_main_ip_wrap_vdd_dyn_max","sam62p_main_ip_wrap","vdd_dyn_max","",0.4,"",""]
["sam62p_main_ip_wrap_vdd_dyn_peak","sam62p_main_ip_wrap","vdd_dyn_peak","",0.48,"",""]
["sam62p_main_ip_wrap_vdd_dyn_sw_trk","sam62p_main_ip_wrap","vdd_dyn_sw_trk","",457.4,"AM62P tracker dump - 5-24-23","459.2"]
["sam62p_main_ip_wrap_vdd_lkg","sam62p_main_ip_wrap","vdd_lkg","",78.8,"AM62P tracker dump - 5-24-23","82.9"]
["sam62p_main_ip_wrap_vddr_lkg","sam62p_main_ip_wrap","vddr_lkg","",5.8,"AM62P tracker dump - 5-24-23","5.7"]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
["sam62p_main_rt_wrap_vdd_dyn_idle","sam62p_main_rt_wrap","vdd_dyn_idle","",4.2999999999999997E-2,"","0.065"]
["sam62p_main_rt_wrap_vdd_dyn_int_trk","sam62p_main_rt_wrap","vdd_dyn_int_trk","",86.7,"AM62P tracker update 03-31-23","86"]
["sam62p_main_rt_wrap_vdd_dyn_max","sam62p_main_rt_wrap","vdd_dyn_max","",0.4,"",""]
["sam62p_main_rt_wrap_vdd_dyn_peak","sam62p_main_rt_wrap","vdd_dyn_peak","",0.48,"",""]
["sam62p_main_rt_wrap_vdd_dyn_sw_trk","sam62p_main_rt_wrap","vdd_dyn_sw_trk","",83.8,"AM62P tracker update 03-31-23","84.2"]
["sam62p_main_rt_wrap_vdd_lkg","sam62p_main_rt_wrap","vdd_lkg","",15.8,"AM62P tracker update 03-31-23","13.6"]
["sam62p_main_rt_wrap_vddr_lkg","sam62p_main_rt_wrap","vddr_lkg","",0.3,"AM62P C1 tracker update","0.230769231"]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
["sam67_cpsw3_wrap_vdd_dyn_idle","sam67_cpsw3_wrap","vdd_dyn_idle","",0.33900000000000002,"","0.19"]
["sam67_cpsw3_wrap_vdd_dyn_int_trk","sam67_cpsw3_wrap","vdd_dyn_int_trk","",85.3,"AM62P tracker dump - 5-24-23","85.1"]
["sam67_cpsw3_wrap_vdd_dyn_max","sam67_cpsw3_wrap","vdd_dyn_max","",0.48,"",""]
["sam67_cpsw3_wrap_vdd_dyn_peak","sam67_cpsw3_wrap","vdd_dyn_peak","",0.57999999999999996,""," Joules value if simulated."]
["sam67_cpsw3_wrap_vdd_dyn_sw_trk","sam67_cpsw3_wrap","vdd_dyn_sw_trk","",56.3,"AM62P tracker update 03-31-23","86.8"]
["sam67_cpsw3_wrap_vdd_lkg","sam67_cpsw3_wrap","vdd_lkg","",9.5,"AM62P tracker dump - 5-24-23","9.4"]
["sam67_cpsw3_wrap_vddr_lkg","sam67_cpsw3_wrap","vddr_lkg","",1.5,"","1.5"]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
["sam67_csirx_wrap_vdd_dyn_idle","sam67_csirx_wrap","vdd_dyn_idle","",0.22800000000000001,"","0.232"]
["sam67_csirx_wrap_vdd_dyn_int_trk","sam67_csirx_wrap","vdd_dyn_int_trk","",40,"AM62P tracker update 03-31-23","39.9"]
["sam67_csirx_wrap_vdd_dyn_max","sam67_csirx_wrap","vdd_dyn_max","",0.48,"",""]
["sam67_csirx_wrap_vdd_dyn_peak","sam67_csirx_wrap","vdd_dyn_peak","",0.57999999999999996,"",""]
["sam67_csirx_wrap_vdd_dyn_sw_trk","sam67_csirx_wrap","vdd_dyn_sw_trk","",28.6,"AM62P tracker update 03-31-23","28.5"]
["sam67_csirx_wrap_vdd_lkg","sam67_csirx_wrap","vdd_lkg","",6.5,"AM62P tracker update 03-31-23","6.3"]
["sam67_csirx_wrap_vddr_lkg","sam67_csirx_wrap","vddr_lkg","",3.2,"AM62P tracker update 01/10/23","3.3"]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
["sam67_ddr_wrap_vdd_dyn_idle","sam67_ddr_wrap","vdd_dyn_idle","",0.17299999999999999,"","0.185"]
["sam67_ddr_wrap_vdd_dyn_int_trk","sam67_ddr_wrap","vdd_dyn_int_trk","",293.89999999999998,"AM62P tracker dump - 5-24-23","294"]
["sam67_ddr_wrap_vdd_dyn_max","sam67_ddr_wrap","vdd_dyn_max","",0.45,"",""]
["sam67_ddr_wrap_vdd_dyn_peak","sam67_ddr_wrap","vdd_dyn_peak","",0.75,""," Joules value if simulated."]
["sam67_ddr_wrap_vdd_dyn_sw_trk","sam67_ddr_wrap","vdd_dyn_sw_trk","",390.1,"AM62P tracker update 03-31-23","382.6"]
["sam67_ddr_wrap_vdd_lkg","sam67_ddr_wrap","vdd_lkg","",58.4,"AM62P tracker dump - 5-24-23","58.6"]
["sam67_ddr_wrap_vddr_lkg","sam67_ddr_wrap","vddr_lkg","",0,"","0"]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
["sam67_debug_wrap_vdd_dyn_idle","sam67_debug_wrap","vdd_dyn_idle","",0.29899999999999999,"","0.26"]
["sam67_debug_wrap_vdd_dyn_int_trk","sam67_debug_wrap","vdd_dyn_int_trk","",20.6,"AM62P tracker update 03-31-23","21"]
["sam67_debug_wrap_vdd_dyn_max","sam67_debug_wrap","vdd_dyn_max","",0.48,"",""]
["sam67_debug_wrap_vdd_dyn_peak","sam67_debug_wrap","vdd_dyn_peak","",0.57999999999999996,"",""]
["sam67_debug_wrap_vdd_dyn_sw_trk","sam67_debug_wrap","vdd_dyn_sw_trk","",16.5,"AM62P tracker update 03-31-23","16.7"]
["sam67_debug_wrap_vdd_lkg","sam67_debug_wrap","vdd_lkg","",4.4000000000000004,"AM62P tracker update 03-31-23","4.3"]
["sam67_debug_wrap_vddr_lkg","sam67_debug_wrap","vddr_lkg","",1,"",""]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
["sam67_dm_wrap_vdd_dyn_idle","sam67_dm_wrap","vdd_dyn_idle","",0.17299999999999999,"","0.08"]
["sam67_dm_wrap_vdd_dyn_int_trk","sam67_dm_wrap","vdd_dyn_int_trk","",244.9,"AM62P tracker dump - 5-24-23","244.3"]
["sam67_dm_wrap_vdd_dyn_max","sam67_dm_wrap","vdd_dyn_max","",0.3,"",""]
["sam67_dm_wrap_vdd_dyn_peak","sam67_dm_wrap","vdd_dyn_peak","",0.36,""," Joules value if simulated."]
["sam67_dm_wrap_vdd_dyn_sw_trk","sam67_dm_wrap","vdd_dyn_sw_trk","",249,"AM62P tracker dump - 5-24-23","248.3"]
["sam67_dm_wrap_vdd_lkg","sam67_dm_wrap","vdd_lkg","",37.799999999999997,"AM62P tracker dump - 5-24-23","39.6"]
["sam67_dm_wrap_vddr_lkg","sam67_dm_wrap","vddr_lkg","",6.5,"AM62P C1 tracker update","6.4"]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
["sam67_dss_dsi_oldi_wrap_vdd_dyn_idle","sam67_dss_dsi_oldi_wrap","vdd_dyn_idle","",7.8E-2,"","0.188"]
["sam67_dss_dsi_oldi_wrap_vdd_dyn_int_trk","sam67_dss_dsi_oldi_wrap","vdd_dyn_int_trk","",193,"AM62P tracker update 03-31-23","187.6"]
["sam67_dss_dsi_oldi_wrap_vdd_dyn_max","sam67_dss_dsi_oldi_wrap","vdd_dyn_max","",0.48,"","0.48"]
["sam67_dss_dsi_oldi_wrap_vdd_dyn_peak","sam67_dss_dsi_oldi_wrap","vdd_dyn_peak","",0.57999999999999996,"","0.58"]
["sam67_dss_dsi_oldi_wrap_vdd_dyn_sw_trk","sam67_dss_dsi_oldi_wrap","vdd_dyn_sw_trk","",165.4,"AM62P tracker update 03-31-23","166.9"]
["sam67_dss_dsi_oldi_wrap_vdd_lkg","sam67_dss_dsi_oldi_wrap","vdd_lkg","",19.899999999999999,"AM62P tracker update 03-31-23","20.5"]
["sam67_dss_dsi_oldi_wrap_vddr_lkg","sam67_dss_dsi_oldi_wrap","vddr_lkg","",4.2,"AM62P C1 tracker update","4"]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
["sam67_emmc_8bit_wrap_vdd_dyn_idle","sam67_emmc_8bit_wrap","vdd_dyn_idle","",0.30299999999999999,"","0.298"]
["sam67_emmc_8bit_wrap_vdd_dyn_int_trk","sam67_emmc_8bit_wrap","vdd_dyn_int_trk","",8.3000000000000007,"AM62P tracker update 03-31-23","9.3"]
["sam67_emmc_8bit_wrap_vdd_dyn_max","sam67_emmc_8bit_wrap","vdd_dyn_max","",0.48,"",""]
["sam67_emmc_8bit_wrap_vdd_dyn_peak","sam67_emmc_8bit_wrap","vdd_dyn_peak","",0.57999999999999996,"",""]
["sam67_emmc_8bit_wrap_vdd_dyn_sw_trk","sam67_emmc_8bit_wrap","vdd_dyn_sw_trk","",8.1,"AM62P tracker update 03-31-23","8.3"]
["sam67_emmc_8bit_wrap_vdd_lkg","sam67_emmc_8bit_wrap","vdd_lkg","",1.3,"AM62P tracker dump - 5-24-23","1.4"]
["sam67_emmc_8bit_wrap_vddr_lkg","sam67_emmc_8bit_wrap","vddr_lkg","",1.3,"AM62P tracker update 03-31-23","1.2"]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
["sam67_gpu_bxs464_dust_vdd_dyn_idle","sam67_gpu_bxs464_dust","vdd_dyn_idle","",3.0000000000000001E-3,"","0.002"]
["sam67_gpu_bxs464_dust_vdd_dyn_int_trk","sam67_gpu_bxs464_dust","vdd_dyn_int_trk","",1090.0999999999999,"AM62P tracker dump - 5-24-23","1085.5"]
["sam67_gpu_bxs464_dust_vdd_dyn_max","sam67_gpu_bxs464_dust","vdd_dyn_max","",0.22,"",""]
["sam67_gpu_bxs464_dust_vdd_dyn_peak","sam67_gpu_bxs464_dust","vdd_dyn_peak","",0.36,"",""]
["sam67_gpu_bxs464_dust_vdd_dyn_sw_trk","sam67_gpu_bxs464_dust","vdd_dyn_sw_trk","",1060.5999999999999,"AM62P tracker dump - 5-24-23","1056.5"]
["sam67_gpu_bxs464_dust_vdd_lkg","sam67_gpu_bxs464_dust","vdd_lkg","",144.6,"AM62P tracker dump - 5-24-23","147.4"]
["sam67_gpu_bxs464_dust_vddr_lkg","sam67_gpu_bxs464_dust","vddr_lkg","",18.5,"AM62P tracker update 01/10/23","18.9"]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
["sam67_gpu_bxs464_rslc256_vdd_dyn_idle","sam67_gpu_bxs464_rslc256","vdd_dyn_idle","",1.0999999999999999E-2,"","0.01"]
["sam67_gpu_bxs464_rslc256_vdd_dyn_int_trk","sam67_gpu_bxs464_rslc256","vdd_dyn_int_trk","",977.8,"AM62P tracker dump - 5-24-23","977.1"]
["sam67_gpu_bxs464_rslc256_vdd_dyn_max","sam67_gpu_bxs464_rslc256","vdd_dyn_max","",0.22,"",""]
["sam67_gpu_bxs464_rslc256_vdd_dyn_peak","sam67_gpu_bxs464_rslc256","vdd_dyn_peak","",0.36,"",""]
["sam67_gpu_bxs464_rslc256_vdd_dyn_sw_trk","sam67_gpu_bxs464_rslc256","vdd_dyn_sw_trk","",632,"AM62P tracker dump - 5-24-23","631.5"]
["sam67_gpu_bxs464_rslc256_vdd_lkg","sam67_gpu_bxs464_rslc256","vdd_lkg","",86.9,"AM62P tracker dump - 5-24-23","87.1"]
["sam67_gpu_bxs464_rslc256_vddr_lkg","sam67_gpu_bxs464_rslc256","vddr_lkg","",53.7,"AM62P tracker update 03-31-23","53.9"]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
["sam67_gpu_bxs464_wrap_vdd_dyn_idle","sam67_gpu_bxs464_wrap","vdd_dyn_idle","",0.26300000000000001,"","0.22"]
["sam67_gpu_bxs464_wrap_vdd_dyn_int_trk","sam67_gpu_bxs464_wrap","vdd_dyn_int_trk","",100.5,"AM62P tracker dump - 5-24-23","100.4"]
["sam67_gpu_bxs464_wrap_vdd_dyn_max","sam67_gpu_bxs464_wrap","vdd_dyn_max","",0.36,"",""]
["sam67_gpu_bxs464_wrap_vdd_dyn_peak","sam67_gpu_bxs464_wrap","vdd_dyn_peak","",0.47,"",""]
["sam67_gpu_bxs464_wrap_vdd_dyn_sw_trk","sam67_gpu_bxs464_wrap","vdd_dyn_sw_trk","",98.8,"AM62P tracker dump - 5-24-23","98.7"]
["sam67_gpu_bxs464_wrap_vdd_lkg","sam67_gpu_bxs464_wrap","vdd_lkg","",21.5,"AM62P tracker dump - 5-24-23","21.8"]
["sam67_gpu_bxs464_wrap_vddr_lkg","sam67_gpu_bxs464_wrap","vddr_lkg","",0.8,"",""]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
["sam67_ls_mcu_can_vdd_dyn_idle","sam67_ls_mcu_can","vdd_dyn_idle","",0,"SAM62a - 04-11-22 update","0.02"]
["sam67_ls_mcu_can_vdd_dyn_int_trk","sam67_ls_mcu_can","vdd_dyn_int_trk","",0.2,"AM62P tracker update 03-31-23",""]
["sam67_ls_mcu_can_vdd_dyn_max","sam67_ls_mcu_can","vdd_dyn_max","",0.4,"SAM62a - 04-11-22 update",""]
["sam67_ls_mcu_can_vdd_dyn_peak","sam67_ls_mcu_can","vdd_dyn_peak","",0.48,"SAM62a - 04-11-22 update"," Joules value if simulated."]
["sam67_ls_mcu_can_vdd_dyn_sw_trk","sam67_ls_mcu_can","vdd_dyn_sw_trk","",0.7,"AM62P tracker update 03-31-23",""]
["sam67_ls_mcu_can_vdd_dyn_trk","sam67_ls_mcu_can","vdd_dyn_trk","",0.9,"SAM62a - 04-11-22 update","1"]
["sam67_ls_mcu_can_vdd_lkg","sam67_ls_mcu_can","vdd_lkg","",0.1,"SAM62a - 04-11-22 update","0.1"]
["sam67_ls_mcu_can_vddr_lkg","sam67_ls_mcu_can","vddr_lkg","",0,"SAM62a - 04-11-22 update","0"]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
["sam67_main_infra_phys_vdd_dyn_idle","sam67_main_infra_phys","vdd_dyn_idle","",0.219,"","0.12"]
["sam67_main_infra_phys_vdd_dyn_int_trk","sam67_main_infra_phys","vdd_dyn_int_trk","",33.299999999999997,"AM62P tracker update 03-31-23","33.9"]
["sam67_main_infra_phys_vdd_dyn_max","sam67_main_infra_phys","vdd_dyn_max","",0.4,"",""]
["sam67_main_infra_phys_vdd_dyn_peak","sam67_main_infra_phys","vdd_dyn_peak","",0.48,"",""]
["sam67_main_infra_phys_vdd_dyn_sw_trk","sam67_main_infra_phys","vdd_dyn_sw_trk","",40.200000000000003,"AM62P tracker dump - 5-24-23","40.1"]
["sam67_main_infra_phys_vdd_lkg","sam67_main_infra_phys","vdd_lkg","",11.3,"AM62P tracker update 03-31-23","11.7"]
["sam67_main_infra_phys_vddr_lkg","sam67_main_infra_phys","vddr_lkg","",0.1,"AM62P C1 tracker update","0"]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
["sam67_mcu_infra_phys_vdd_dyn_idle","sam67_mcu_infra_phys","vdd_dyn_idle","",0.20499999999999999,"","0.18"]
["sam67_mcu_infra_phys_vdd_dyn_int_trk","sam67_mcu_infra_phys","vdd_dyn_int_trk","",9.1999999999999993,"AM62P tracker dump - 5-24-23","9.1"]
["sam67_mcu_infra_phys_vdd_dyn_max","sam67_mcu_infra_phys","vdd_dyn_max","",0.48,"",""]
["sam67_mcu_infra_phys_vdd_dyn_peak","sam67_mcu_infra_phys","vdd_dyn_peak","",0.57999999999999996,""," Joules value if simulated."]
["sam67_mcu_infra_phys_vdd_dyn_sw_trk","sam67_mcu_infra_phys","vdd_dyn_sw_trk","",11.5,"AM62P tracker update 03-31-23","11.4"]
["sam67_mcu_infra_phys_vdd_lkg","sam67_mcu_infra_phys","vdd_lkg","",3.2,"AM62P C1 tracker update","3.4"]
["sam67_mcu_infra_phys_vddr_lkg","sam67_mcu_infra_phys","vddr_lkg","",0,"","0"]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
["sam67_mcu_wrap_vdd_dyn_idle","sam67_mcu_wrap","vdd_dyn_idle","",0.126,"","0.14"]
["sam67_mcu_wrap_vdd_dyn_int_trk","sam67_mcu_wrap","vdd_dyn_int_trk","",65.599999999999994,"AM62P tracker dump - 5-24-23","68.3"]
["sam67_mcu_wrap_vdd_dyn_max","sam67_mcu_wrap","vdd_dyn_max","",0.48,"",""]
["sam67_mcu_wrap_vdd_dyn_peak","sam67_mcu_wrap","vdd_dyn_peak","",0.57999999999999996,""," Joules value if simulated."]
["sam67_mcu_wrap_vdd_dyn_sw_trk","sam67_mcu_wrap","vdd_dyn_sw_trk","",66.2,"AM62P tracker dump - 5-24-23","66.3"]
["sam67_mcu_wrap_vdd_lkg","sam67_mcu_wrap","vdd_lkg","",18.3,"AM62P tracker dump - 5-24-23","18.5"]
["sam67_mcu_wrap_vddr_lkg","sam67_mcu_wrap","vddr_lkg","",15.3,"","15.3"]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
["sam67_sec_wrap_vdd_dyn_idle","sam67_sec_wrap","vdd_dyn_idle","",0.11899999999999999,"","0.12"]
["sam67_sec_wrap_vdd_dyn_int_trk","sam67_sec_wrap","vdd_dyn_int_trk","",305.89999999999998,"AM62P tracker dump - 5-24-23","305.3"]
["sam67_sec_wrap_vdd_dyn_max","sam67_sec_wrap","vdd_dyn_max","",0.4,"",""]
["sam67_sec_wrap_vdd_dyn_peak","sam67_sec_wrap","vdd_dyn_peak","",0.48,""," Joules value if simulated."]
["sam67_sec_wrap_vdd_dyn_sw_trk","sam67_sec_wrap","vdd_dyn_sw_trk","",317.89999999999998,"AM62P tracker dump - 5-24-23","317.3"]
["sam67_sec_wrap_vdd_lkg","sam67_sec_wrap","vdd_lkg","",58.3,"AM62P tracker dump - 5-24-23","58.6"]
["sam67_sec_wrap_vddr_lkg","sam67_sec_wrap","vddr_lkg","",14.6,"AM62P tracker update 01/10/23","14.5"]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
["sam67_usb2_wrap_vdd_dyn_idle","sam67_usb2_wrap","vdd_dyn_idle","",0.27600000000000002,"","0.0284"]
["sam67_usb2_wrap_vdd_dyn_int_trk","sam67_usb2_wrap","vdd_dyn_int_trk","",21,"AM62P tracker update 03-31-23","21.1"]
["sam67_usb2_wrap_vdd_dyn_max","sam67_usb2_wrap","vdd_dyn_max","",0.35,"Hack to fix max less than idle",0.24]
["sam67_usb2_wrap_vdd_dyn_peak","sam67_usb2_wrap","vdd_dyn_peak","",0.28999999999999998,""," Joules value if simulated."]
["sam67_usb2_wrap_vdd_dyn_sw_trk","sam67_usb2_wrap","vdd_dyn_sw_trk","",23.5,"AM62P tracker update 03-31-23","24"]
["sam67_usb2_wrap_vdd_lkg","sam67_usb2_wrap","vdd_lkg","",4,"AM62P tracker update 01/10/23","3.9"]
["sam67_usb2_wrap_vddr_lkg","sam67_usb2_wrap","vddr_lkg","",1,"","1"]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
["sam67_vpu_wave521cl_wrap_vdd_dyn_idle","sam67_vpu_wave521cl_wrap","vdd_dyn_idle","",0.104,"","0.14"]
["sam67_vpu_wave521cl_wrap_vdd_dyn_int_trk","sam67_vpu_wave521cl_wrap","vdd_dyn_int_trk","",813.2,"AM62P tracker dump - 5-24-23","811.8"]
["sam67_vpu_wave521cl_wrap_vdd_dyn_max","sam67_vpu_wave521cl_wrap","vdd_dyn_max","",0.4,"",""]
["sam67_vpu_wave521cl_wrap_vdd_dyn_peak","sam67_vpu_wave521cl_wrap","vdd_dyn_peak","",0.6,""," Joules value if simulated."]
["sam67_vpu_wave521cl_wrap_vdd_dyn_sw_trk","sam67_vpu_wave521cl_wrap","vdd_dyn_sw_trk","",951.3,"AM62P tracker dump - 5-24-23","949.1"]
["sam67_vpu_wave521cl_wrap_vdd_lkg","sam67_vpu_wave521cl_wrap","vdd_lkg","",118.1,"AM62P tracker dump - 5-24-23","120.3"]
["sam67_vpu_wave521cl_wrap_vddr_lkg","sam67_vpu_wave521cl_wrap","vddr_lkg","",14.6,"AM62P tracker update 01/10/23","14.4"]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
["sam67_wiz16b8m4cdt3_wrap_vdd_dyn_idle","sam67_wiz16b8m4cdt3_wrap","vdd_dyn_idle","",0.373,"J7AEP Update 12/20/21","0.062"]
["sam67_wiz16b8m4cdt3_wrap_vdd_dyn_int_trk","sam67_wiz16b8m4cdt3_wrap","vdd_dyn_int_trk","",2.1,"AM62P tracker update 03-31-23","2.5"]
["sam67_wiz16b8m4cdt3_wrap_vdd_dyn_max","sam67_wiz16b8m4cdt3_wrap","vdd_dyn_max","",0.48,"Subchip Vdd dynamic max power as a percent of Vdd tracker dyn power.",""]
["sam67_wiz16b8m4cdt3_wrap_vdd_dyn_peak","sam67_wiz16b8m4cdt3_wrap","vdd_dyn_peak","",0.57999999999999996,"Subchip Vdd dynamic power peak as a % of tracker dyn power.  Max +20% for most Joules value if simulated.",""]
["sam67_wiz16b8m4cdt3_wrap_vdd_dyn_sw_trk","sam67_wiz16b8m4cdt3_wrap","vdd_dyn_sw_trk","",4.5999999999999996,"AM62P tracker update 03-31-23","5.6"]
["sam67_wiz16b8m4cdt3_wrap_vdd_lkg","sam67_wiz16b8m4cdt3_wrap","vdd_lkg","",0.5,"AM62P tracker update 01/10/23","0.6"]
["sam67_wiz16b8m4cdt3_wrap_vddr_lkg","sam67_wiz16b8m4cdt3_wrap","vddr_lkg","",0,"Subchip SRAM Array Supply Leakage",""]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
["sd0901_rx4_vdda_dyn_1p5g4l","sd0901_rx4","vdda_dyn","1p5g4l",15.04,"",""]
["sd0901_rx4_vdda_dyn_2p5g4l","sd0901_rx4","vdda_dyn","2p5g4l",20.831,"",""]
["sd0901_rx4_vdda_dyn_lpm_reset","sd0901_rx4","vdda_dyn","lpm_reset",0.53,"",""]
["sd0901_rx4_vdda_dyn_lprx","sd0901_rx4","vdda_dyn","lprx",20.831,"",""]
["sd0901_rx4_vdda_dyn_ulps","sd0901_rx4","vdda_dyn","ulps",4.1920000000000002,"",""]
["sd0901_rx4_vddh1_dyn_1p5g4l","sd0901_rx4","vddh1_dyn","1p5g4l",18.619,"",""]
["sd0901_rx4_vddh1_dyn_2p5g4l","sd0901_rx4","vddh1_dyn","2p5g4l",26.558,"",""]
["sd0901_rx4_vddh1_dyn_lpm_reset","sd0901_rx4","vddh1_dyn","lpm_reset",0.72,"",""]
["sd0901_rx4_vddh1_dyn_lprx","sd0901_rx4","vddh1_dyn","lprx",17.105,"",""]
["sd0901_rx4_vddh1_dyn_ulps","sd0901_rx4","vddh1_dyn","ulps",1.966,"",""]
[]
[]
[]
[]
[]
[]
[]
[]
[]
["sd0901_tx4_vdda_dyn_1p0g4l","sd0901_tx4","vdda_dyn","1p0g4l",7.1120000000000001,"",""]
["sd0901_tx4_vdda_dyn_1p5g4l","sd0901_tx4","vdda_dyn","1p5g4l",7.6619999999999999,"",""]
["sd0901_tx4_vdda_dyn_2p5g4l","sd0901_tx4","vdda_dyn","2p5g4l",9.2040000000000006,"",""]
["sd0901_tx4_vdda_dyn_lptx","sd0901_tx4","vdda_dyn","lptx",4.3520000000000003,"",""]
["sd0901_tx4_vdda_dyn_ulps","sd0901_tx4","vdda_dyn","ulps",0.73199999999999998,"",""]
["sd0901_tx4_vdda_lkg","sd0901_tx4","vdda_lkg","disable",0,"",""]
["sd0901_tx4_vddh1_dyn_1p0g4l","sd0901_tx4","vddh1_dyn","1p0g4l",28.448,"",""]
["sd0901_tx4_vddh1_dyn_1p5g4l","sd0901_tx4","vddh1_dyn","1p5g4l",30.648,"",""]
["sd0901_tx4_vddh1_dyn_2p5g4l","sd0901_tx4","vddh1_dyn","2p5g4l",36.816000000000003,"",""]
["sd0901_tx4_vddh1_dyn_lptx","sd0901_tx4","vddh1_dyn","lptx",17.408000000000001,"",""]
["sd0901_tx4_vddh1_dyn_ulps","sd0901_tx4","vddh1_dyn","ulps",2.9279999999999999,"",""]
["sd0901_tx4_vddh1_lkg","sd0901_tx4","vddh1_lkg","disable",0,"",""]
["sd0901_tx4_vddh2_dyn_1p0g4l","sd0901_tx4","vddh2_dyn","1p0g4l",4.6399999999999997,"",""]
["sd0901_tx4_vddh2_dyn_1p5g4l","sd0901_tx4","vddh2_dyn","1p5g4l",4.1900000000000004,"",""]
["sd0901_tx4_vddh2_dyn_2p5g4l","sd0901_tx4","vddh2_dyn","2p5g4l",5.22,"",""]
["sd0901_tx4_vddh2_dyn_lptx","sd0901_tx4","vddh2_dyn","lptx",7.58,"",""]
["sd0901_tx4_vddh2_dyn_ulps","sd0901_tx4","vddh2_dyn","ulps",0.16,"",""]
[]
[]
[]
[]
[]
[]
[]
[]
[]
["sd1000_vdd_dyn_device_fs","sd1000","vdd_dyn","device_fs",1.59,"",""]
["sd1000_vdd_dyn_device_fs_idle","sd1000","vdd_dyn","device_fs_idle",1.56,"",""]
["sd1000_vdd_dyn_device_hs","sd1000","vdd_dyn","device_hs",1.65,"",""]
["sd1000_vdd_dyn_device_hs_idle","sd1000","vdd_dyn","device_hs_idle",1.28,"",""]
["sd1000_vdd_dyn_device_ls","sd1000","vdd_dyn","device_ls",1.58,"",""]
["sd1000_vdd_dyn_device_ls_idle","sd1000","vdd_dyn","device_ls_idle",1.56,"",""]
["sd1000_vdd_dyn_host_fs","sd1000","vdd_dyn","host_fs",1.59,"",""]
["sd1000_vdd_dyn_host_fs_idle","sd1000","vdd_dyn","host_fs_idle",1.56,"",""]
["sd1000_vdd_dyn_host_hs","sd1000","vdd_dyn","host_hs",1.63,"",""]
["sd1000_vdd_dyn_host_hs_idle","sd1000","vdd_dyn","host_hs_idle",1.28,"",""]
["sd1000_vdd_dyn_host_ls","sd1000","vdd_dyn","host_ls",1.57,"",""]
["sd1000_vdd_dyn_host_ls_idle","sd1000","vdd_dyn","host_ls_idle",1.56,"",""]
["sd1000_vdd_dyn_Power_down","sd1000","vdd_dyn","Power_down",0.26,"",""]
["sd1000_vdd_dyn_sleep","sd1000","vdd_dyn","sleep",0.26,"",""]
["sd1000_vdd_dyn_suspend","sd1000","vdd_dyn","suspend",0.51200000000000001,"",""]
["sd1000_vdd_lkg","sd1000","vdd_lkg","",0,"",""]
["sd1000_vdda_dyn_device_fs","sd1000","vdda_dyn","device_fs",0.19,"",""]
["sd1000_vdda_dyn_device_fs_idle","sd1000","vdda_dyn","device_fs_idle",0.19,"",""]
["sd1000_vdda_dyn_device_hs","sd1000","vdda_dyn","device_hs",5.47,"",""]
["sd1000_vdda_dyn_device_hs_idle","sd1000","vdda_dyn","device_hs_idle",0.51,"",""]
["sd1000_vdda_dyn_device_ls","sd1000","vdda_dyn","device_ls",0.19,"",""]
["sd1000_vdda_dyn_device_ls_idle","sd1000","vdda_dyn","device_ls_idle",0.19,"",""]
["sd1000_vdda_dyn_host_fs","sd1000","vdda_dyn","host_fs",0.19,"",""]
["sd1000_vdda_dyn_host_fs_idle","sd1000","vdda_dyn","host_fs_idle",0.19,"",""]
["sd1000_vdda_dyn_host_hs","sd1000","vdda_dyn","host_hs",5.47,"",""]
["sd1000_vdda_dyn_host_hs_idle","sd1000","vdda_dyn","host_hs_idle",0.51,"",""]
["sd1000_vdda_dyn_host_ls","sd1000","vdda_dyn","host_ls",0.19,"",""]
["sd1000_vdda_dyn_host_ls_idle","sd1000","vdda_dyn","host_ls_idle",0.19,"",""]
["sd1000_vdda_dyn_Power_down","sd1000","vdda_dyn","Power_down",0.03,"",""]
["sd1000_vdda_dyn_sleep","sd1000","vdda_dyn","sleep",0.03,"",""]
["sd1000_vdda_dyn_suspend","sd1000","vdda_dyn","suspend",0.05,"",""]
["sd1000_vdda_lkg","sd1000","vdda_lkg","",0,"",""]
["sd1000_vddh1_dyn_device_fs","sd1000","vddh1_dyn","device_fs",5.64,"",""]
["sd1000_vddh1_dyn_device_fs_idle","sd1000","vddh1_dyn","device_fs_idle",5.34,"",""]
["sd1000_vddh1_dyn_device_hs","sd1000","vddh1_dyn","device_hs",12.89,"",""]
["sd1000_vddh1_dyn_device_hs_idle","sd1000","vddh1_dyn","device_hs_idle",9.42,"",""]
["sd1000_vddh1_dyn_device_ls","sd1000","vddh1_dyn","device_ls",5.59,"",""]
["sd1000_vddh1_dyn_device_ls_idle","sd1000","vddh1_dyn","device_ls_idle",5.39,"",""]
["sd1000_vddh1_dyn_host_fs","sd1000","vddh1_dyn","host_fs",5.63,"",""]
["sd1000_vddh1_dyn_host_fs_idle","sd1000","vddh1_dyn","host_fs_idle",5.35,"",""]
["sd1000_vddh1_dyn_host_hs","sd1000","vddh1_dyn","host_hs",12.88,"",""]
["sd1000_vddh1_dyn_host_hs_idle","sd1000","vddh1_dyn","host_hs_idle",9.42,"",""]
["sd1000_vddh1_dyn_host_ls","sd1000","vddh1_dyn","host_ls",5.59,"",""]
["sd1000_vddh1_dyn_host_ls_idle","sd1000","vddh1_dyn","host_ls_idle",5.39,"",""]
["sd1000_vddh1_dyn_Power_down","sd1000","vddh1_dyn","Power_down",0.18,"",""]
["sd1000_vddh1_dyn_sleep","sd1000","vddh1_dyn","sleep",0.24,"",""]
["sd1000_vddh1_dyn_suspend","sd1000","vddh1_dyn","suspend",0.23899999999999999,"",""]
["sd1000_vddh1_lkg","sd1000","vddh1_lkg","",0,"",""]
["sd1000_vddh2_dyn_device_fs","sd1000","vddh2_dyn","device_fs",11.7,"",""]
["sd1000_vddh2_dyn_device_fs_idle","sd1000","vddh2_dyn","device_fs_idle",3.46,"",""]
["sd1000_vddh2_dyn_device_hs","sd1000","vddh2_dyn","device_hs",1.91,"",""]
["sd1000_vddh2_dyn_device_hs_idle","sd1000","vddh2_dyn","device_hs_idle",2.72,"",""]
["sd1000_vddh2_dyn_device_ls","sd1000","vddh2_dyn","device_ls",7.34,"",""]
["sd1000_vddh2_dyn_device_ls_idle","sd1000","vddh2_dyn","device_ls_idle",3.3,"",""]
["sd1000_vddh2_dyn_host_fs","sd1000","vddh2_dyn","host_fs",9.2200000000000006,"",""]
["sd1000_vddh2_dyn_host_fs_idle","sd1000","vddh2_dyn","host_fs_idle",2.46,"",""]
["sd1000_vddh2_dyn_host_hs","sd1000","vddh2_dyn","host_hs",1.91,"",""]
["sd1000_vddh2_dyn_host_hs_idle","sd1000","vddh2_dyn","host_hs_idle",2.72,"",""]
["sd1000_vddh2_dyn_host_ls","sd1000","vddh2_dyn","host_ls",4.9000000000000004,"",""]
["sd1000_vddh2_dyn_host_ls_idle","sd1000","vddh2_dyn","host_ls_idle",2.39,"",""]
["sd1000_vddh2_dyn_Power_down","sd1000","vddh2_dyn","Power_down",0.16,"",""]
["sd1000_vddh2_dyn_sleep","sd1000","vddh2_dyn","sleep",1.02,"",""]
["sd1000_vddh2_dyn_suspend","sd1000","vddh2_dyn","suspend",1.024,"",""]
["sd1000_vddh2_lkg","sd1000","vddh2_lkg","",0,"",""]
[]
[]
[]
[]
[]
[]
["spi_vdd_dyn_Controller_1.563_Mbaud_1p8v","spi","vdd_dyn","Controller_1.563_Mbaud_1p8v",2.6507999999999999E-7,"",""]
["spi_vdd_dyn_Controller_1.563_Mbaud_3p3v","spi","vdd_dyn","Controller_1.563_Mbaud_3p3v",2.6507999999999999E-7,"",""]
["spi_vdd_dyn_Controller_12.5_Mbaud_1p8v","spi","vdd_dyn","Controller_12.5_Mbaud_1p8v",2.1199600000000002E-6,"",""]
["spi_vdd_dyn_Controller_12.5_Mbaud_3p3v","spi","vdd_dyn","Controller_12.5_Mbaud_3p3v",2.1199600000000002E-6,"",""]
["spi_vdd_dyn_Controller_2.083_Mbaud_1p8v","spi","vdd_dyn","Controller_2.083_Mbaud_1p8v",3.5326999999999999E-7,"",""]
["spi_vdd_dyn_Controller_2.083_Mbaud_3p3v","spi","vdd_dyn","Controller_2.083_Mbaud_3p3v",3.5326999999999999E-7,"",""]
["spi_vdd_dyn_Controller_25_Mbaud_1p8v","spi","vdd_dyn","Controller_25_Mbaud_1p8v",4.2399200000000004E-6,"",""]
["spi_vdd_dyn_Controller_25_Mbaud_3p3v","spi","vdd_dyn","Controller_25_Mbaud_3p3v",4.2399200000000004E-6,"",""]
["spi_vdd_dyn_Controller_3.125_Mbaud_1p8v","spi","vdd_dyn","Controller_3.125_Mbaud_1p8v",5.2999000000000005E-7,"",""]
["spi_vdd_dyn_Controller_3.125_Mbaud_3p3v","spi","vdd_dyn","Controller_3.125_Mbaud_3p3v",5.2999000000000005E-7,"",""]
["spi_vdd_dyn_Controller_6.25_Mbaud_1p8v","spi","vdd_dyn","Controller_6.25_Mbaud_1p8v",1.0599800000000001E-6,"",""]
["spi_vdd_dyn_Controller_6.25_Mbaud_3p3v","spi","vdd_dyn","Controller_6.25_Mbaud_3p3v",1.0599800000000001E-6,"",""]
["spi_vdd_dyn_off","spi","vdd_dyn","off",0,"",""]
["spi_vdd_dyn_Peripheral_12.5_Mbaud_1p8v","spi","vdd_dyn","Peripheral_12.5_Mbaud_1p8v",1.9468999999999999E-6,"",""]
["spi_vdd_dyn_Peripheral_12.5_Mbaud_3p3v","spi","vdd_dyn","Peripheral_12.5_Mbaud_3p3v",1.9468999999999999E-6,"",""]
["spi_vdd_dyn_Peripheral_2.083_Mbaud_1p8v","spi","vdd_dyn","Peripheral_2.083_Mbaud_1p8v",2.4344000000000001E-7,"",""]
["spi_vdd_dyn_Peripheral_2.083_Mbaud_3p3v","spi","vdd_dyn","Peripheral_2.083_Mbaud_3p3v",2.4344000000000001E-7,"",""]
["spi_vdd_dyn_Peripheral_25_Mbaud_1p8v","spi","vdd_dyn","Peripheral_25_Mbaud_1p8v",3.8937999999999999E-6,"",""]
["spi_vdd_dyn_Peripheral_25_Mbaud_3p3v","spi","vdd_dyn","Peripheral_25_Mbaud_3p3v",3.8937999999999999E-6,"",""]
["spi_vdd_dyn_Peripheral_3.125_Mbaud_1p8v","spi","vdd_dyn","Peripheral_3.125_Mbaud_1p8v",4.8672499999999999E-7,"",""]
["spi_vdd_dyn_Peripheral_3.125_Mbaud_3p3v","spi","vdd_dyn","Peripheral_3.125_Mbaud_3p3v",4.8672499999999999E-7,"",""]
["spi_vdd_dyn_Peripheral_6.25_Mbaud_1p8v","spi","vdd_dyn","Peripheral_6.25_Mbaud_1p8v",9.7344899999999994E-7,"",""]
["spi_vdd_dyn_Peripheral_6.25_Mbaud_3p3v","spi","vdd_dyn","Peripheral_6.25_Mbaud_3p3v",9.7344899999999994E-7,"",""]
["spi_vddh1_dyn_Controller_1.563_Mbaud_1p8v","spi","vddh1_dyn","Controller_1.563_Mbaud_1p8v",0.31943214599999997,"",""]
["spi_vddh1_dyn_Controller_12.5_Mbaud_1p8v","spi","vddh1_dyn","Controller_12.5_Mbaud_1p8v",2.5546396819999999,"",""]
["spi_vddh1_dyn_Controller_2.083_Mbaud_1p8v","spi","vddh1_dyn","Controller_2.083_Mbaud_1p8v",0.425705157,"",""]
["spi_vddh1_dyn_Controller_25_Mbaud_1p8v","spi","vddh1_dyn","Controller_25_Mbaud_1p8v",5.1092793629999997,"",""]
["spi_vddh1_dyn_Controller_3.125_Mbaud_1p8v","spi","vddh1_dyn","Controller_3.125_Mbaud_1p8v",0.63865992000000005,"",""]
["spi_vddh1_dyn_Controller_6.25_Mbaud_1p8v","spi","vddh1_dyn","Controller_6.25_Mbaud_1p8v",1.277319841,"",""]
["spi_vddh1_dyn_Peripheral_12.5_Mbaud_1p8v","spi","vddh1_dyn","Peripheral_12.5_Mbaud_1p8v",0.51090749999999996,"",""]
["spi_vddh1_dyn_Peripheral_2.083_Mbaud_1p8v","spi","vddh1_dyn","Peripheral_2.083_Mbaud_1p8v",6.3883873999999993E-2,"",""]
["spi_vddh1_dyn_Peripheral_25_Mbaud_1p8v","spi","vddh1_dyn","Peripheral_25_Mbaud_1p8v",1.0218149999999999,"",""]
["spi_vddh1_dyn_Peripheral_3.125_Mbaud_1p8v","spi","vddh1_dyn","Peripheral_3.125_Mbaud_1p8v",0.12772687499999999,"",""]
["spi_vddh1_dyn_Peripheral_6.25_Mbaud_1p8v","spi","vddh1_dyn","Peripheral_6.25_Mbaud_1p8v",0.25545374999999998,"",""]
["spi_vddh2_dyn_Controller_1.563_Mbaud_3p3v","spi","vddh2_dyn","Controller_1.563_Mbaud_3p3v",1.872392593,"",""]
["spi_vddh2_dyn_Controller_12.5_Mbaud_3p3v","spi","vddh2_dyn","Controller_12.5_Mbaud_3p3v",14.97434895,"",""]
["spi_vddh2_dyn_Controller_2.083_Mbaud_3p3v","spi","vddh2_dyn","Controller_2.083_Mbaud_3p3v",2.4953255090000002,"",""]
["spi_vddh2_dyn_Controller_25_Mbaud_3p3v","spi","vddh2_dyn","Controller_25_Mbaud_3p3v",29.948697899999999,"",""]
["spi_vddh2_dyn_Controller_3.125_Mbaud_3p3v","spi","vddh2_dyn","Controller_3.125_Mbaud_3p3v",3.7435872379999999,"",""]
["spi_vddh2_dyn_Controller_6.25_Mbaud_3p3v","spi","vddh2_dyn","Controller_6.25_Mbaud_3p3v",7.4871744749999998,"",""]
["spi_vddh2_dyn_Peripheral_12.5_Mbaud_3p3v","spi","vddh2_dyn","Peripheral_12.5_Mbaud_3p3v",2.9947499999999998,"",""]
["spi_vddh2_dyn_Peripheral_2.083_Mbaud_3p3v","spi","vddh2_dyn","Peripheral_2.083_Mbaud_3p3v",0.37446353999999998,"",""]
["spi_vddh2_dyn_Peripheral_25_Mbaud_3p3v","spi","vddh2_dyn","Peripheral_25_Mbaud_3p3v",5.9894999999999996,"",""]
["spi_vddh2_dyn_Peripheral_3.125_Mbaud_3p3v","spi","vddh2_dyn","Peripheral_3.125_Mbaud_3p3v",0.74868749999999995,"",""]
["spi_vddh2_dyn_Peripheral_6.25_Mbaud_3p3v","spi","vddh2_dyn","Peripheral_6.25_Mbaud_3p3v",1.4973749999999999,"",""]
[]
[]
[]
[]
[]
[]
[]
[]
[]
["TEF16FCLL256X32HD18_PHRM_vdd_dyn_on","TEF16FCLL256X32HD18_PHRM","vdd_dyn","on",5.28E-3,"",""]
["TEF16FCLL256X32HD18_PHRM_vdd_lkg","TEF16FCLL256X32HD18_PHRM","vdd_lkg","on",5.28E-3,"",""]
[]
[]
[]
[]
[]
[]
[]
[]
[]
["TODP16FFC18_C170915_vdd_lkg","TODP16FFC18_C170915","vdd_lkg","on",0.05,"",""]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
["uart_modem_vdd_dyn_112k_1p8v","uart_modem","vdd_dyn","112k_1p8v",6.1944299999999997E-9,"",""]
["uart_modem_vdd_dyn_112k_3p3v","uart_modem","vdd_dyn","112k_3p3v",6.1944299999999997E-9,"",""]
["uart_modem_vdd_dyn_1m_1p8v","uart_modem","vdd_dyn","1m_1p8v",5.5307400000000002E-8,"",""]
["uart_modem_vdd_dyn_1m_3p3v","uart_modem","vdd_dyn","1m_3p3v",5.5307400000000002E-8,"",""]
["uart_modem_vdd_dyn_3p6m_1p8v","uart_modem","vdd_dyn","3p6m_1p8v",1.9910700000000001E-7,"",""]
["uart_modem_vdd_dyn_3p6m_3p3v","uart_modem","vdd_dyn","3p6m_3p3v",1.9910700000000001E-7,"",""]
["uart_modem_vdd_dyn_off","uart_modem","vdd_dyn","off",0,"",""]
["uart_modem_vddh1_dyn_112k_1p8v","uart_modem","vddh1_dyn","112k_1p8v",4.6692859999999999E-3,"",""]
["uart_modem_vddh1_dyn_1m_1p8v","uart_modem","vddh1_dyn","1m_1p8v",4.1690051999999998E-2,"",""]
["uart_modem_vddh1_dyn_3p6m_1p8v","uart_modem","vddh1_dyn","3p6m_1p8v",0.15008418700000001,"",""]
["uart_modem_vddh1_dyn_off","uart_modem","vddh1_dyn","off",0,"",""]
["uart_modem_vddh2_dyn_112k_3p3v","uart_modem","vddh2_dyn","112k_3p3v",2.7369619000000001E-2,"",""]
["uart_modem_vddh2_dyn_1m_3p3v","uart_modem","vddh2_dyn","1m_3p3v",0.24437159999999999,"",""]
["uart_modem_vddh2_dyn_3p6m_3p3v","uart_modem","vddh2_dyn","3p6m_3p3v",0.87973776000000004,"",""]
["uart_modem_vddh2_dyn_off","uart_modem","vddh2_dyn","off",0,"",""]
[]
[]
[]
[]
["uart_vdd_dyn_112k_1p8v","uart","vdd_dyn","112k_1p8v",6.1944299999999997E-9,"",""]
["uart_vdd_dyn_112k_3p3v","uart","vdd_dyn","112k_3p3v",6.1944299999999997E-9,"",""]
["uart_vdd_dyn_1m_1p8v","uart","vdd_dyn","1m_1p8v",5.5307400000000002E-8,"",""]
["uart_vdd_dyn_1m_3p3v","uart","vdd_dyn","1m_3p3v",5.5307400000000002E-8,"",""]
["uart_vdd_dyn_3p6m_1p8v","uart","vdd_dyn","3p6m_1p8v",1.9910700000000001E-7,"",""]
["uart_vdd_dyn_3p6m_3p3v","uart","vdd_dyn","3p6m_3p3v",1.9910700000000001E-7,"",""]
["uart_vdd_dyn_off","uart","vdd_dyn","off",0,"",""]
["uart_vddh1_dyn_112k_1p8v","uart","vddh1_dyn","112k_1p8v",4.6692859999999999E-3,"",""]
["uart_vddh1_dyn_1m_1p8v","uart","vddh1_dyn","1m_1p8v",4.1690051999999998E-2,"",""]
["uart_vddh1_dyn_3p6m_1p8v","uart","vddh1_dyn","3p6m_1p8v",0.15008418700000001,"",""]
["uart_vddh1_dyn_off","uart","vddh1_dyn","off",0,"",""]
["uart_vddh2_dyn_112k_3p3v","uart","vddh2_dyn","112k_3p3v",2.7369619000000001E-2,"",""]
["uart_vddh2_dyn_1m_3p3v","uart","vddh2_dyn","1m_3p3v",0.24437159999999999,"",""]
["uart_vddh2_dyn_3p6m_3p3v","uart","vddh2_dyn","3p6m_3p3v",0.87973776000000004,"",""]
["uart_vddh2_dyn_off","uart","vddh2_dyn","off",0,"",""]

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[]
["label","lkg_scale","dynint_scale",null,"Normalized Leakage at S_125_0.88",null,null,"Normalized Dyn Int at S_125_0.88"]
["l16_nominal_0.63_-55C",1.0476601928062485E-4,0.35273169209046945,null,"SVT20",1,null,"SVT20",1]
["l16_nominal_0.63_-40C",2.451026286987237E-4,0.35304823069106661,null,"SVT16",1.9775,null,"SVT16",0.97857700000000003]
["l16_nominal_0.63_-20C",7.7623274665988601E-4,0.35387950011615366,null,"LVT20",9.4344699999999992,null,"LVT20",1.2461899999999999]
["l16_nominal_0.63_0C",2.2608253135589008E-3,0.35534170242730378,null,"LVT16",15.877800000000001,null,"LVT16",1.2442500000000001]
["l16_nominal_0.63_25C",7.4358475625597676E-3,0.35838632434874607,null,"ULVT20",61.857669999999999,null,"ULVT20",1.506588]
["l16_nominal_0.63_50C",2.1127094999087929E-2,0.36310886210144977,null,"ULVT16",99.094785000000002,null,"ULVT16",1.5980000000000001]
["l16_nominal_0.63_75C",5.3066423632031928E-2,0.36981098439753618]
["l16_nominal_0.63_80C",6.2978111681692803E-2,0.37143288689871024]
["l16_nominal_0.63_85C",7.4444500489201634E-2,0.37313402174996957]
["l16_nominal_0.63_90C",8.7661132515601939E-2,0.37493736897902391]
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["u20_weak_0.85_105C",0.16687515130877098,0.77242546583850946]
["u20_weak_0.85_110C",0.19045972149431434,0.77718955601564321]
["u20_weak_0.85_115C",0.21674785241309222,0.78191614906832307]
["u20_weak_0.85_120C",0.24597126264010194,0.78659719346675872]
["u20_weak_0.85_125C",0.27837355375418676,0.79123073383942955]
["u20_weak_0.85_130C",0.31420976694237007,0.79582114101679335]
["u20_weak_0.85_135C",0.3537465603581218,0.800409247757074]
["u20_weak_0.85_140C",0.39726185440482553,0.8049014262709917]
["u20_weak_0.85_145C",0.44504429966097964,0.80933390844260422]
["u20_weak_0.85_150C",0.49739309952193078,0.8137223372440765]
["u20_weak_0.88_-55C",2.509251450568921E-4,0.69731003163101002]
["u20_weak_0.88_-40C",5.9795878371248098E-4,0.70852082493673818]
["u20_weak_0.88_-20C",1.7414497796766936E-3,0.7247357200368072]
["u20_weak_0.88_0C",4.5360830958949541E-3,0.74237443754313326]
["u20_weak_0.88_25C",1.3038386536379284E-2,0.76607800782148627]
["u20_weak_0.88_50C",3.2846706590012424E-2,0.79121871405567068]
["u20_weak_0.88_75C",7.4189929420277897E-2,0.81723948700253057]
["u20_weak_0.88_80C",8.6326387096831408E-2,0.82245939728548434]
["u20_weak_0.88_85C",0.10009568478470035,0.82769979296066265]
["u20_weak_0.88_90C",0.11566747453356992,0.83296353807223389]
["u20_weak_0.88_95C",0.13322283913339203,0.83814170692431578]
["u20_weak_0.88_100C",0.15295518777363054,0.84336542443064211]
["u20_weak_0.88_105C",0.17506963528932895,0.84847032436162872]
["u20_weak_0.88_110C",0.19978380027330908,0.85363146997929629]
["u20_weak_0.88_115C",0.2273275390387714,0.85871474580170259]
["u20_weak_0.88_120C",0.25794303429842835,0.86377927306188185]
["u20_weak_0.88_125C",0.29188470648537107,0.86877156659765375]
["u20_weak_0.88_130C",0.32941930243220258,0.87375971934667596]
["u20_weak_0.88_135C",0.37082545197537203,0.87872394755003469]
["u20_weak_0.88_140C",0.41639340191777491,0.88355923625488852]
["u20_weak_0.88_145C",0.4664250160287533,0.88836059351276764]
["u20_weak_0.88_150C",0.52123288825276393,0.89309178743961359]
["u20_weak_0.935_-55C",2.8670637718250432E-4,0.82575971060501507]
["u20_weak_0.935_-40C",6.7096006689953795E-4,0.83919758971704639]
["u20_weak_0.935_-20C",1.9307619931876688E-3,0.8584220784449047]
["u20_weak_0.935_0C",4.9985252660152291E-3,0.87906781458477123]
["u20_weak_0.935_25C",1.430446738869217E-2,0.9065656889809065]
["u20_weak_0.935_50C",3.5934177026606395E-2,0.93555282953761232]
["u20_weak_0.935_75C",8.0996700249454393E-2,0.96527522429261581]
["u20_weak_0.935_80C",9.4213775239189793E-2,0.9712162410858064]
["u20_weak_0.935_85C",0.10920480534486871,0.97718023924545672]
["u20_weak_0.935_90C",0.12615369335287821,0.98311249137336099]
["u20_weak_0.935_95C",0.14525686354321024,0.98904244306418221]
["u20_weak_0.935_100C",0.1667235986701677,0.99497043938348306]
["u20_weak_0.935_105C",0.19077639467889729,1.0008107890499198]
["u20_weak_0.935_110C",0.2176508720262561,1.0067007131354959]
["u20_weak_0.935_115C",0.24759613039734457,1.012493098688751]
["u20_weak_0.935_120C",0.28087448266810683,1.0182261329652635]
["u20_weak_0.935_125C",0.31776180962186329,1.0239158040027607]
["u20_weak_0.935_130C",0.35854711655364513,1.029554175293306]
["u20_weak_0.935_135C",0.40353235591192743,1.0351222682309642]
["u20_weak_0.935_140C",0.45303242729862964,1.0406337704163793]
["u20_weak_0.935_145C",0.5073748227525825,1.0461067402806536]
["u20_weak_0.935_150C",0.56689882863732977,1.0514277662755929]
["u20_weak_1.15_135C",0.57114310063041995,1.820119852772027]

{"sheet":"Notes","index":6,"n_rows":257,"n_cols":17,"rows_kept":257,"cut":false,"hidden":true,"merged":[[244,1,246,1]]}
["This is a protected version of J722S_AM62P_PowerEstimationTool_unprotected_8.xlsm"]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
["I started at the top with projects, that got me to the right database.  I selected tags…"]
["This will get you a break down of the blocks"]
[]
[]
["sam67_dss_dsi_oldi_wrap"]
[0.38100000000000001,"Ik3_dss_ul_main_0",null,"(k3_dss_ul)"]
[0.38100000000000001,"Ik3_dss_ul_main_1",null,"(k3_dss_ul_1)"]
[0.23100000000000001,"Ik3_dss_dsi_0",null,"(k3_dss_dsi)"]
[2E-3,"I_dss_dsi_oldi_mdp_wrap",null,"(sam67_dss_dsi_oldi_mdp_wrap)"]
[]
["main_ip_wrap",null,"data_cbass is biggest component -- estimate as max(DDR,average(A53s))"]
[2940954,2326518,1,"sam67_main_ip_wrap","()","Area %"]
[1392553,810204,0.34799999999999998,"Isam67_main_cbass_wrap_main_0","(sam67_main_cbass_wrap)",{"$f":"B43/B$42","v":0.34824746681521485},null,"Isam67_main_cbass_wrap_main_0"]
[21024,248258,0.107,"Imsram8kx256e_main_0\\/I_msram0","(msram8kx256e_msram0)",{"$f":"B44/B$42","v":0.10670796443440368},null,1104865,661112,0.28399999999999997,"I_main_data_cbass_main_0","(am67_main_data_cbass)",null,{"$f":"I44/B$42","v":0.2841637159050564}]
[65107,63633,2.7E-2,"Ik3_jpgenc_e5010_main_0\\/I_jasper_sys_if\\/i_jasper_","sys (SM_e5010_jasper_sys)",2.7351174587946451E-2,null,25999,12573,5.0000000000000001E-3,"I_vpac_rsws_bw_limiter_main_mst1_0","(sam67_vpac_rsws_bw_limiter)",null,{"$f":"I45/B$42","v":5.4042135070521699E-3}]
[59596,58915,2.5000000000000001E-2,"Isam67_pdma_spi_main_0","(sam67_pdma_spi)",2.5323251313765893E-2,null,26004,12525,5.0000000000000001E-3,"I_vpac_rsws_bw_limiter_main_mst0_0","(sam67_vpac_rsws_bw_limiter_1)",null,5.3835818162593198E-3]
[35826,43746,1.9E-2,"Isam62_pdma_uart_main_0\\/I_pdma_core","(sam62_pdma_uart_pdma_core)",1.880320719633375E-2,null,25995,12396,5.0000000000000001E-3,"I_c7xv_rsws_bs_limiter_main_1","(sam67_c7xv_rsws_bs_limiter_1)",null,5.3281341472535349E-3]
[43947,42891,1.7999999999999999E-2,"Idmss_am67_main_0\\/I_bcdma\\/I_cfg","(dmss_am67_bcdma_cfg)",1.8435705204086106E-2,null,25989,12381,5.0000000000000001E-3,"I_c7xv_rsws_bs_limiter_main_0","(sam67_c7xv_rsws_bs_limiter)",null,5.3216867438807694E-3]
[27741,38212,1.6E-2,"Idmss_am67_main_0\\/I_pktdma\\/I_tpcfifo","(dmss_am67_pktdma_tpcfifo)",1.642454517867474E-2,null,14057,6603,3.0000000000000001E-3,"I_a53_ws_bw_limiter_main_0","(sam67_a53_ws_bw_limiter)",null,2.8381469646914402E-3]
[62761,37642,1.6E-2,"Idmss_am67_main_0\\/I_psilss","(dmss_am67_psilss)",1.6179543850509646E-2,null,13923,6522,3.0000000000000001E-3,"I_gpu_ws_bw_limiter_main_0","(sam67_gpu_ws_bw_limiter)",null,2.8033309864785058E-3]
[18271,33351,1.4E-2,"Imcanss_main_0","(mcanss)",1.4335156659007151E-2,null,13554,6197,3.0000000000000001E-3,"I_wave521_ws_bw_limiter_main_pri_0","(sam67_wave521_ws_bw_limiter)",null,2.6636372467352498E-3]
[18245,33329,1.4E-2,"Imcanss_main_1","(mcanss_1)",1.4325700467393761E-2,null,11293,5106,2E-3,"I_e5010_ws_bw_limiter_main_0","(sam67_e5010_ws_bw_limiter)",null,2.1946961080894279E-3]
[43323,31996,1.4E-2,"Idmss_am67_main_0\\/I_bcdma\\/I_trcu","(dmss_am67_bcdma_trcu)",1.3752741221000654E-2,null,1416,1028,0,"I_main_misc_peri_cbass_main_0\\/I_Iecap_main_0_ecap_","vbusp_p2p_bridge (am67_main_misc_peri_cbass_Iecap_main_0_ecap_vbusp_)",null,4.4186204448020604E-4]
[16253,31526,1.4E-2,"Idmss_am67_main_0\\/I_bcdma\\/I_pcfifo\\/I_dfifo","(dmss_am67_bcdma_pcfifo_dfifo)",1.3550722581987331E-2,null,1352,961,0,"I_main_misc_peri_cbass_main_0\\/I_Ispi_main_1_slv_p2","p_bridge (am67_main_misc_peri_cbass_Ispi_main_1_slv_p2p_brid)",null,4.1306364274851947E-4]
[61626,29579,1.2999999999999999E-2,"Igic500ss_1_4_main_0\\/Igic500","(gic500_1_4)",1.2713849624202349E-2,null,797,394,0,"I_gpu_rs_bw_limiter_main_0\\/I_rdtxn_stats","(sam67_gpu_rs_bw_limiter_rdtxn_stats)",null,1.6935179525797781E-4]
[33009,28694,1.2E-2,"Idmss_am67_main_0\\/I_ipcss\\/I_ringacc","(dmss_am67_ipcss_ringacc)",1.2333452825209175E-2,null,797,394,0,"I_a53_rs_bw_limiter_main_0\\/I_rdtxn_stats","(sam67_a53_rs_bw_limiter_rdtxn_stats)",null,1.6935179525797781E-4]
[15714,28199,1.2E-2,"Idmss_am67_main_0\\/I_bcdma\\/I_tpcfifo","(dmss_am67_bcdma_tpcfifo)",1.2120688513907909E-2,null,16,14,0,"Iclk_pwr_ipg_main_sysclk0_div4_clk","(kp_ti_ipg_clk_s1c1fps_56)",null,6.0175764812479421E-6]
[26821,24900,1.0999999999999999E-2,"Idmss_am67_main_0\\/I_pktdma\\/I_cfg","(dmss_am67_pktdma_cfg)",1.0702689598790983E-2,null,16,14,0,"Iclk_pwr_ipg_main_sysclk0_div2_clk","(kp_ti_ipg_clk_s1c1fps_57)",null,6.0175764812479421E-6]
[13379,23582,0.01,"Idmss_am67_main_0\\/I_intaggr","(dmss_am67_intaggr)",1.013617775577064E-2,null,16,14,0,"Iclk_pwr_ipg_main_sysclk0_div1_clk","(kp_ti_ipg_clk_s1c1fps_58)",null,6.0175764812479421E-6]
[7162,22284,0.01,"Idmss_am67_main_0\\/I_ipcss\\/I_msram","(dmss_am67_ipcss_msram)",9.5782624505806532E-3,null,4,2,0,"Ipwr_aggr_clkstop","(kp_ti_ipg_pwrclkstop_19)",null,8.5965378303542033E-7]
[27060,18278,8.0000000000000002E-3,"Ik3_jpgenc_e5010_main_0\\/I_axi2vbusm\\/I_ksbus_axi2v","busm_r (k3_jpgenc_e5010_axi2vbusm_ksbus_axi2vbusm_r)",7.8563759231607064E-3]
[26186,16278,7.0000000000000001E-3,"Isam62_pdma_mcasp_main_0\\/I_pdma_core","(sam62_pdma_mcasp_pdma_core)",6.9967221401252859E-3]
[17392,11835,5.0000000000000001E-3,"Isam67_main_ip_wrap_pbist_test_wrap\\/Ik3_pbist_8c28","p_4bit_wrap (k3_pbist_8c28p_4bit_wrap)",5.0870012611120997E-3]
[7681,10476,5.0000000000000001E-3,"Idmss_am67_main_0\\/I_pktdma\\/I_stats","(dmss_am67_pktdma_stats)",4.5028665155395315E-3]
[12347,7365,3.0000000000000001E-3,"Iusart_main_2","(usart_2)",3.1656750560279355E-3]
[12458,7317,3.0000000000000001E-3,"Iusart_main_3","(usart_3)",3.1450433652350854E-3]
[12413,7315,3.0000000000000001E-3,"Iusart_main_4","(usart_4)",3.1441837114520497E-3]
[12401,7311,3.0000000000000001E-3,"Iusart_main_6","(usart_6)",3.1424644038859791E-3]
[12397,7305,3.0000000000000001E-3,"Iusart_main_5","(usart_5)",3.1398854425368728E-3]
[12215,7294,3.0000000000000001E-3,"Iusart_main_0","(usart)",3.135157346730178E-3]
[12167,7167,3.0000000000000001E-3,"Iusart_main_1","(usart_1)",3.0805693315074287E-3]
[12537,7076,3.0000000000000001E-3,"Idmss_am67_main_0\\/I_bcdma\\/I_evtcu","(dmss_am67_bcdma_evtcu)",3.0414550843793171E-3]
[9530,6749,3.0000000000000001E-3,"Icpt2_probe_vbusm_16_main_probe_Isam67_c7xv_wrap_ma","in_1_soc_c7xv (cpt2_probe_vbusm_16_11)",2.9009016908530258E-3]
[9512,6736,3.0000000000000001E-3,"Icpt2_probe_vbusm_16_main_probe_Isam67_ddr_wrap_mai","n_0_ddrss_hpt (cpt2_probe_vbusm_16)",2.8953139412632957E-3]
[9377,6577,3.0000000000000001E-3,"Icpt2_probe_vbusm_16_main_probe_Isam67_vpac_wrap_ma","in_0_data_mst_1 (cpt2_probe_vbusm_16_5)",2.8269714655119798E-3]
[9258,6508,3.0000000000000001E-3,"Icpt2_probe_vbusm_16_main_probe_Isam67_c7xv_wrap_ma","in_0_c7xv_soc (cpt2_probe_vbusm_16_2)",2.7973134099972576E-3]
[8987,6296,3.0000000000000001E-3,"Icpt2_probe_vbusm_16_main_probe_Isam67_gpu_bxs464_w","rap_main_0_m_vbusm_w_sync (cpt2_probe_vbusm_16_7)",2.706190108995503E-3]
[12085,5430,2E-3,"Imdp","(sam67_main_ip_mdp_wrap)",2.3339600209411663E-3]
[8342,5128,2E-3,"Ispi_main_2","(spi_2)",2.2041522997028177E-3]
[8333,5116,2E-3,"Ispi_main_0","(spi)",2.1989943770046052E-3]
[8298,5083,2E-3,"Ispi_main_1","(spi_1)",2.1848100895845209E-3]
[7487,4876,2E-3,"Icpt2_probe_vbusm_8_main_probe_Isam67_vpac_wrap_mai","n_0_mem_slv (cpt2_probe_vbusm_8_7)",2.0958359230403545E-3]
[7502,4872,2E-3,"Icpt2_probe_vbusm_8_main_probe_export_am67_main_RT_","data_cbass_to_am67_main_data_cbass_data_l0 (cpt2_probe_vbusm_8_3)",2.094116615474284E-3]
[7213,4686,2E-3,"Icpt2_probe_vbusm_8_main_probe_br_SCRM_128b_clk1_VP","U_primary_to_SCRM_256b_clk1_l0 (cpt2_probe_vbusm_8_10)",2.0141688136519897E-3]
[7115,4610,2E-3,"Icpt2_probe_vbusm_8_main_probe_Isam62a_a53_512kb_wr","ap_main_0_a53_quad_wrap_cba_axi_r (cpt2_probe_vbusm_8)",1.981501969896644E-3]
[7040,4526,2E-3,"Icpt2_probe_vbusm_8_main_probe_Isam62a_a53_512kb_wr","ap_main_0_a53_quad_wrap_cba_axi_w (cpt2_probe_vbusm_8_1)",1.9453965110091563E-3]
[4238,4481,2E-3,"Idmss_am67_main_0\\/I_pktdma\\/I_ringocc","(dmss_am67_pktdma_ringocc)",1.9260543008908593E-3]
[6824,4293,2E-3,"Icpt2_probe_vbusm_8_main_probe_Ik3_jpgenc_e5010_mai","n_0_m_vbusm_w (cpt2_probe_vbusm_8_9)",1.8452468452855298E-3]
[5301,3850,2E-3,"Idmtimer_dmc1ms_main_0","(dmtimer_dmc1ms)",1.6548335323431842E-3]
[5308,3848,2E-3,"Idmtimer_dmc1ms_main_6","(dmtimer_dmc1ms_6)",1.6539738785601487E-3]
[5249,3847,2E-3,"Idmtimer_dmc1ms_main_3","(dmtimer_dmc1ms_3)",1.653544051668631E-3]
[5295,3847,2E-3,"Idmtimer_dmc1ms_main_7","(dmtimer_dmc1ms_7)",1.653544051668631E-3]
[5249,3847,2E-3,"Idmtimer_dmc1ms_main_1","(dmtimer_dmc1ms_1)",1.653544051668631E-3]
[5290,3847,2E-3,"Idmtimer_dmc1ms_main_2","(dmtimer_dmc1ms_2)",1.653544051668631E-3]
[5165,3842,2E-3,"Idmtimer_dmc1ms_main_5","(dmtimer_dmc1ms_5)",1.6513949172110424E-3]
[5161,3835,2E-3,"Idmtimer_dmc1ms_main_4","(dmtimer_dmc1ms_4)",1.6483861289704185E-3]
[6329,3642,2E-3,"Imshsi2c_main_4","(mshsi2c_4)",1.5654295389075003E-3]
[6365,3642,2E-3,"Imshsi2c_main_2","(mshsi2c_2)",1.5654295389075003E-3]
[6365,3642,2E-3,"Imshsi2c_main_1","(mshsi2c_1)",1.5654295389075003E-3]
[6341,3640,2E-3,"Imshsi2c_main_0","(mshsi2c)",1.5645698851244651E-3]
[6362,3637,2E-3,"Imshsi2c_main_3","(mshsi2c_3)",1.5632804044499119E-3]
[6813,2873,1E-3,"Idmss_am67_main_0\\/I_bcdma\\/I_rwu2","(dmss_am67_bcdma_rwu2)",1.2348926593303813E-3]
[6101,2834,1E-3,"Idmss_am67_main_0\\/I_bcdma\\/I_rwu3","(dmss_am67_bcdma_rwu3)",1.2181294105611906E-3]
[5581,2817,1E-3,"Igic500ss_1_4_main_0\\/Iaxi2vbusm\\/I_ksbus_axi2vbusm","_w (gic500ss_1_4_axi2vbusm_ksbus_axi2vbusm_w)",1.2108223534053894E-3]
[2636,1787,1E-3,"Iatl_main_0","(atl)",7.6810065514214807E-4]
[2963,1432,1E-3,"Idmss_am67_main_0\\/I_pktdma\\/I_tdu3","(dmss_am67_pktdma_tdu3)",6.1551210865336096E-4]
[2840,1429,1E-3,"Idmss_am67_main_0\\/I_pktdma\\/I_tdu2","(dmss_am67_pktdma_tdu2)",6.1422262797880783E-4]
[2508,1377,1E-3,"Ieqep_t2_main_1","(eqep_t2_1)",{"$f":"B108/B$42","v":5.9187162961988693E-4}]
[2464,1373,1E-3,"Ieqep_t2_main_0","(eqep_t2)",5.9015232205381605E-4]
[2442,1367,1E-3,"Ieqep_t2_main_2","(eqep_t2_2)",5.8757336070470979E-4]
[2066,1285,1E-3,"Idmss_am67_main_0\\/I_eccaggr","(dmss_am67_eccaggr)",5.5232755560025756E-4]
[2421,1252,1E-3,"Ik3_epwm_main_2","(k3_epwm_2)",5.381432681801731E-4]
[2404,1240,1E-3,"Ik3_epwm_main_1","(k3_epwm_1)",5.3298534548196057E-4]
[2424,1237,1E-3,"Ik3_epwm_main_0","(k3_epwm)",5.3169586480740743E-4]
[1205,676,0,"Iecap_main_0","(ecap)",2.9056297866597206E-4]
[1203,675,0,"Iecap_main_2","(ecap_2)",2.9013315177445437E-4]
[1197,674,0,"Iecap_main_1","(ecap_1)",2.8970332488293662E-4]
[]
["sec_wrap"]
[1829529,1481772,1,"sam67_sec_wrap","()"]
[587268,781834,0.52800000000000002,"Isms_main_0","(sms)",{"$f":"B121/B$120","v":0.52763448087829978}]
[814847,467005,0.315,"Isa3ss_am62a_main_0","(sa3ss_am62a)",{"$f":"B122/B$120","v":0.31516657083545918}]
[212957,105553,7.0999999999999994E-2,"Ifss_ul_main_0","(fss_ul)",7.1234305952602689E-2]
[149000,89877,6.0999999999999999E-2,"Isec_cbass_wrap_main_0","(sam67_sec_cbass_wrap)",6.0655080538706357E-2]
[26545,15096,0.01,"Imailbox8_main_0","(mailbox8)",1.0187802171994073E-2]
[3855,2243,2E-3,"Imdp","(sam67_sec_mdp_wrap)",1.5137281579082342E-3]
[]
["vpac_wrap"]
[1904350,2672227,1,"j7aen_vpac_wrap","()",null,{"$f":"D130","v":"Isam67_vpac_wrap_main_0"}]
[1894955,2669865,0.999,"Isam67_vpac_wrap_main_0","(sam67_vpac_wrap)",null,1775201,2547067,0.95299999999999996,"I_Ivpac_top_0","(vpac_top)",null,{"$f":"J130","v":"I_Ivpac_top_0"}]
[null,null,null,null,null,null,19436,15976,6.0000000000000001E-3,"I_data_mst_0_m2m","(sam67_vpac_wrap_data_mst_0_m2m)",null,713791,1314202,0.49199999999999999,"I_vpac_viss0","(vpac_viss)"]
[null,null,null,null,null,null,17418,11852,4.0000000000000001E-3,"I_Isam67_vpac_pbist_test_wrap\\/Ik3_pbist_8c28p_4bit_wrap","(k3_pbist_8c28p_4bit_wrap)",null,764585,929690,0.34799999999999998,"I_pac_base","(vpac_top_pac_base)"]
[null,null,null,null,null,null,14383,7232,3.0000000000000001E-3,"I_Isam67_vpac_mdp_wrap","(sam67_vpac_mdp_wrap)",null,65352,48431,1.7999999999999999E-2,"I_vpac_msc\\/I_lse","(vpac_msc_lse)"]
[null,null,null,null,null,null,7548,5740,2E-3,"I_ldc0_m_mst_m2m","(sam67_vpac_wrap_ldc0_m_mst_m2m)",null,87410,38917,1.4999999999999999E-2,"I_vpac_msc\\/I_core","(vpac_msc_core)"]
[null,null,null,null,null,null,5955,5326,2E-3,"I_mem_slv_m2m\\/I_wfifo_wrap\\/I_wfifo","(sam67_vpac_wrap_mem_slv_m2m_wfifo_wrap_wfifo)",null,14799,5509,2E-3,"I_vpac_ldc0\\/I_Ildc_ld\\/Ildc_ld_affine","(ldc_ld_affine)"]
[null,null,null,null,null,null,null,null,null,null,null,null,6006,2692,1E-3,"I_vpac_ldc0\\/I_Ildc_ld\\/Ildc_bicubic_interpolate","(ldc_bicubic_interpolate)"]
["vpac_viss and top_pac account for 85%. Not breaking this MODULE down."]
[]
["rt_wrap",null,"rt cbass relies upon the complex I/Os -- max(DSS, CSI, McASP, USB, WIZ, emmc8)"]
[481097,424114,1,"sam67_main_rt_wrap","()"]
[212387,140478,0.33100000000000002,"Isam67_main_rt_cbass_wrap_main_0","(sam67_main_rt_cbass_wrap)",null,null,null,{"$f":"D141","v":"Isam67_main_rt_cbass_wrap_main_0"}]
[25676,62919,0.14799999999999999,"Idmss_csi_am67_main_0\\/I_bcdma\\/I_rpcfifo","(dmss_csi_am67_bcdma_rpcfifo)",null,null,null,13651,7003,1.7000000000000001E-2,"I_main_data_cbass_main_0\\/I_SCRM_256b_clk1_scr","(am67_main_RT_data_cbass_SCRM_256b_clk1_scr)"]
[29938,31066,7.2999999999999995E-2,"Idmss_csi_am67_main_0\\/I_bcdma\\/I_cfg","(dmss_csi_am67_bcdma_cfg)",null,null,null,11970,6892,1.6E-2,"I_main_RT_cfg_cbass_main_0\\/I_SCRM_128b_CLK2_scr","(am67_main_RT_cfg_cbass_SCRM_128b_CLK2_scr)"]
[25976,18150,4.2999999999999997E-2,"Idmss_csi_am67_main_0\\/I_bcdma\\/I_trcu","(dmss_csi_am67_bcdma_trcu)",null,null,null,6364,4906,1.2E-2,"I_main_data_cbass_main_0\\/I_Idmss_csi_am67_main_0_bcdma_memw_m2m_bridge\\/I_wfifo_wrap\\/I_wfifo","(am67_main_RT_data_cbass_Idmss_csi_am67_main_0_bcdm)"]
[30854,18011,4.2000000000000003E-2,"Idmss_csi_am67_main_0\\/I_psilss","(dmss_csi_am67_psilss)",null,null,null,6332,4689,1.0999999999999999E-2,"I_main_data_cbass_main_0\\/I_Ik3_dss_ul_main_1_vbusm_dma_m2m_bridge\\/I_wfifo_wrap\\/I_wfifo","(am67_main_RT_data_cbass_Ik3_dss_ul_main_1_vbusm_dm)"]
[17359,11836,2.8000000000000001E-2,"Isam67_main_rt_wrap_pbist_test_wrap\\/Ik3_pbist_8c28p_4bit_wrap","(k3_pbist_8c28p_4bit_wrap)",null,null,null,3873,2745,6.0000000000000001E-3,"I_main_RT_cfg_cbass_main_0\\/I_Idmss_csi_am67_main_0_intaggr_cfg_p2p_bridge","(am67_main_RT_cfg_cbass_Idmss_csi_am67_main_0_intag)"]
[5171,6043,1.4E-2,"Idmss_csi_am67_main_0\\/I_intaggr\\/I_statreg","(dmss_csi_am67_intaggr_statreg)",null,null,null,3411,2302,5.0000000000000001E-3,"I_main_RT_cfg_cbass_main_0\\/I_Iusb2ss_16ffc_main_0_mstw0_m2m_bridge\\/I_wfifo_wrap\\/I_wfifo","(am67_main_RT_cfg_cbass_Iusb2ss_16ffc_main_0_mstw0_)"]
[6947,2893,7.0000000000000001E-3,"Idmss_csi_am67_main_0\\/I_bcdma\\/I_rwu2","(dmss_csi_am67_bcdma_rwu2)",null,null,null,3411,2301,5.0000000000000001E-3,"I_main_RT_cfg_cbass_main_0\\/I_Iemmc8ss_16ffc_main_0_emmcss_wr_m2m_bridge\\/I_wfifo_wrap\\/I_wfifo","(am67_main_RT_cfg_cbass_Iemmc8ss_16ffc_main_0_emmcs)"]
[6647,2880,7.0000000000000001E-3,"Idmss_csi_am67_main_0\\/I_bcdma\\/I_rwu1","(dmss_csi_am67_bcdma_rwu1)",null,null,null,3449,2267,5.0000000000000001E-3,"I_main_RT_cfg_cbass_main_0\\/I_Ik3_dss_ul_main_0_vbusp_cfg_p2p_bridge","(am67_main_RT_cfg_cbass_Ik3_dss_ul_main_0_vbusp_cfg)"]
[6620,2871,7.0000000000000001E-3,"Idmss_csi_am67_main_0\\/I_bcdma\\/I_rwu0","(dmss_csi_am67_bcdma_rwu0)",null,null,null,3183,2121,5.0000000000000001E-3,"I_main_RT_cfg_cbass_main_0\\/I_Ik3_dss_ul_main_1_vbusp_cfg_p2p_bridge","(am67_main_RT_cfg_cbass_Ik3_dss_ul_main_1_vbusp_cfg)"]
[5939,2609,6.0000000000000001E-3,"Idmss_csi_am67_main_0\\/I_bcdma\\/I_tru1","(dmss_csi_am67_bcdma_tru1)",null,null,null,2794,2075,5.0000000000000001E-3,"I_main_data_cbass_main_0\\/I_cbass_default_mmrs","(am67_main_RT_data_cbass_cbass_default_mmrs)"]
[5950,2607,6.0000000000000001E-3,"Idmss_csi_am67_main_0\\/I_bcdma\\/I_tru2","(dmss_csi_am67_bcdma_tru2)",null,null,null,2849,2018,5.0000000000000001E-3,"I_main_RT_cfg_cbass_main_0\\/I_Iusb2ss_16ffc_main_0_core_vbusp_p2p_bridge","(am67_main_RT_cfg_cbass_Iusb2ss_16ffc_main_0_core_v)"]
[5522,2586,6.0000000000000001E-3,"Idmss_csi_am67_main_0\\/I_bcdma\\/I_tru0","(dmss_csi_am67_bcdma_tru0)",null,null,null,2711,1905,4.0000000000000001E-3,"I_main_RT_cfg_cbass_main_0\\/I_Iusb2ss_16ffc_main_0_usb2_vbusp_p2p_bridge","(am67_main_RT_cfg_cbass_Iusb2ss_16ffc_main_0_usb2_v)"]
[2752,1167,3.0000000000000001E-3,"Imdp","(sam67_main_rt_mdp_wrap)",null,null,null,2599,1857,4.0000000000000001E-3,"I_main_RT_cfg_cbass_main_0\\/I_Iwiz16b8m4cdt3_main_0_slv_p2p_bridge","(am67_main_RT_cfg_cbass_Iwiz16b8m4cdt3_main_0_slv_p)"]
[490,184,0,"Idivh_pll_ctrl_clk4_clk\\/Ikp_ti_ipg_clk_divhdist5","(kp_ti_ipg_clk_divhdist5_2)",null,null,null,2573,1833,4.0000000000000001E-3,"I_main_RT_cfg_cbass_main_0\\/I_Ik3_pbist_8c28p_4bit_wrap_main_1_cfg_p2p_bridge","(am67_main_RT_cfg_cbass_Ik3_pbist_8c28p_4bit_wrap_m)"]
[490,184,0,"Idivh_pll_ctrl_clk2_clk\\/Ikp_ti_ipg_clk_divhdist5","(kp_ti_ipg_clk_divhdist5_1)",null,null,null,2562,1828,4.0000000000000001E-3,"I_main_RT_cfg_cbass_main_0\\/I_IK3_DPHY_RX_main_0_vbusp_p2p_bridge","(am67_main_RT_cfg_cbass_IK3_DPHY_RX_main_0_vbusp_p2)"]
[490,184,0,"Idivh_pll_ctrl_clk1_clk\\/Ikp_ti_ipg_clk_divhdist5","(kp_ti_ipg_clk_divhdist5)",null,null,null,2568,1825,4.0000000000000001E-3,"I_main_RT_cfg_cbass_main_0\\/I_IK3_DPHY_RX_main_3_vbusp_p2p_bridge","(am67_main_RT_cfg_cbass_IK3_DPHY_RX_main_3_vbusp_p2)"]
[488,183,0,"Idivh_pll_vpac_clk1_clk\\/Ikp_ti_ipg_clk_divhdist5","(kp_ti_ipg_clk_divhdist5_3)",null,null,null,2567,1823,4.0000000000000001E-3,"I_main_RT_cfg_cbass_main_0\\/I_IK3_DPHY_RX_main_1_vbusp_p2p_bridge","(am67_main_RT_cfg_cbass_IK3_DPHY_RX_main_1_vbusp_p2)"]
[492,183,0,"Idivh_main_pll1_hsdiv4_clkout_clk1_clk\\/Ikp_ti_ipg_clk_divhdist5","(kp_ti_ipg_clk_divhdist5_4)",null,null,null,2560,1823,4.0000000000000001E-3,"I_main_RT_cfg_cbass_main_0\\/I_IK3_DPHY_RX_main_2_vbusp_p2p_bridge","(am67_main_RT_cfg_cbass_IK3_DPHY_RX_main_2_vbusp_p2)"]
[15,14,0,"Isam67_main_rt_wrap_pbist_test_wrap\\/Imdp\\/sam67_main_rt_wrap_pbist_test_wrap_core_7_inst\\/Cgated_vp_clk_cgate_0","(kp_ti_ipg_clk_s1c1fps_26)",null,null,null,2328,1652,4.0000000000000001E-3,"I_main_RT_cfg_cbass_main_0\\/I_Idmss_csi_am67_main_0_eccaggr_cfg_p2p_bridge","(am67_main_RT_cfg_cbass_Idmss_csi_am67_main_0_eccag)"]
[15,14,0,"Isam67_main_rt_wrap_pbist_test_wrap\\/Imdp\\/sam67_main_rt_wrap_pbist_test_wrap_core_13_inst\\/Cgated_clk2_clk_cgate_0","(kp_ti_ipg_clk_s1c1fps_19)",null,null,null,2327,1640,4.0000000000000001E-3,"I_main_RT_cfg_cbass_main_0\\/I_Idmss_csi_am67_main_0_psilcfg_cfg_p2p_bridge","(am67_main_RT_cfg_cbass_Idmss_csi_am67_main_0_psilc)"]
[15,14,0,"Idmss_csi_am67_main_0\\/Cvd2clk","(kp_ti_ipg_clk_s1c1fps)",null,null,null,2254,1586,4.0000000000000001E-3,"I_main_RT_cfg_cbass_main_0\\/I_Idmss_csi_am67_main_0_psilss_cfg_p2p_bridge","(am67_main_RT_cfg_cbass_Idmss_csi_am67_main_0_psils)"]
[15,14,0,"Isam67_main_rt_wrap_pbist_test_wrap\\/Ik3_pbist_32kx32_rom_wrap_16ffc\\/Ik3_pbist_32kx32_irom_mdp\\/Cgated_clk4_clk_cgate_0","(kp_ti_ipg_clk_s1c1fps_7)",null,null,null,2254,1568,4.0000000000000001E-3,"I_main_RT_cfg_cbass_main_0\\/I_Iusb2ss_16ffc_main_1_core_vbusp_p2p_bridge","(am67_main_RT_cfg_cbass_Iusb2ss_16ffc_main_1_core_v)"]
[15,14,0,"Isam67_main_rt_wrap_pbist_test_wrap\\/Imdp\\/sam67_main_rt_wrap_pbist_test_wrap_level1_inst\\/Cgated_vp_clk_cgate_0","(kp_ti_ipg_clk_s1c1fps_13)",null,null,null,2259,1567,4.0000000000000001E-3,"I_main_RT_cfg_cbass_main_0\\/I_Iusb2ss_16ffc_main_1_usb2_vbusp_p2p_bridge","(am67_main_RT_cfg_cbass_Iusb2ss_16ffc_main_1_usb2_v)"]
[15,14,0,"Isam67_main_rt_wrap_pbist_test_wrap\\/Imdp\\/sam67_main_rt_wrap_pbist_test_wrap_core_11_inst\\/Cgated_vp_clk_cgate_0","(kp_ti_ipg_clk_s1c1fps_17)",null,null,null,618,445,1E-3,"I_main_data_cbass_main_0\\/I_Ik3_dss_ul_main_0_vbusm_dma_m2m_bridge\\/I_sfifo_wrap\\/I_sfifo","(am67_main_RT_data_cbass_Ik3_dss_ul_main_0_vbusm_dm)"]
[15,14,0,"Isam67_main_rt_wrap_pbist_test_wrap\\/Imdp\\/sam67_main_rt_wrap_pbist_test_wrap_core_8_inst\\/Cgated_clk1_clk_cgate_0","(kp_ti_ipg_clk_s1c1fps_27)",null,null,null,610,444,1E-3,"I_main_data_cbass_main_0\\/I_Ik3_dss_ul_main_1_vbusm_dma_m2m_bridge\\/I_sfifo_wrap\\/I_sfifo","(am67_main_RT_data_cbass_Ik3_dss_ul_main_1_vbusm_dm)"]
[15,14,0,"Isam67_main_rt_wrap_pbist_test_wrap\\/Imdp\\/sam67_main_rt_wrap_pbist_test_wrap_core_6_inst\\/Cgated_clk1_clk_cgate_0","(kp_ti_ipg_clk_s1c1fps_25)",null,null,null,848,437,1E-3,"I_main_RT_cfg_cbass_main_0\\/I_Iusb2ss_16ffc_main_1_mstr0_m2m_bridge","(am67_main_RT_cfg_cbass_Iusb2ss_16ffc_main_1_mstr0_)"]
[15,14,0,"Isam67_main_rt_wrap_pbist_test_wrap\\/Imdp\\/sam67_main_rt_wrap_pbist_test_wrap_core_2_inst\\/Cgated_dss_clk_cgate_0","(kp_ti_ipg_clk_s1c1fps_21)",null,null,null,368,258,1E-3,"I_main_data_cbass_main_0\\/I_Idmss_csi_am67_main_0_bcdma_memw_m2m_bridge\\/I_sfifo_wrap\\/I_sfifo","(am67_main_RT_data_cbass_Idmss_csi_am67_main_0_bcdm)"]
[15,14,0,"Isam67_main_rt_wrap_pbist_test_wrap\\/Imdp\\/sam67_main_rt_wrap_pbist_test_wrap_level1_inst\\/Cgated_dss_clk_cgate_0","(kp_ti_ipg_clk_s1c1fps_11)",null,null,null,225,139,0,"I_main_data_cbass_main_0\\/I_Idmss_csi_am67_main_0_bcdma_memw_m2m_bridge\\/I_cfifo_epri","(am67_main_RT_data_cbass_Idmss_csi_am67_main_0_bcdm)"]
[15,14,0,"Isam67_main_rt_wrap_pbist_test_wrap\\/Imdp\\/sam67_main_rt_wrap_pbist_test_wrap_core_1_inst\\/Cgated_clk1_clk_cgate_0","(kp_ti_ipg_clk_s1c1fps_20)",null,null,null,15,14,0,"Iclk_pwr_ipg_main_sysclk0_div2_clk","(kp_ti_ipg_clk_s1c1fps_2)"]
[15,14,0,"Isam67_main_rt_wrap_pbist_test_wrap\\/Imdp\\/sam67_main_rt_wrap_pbist_test_wrap_level1_inst\\/Cgated_clk1_clk_cgate_0","(kp_ti_ipg_clk_s1c1fps_10)",null,null,null,15,14,0,"Iclk_pwr_ipg_dss_fclk_1_clk","(kp_ti_ipg_clk_s1c1fps_4)"]
[15,14,0,"Isam67_main_rt_wrap_pbist_test_wrap\\/Imdp\\/sam67_main_rt_wrap_pbist_test_wrap_core_12_inst\\/Cgated_clk1_clk_cgate_0","(kp_ti_ipg_clk_s1c1fps_18)",null,null,null,15,14,0,"Iclk_pwr_ipg_main_sysclk0_div1_clk","(kp_ti_ipg_clk_s1c1fps_3)"]
[15,14,0,"Isam67_main_rt_wrap_pbist_test_wrap\\/Imdp\\/sam67_main_rt_wrap_pbist_test_wrap_core_9_inst\\/Cgated_vp_clk_cgate_0","(kp_ti_ipg_clk_s1c1fps_15)",null,null,null,15,14,0,"Iclk_pwr_ipg_main_sysclk0_div4_clk","(kp_ti_ipg_clk_s1c1fps_1)"]
[15,14,0,"Isam67_main_rt_wrap_pbist_test_wrap\\/Imdp\\/sam67_main_rt_wrap_pbist_test_wrap_level1_inst\\/Cgated_clk2_clk_cgate_0","(kp_ti_ipg_clk_s1c1fps_12)",null,null,null,4,2,0,"Ipwr_aggr_clkstop","(kp_ti_ipg_pwrclkstop_1)"]
[15,14,0,"Isam67_main_rt_wrap_pbist_test_wrap\\/Imdp\\/sam67_main_rt_wrap_pbist_test_wrap_core_10_inst\\/Cgated_clk1_clk_cgate_0","(kp_ti_ipg_clk_s1c1fps_16)"]
[15,14,0,"Isam67_main_rt_wrap_pbist_test_wrap\\/Imdp\\/sam67_main_rt_wrap_pbist_test_wrap_core_4_inst\\/Cgated_clk1_clk_cgate_0","(kp_ti_ipg_clk_s1c1fps_23)"]
[15,14,0,"Isam67_main_rt_wrap_pbist_test_wrap\\/Ik3_pbist_32kx32_rom_wrap_16ffc\\/Iclk4_gclk","(kp_ti_ipg_clk_s1c1fps_8)"]
[15,14,0,"Isam67_main_rt_wrap_pbist_test_wrap\\/Imdp\\/sam67_main_rt_wrap_pbist_test_wrap_core_0_inst\\/Cgated_clk8_clk_cgate_0","(kp_ti_ipg_clk_s1c1fps_14)"]
[15,14,0,"Isam67_main_rt_wrap_pbist_test_wrap\\/Imdp\\/sam67_main_rt_wrap_pbist_test_wrap_core_3_inst\\/Cgated_clk2_clk_cgate_0","(kp_ti_ipg_clk_s1c1fps_22)"]
[15,14,0,"Isam67_main_rt_wrap_pbist_test_wrap\\/Imdp\\/sam67_main_rt_wrap_pbist_test_wrap_core_5_inst\\/Cgated_vp_clk_cgate_0","(kp_ti_ipg_clk_s1c1fps_24)"]
[15,14,0,"Isam67_main_rt_wrap_pbist_test_wrap\\/Imdp\\/sam67_main_rt_wrap_pbist_test_wrap_level1_inst\\/Cgated_clk8_clk_cgate_0","(kp_ti_ipg_clk_s1c1fps_9)"]
[6,7,0,"Idmss_csi_am67_main_0\\/I_clkenack","(kp_ti_ipg_clkenack_aggr_v2)"]
[4,2,0,"Idmss_csi_am67_main_0\\/I_clkstop","(kp_ti_ipg_pwrclkstop)"]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
[]
["Filtered attributes to:"]
["vdd_dyn_idle"]
["vdd_dyn_int_trk"]
["vdd_dyn_max"]
["vdd_dyn_peak"]
["vdd_dyn_sw_trk"]
["vdd_lkg"]
["vddr_lkg"]
["vdd_dyn"]
["vddh1_dyn"]
["vddh1_lkg"]
["vddh2_dyn"]
["vdda_dyn"]
["vdda_lkg"]
["vddh2_lkg"]
[]
[]
["PLLs"]
["MCU_PLL0","MCU_R5FSS"]
["MAIN_PLL0"]
["MAIN_PLL1"]
["MAIN_PLL2"]
["MAIN_PLL5","VPAC / DMPAC"]
["MAIN_PLL6","GPU"]
["MAIN_PLL7","C7x"]
["MAIN_PLL8","A63"]
["MAIN_PLL12","DDR"]
["MAIN_PLL15","WKUP_R5FSS / SMS"]
["MAIN_PLL16","DSS"]
["MAIN_PLL17"]
["MAIN_PLL18"]
[]
[]
["PD_HSM is removed (replaced by GP_Core_CTL for blocks mcu_wrap, sec_wrap, ip_wrap, rt_wrap); it does not correlate to any design PD block."]
[]
["A12:B12 reseved for later low power modes if necessary"]
[]
["From J7ES TRM: The WKUP_I2C0, MCU_I2C0, I2C0, and I2C1 controllers have dedicated I2C compliant open drain buffers and support high speed mode (up to 3.4 Mbps in 1.8 V mode and up to 400 Kbps in 3.3 V mode). The MCU_I2C1, I2C2, I2C3, I2C4, I2C5, and I2C6 controllers are multiplexed with standard LVCMOS I/O, connected to emulate open drain, and support fast mode (up to 400 Kbps in 1.8 V/3.3 V mode). The I2C emulation is achieved by configuring the LVCMOS buffers to output Hi-Z instead of driving high when transmitting logic 1."]
["I2C OD adds 3.4 Mbps in 1.8V mode to the maximum 400 Kbps in 3.3V / 1.8V mode"]
[]
["CR Notes","Updated scaling factor of main IP and RT infra as power consumption was very high and caused scaling to break across dhrystone. "]

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[null,"Max Freq",null,null,null,null,"Pull-down menus",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"PD_State_Table",null,null,"pwr_scale_table",null,null,"Margining",null,"Caution:","This power estimation spreadsheet is subject to change. SoC power estimates provide approximate power and current consumption based on measured and simulated data; they are provided “as is” and are not guaranteed within a specified precision. Power consumption depends on electrical parameters, silicon process variations, environmental conditions, and uses cases running on the processor during operation. Actual power consumption should be verified in the real system. An end product’s SoC power, PDN integrity & thermal performance can vary depending on final use cases, features supported, software characteristics and system thermal design.  ",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"Use Case",{"$f":"'Use Case'!D3","v":"UC1 0.75V Automotive Cluster"},{"$f":"MATCH(CB1,DF2:FAW2,0)+COLUMN(DE1)","v":118},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,100,101,24,25,14,15,20,21,22,23]
["MAIN SMS 0 Frequency [MHz]",400,null,null,null,null,"ddr32_3733_ios_modes","sd0805_lane_modes","sd0901_rx4_modes","sd0901_tx4_modes","emmc51phy_top_modes","PRWDWUWSWEWCDGSDIO_modes","sd1000_modes","canfd_modes","dpi_modes","ecap_modes","eqep_modes","epwm_modes","ethernet_modes","gpmc_modes","gpio_modes","i2c_modes","uart_modes","mcasp_modes","fssul_modes","spi_modes","LVDSTS16LLBI1E_modes","Voltages","Temperatures","Processes","pcie_modes","usb3_modes",null,"Power Domain","Status",null,"Voltage Domain","VDD_CORE",null,0.2,null,{"$f":"\"Conditions: \"&Process&\" Process\"","v":"Conditions: Strong Process"},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"'Use Case'!B14","v":"Add Test Name"},null,null,null,null,null,null,null,"Index1",null,"Index","Template for pre-populating a use case",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"Use Case Column Index","Use Case Name","Use Cases","Instance","QTY","ARM only (thermal)",null,"UC2 Industrial HMI","UC2 Industrial HMI UC Mode or Frequency","Idle","Idle UC Mode or Frequency","UC1 Automotive Cluster","UC1 Automotive Cluster UC Mode or Frequency","UC1 0.75V Automotive Cluster","UC1 0.75V Automotive Cluster UC Mode or Frequency"]
["Domain Manager (WKUP) R5FSS 0 Frequency [MHz]",800,null,null,null,null,"sleep","disable","ulps","ulps","off","unused","suspend","unused","unused","unused","unused","unused","unused","unused","unused","unused","unused","unused","unused","unused","unused",0,-55,"strong","disable","suspend",null,"PD_Pulsar_MCU",{"$f":"IF(SUMIF(PWRCALC!$J$4:$J$171,AH3,PWRCALC!$S$4:$S$171)=0,\"OFF\",\"ON\")","v":"ON"},null,"vddr_lkg",{"$f":"VLOOKUP(\"s20_\"&Process&\"_\"&VDDAR_Core&\"_\"&Tj&\"C\",POWER_SCALING,2,0)*(1+Margining)","v":{"$error":"#N/A"}},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"DC3","v":"Tj"},null,null,{"$f":"Tj","v":150},null,null,null,null,null,null,{"$f":"INDIRECT(ADDRESS(BX3,107))","v":{"$error":"#VALUE!"}},null,null,3,"Tj",{"$f":"INDIRECT(ADDRESS(BZ3,CC$1))","v":125},"C",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"COLUMN(DF1)","v":110},{"$f":"INDIRECT(ADDRESS(2,DA3))","v":"ARM only (thermal)"},"Tj",null,null,125,0,125,0,125,0,125,0,125,0]
["MAIN R5FSS 1 Frequency [MHz]",800,null,null,null,null,"deep_sleep","1g","1p5g4l","1p5g4l","sdr_25mbs","hs200_200mbs","device_fs","250kbs_1p8v","2K_|_2048x1080x60_fps_24b_|_3p3V","capture_in_1m_1p8v","on_1p8v","on_1p8v","rmii_10_3p3v","16b_80_MHz_1p8V","1mbs_1p8v_20pf","i2c_100k_3p3v","112k_3p3v","2Ch_RXTX_48_ksps_24b_1p8v","ospi_sdr_controller_108_3p3v","Peripheral_2.083_Mbaud_1p8v","oldi_single_18b_modes",0.63,-40,"nominal","3g","5g",null,"GP_Core_CTL","ON",null,"vdd_lkg (ulvt20)",{"$f":"VLOOKUP(\"u20_\"&Process&\"_\"&VDD_Core&\"_\"&Tj&\"C\",POWER_SCALING,2,0)*(1+Margining)","v":{"$error":"#N/A"}},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"VDD_CORE_SRAM_Voltage",null,null,{"$f":"VDDAR_Core","v":0.85},null,null,null,null,null,null,{"$f":"INDIRECT(ADDRESS(BX4,107))","v":{"$error":"#VALUE!"}},null,null,4,"SRAM_Voltage",{"$f":"INDIRECT(ADDRESS(BZ4,CC$1))","v":0.85},"V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"2+DA3","v":112},{"$f":"INDIRECT(ADDRESS(2,DA4))","v":"UC2 Industrial HMI"},"VDD_CORE_SRAM_Voltage",null,null,0.85,0,0.85,0,0.85,0,0.85,0,0.85,0]
["MCU R5FSS 0 Frequency [MHz]",800,null,null,null,null,"lpddr4_4000_32","3g","2p5g4l","2p5g4l","sdr_50mbs","ddr_100mbs","device_hs","1mbs_1p8v","2K_|_2048x1080x60_fps_24b_|_1p8V","capture_in_5m_1p8v","on_3p3v","on_3p3v","rmii_100_3p3v","16b_100_MHz_1p8V","1mbs_3p3v_20pf","i2c_400k_3p3v","1m_3p3v","4Ch_RXTX_48_ksps_24b_1p8v","ospi_sdr_controller_133_3p3v","Peripheral_2.083_Mbaud_1p8v","oldi_single_24b_modes",0.67500000000000004,-20,"weak","5g","device_fs",null,"PD_A53_0",{"$f":"IF(SUMIF(PWRCALC!$J$4:$J$171,AH5,PWRCALC!$S$4:$S$171)=0,\"OFF\",\"ON\")","v":"ON"},null,"vdd_int (ulvt20)",{"$f":"VLOOKUP(\"u20_strong\"&\"_\"&VDD_Core&\"_125C\",POWER_SCALING,3,0)","v":{"$error":"#N/A"}},null,"UC_Name:",{"$f":"'Use Case'!B14","v":"Add Test Name"},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"VDD_CORE_Voltage",null,null,{"$f":"VDD_Core","v":0.75},null,null,null,null,null,null,{"$error":"#VALUE!"},null,null,5,"CORE_Voltage",0.75,"V",null,"Processor Core Utilization (%)",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"2+DA4","v":114},"Idle","VDD_CORE_Voltage",null,null,0.75,0,0.75,0,0.75,0,0.85,0,0.75,0]
["MAIN A53SS Frequency [MHz]",1250,null,null,null,null,"lpddr4_3733_32","5g",null,null,"ddr_100mbs","sdr_50mbs","device_ls","5mbs_1p8v","2K_|_2048x1080x60_fps_18b_|_3p3V","capture_in_1m_3p3v",null,null,"rgmii_10_3p3v","16b_133_MHz_1p8V",null,"i2c_100k_1p8v","3p6m_3p3v","8Ch_RXTX_48_ksps_24b_1p8v","ospi_ddr_controller_133_3p3v","Peripheral_3.125_Mbaud_1p8v","oldi_dual_18b_modes",0.7,0,null,"8g","device_hs",null,"PD_A53_1",{"$f":"IF(SUMIF(PWRCALC!$J$4:$J$171,AH6,PWRCALC!$S$4:$S$171)=0,\"OFF\",\"ON\")","v":"ON"},null,"vdd_lkg (ulvt16)",{"$f":"VLOOKUP(\"u16_\"&Process&\"_\"&VDD_Core&\"_\"&Tj&\"C\",POWER_SCALING,2,0)*(1+Margining)","v":{"$error":"#N/A"}},null,"UC_Description:",{"$f":"'Use Case'!B13","v":"Add Test Description"},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"Leakage_Margin",null,null,{"$f":"Margining","v":0.2},null,null,null,null,null,null,"HSM AM67",66,null,7,"Process_Corner","Strong",null,null,"MAIN SMS 0",{"$f":"INDIRECT(ADDRESS(BX6,CC$1))","v":0.05},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,116,"UC1 Automotive Cluster","Leakage_Margin",null,null,0.2,0,0.2,0,0.2,0,0.2,0,0.2,0]
["MAIN C71SS 0 and 1 Frequency [MHz]",912.5,null,null,null,null,"lpddr4_3467_32","8g",null,null,"sdr_100mbs","sdr_25mbs","device_hs_idle","8mbs_1p8v","2K_|_2048x1080x60_fps_18b_|_1p8V","capture_in_5m_3p3v",null,null,"rgmii_100_3p3v","16b_80_MHz_3p3V",null,"i2c_400k_1p8v","112k_1p8v","12Ch_RXTX_48_ksps_24b_1p8v","ospi_ddr_controller_160_3p3v","Peripheral_6.25_Mbaud_1p8v","oldi_dual_24b_modes",0.72,25,null,null,"device_ls",null,"PD_A53_2",{"$f":"IF(SUMIF(PWRCALC!$J$4:$J$171,AH7,PWRCALC!$S$4:$S$171)=0,\"OFF\",\"ON\")","v":"ON"},null,"vdd_int (ulvt16)",{"$f":"VLOOKUP(\"u16_strong_\"&VDD_Core&\"_125C\",POWER_SCALING,3,0)","v":{"$error":"#N/A"}},null,"Based on Loaded Use Case:",{"$f":"'Use Case'!D3","v":"UC1 0.75V Automotive Cluster"},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"Process_Corner",null,null,{"$f":"Process","v":"Strong"},null,null,null,null,null,null,"Pulsar UL (DM) AM67",13,null,166,"OPP","high",null,null,"MAIN (WKUP) R5FSS 0",0.25,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,118,"UC1 0.75V Automotive Cluster","Process_Corner",null,null,"strong",0,"Strong",0,"strong",0,"Strong",0,"Strong",0]
["MAIN VPAC 0 Frequency [MHz]",600,null,null,null,null,"lpddr4_3200_32","10g",null,null,"ddr_200mbs",null,"device_fs_idle","12mbs_1p8v","2K_|_2048x1080x30_fps_24b_|_3p3V","pwm_out_1m_1p8v",null,null,"rgmii_1000_3p3v","16b_100_MHz_3p3V",null,"i2c_1m_1p8v","1m_1p8v","16Ch_RXTX_48ksps_24b_1p8v","qspi_sdr_controller_108_3p3v","Peripheral_12.5_Mbaud_1p8v",null,0.74,50,null,null,"device_hs_idle",null,"PD_A53_3",{"$f":"IF(SUMIF(PWRCALC!$J$4:$J$171,AH8,PWRCALC!$S$4:$S$171)=0,\"OFF\",\"ON\")","v":"ON"},null,"vdd_lkg (lvt20)",{"$f":"VLOOKUP(\"l20_\"&Process&\"_\"&VDD_Core&\"_\"&Tj&\"C\",POWER_SCALING,2,0)*(1+Margining)","v":{"$error":"#N/A"}},null,"Internal Reference Date:","2023-09-12",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"uc_source",null,null,null,null,null,null,null,null,null,"Pulsar ULS",14,null,null,null,null,null,null,"MAIN R5FSS 2",{"$f":"IFERROR(INDIRECT(ADDRESS(BX8,CC$1))*1,0)","v":0},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,120,0,"uc_source",null,null,"J Wang",0,"K.Shin",0,"P Carson",0,"K.Shin",0,"K.Shin",0]
["MAIN DMPAC 0 Frequency [MHz]",428,null,null,null,null,"lpddr4_2933_32",null,null,null,"hs200",null,"device_ls_idle","250kbs_3p3v","2K_|_2048x1080x30_fps_24b_|_1p8V","pwm_out_5m_1p8v",null,null,"rmii_10_1p8v","16b_133_MHz_3p3V",null,"i2c_3p4m_1p8v","3p6m_1p8v","2Ch_TX_48_ksps_24b_1p8v","qspi_sdr_controller_133_3p3v","Peripheral_25_Mbaud_1p8v",null,0.75,75,null,null,"device_fs_idle",null,"PD_A53_Cluster_0",{"$f":"IF(SUMIF(PWRCALC!$J$4:$J$171,AH9,PWRCALC!$S$4:$S$171)=0,\"OFF\",\"ON\")","v":"ON"},null,"vdd_int (lvt20)",{"$f":"VLOOKUP(\"l20_strong_\"&VDD_Core&\"_125C\",POWER_SCALING,3,0)","v":{"$error":"#N/A"}},null,"Internal Reference Revision:",2.1,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"UC_Description",null,null,{"$f":"'Use Case'!B13","v":"Add Test Description"},null,null,null,null,null,null,"A53 CPU 1.4 GHz AM62",16,null,9,"UC_Description","Paul",null,null,"MAIN A53SS 0: 0",0.8,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,122,0,"UC_Description",null,null,0,0,"SRD 0.8.2",0,"Idle",0,"SRD 0.8.2",0,"Paul",0]
["MAIN GPU 0 Frequency [MHz]",720,null,null,null,null,"lpddr4_2667_32",null,null,null,"hs400",null,"host_fs","1mbs_3p3v","2K_|_2048x1080x30_fps_18b_|_3p3V","pwm_out_1m_3p3v",null,null,"rmii_100_1p8v",null,null,null,null,"4Ch_TX_48_ksps_24b_1p8v","qspi_ddr_controller_133_3p3v","Controller_1.563_Mbaud_1p8v",null,0.76,80,null,null,"device_ls_idle",null,"PD_DSS",{"$f":"IF(SUMIF(PWRCALC!$J$4:$J$171,AH10,PWRCALC!$S$4:$S$171)=0,\"OFF\",\"ON\")","v":"ON"},null,"vdd_lkg (lvt16)",{"$f":"VLOOKUP(\"l16_\"&Process&\"_\"&VDD_Core&\"_\"&Tj&\"C\",POWER_SCALING,2,0)*(1+Margining)","v":{"$error":"#N/A"}},null,"Date:",{"$f":"NOW()","v":"2025-05-26T10:41:42.490"},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"'Use Case'!B11","v":"high"},null,null,null,null,null,null,"A53 CPU 1.4 GHz AM62",17,null,2,"UC_Name","UC1 0.75V Automotive Cluster",null,null,"MAIN A53SS 0: 1",0.8,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,124,0,"UC_Target_mW",null,null,0,0,"3W",0,"TBD",0,"4W",0,"4W",0]
["MAIN Video Encoder/Decoder 0 Frequency [MHz]",500,null,null,null,null,"lpddr4_2400_32",null,null,null,null,null,"host_hs","5mbs_3p3v","2K_|_2048x1080x30_fps_18b_|_1p8V","pwm_out_5m_3p3v",null,null,"rgmii_10_1p8v",null,null,null,null,"8Ch_TX_48_ksps_24b_1p8v","qspi_ddr_controller_160_3p3v","Controller_2.083_Mbaud_1p8v",null,0.76500000000000001,85,null,null,"host_fs",null,"PD_GPU",{"$f":"IF(SUMIF(PWRCALC!$J$4:$J$171,AH11,PWRCALC!$S$4:$S$171)=0,\"OFF\",\"ON\")","v":"ON"},null,"vdd_int (lvt16)",{"$f":"VLOOKUP(\"l16_strong_\"&VDD_Core&\"_125C\",POWER_SCALING,3,0)","v":{"$error":"#N/A"}},null,"Tool Revision / Date",{"$f":"INDIRECT(ADDRESS('revision History'!E1-1,2,,,\"revision History\"))","v":1.1000000000000001},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"NOW()","v":"2025-05-26T10:41:42.490"},null,null,null,null,null,null,"A53 CPU 1.4 GHz AM62",18,null,null,null,null,null,null,"MAIN A53SS 0: 2",0.8,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,126,0,"UC_Update",null,null,45245,0,44780,0,44839,0,44832,0,44832,0]
["MAIN JPEG Encoder 0 Frequency [MHz]",250,null,null,null,null,"lpddr4_2133_32",null,null,null,null,null,"host_ls","8mbs_3p3v","Full_HD_|_1920x1080x60_fps_24b_|_3p3V",null,null,null,"rgmii_100_1p8v",null,null,null,null,"12Ch_TX_48_ksps_24b_1p8v",null,"Controller_3.125_Mbaud_1p8v",null,0.77,90,null,null,"host_hs",null,"PD_CPSW",{"$f":"IF(SUMIF(PWRCALC!$J$4:$J$171,AH12,PWRCALC!$S$4:$S$171)=0,\"OFF\",\"ON\")","v":"ON"},null,"vdd_lkg (svt20)",{"$f":"VLOOKUP(\"s20_\"&Process&\"_\"&VDD_Core&\"_\"&Tj&\"C\",POWER_SCALING,2,0)*(1+Margining)","v":{"$error":"#N/A"}},null,null,{"$f":"MID(CELL(\"filename\",A1),FIND(\"[\",CELL(\"filename\",A1))+1,FIND(\"]\",CELL(\"filename\",A1))-FIND(\"[\",CELL(\"filename\",A1))-1)","v":"Power Estimation Tool Sitara 2.0.xlsm"},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"sam62a_mcu_pulsar_ul_wrap_0",{"$f":"_xlfn.IFNA(MATCH(BN12,PWRCALC!AS:AS,0),0)","v":4},{"$f":"IFERROR(INDIRECT(ADDRESS($BO12,COLUMN(S$1),,,\"PWRCALC\")),0)","v":1},{"$f":"IFERROR(INDIRECT(ADDRESS($BO12,COLUMN(R$1),,,\"PWRCALC\")),0)","v":800},null,null,null,null,null,"A53 CPU 1.4 GHz AM62",19,null,null,"Key IP Frequency selection",null,"Frequency [MHz]",null,"MAIN A53SS 0: 3",0.8,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,128,0,"Pulsar ULS","_0",1,0.25,800,0.25,800,0.01,0,0.25,800,0.25,800]
["LPDDR4 EMIF 0 [MT/s]",3733,null,null,null,null,"lpddr4_1867_32",null,null,null,null,null,"host_hs_idle","12mbs_3p3v","Full_HD_|_1920x1080x60_fps_24b_|_1p8V",null,null,null,"rgmii_1000_1p8v",null,null,null,null,"16Ch_TX_48_ksps_24b_1p8v",null,"Controller_6.25_Mbaud_1p8v",null,0.8,95,null,null,"host_ls",null,"PD_ENCODE",{"$f":"IF(SUMIF(PWRCALC!$J$4:$J$171,AH13,PWRCALC!$S$4:$S$171)=0,\"OFF\",\"ON\")","v":"ON"},null,"vdd_int (svt20)",{"$f":"VLOOKUP(\"s20_strong_\"&VDD_Core&\"_125C\",POWER_SCALING,3,0)","v":{"$error":"#N/A"}},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"sam67_dm_wrap_0",{"$f":"_xlfn.IFNA(MATCH(BN13,PWRCALC!AS:AS,0),0)","v":5},{"$f":"IFERROR(INDIRECT(ADDRESS($BO13,COLUMN(S$1),,,\"PWRCALC\")),0)","v":1},{"$f":"IFERROR(INDIRECT(ADDRESS($BO13,COLUMN(R$1),,,\"PWRCALC\")),0)","v":800},null,null,null,null,null,"C7xV-256 1M 4T",23,null,66,"MAIN PLL 15 HSDIV 0","MAIN SMS 0 Frequency [MHz]",{"$f":"IF(INDIRECT(ADDRESS(BZ13,CC$1+1))=0,IF(CB$7=\"high\",400,133),INDIRECT(ADDRESS(BZ13,CC$1+1)))","v":400},null,"MAIN C71SS 0: C71x",{"$f":"IFERROR((INDIRECT(ADDRESS(BX13,CC$1))-CF14*0.8)/0.66*1,0)","v":0},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,130,0,"Pulsar UL (DM) AM67","_0",1,0.25,800,0.25,800,0.01,0,0.25,800,0.25,800]
["MCU SS / WKUP Modules CLK [MHz] (MCU SYSCLK)",400,null,null,null,null,"lpddr4_1600_32",null,null,null,null,null,"host_fs_idle",null,"Full_HD_|_1920x1080x60_fps_18b_|_3p3V",null,null,null,null,null,null,null,null,"2Ch_RX_48_ksps_24b_1p8v",null,"Controller_12.5_Mbaud_1p8v",null,0.82499999999999996,100,null,null,"host_hs_idle",null,"PD_DDR",{"$f":"IF(SUMIF(PWRCALC!$J$4:$J$171,AH14,PWRCALC!$S$4:$S$171)=0,\"OFF\",\"ON\")","v":"ON"},null,"vdd_lkg (svt16)",{"$f":"VLOOKUP(\"s16_\"&Process&\"_\"&VDD_Core&\"_\"&Tj&\"C\",POWER_SCALING,2,0)*(1+Margining)","v":{"$error":"#N/A"}},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"_xlfn.IFNA(MATCH(BN14,PWRCALC!AS:AS,0),0)","v":0},0,0,null,null,null,null,null,"Double MMA256 subchip  inside C7xv256 subchip",24,null,13,"MAIN PLL 15 HSDIV 2\nMCU PLL 0 HSDIV 0","Domain Manager (WKUP) R5FSS 0 Frequency [MHz]",{"$f":"IFERROR(INDIRECT(ADDRESS(BZ14,CC$1+1))*1,0)","v":800},null,"MAIN C71SS 0: MMA",{"$f":"IFERROR(INDIRECT(ADDRESS(BX14,CC$1))*1,0)","v":0},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,132,0,"Pulsar ULS","_1",1,0,800,"","","","","","","",""]
["MAIN Modules CLK [MHz] (SYSCLK)",500,null,null,null,null,"lpddr4_1333_32",null,null,null,null,null,"host_ls_idle",null,"Full_HD_|_1920x1080x60_fps_18b_|_1p8V",null,null,null,null,null,null,null,null,"4Ch_RX_48_ksps_24b_1p8v",null,"Controller_25_Mbaud_1p8v",null,0.85,105,null,null,"host_fs_idle",null,"PD_Debug",{"$f":"IF(SUMIF(PWRCALC!$J$4:$J$171,AH15,PWRCALC!$S$4:$S$171)=0,\"OFF\",\"ON\")","v":"OFF"},null,"vdd_int (svt16)",{"$f":"VLOOKUP(\"s16_strong_\"&VDD_Core&\"_125C\",POWER_SCALING,3,0)","v":{"$error":"#N/A"}},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"sam62a_a53_512kb_wrap_0",{"$f":"_xlfn.IFNA(MATCH(BN15,PWRCALC!AS:AS,0),0)","v":7},1,1250,null,null,null,null,null,"C7xV-256 1M 4T",21,null,14,"MAIN PLL 15 HSDIV 3","MAIN R5FSS 1 Frequency [MHz]",{"$f":"IFERROR(INDIRECT(ADDRESS(BZ15,CC$1+1))*1,0)","v":0},null,"MAIN C71SS 1: C71x",{"$f":"IFERROR((INDIRECT(ADDRESS(BX15,CC$1))-CF16*0.8)/0.66*1,0)","v":0},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,134,0,"A53 Quad Cluster 1.4 GHz 512KB AM62A","_0",1,0.7,1250,0.8,1250,0.01,0,0.8,1400,0.8,1250]
["Device Manager Domain CLK [MHz]",400,null,null,null,null,"lpddr4_1067_32",null,null,null,null,null,null,null,"Full_HD_|_1920x1080x60_fps_16b_|_3p3V",null,null,null,null,null,null,null,null,"8Ch_RX_48_ksps_24b_1p8v",null,"Peripheral_2.083_Mbaud_3p3v",null,0.88,110,null,null,"host_ls_idle",null,"PD_HSM",{"$f":"IF(SUMIF(PWRCALC!$J$4:$J$171,AH16,PWRCALC!$S$4:$S$171)=0,\"OFF\",\"ON\")","v":"ON"},null,"vdd_sw",{"$f":"VDD_Core^2/0.88^2","v":0.72636880165289264},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"sam62_a53_dual_wrap_cba_cpu_phys_0",{"$f":"_xlfn.IFNA(MATCH(BN16,PWRCALC!AS:AS,0),0)","v":8},1,1250,null,null,null,null,null,"Double MMA256 subchip  inside C7xv256 subchip",22,null,12,"MCU PLL 0 HSDIV 3","MCU R5FSS 0 Frequency [MHz]",{"$f":"IFERROR(INDIRECT(ADDRESS(BZ16,CC$1+1))*1,0)","v":800},null,"MAIN C71SS 1: MMA",{"$f":"IFERROR(INDIRECT(ADDRESS(BX16,CC$1))*1,0)","v":0},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,136,0,"A53 CPU 1.4 GHz AM62","_0",1,0.7,1250,0.8,1250,0.01,0,0.8,1400,0.8,1250]
["HSM Domain CLK",400,null,null,null,null,"lpddr4_800_32",null,null,null,null,null,null,null,"Full_HD_|_1920x1080x60_fps_16b_|_1p8V",null,null,null,null,null,null,null,null,"2Ch_RXTX_48_ksps_24b_3p3v",null,"Peripheral_2.083_Mbaud_3p3v",null,0.93500000000000005,115,null,null,null,null,"GP_Core_CTL_MCU",{"$f":"IF(SUMIF(PWRCALC!$J$4:$J$171,AH17,PWRCALC!$S$4:$S$171)=0,\"OFF\",\"ON\")","v":"ON"},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"sam62_a53_dual_wrap_cba_cpu_phys_1",{"$f":"_xlfn.IFNA(MATCH(BN17,PWRCALC!AS:AS,0),0)","v":9},1,1250,null,null,null,null,null,"VPAC3L",28,null,16,"MAIN PLL 8 HSDIV0","MAIN A53SS Frequency [MHz]",1250,null,"MAIN VPAC 0",{"$f":"IFERROR(INDIRECT(ADDRESS(BX17,CC$1))*1,0)","v":0},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,138,0,"A53 CPU 1.4 GHz AM62","_1",1,0.7,1250,0.8,1250,0.01,0,0.8,1400,0.8,1250]
[null,null,null,null,null,null,"lpddr4_533_32",null,null,null,null,null,null,null,"Full_HD_|_1920x1080x60_fps_12b_|_3p3V",null,null,null,null,null,null,null,null,"4Ch_RXTX_48_ksps_24b_3p3v",null,"Peripheral_3.125_Mbaud_3p3v",null,1.1499999999999999,120,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"sam62_a53_dual_wrap_cba_cpu_phys_2",{"$f":"_xlfn.IFNA(MATCH(BN18,PWRCALC!AS:AS,0),0)","v":10},1,1250,null,null,null,null,null,"DMPAC J7AEP",29,null,22,"MAIN PLL 7 HSDIV 0","MAIN C71SS 0 and 1 Frequency [MHz]",0,null,"MAIN DMPAC 0",0,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,140,0,"A53 CPU 1.4 GHz AM62","_2",1,0.7,1250,0.8,1250,0.01,0,0.8,1400,0.8,1250]
[null,"Max Instances",null,null,null,null,"lpddr4_50_32",null,null,null,null,null,null,null,"Full_HD_|_1920x1080x60_fps_12b_|_1p8V",null,null,null,null,null,null,null,null,"8Ch_RXTX_48_ksps_24b_3p3v",null,"Peripheral_6.25_Mbaud_3p3v",null,null,125,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"sam62_a53_dual_wrap_cba_cpu_phys_3",{"$f":"_xlfn.IFNA(MATCH(BN19,PWRCALC!AS:AS,0),0)","v":11},1,1250,null,null,null,null,null,"GPU BXS4-64-256KB DUST AM67",25,null,28,"MAIN PLL 5 HSDIV 0","MAIN VPAC 0 Frequency [MHz]",{"$f":"IFERROR(INDIRECT(ADDRESS(BZ19,CC$1+1))*1,0)","v":0},null,"MAIN GPU 0",{"$f":"INDIRECT(ADDRESS(BX19,CC$1))","v":0.5},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,142,0,"A53 CPU 1.4 GHz AM62","_3",1,0.7,1250,0.8,1250,0.01,0,0.8,1400,0.8,1250]
["WKUP I2C",1,null,null,null,null,null,null,null,null,null,null,null,null,"Full_HD_|_1920x1080x30_fps_24b_|_3p3V",null,null,null,null,null,null,null,null,"12Ch_RXTX_48_ksps_24b_3p3v",null,"Peripheral_12.5_Mbaud_3p3v",null,null,130,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"sam67_dss_dsi_oldi_wrap_0",{"$f":"_xlfn.IFNA(MATCH(BN20,PWRCALC!AS:AS,0),0)","v":12},0.76,0,null,null,null,null,null,"WAVE521CL Video Codec AM62A",31,null,29,"MAIN PLL 5 HSDIV 2","MAIN DMPAC 0 Frequency [MHz]",0,null,"MAIN Video Encoder/Decoder 0",1,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,144,0,"Double DSS7UL + DSI + OLDI wrap","_0",1,0,0,2,0,0.01,0,2,0,2,0]
["WKUP UART",1,null,null,null,null,null,null,null,null,null,null,null,null,"Full_HD_|_1920x1080x30_fps_24b_|_1p8V",null,null,null,null,null,null,null,null,"16Ch_RXTX_48ksps_24b_3p3v",null,"Peripheral_25_Mbaud_3p3v",null,null,132,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"_xlfn.IFNA(MATCH(BN21,PWRCALC!AS:AS,0),0)","v":0},0,0,null,null,null,null,null,"Pulsar ULS",12,null,25,"MAIN PLL 6 HSDIV 0","MAIN GPU 0 Frequency [MHz]",{"$f":"IF(INDIRECT(ADDRESS(BZ21,CC$1+1))=0,IF(CB$5=0.85,800,720),INDIRECT(ADDRESS(BZ21,CC$1+1)))","v":720},null,"MCU R5FSS",0.25,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,146,0,"C7xV-256 1M 4T","_1",1,0,912.5,"","","","","","","",""]
["MCU I2C",1,null,null,null,null,null,null,null,null,null,null,null,null,"Full_HD_|_1920x1080x30_fps_18b_|_3p3V",null,null,null,null,null,null,null,null,"2Ch_TX_48_ksps_24b_3p3v",null,"Controller_1.563_Mbaud_3p3v",null,null,135,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"_xlfn.IFNA(MATCH(BN22,PWRCALC!AS:AS,0),0)","v":0},0,0,null,null,null,null,null,{"$error":"#VALUE!"},null,null,31,"MAIN PLL 2 HSDIV 4","MAIN Video Encoder/Decoder 0 Frequency [MHz]",100,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,148,0,"Double MMA256 subchip  inside C7xv256 subchip","_1",1,0,912.5,"","","","","","","",""]
["MCU UART",1,null,null,null,null,null,null,null,null,null,null,null,null,"Full_HD_|_1920x1080x30_fps_18b_|_1p8V",null,null,null,null,null,null,null,null,"4Ch_TX_48_ksps_24b_3p3v",null,"Controller_2.083_Mbaud_3p3v",null,null,140,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"_xlfn.IFNA(MATCH(BN23,PWRCALC!AS:AS,0),0)","v":0},0,0,null,null,null,null,null,{"$error":"#VALUE!"},null,null,null,"MAIN PLL 0 HSDIV 0 div 2","MAIN JPEG Encoder 0 Frequency [MHz]",{"$f":"CC26/2","v":250},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,150,0,"C7xV-256 1M 4T","_0",1,0,912.5,"","","","","","","",""]
["MCU McSPI",2,null,null,null,null,null,null,null,null,null,null,null,null,"Full_HD_|_1920x1080x30_fps_16b_|_3p3V",null,null,null,null,null,null,null,null,"8Ch_TX_48_ksps_24b_3p3v",null,"Controller_3.125_Mbaud_3p3v",null,null,145,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"_xlfn.IFNA(MATCH(BN24,PWRCALC!AS:AS,0),0)","v":0},0,0,null,null,null,null,null,{"$error":"#VALUE!"},null,null,47,"MAIN PLL 12 HSDIV0","LPDDR4 EMIF 0 [MT/s]",{"$f":"IFERROR(INDIRECT(ADDRESS(BZ24,CC$1+1))*4,0)","v":3733},null,"Memory Interfaces","Mode","Utilization",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,152,0,"Double MMA256 subchip  inside C7xv256 subchip","_0",1,0,912.5,"","","","","","","",""]
["MCU MCAN",2,null,null,null,null,null,null,null,null,null,null,null,null,"Full_HD_|_1920x1080x30_fps_16b_|_1p8V",null,null,null,null,null,null,null,null,"12Ch_TX_48_ksps_24b_3p3v",null,"Controller_6.25_Mbaud_3p3v",null,null,150,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"sam67_gpu_bxs464_dust_0",{"$f":"_xlfn.IFNA(MATCH(BN25,PWRCALC!AS:AS,0),0)","v":17},1,720,null,null,null,null,null,"LP/DDR4-32 IO 3733",92,null,13,"MCU PLL 0 HSDIV 0","MCU SS / WKUP Modules CLK [MHz] (MCU SYSCLK)",{"$f":"IF(INDIRECT(ADDRESS(BZ25,CC$1+1))=0,IF(CB$7=\"high\",400,200),INDIRECT(ADDRESS(BZ25,CC$1+1))/2)","v":400},null,"DDRSS 0",{"$f":"INDIRECT(ADDRESS(BX25,CC$1+1))","v":"lpddr4_3733_32"},{"$f":"INDIRECT(ADDRESS(BX25,CC$1))/1.1","v":0.45454545454545453},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,154,0,"GPU BXS4-64-256KB DUST AM67","_0",1,0,0,0.5,720,0.01,0,0.5,800,0.5,720]
["MCU GPIO",1,null,null,null,null,null,null,null,null,null,null,null,null,"Full_HD_|_1920x1080x30_fps_12b_|_3p3V",null,null,null,null,null,null,null,null,"16Ch_TX_48_ksps_24b_3p3v",null,"Controller_12.5_Mbaud_3p3v",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"sam67_gpu_bxs464_rslc256_0",{"$f":"_xlfn.IFNA(MATCH(BN26,PWRCALC!AS:AS,0),0)","v":18},1,720,null,null,null,null,null,"GPMC LVCMOS IO",138,null,56,"MAIN PLL 0 HSDIV 0","MAIN Modules CLK [MHz] (SYSCLK)",{"$f":"IF(INDIRECT(ADDRESS(BZ26,CC$1+1))=0,IF(CB$7=\"high\",500,250),INDIRECT(ADDRESS(BZ26,CC$1+1)))","v":500},null,"GPMC / ELM",{"$f":"INDIRECT(ADDRESS(BX26,CC$1+1))","v":"unused"},{"$f":"INDIRECT(ADDRESS(BX26,CC$1))","v":0},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,156,0,"GPU BXS4-64-256KB Rascal AM67","_0",1,0,0,0.5,720,0.01,0,0.5,800,0.5,720]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,"Full_HD_|_1920x1080x30_fps_12b_|_1p8V",null,null,null,null,null,null,null,null,"2Ch_RX_48_ksps_24b_3p3v",null,"Controller_25_Mbaud_3p3v",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"sam67_gpu_bxs464_wrap_0",{"$f":"_xlfn.IFNA(MATCH(BN27,PWRCALC!AS:AS,0),0)","v":19},1,720,null,null,null,null,null,{"$error":"#VALUE!"},null,null,66,"MAIN PLL 15 HSDIV 0\nMCU PLL 0 HSDIV 0","Device Manager Domain CLK [MHz]",{"$f":"IF(INDIRECT(ADDRESS(BZ27,CC$1+1))=0,IF(CB$7=\"high\",400,133),INDIRECT(ADDRESS(BZ27,CC$1+1)))","v":400},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,158,0,"GPU BXS4-64-256KB Wrap AM67","_0",1,0,0,0.5,720,0.01,0,0.5,800,0.5,720]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,"Full_HD_|_1920x720x60_fps_24b_|_3p3V",null,null,null,null,null,null,null,null,"4Ch_RX_48_ksps_24b_3p3v",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"_xlfn.IFNA(MATCH(BN28,PWRCALC!AS:AS,0),0)","v":0},0,0,null,null,null,null,null,{"$error":"#VALUE!"},null,null,null,"MAIN PLL 15 HSDIV 0","HSM Domain CLK",{"$f":"CC13","v":400},null,"PHYs","Mode","Utilization","Instances",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,160,0,"VPAC3L","_0",1,0,600,"","","","","","","",""]
["MAIN GPIO",2,null,null,null,null,null,null,null,null,null,null,null,null,"Full_HD_|_1920x720x60_fps_24b_|_1p8V",null,null,null,null,null,null,null,null,"8Ch_RX_48_ksps_24b_3p3v",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"_xlfn.IFNA(MATCH(BN29,PWRCALC!AS:AS,0),0)","v":0},0,0,null,null,null,null,null,"DPHY 1.2 RX - 4L",103,null,null,null,null,null,null,"CSI2.0 D_PHY 4L Rx",{"$f":"INDIRECT(ADDRESS(BX29,CC$1+1))","v":"1p5g4l"},{"$f":"INDIRECT(ADDRESS(BX29,CC$1))","v":0.1},{"$f":"IF(CG29>0,SUM(INDIRECT(ADDRESS(BX29,CC$1)&\":\"&ADDRESS(BX29+3,CC$1)))/CG29,0)","v":1},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,162,0,"DMPAC J7AEP","_0",1,0,428,"","","","","","","",""]
["MAIN I2C",4,null,null,null,null,null,null,null,null,null,null,null,null,"Full_HD_|_1920x720x60_fps_18b_|_3p3V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"sam67_cpsw3_wrap_0",{"$f":"_xlfn.IFNA(MATCH(BN30,PWRCALC!AS:AS,0),0)","v":22},1,0,null,null,null,null,null,"DPHY 1.2 TX - 4L",107,null,null,"IP for Complex IOs","Mode","Utilization","Instances","CSI2.0 / DSI D_PHY 4L Tx",{"$f":"IFERROR(INDIRECT(ADDRESS(BX30,CC$1+1))*1,\"off\")","v":"off"},{"$f":"IFERROR(INDIRECT(ADDRESS(BX30,CC$1))*1,0)","v":0},{"$f":"IF(AND(CG30>0,CF30<>\"ulps\"),1,0)","v":0},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,164,0,"CPSW3x eAVB AM62","_0",1,0.25,0,0.1,0,0.01,0,0.1,0,0.1,0]
["MAIN UART",7,null,null,null,null,null,null,null,null,null,null,null,null,"Full_HD_|_1920x720x60_fps_18b_|_1p8V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"sam67_vpu_wave521cl_wrap_0",{"$f":"_xlfn.IFNA(MATCH(BN31,PWRCALC!AS:AS,0),0)","v":23},1,100,null,null,null,null,null,"Arasan HS400 8 bit",112,null,null,"CPSW3",null,null,null,"MAIN MMCSD0",{"$f":"INDIRECT(ADDRESS(BX31,CC$1+1))","v":"off"},{"$f":"INDIRECT(ADDRESS(BX31,CC$1))","v":0},{"$f":"IF(AND(CG31>0,CF31<>\"off\"),1,0)","v":0},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,166,0,"WAVE521CL Video Codec AM62A","_0",1,0,500,1,100,0.01,0,1,100,1,100]
["MAIN McSPI",3,null,null,null,null,null,null,null,null,null,null,null,null,"Full_HD_|_1920x720x60_fps_16b_|_3p3V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"sam62_mcasp_wrap_0",{"$f":"_xlfn.IFNA(MATCH(BN32,PWRCALC!AS:AS,0),0)","v":24},1,0,null,null,null,null,null,"LVDS IO",108,45,101,"1G SGMII SerDes ports",{"$f":"IF(OR(INDIRECT(ADDRESS(BZ32,CC$1+1))=\"1g\",INDIRECT(ADDRESS(BZ32+1,CC$1+1))=\"1g\"),\"1g\",\"disable\")","v":"disable"},{"$f":"IF(INDIRECT(ADDRESS(BZ32,CC$1+1))=\"1g\",INDIRECT(ADDRESS(BY32,CC$1))*10,IF(INDIRECT(ADDRESS(BZ32+1,CC$1+1))=\"1g\",INDIRECT(ADDRESS(BY32+1,CC$1))*10,0))","v":0},{"$f":"IF(INDIRECT(ADDRESS(BZ32,CC$1+1))=\"1g\",1,0)+IF(INDIRECT(ADDRESS(BZ32+1,CC$1+1))=\"1g\",1,0)","v":0},"OLDI (2 Link)",{"$f":"INDIRECT(ADDRESS(BX32,CC$1+1))","v":"oldi_dual_24b_modes"},{"$f":"INDIRECT(ADDRESS(BX32,CC$1))","v":1},{"$f":"IF(AND(CG32>0,CF32<>\"disabled\"),1,0)","v":1},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,168,0,"MCASP AM62","_0",1,0,0,0.2,0,0.01,0,0.2,0,0.2,0]
["MAIN McASP",3,null,null,null,null,null,null,null,null,null,null,null,null,"Full_HD_|_1920x720x60_fps_16b_|_1p8V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"sam62_mcasp_wrap_1",{"$f":"_xlfn.IFNA(MATCH(BN33,PWRCALC!AS:AS,0),0)","v":25},1,0,null,null,null,null,null,null,null,null,133,"LVCMOS ports",{"$f":"IF(INDIRECT(ADDRESS(BZ33,CC$1))>0,INDIRECT(ADDRESS(BZ33,CC$1+1)),IF(INDIRECT(ADDRESS(BZ33+1,CC$1))>0,INDIRECT(ADDRESS(BZ33,CC$1+1)),\"unused\"))","v":"rgmii_1000_1p8v"},{"$f":"IF(INDIRECT(ADDRESS(BZ33,CC$1))>0,INDIRECT(ADDRESS(BZ33,CC$1)),IF(INDIRECT(ADDRESS(BZ33+1,CC$1))>0,INDIRECT(ADDRESS(BZ33,CC$1)),0))","v":0.2},{"$f":"IF(INDIRECT(ADDRESS(BZ33,CC$1))>0,1,0)+IF(INDIRECT(ADDRESS(BZ33+1,CC$1))>0,1,0)","v":2},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,170,0,"MCASP AM62","_1",1,0,0,0,0,0.01,0,0,0,0,0]
["MAIN ECAP",3,null,null,null,null,null,null,null,null,null,null,null,null,"Full_HD_|_1920x720x60_fps_12b_|_3p3V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"sam62_mcasp_wrap_2",{"$f":"_xlfn.IFNA(MATCH(BN34,PWRCALC!AS:AS,0),0)","v":26},1,0,null,null,null,null,null,null,null,null,null,"CSI (TX) / DSI D-PHY",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,172,0,"MCASP AM62","_2",1,0,0,0,0,0.01,0,0,0,0,0]
["MAIN EPWM",3,null,null,null,null,null,null,null,null,null,null,null,null,"Full_HD_|_1920x720x60_fps_12b_|_1p8V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"_xlfn.IFNA(MATCH(BN35,PWRCALC!AS:AS,0),0)","v":0},0,0,null,null,null,null,null,null,null,null,41,"CSI Tx ports",{"$f":"IF(INDIRECT(ADDRESS(BZ35,CC$1))>0,INDIRECT(ADDRESS(BZ36,CC$1+1)),\"ulps\")","v":""},{"$f":"INDIRECT(ADDRESS(BZ35,CC$1))","v":""},{"$f":"IF(AND(CB35<>\"ulps\",CC35>0),1,0)","v":1},"High Speed Serial Interfaces","Mode","Utilization",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,174,0,"MCASP AM62","_3",1,0,0,"","","","","","","",""]
["MAIN EQEP",3,null,null,null,null,null,null,null,null,null,null,null,null,"Full_HD_|_1920x720x30_fps_24b_|_3p3V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"_xlfn.IFNA(MATCH(BN36,PWRCALC!AS:AS,0),0)","v":0},0,0,null,null,null,null,null,null,null,null,107,"DSI Tx ports",{"$f":"IF(CB35=\"ulps\",INDIRECT(ADDRESS(BZ36,CC$1+1)),\"ulps\")","v":"ulps"},{"$f":"IF(CB36<>\"ulps\",INDIRECT(ADDRESS(BZ36,CC$1)),0)","v":0},{"$f":"IF(AND(CB36<>\"ulps\",CC36>0),1,0)","v":0},"SerDes 0 (PCIE_3, PCIE_1, USB_0, Hyperlink_0)",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,176,0,"MCASP AM62","_4",1,0,0,"","","","","","","",""]
["MAIN MCAN",2,null,null,null,null,null,null,null,null,null,null,null,null,"Full_HD_|_1920x720x30_fps_24b_|_1p8V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"sam67_csirx_wrap_0",{"$f":"_xlfn.IFNA(MATCH(BN37,PWRCALC!AS:AS,0),0)","v":29},0.1,0,null,null,null,null,null,null,101,null,null,"PCIE",null,null,null,"Lane0",{"$f":"INDIRECT(ADDRESS(BX37,CC$1+1))","v":""},{"$f":"INDIRECT(ADDRESS(BX37,CC$1))","v":""},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,178,0,"CSI_RX","_0",1,0,0,0.05,0,0.01,0,0.05,0,0.05,0]
["MAIN MMCSD1",2,null,null,null,null,null,null,null,null,null,null,null,null,"Full_HD_|_1920x720x30_fps_18b_|_3p3V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"_xlfn.IFNA(MATCH(BN38,PWRCALC!AS:AS,0),0)","v":0},0,0,null,null,null,null,null,null,null,102,42,"PCIE_0 (1 Lane)",{"$f":"IF(INDIRECT(ADDRESS(BZ38,CC$1))>0,INDIRECT(ADDRESS(BY38,CC$1+1)),\"disable\")","v":""},{"$f":"INDIRECT(ADDRESS(BZ38,CC$1))","v":""},{"$f":"IF(AND(CB38<>\"disable\",CC38>0),1,0)","v":1},"SerDes 1 (CPSW3_0, PCIE_0, PCIE_2, n/a)",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,180,0,"CSI_RX","_1",1,0,0,"","","","","","","",""]
["MAIN DSS 0: DPI",1,null,null,null,null,null,null,null,null,null,null,null,null,"Full_HD_|_1920x720x30_fps_18b_|_1p8V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"_xlfn.IFNA(MATCH(BN39,PWRCALC!AS:AS,0),0)","v":0},0,0,null,null,null,null,null,null,102,null,null,"USB",null,null,null,"Lane0",{"$f":"INDIRECT(ADDRESS(BX39,CC$1+1))","v":""},{"$f":"INDIRECT(ADDRESS(BX39,CC$1))","v":""},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,182,0,"CSI_RX","_2",1,0,0,"","","","","","","",""]
["MAIN FSS OSPI1 (QSPI)",1,null,null,null,null,null,null,null,null,null,null,null,null,"Full_HD_|_1920x720x30_fps_16b_|_3p3V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"_xlfn.IFNA(MATCH(BN40,PWRCALC!AS:AS,0),0)","v":0},0,0,null,null,null,{"$f":"DC115","v":"USB2 - PHY"},null,null,null,101,44,"3.0",{"$f":"IF(CC40=0,\"suspend\",INDIRECT(ADDRESS(BY40,CC$1+1)))","v":""},{"$f":"INDIRECT(ADDRESS(BZ40,CC$1))","v":""},{"$f":"IF(AND(CB40<>\"suspend\",CC40>0),1,0)","v":1},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,184,0,"CSI_RX","_3",1,0,0,"","","","","","","",""]
["MAIN Ethernet",2,null,null,null,null,null,null,null,null,null,null,null,null,"Full_HD_|_1920x720x30_fps_16b_|_1p8V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"_xlfn.IFNA(MATCH(BN41,PWRCALC!AS:AS,0),0)","v":0},0,0,null,null,null,{"$f":"DC116","v":"USB2 - PHY"},null,null,null,116,43,"2.0 (dedicated)",{"$f":"IF(CC41=0,\"suspend\",IF(INDIRECT(ADDRESS(BY41,CC$1+1))<>\"suspend\",INDIRECT(ADDRESS(BY41,CC$1+1)),IF(INDIRECT(ADDRESS(BY41-1,CC$1+1))<>\"suspend\",INDIRECT(ADDRESS(BY41-1,CC$1+1)),\"suspend\")))","v":"suspend"},{"$f":"MAX(INDIRECT(ADDRESS(BZ41,CC$1)),INDIRECT(ADDRESS(BZ41-1,CC$1)))","v":0},{"$f":"IF(AND(INDIRECT(ADDRESS(BY41,CC$1+1))<>\"suspend\",INDIRECT(ADDRESS(BY41,CC$1))>0),1,0)+IF(AND(INDIRECT(ADDRESS(BY41-1,CC$1+1))<>\"suspend\",INDIRECT(ADDRESS(BY41-1,CC$1))>0),1,0)","v":1},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,186,0,"CSI_TX","_0",1,0,0,"","","","","","","",""]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,"Full_HD_|_1920x720x30_fps_12b_|_3p3V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"_xlfn.IFNA(MATCH(BN42,PWRCALC!AS:AS,0),0)","v":0},0,0,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,188,0,"PCIE_G3 4L sam67","_0",1,0.25,0,"","","","","","","",""]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,"Full_HD_|_1920x720x30_fps_12b_|_1p8V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"sam67_usb2_wrap_0",{"$f":"_xlfn.IFNA(MATCH(BN43,PWRCALC!AS:AS,0),0)","v":35},1,0,null,null,null,null,null,null,null,null,null,"LVCMOS IO","Mode","Utilization","Instances",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,190,0,"USB2 Controller","_0",1,0,0,0,0,0.01,0,0,0,0,0]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,"UXGA_|_1600x1200x60_fps_24b_|_3p3V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"_xlfn.IFNA(MATCH(BN44,PWRCALC!AS:AS,0),0)","v":0},0,0,null,null,null,null,null,null,null,null,145,"WKUP I2C",{"$f":"INDIRECT(ADDRESS($BZ44,$CC$1+1))","v":"i2c_400k_3p3v"},{"$f":"INDIRECT(ADDRESS($BZ44,$CC$1))","v":0.05},{"$f":"IF(AND(CB44<>\"unused\",CC44>0),1,0)","v":1},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,192,0,"USB3P0TCx1 AM6","_0",1,0,0,"","","","","","","",""]
["Used to Reset Sheet",null,null,null,null,null,null,null,null,null,null,null,null,null,"UXGA_|_1600x1200x60_fps_24b_|_1p8V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"_xlfn.IFNA(MATCH(BN45,PWRCALC!AS:AS,0),0)","v":0},0,0,null,null,null,null,null,null,null,null,164,"WKUP UART",{"$f":"INDIRECT(ADDRESS($BZ45,$CC$1+1))","v":"unused"},{"$f":"INDIRECT(ADDRESS($BZ45,$CC$1))","v":0},{"$f":"IF(AND(CB45<>\"unused\",CC45>0),1,0)","v":0},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,194,0,"PCS_MUX 1L 10G","_0",1,0.2,0,"","","","","","","",""]
["J722S, TDA4VEN, TDA4AEN, AM67 Power Estimation Tool",null,null,null,null,null,null,null,null,null,null,null,null,null,"UXGA_|_1600x1200x60_fps_18b_|_3p3V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"_xlfn.IFNA(MATCH(BN46,PWRCALC!AS:AS,0),0)","v":0},0,0,null,null,null,null,null,null,null,null,144,"MCU I2C","off",0,0,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,196,0,"PCS_MUX 1L 10G","_1",1,6.25E-2,0,"","","","","","","",""]
[null,null,null,"Starting Use Case",null,null,null,null,null,null,null,null,null,null,"UXGA_|_1600x1200x60_fps_18b_|_1p8V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"ddr32_3733_phy_0",{"$f":"_xlfn.IFNA(MATCH(BN47,PWRCALC!AS:AS,0),0)","v":39},1.1000000000000001,533.25,null,null,null,null,null,null,null,null,163,"MCU UART","unused",0,0,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,198,0,"LP/DDR4-32 PHY 3733","_0",1,0.44000000000000006,933.25,0.5,933.25,0.01,0,0.5,933.25,0.5,933.25]
[null,"Modifiable Field",null,{"$f":"'Use Case'!D3","v":"UC1 0.75V Automotive Cluster"},null,null,null,null,null,null,null,null,null,null,"UXGA_|_1600x1200x60_fps_16b_|_3p3V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"sam62_emmc_4bit_wrap_1",{"$f":"_xlfn.IFNA(MATCH(BN48,PWRCALC!AS:AS,0),0)","v":40},1,0,null,null,null,null,null,null,null,null,155,"MCU McSPI","Controller_2.083_Mbaud_3p3v",0.1,{"$f":"IF(CC48=0,0,SUM(INDIRECT(ADDRESS($BZ48,$CC$1)&\":\"&ADDRESS($BZ48+1,$CC$1)))/CC48)","v":2},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,200,0,"EMMC 4 AM62","_1",1,0,0,0,0,0.01,0,0,0,0,0]
[null,"Descriptor",null,null,null,null,null,null,null,null,null,null,null,null,"UXGA_|_1600x1200x60_fps_16b_|_1p8V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"sam62_emmc_4bit_wrap_2",{"$f":"_xlfn.IFNA(MATCH(BN49,PWRCALC!AS:AS,0),0)","v":41},1,0,null,null,null,null,null,null,null,null,121,"MCU MCAN","unused",0,{"$f":"IF(CC49=0,0,SUM(INDIRECT(ADDRESS($BZ49,$CC$1)&\":\"&ADDRESS($BZ49+1,$CC$1)))/CC49)","v":0},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,202,0,"EMMC 4 AM62","_2",1,0,0,0,0,0.01,0,0,0,0,0]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,"UXGA_|_1600x1200x60_fps_12b_|_3p3V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"sam67_emmc_8bit_wrap_0",{"$f":"_xlfn.IFNA(MATCH(BN50,PWRCALC!AS:AS,0),0)","v":42},1,0,null,null,null,null,null,null,null,null,137,"MCU GPIO","1mbs_3p3v_20pf",0.1,1,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,204,0,"EMMC 8 AM62","_0",1,0,0,0.05,0,0.01,0,0.05,0,0.05,0]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,"UXGA_|_1600x1200x60_fps_12b_|_1p8V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"sam62_gpmc_elm_wrap_0",{"$f":"_xlfn.IFNA(MATCH(BN51,PWRCALC!AS:AS,0),0)","v":43},0,0,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,206,0,"GPMC_ELM AM62","_0",1,0,0,0,0,0.01,0,0,0,0,0]
["Tj",125,"C",null,null,null,null,null,null,null,null,null,null,null,"UXGA_|_1600x1200x30_fps_24b_|_3p3V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"sam67_ddr_wrap_0",{"$f":"_xlfn.IFNA(MATCH(BN52,PWRCALC!AS:AS,0),0)","v":44},1,533.25,null,null,null,null,null,null,null,null,null,"LVCMOS IO","Mode","Utilization","Instances",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,208,0,"LP/DDR4-32 EMIF AM62A","_0",1,0.4,933.25,0.5,933.25,0.01,0,0.5,933.25,0.5,933.25]
["SRAM_Voltage",0.85,"V",null,null,null,null,null,null,null,null,null,null,null,"UXGA_|_1600x1200x30_fps_24b_|_1p8V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"sam67_debug_wrap_0",{"$f":"_xlfn.IFNA(MATCH(BN53,PWRCALC!AS:AS,0),0)","v":45},0,0,null,null,null,null,null,null,null,null,135,"MAIN GPIO",{"$f":"INDIRECT(ADDRESS($BZ53,$CC$1+1))","v":"1mbs_1p8v_20pf"},{"$f":"INDIRECT(ADDRESS($BZ53,$CC$1))","v":0.1},{"$f":"IF(CC53=0,0,SUM(INDIRECT(ADDRESS($BZ53,$CC$1)&\":\"&ADDRESS($BZ53+1,$CC$1)))/CC53)","v":2},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,210,0,"Debug SS AM67","_0",1,0,0,0,0,0.01,0,0,0,0,0]
["CORE_Voltage",0.75,"V",null,"Processor Core Utilization (%)",null,null,null,null,null,null,null,null,null,"UXGA_|_1600x1200x30_fps_18b_|_3p3V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"sam62_efuse_ctrl_wrap_0",{"$f":"_xlfn.IFNA(MATCH(BN54,PWRCALC!AS:AS,0),0)","v":46},0,0,null,null,null,null,null,null,null,null,139,"MAIN I2C","i2c_400k_3p3v",0.05,{"$f":"IF(CC54=0,0,SUM(INDIRECT(ADDRESS($BZ54,$CC$1)&\":\"&ADDRESS($BZ54+4,$CC$1)))/CC54)","v":3.0000000000000004},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,212,0,"eFuse Controller AM62","_0",1,0,0,0,0,0.01,0,0,0,0,0]
["Process_Corner","strong",null,null,"MAIN SMS 0",0,null,null,null,null,null,null,null,null,"UXGA_|_1600x1200x30_fps_18b_|_1p8V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"sam62_odp_ctrl_wrap_0",{"$f":"_xlfn.IFNA(MATCH(BN55,PWRCALC!AS:AS,0),0)","v":47},0,0,null,null,null,null,null,null,null,157,165,"MAIN UART","3p6m_1p8v",0.05,{"$f":"IF(CC55=0,0,SUM(INDIRECT(ADDRESS($BY55,$CC$1)&\":\"&ADDRESS($BY55+5,$CC$1)))/CC55+1)","v":3},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,214,0,"ODP Controller AM62","_0",1,0,0,0,0,0.01,0,0,0,0,0]
["OPP","high",null,null,"MAIN (WKUP) R5FSS 0",0,null,null,null,null,null,null,null,null,"UXGA_|_1600x1200x30_fps_16b_|_3p3V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"sam62_pll_ctrl_wrap_0",{"$f":"_xlfn.IFNA(MATCH(BN56,PWRCALC!AS:AS,0),0)","v":48},1,500,null,null,null,null,null,null,null,null,152,"MAIN McSPI","unused",0,{"$f":"IF(CC56=0,0,SUM(INDIRECT(ADDRESS($BZ56,$CC$1)&\":\"&ADDRESS($BZ56+2,$CC$1)))/CC56)","v":0},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,216,0,"PLL Controller AM62","_0",2,0,0,0,0,0.01,0,0,0,0,0]
[null,null,null,null,"MAIN R5FSS 2",0,null,null,null,null,null,null,null,null,"UXGA_|_1600x1200x30_fps_16b_|_1p8V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"_xlfn.IFNA(MATCH(BN57,PWRCALC!AS:AS,0),0)","v":0},0,0,null,null,null,null,null,null,null,null,146,"MAIN McASP","16Ch_TX_48_ksps_24b_3p3v",1,{"$f":"IF(CC57=0,0,SUM(INDIRECT(ADDRESS($BZ57,$CC$1)&\":\"&ADDRESS($BZ57+4,$CC$1)))/CC57)","v":3},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,218,0,"PLL Controller AM62","_1",2,0,0,0,0,0.01,0,0,0,0,0]
["UC_Description","Add Test Description",null,null,"MAIN A53SS 0: 0",0,null,null,null,null,null,null,null,null,"UXGA_|_1600x1200x30_fps_12b_|_3p3V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"sam67_ls_mcu_can_0",{"$f":"_xlfn.IFNA(MATCH(BN58,PWRCALC!AS:AS,0),0)","v":50},1,0,null,null,null,null,null,null,null,null,124,"MAIN ECAP","unused",0,{"$f":"IF(CC58=0,0,SUM(INDIRECT(ADDRESS($BZ58,$CC$1)&\":\"&ADDRESS($BZ58+2,$CC$1)))/CC58)","v":0},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,220,0,"CAN_IO wrap AM62A","_0",1,1,0,0,0,0.01,0,0,0,0,0]
["UC_Name","Add Test Name",null,null,"MAIN A53SS 0: 1",0,null,null,null,null,null,null,null,null,"UXGA_|_1600x1200x30_fps_12b_|_1p8V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"j7_n16_edg_lvl_iopm_0",{"$f":"_xlfn.IFNA(MATCH(BN59,PWRCALC!AS:AS,0),0)","v":51},1,0,null,null,null,null,null,null,null,null,127,"MAIN EPWM","on_1p8v",0.05,3.0000000000000004,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,222,0,"N16_EDG_LS J7ES","_0",1,1,0,0,0,0.01,0,0,0,0,0]
[null,null,null,null,"MAIN A53SS 0: 2",0,null,null,null,null,null,null,null,null,"HD+_|_1600x900x60_fps_24b_|_3p3V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"sam62a_can_io_domain_0",{"$f":"_xlfn.IFNA(MATCH(BN60,PWRCALC!AS:AS,0),0)","v":52},1,0,null,null,null,null,null,null,null,null,130,"MAIN EQEP","off",0,0,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,224,0,"CAN_IO wrap AM62A","_0",1,1,0,0,0,0.01,0,0,0,0,0]
["Key IP Frequency selection",0,"Frequency [MHz]",null,"MAIN A53SS 0: 3",0,null,null,null,null,null,null,null,null,"HD+_|_1600x900x60_fps_18b_|_1p8V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"sam67_main_infra_phys_0",{"$f":"_xlfn.IFNA(MATCH(BN61,PWRCALC!AS:AS,0),0)","v":53},1,250,null,null,null,null,null,null,null,null,119,"MAIN MCAN","1mbs_3p3v",0.2,{"$f":"IF(CC61=0,0,SUM(INDIRECT(ADDRESS($BZ61,$CC$1)&\":\"&ADDRESS($BZ61+1,$CC$1)))/CC61)","v":2},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,226,0,"Main_infra AM67","_0",1,0,0,0.2,0,0.01,0,0.2,0,0.2,0]
["MAIN PLL 15 HSDIV 0","MAIN SMS 0 Frequency [MHz]",400,null,"MAIN C71SS 0: C71x",0,null,null,null,null,null,null,null,null,"HD+_|_1600x900x60_fps_18b_|_3p3V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"sam62p_main_ip_wrap_0",{"$f":"_xlfn.IFNA(MATCH(BN62,PWRCALC!AS:AS,0),0)","v":54},0.4,290,null,null,null,null,null,null,null,null,113,"MAIN MMCSD1","unused",0,{"$f":"IF(CC62=0,0,SUM(INDIRECT(ADDRESS($BZ62,$CC$1)&\":\"&ADDRESS($BZ62+1,$CC$1)))/CC62)","v":0},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,228,0,"Main_IP AM62P_J7AEN","_0",1,0.4,0,0.4,0,0.01,0,0.4,0,0.4,0]
["MAIN PLL 15 HSDIV 2\nMCU PLL 0 HSDIV 0","Domain Manager (WKUP) R5FSS 0 Frequency [MHz]",800,null,"MAIN C71SS 0: MMA",0,null,null,null,null,null,null,null,null,"HD+_|_1600x900x60_fps_18b_|_1p8V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"sam62p_main_rt_wrap_0",{"$f":"_xlfn.IFNA(MATCH(BN63,PWRCALC!AS:AS,0),0)","v":55},0.66971428571428571,290,null,null,null,null,null,null,null,null,123,"MAIN DSS 0: DPI","2K_|_2048x1080x60_fps_24b_|_3p3V",1,{"$f":"IF(INDIRECT(ADDRESS($BZ63,$CC$1))>0,1,0)","v":1},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,230,0,"dmss csi + secondary main cbass","_0",1,0.15,0,0.4,0,0.01,0,0.4,0,0.4,0]
["MAIN PLL 15 HSDIV 3","MAIN R5FSS 1 Frequency [MHz]",800,null,"MAIN C71SS 1: C71x",0,null,null,null,null,null,null,null,null,"HD+_|_1600x900x60_fps_16b_|_3p3V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"sam67_mcu_infra_phys_0",{"$f":"_xlfn.IFNA(MATCH(BN64,PWRCALC!AS:AS,0),0)","v":56},1,200,null,null,null,null,null,null,null,null,151,"MAIN FSS OSPI1 (QSPI)","ospi_ddr_controller_133_3p3v",1,{"$f":"IF(INDIRECT(ADDRESS($BZ64,$CC$1))>0,1,0)","v":1},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,232,0,"MCU_INFRA_WAKEUP AM62A","_0",1,0.1,0,0.5,0,0.01,0,0.5,0,0.5,0]
["MCU PLL 0 HSDIV 3","MCU R5FSS 0 Frequency [MHz]",800,null,"MAIN C71SS 1: MMA",0,null,null,null,null,null,null,null,null,"HD+_|_1600x900x60_fps_16b_|_1p8V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"sam67_mcu_wrap_0",{"$f":"_xlfn.IFNA(MATCH(BN65,PWRCALC!AS:AS,0),0)","v":57},1,266.66669999999999,null,null,null,null,null,null,null,null,null,"MAIN Ethernet",{"$f":"CB33","v":"rgmii_1000_1p8v"},{"$f":"CC33","v":0.2},2,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,234,0,"MCUSS AM62A","_0",1,0.25,0,0.5,0,0.01,0,0.5,0,0.5,0]
["MAIN PLL 8 HSDIV0","MAIN A53SS Frequency [MHz]",1250,null,"MAIN VPAC 0",0,null,null,null,null,null,null,null,null,"HD+_|_1600x900x60_fps_12b_|_3p3V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"sam67_sec_wrap_0",{"$f":"_xlfn.IFNA(MATCH(BN66,PWRCALC!AS:AS,0),0)","v":58},0.05,{"$f":"IFERROR(INDIRECT(ADDRESS($BO66,COLUMN(Q$1),,,\"PWRCALC\")),0)","v":400},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,236,0,"HSM AM67","_0",1,0.25,0,0.05,0,0.01,0,0.05,0,0.05,0]
["MAIN PLL 7 HSDIV 0","MAIN C71SS 0 and 1 Frequency [MHz]",912.5,null,"MAIN DMPAC 0",0,null,null,null,null,null,null,null,null,"HD+_|_1600x900x60_fps_12b_|_1p8V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"sam62p_core_0",{"$f":"_xlfn.IFNA(MATCH(BN67,PWRCALC!AS:AS,0),0)","v":59},0.4,250,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,238,0,"J7AEN top","_0",1,0.25,0,0.4,0,0.01,0,0.4,0,0.4,0]
["MAIN PLL 5 HSDIV 0","MAIN VPAC 0 Frequency [MHz]",600,null,"MAIN GPU 0",0,null,null,null,null,null,null,null,null,"HD+_|_1600x900x30_fps_24b_|_3p3V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"DIVTS16FFC1TO128A_main",{"$f":"_xlfn.IFNA(MATCH(BN68,PWRCALC!AS:AS,0),0)","v":60},1,400,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,240,{"$f":"INDIRECT(ADDRESS(2,DA68))","v":0},"HSDIVIDER","_main",41,1,300,1,400,0.01,300,1,400,1,400]
["MAIN PLL 5 HSDIV 2","MAIN DMPAC 0 Frequency [MHz]",428,null,"MAIN Video Encoder/Decoder 0",0,null,null,null,null,null,null,null,null,"HD+_|_1600x900x30_fps_24b_|_1p8V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"DIVTS16FFC1TO128A_wkup",{"$f":"_xlfn.IFNA(MATCH(BN69,PWRCALC!AS:AS,0),0)","v":61},1,400,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"2+DA68","v":242},0,"HSDIVIDER","_wkup",7,1,200,1,400,0.01,200,1,400,1,400]
["MAIN PLL 6 HSDIV 0","MAIN GPU 0 Frequency [MHz]",720,null,"MCU R5FSS",0,null,null,null,null,null,null,null,null,"HD+_|_1600x900x30_fps_18b_|_3p3V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"PLLTS16FFCLAFRACF_ARM0_PLL",{"$f":"_xlfn.IFNA(MATCH(BN70,PWRCALC!AS:AS,0),0)","v":62},1,3000,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,244,0,"ADPLL - FRACF","_ARM0_PLL8",1,1,2500,1,3000,0.01,3000,1,3000,1,3000]
["MAIN PLL 2 HSDIV 4","MAIN Video Encoder/Decoder 0 Frequency [MHz]",500,null,null,null,null,null,null,null,null,null,null,null,"HD+_|_1600x900x30_fps_18b_|_1p8V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"_xlfn.IFNA(MATCH(BN71,PWRCALC!AS:AS,0),0)","v":0},0,0,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,246,0,"ADPLL - FRACF","_C7x_PLL7",1,1,2500,"","","","","","","",""]
["MAIN PLL 0 HSDIV 0 div 2","MAIN JPEG Encoder 0 Frequency [MHz]",250,null,null,null,null,null,null,null,null,null,null,null,"HD+_|_1600x900x30_fps_16b_|_3p3V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"PLLTS16FFCLAFRACF_DSS0_PLL",{"$f":"_xlfn.IFNA(MATCH(BN72,PWRCALC!AS:AS,0),0)","v":64},1,2500,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,248,0,"ADPLL - FRACF","_DSS0_PLL16",1,1,2500,1,2500,0.01,2500,1,2500,1,2500]
["MAIN PLL 12 HSDIV0","LPDDR4 EMIF 0 [MT/s]",3733,null,"Memory Interfaces","Mode","Utilization",null,null,null,null,null,null,null,"HD+_|_1600x900x30_fps_16b_|_1p8V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"PLLTS16FFCLAFRACF_DSS1_PLL",{"$f":"_xlfn.IFNA(MATCH(BN73,PWRCALC!AS:AS,0),0)","v":65},1,2500,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,250,0,"ADPLL - FRACF","_DSS1_PLL17",1,1,2500,1,2500,0.01,2500,1,2500,1,2500]
["MCU PLL 0 HSDIV 0","MCU SS / WKUP Modules CLK [MHz] (MCU SYSCLK)",400,null,"DDRSS 0","sleep",0,null,null,null,null,null,null,null,"HD+_|_1600x900x30_fps_12b_|_3p3V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"PLLTS16FFCLAFRACF_GPU_PLL",{"$f":"_xlfn.IFNA(MATCH(BN74,PWRCALC!AS:AS,0),0)","v":66},1,2250,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,252,0,"ADPLL - FRACF","_GPU_PLL6",1,1,2500,1,1750,0.01,1750,1,1750,1,1750]
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["MAIN PLL 15 HSDIV 0\nMCU PLL 0 HSDIV 0","Device Manager Domain CLK [MHz]",400,null,0,0,0,null,null,null,null,null,null,null,"SXGA+_|_1400x1050x60_fps_24b_|_3p3V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"PLLTS16FFCLAFRACF_SMS",{"$f":"_xlfn.IFNA(MATCH(BN76,PWRCALC!AS:AS,0),0)","v":68},1,2500,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,256,0,"ADPLL - FRACF","_SEC_PLL15",1,1,2500,1,2500,0.01,2500,1,2500,1,2500]
["MAIN PLL 15 HSDIV 0","HSM Domain CLK",133,null,"PHYs","Mode","Utilization","Instances",null,null,null,null,null,null,"SXGA+_|_1400x1050x60_fps_24b_|_1p8V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"PLLTS16FFCLAFRACF_Per0",{"$f":"_xlfn.IFNA(MATCH(BN77,PWRCALC!AS:AS,0),0)","v":69},{"$f":"IFERROR(INDIRECT(ADDRESS($BO77,COLUMN(S$1),,,\"PWRCALC\")),0)","v":1},{"$f":"IFERROR(INDIRECT(ADDRESS($BO77,COLUMN(R$1),,,\"PWRCALC\")),0)","v":2000},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,258,0,"ADPLL - FRACF","_Per0_PLL1",1,1,2500,1,2000,0.01,2000,1,2000,1,2000]
[null,null,null,null,"CSI2.0 D_PHY 4L Rx","ulps",0,1,null,null,null,null,null,null,"SXGA+_|_1400x1050x60_fps_18b_|_3p3V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"PLLTS16FFCLAFRACF_Per1",{"$f":"_xlfn.IFNA(MATCH(BN78,PWRCALC!AS:AS,0),0)","v":70},1,2000,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,260,0,"ADPLL - FRACF","_Per1_PLL2",1,1,2500,1,2000,0.01,2000,1,2000,1,2000]
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["1G SGMII SerDes ports","disable",0,2,"OLDI (2 Link)","unused",0,1,null,null,null,null,null,null,"SXGA+_|_1400x1050x60_fps_16b_|_1p8V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"PLLTS16FFCLAFRACFDDR_PHY",{"$f":"_xlfn.IFNA(MATCH(BN81,PWRCALC!AS:AS,0),0)","v":73},1,2000,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,266,0,"ADPLL - FRACF","DDR_PHY_PLL12",1,1,2500,1,2000,0.01,2000,1,2000,1,2000]
["LVCMOS ports","unused",0,2,null,null,null,null,null,null,null,null,null,null,"SXGA+_|_1400x1050x60_fps_12b_|_3p3V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"PLLTS16FFCLAFRACF_MCU_PERIPHERIAL",{"$f":"_xlfn.IFNA(MATCH(BN82,PWRCALC!AS:AS,0),0)","v":74},1,2500,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,268,0,"ADPLL - FRACF","MCU_PLL?",1,1,2500,1,2500,0.01,2500,1,2500,1,2500]
["CSI (TX) / DSI D-PHY",0,0,0,null,null,null,null,null,null,null,null,null,null,"SXGA+_|_1400x1050x60_fps_12b_|_1p8V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"TEF16FCLL256X32HD18_PHRM_main",{"$f":"_xlfn.IFNA(MATCH(BN83,PWRCALC!AS:AS,0),0)","v":75},1,"on",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,270,0,"eFuse","_main",2,1,"on",1,"on",0.01,"on",1,"on",1,"on"]
["CSI Tx ports","ulps",0,1,"High Speed Serial Interfaces","Mode","Utilization",null,null,null,null,null,null,null,"SXGA_|_1280x1024x60_fps_24b_|_3p3V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"N16FFC_POK_PMIC_IN_OV",{"$f":"_xlfn.IFNA(MATCH(BN84,PWRCALC!AS:AS,0),0)","v":76},1,"on",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,272,0,"POK","_VMON_1P8_SOC",1,1,"on",1,"on",0.01,"on",1,"on",1,"on"]
["DSI Tx ports","ulps",0,1,"SerDes 0 (PCIE_3, PCIE_1, USB_0, Hyperlink_0)",0,0,null,null,null,null,null,null,null,"SXGA_|_1280x1024x60_fps_24b_|_1p8V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"N16FFC_POK_VDD_CORE_OV",{"$f":"_xlfn.IFNA(MATCH(BN85,PWRCALC!AS:AS,0),0)","v":77},1,"on",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,274,0,"POK","_VMON_3P3_SOC",1,1,"on",1,"on",0.01,"on",1,"on",1,"on"]
["PCIE",0,0,0,"Lane0","disable",0,null,null,null,null,null,null,null,"SXGA_|_1280x1024x60_fps_18b_|_3p3V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"N16FFC_POK_VDD_CORE_UV",{"$f":"_xlfn.IFNA(MATCH(BN86,PWRCALC!AS:AS,0),0)","v":78},1,"on",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,276,0,"POK","_CAP_VDDS_MCU",1,1,"on",1,"on",0.01,"on",1,"on",1,"on"]
["PCIE_0 (1 Lane)","disable",0,1,"SerDes 1 (CPSW3_0, PCIE_0, PCIE_2, n/a)",0,0,null,null,null,null,null,null,null,"SXGA_|_1280x1024x60_fps_18b_|_1p8V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"N16FFC_POK_VDDR_CORE_OV",{"$f":"_xlfn.IFNA(MATCH(BN87,PWRCALC!AS:AS,0),0)","v":79},1,"on",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,278,0,"POK","_VDD_CORE",1,1,"on",1,"on",0.01,"on",1,"on",1,"on"]
["USB",0,0,0,"Lane0","disable",0,null,null,null,null,null,null,null,"SXGA_|_1280x1024x60_fps_16b_|_3p3V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"N16FFC_POK_VDDR_CORE_UV",{"$f":"_xlfn.IFNA(MATCH(BN88,PWRCALC!AS:AS,0),0)","v":80},1,"on",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,280,0,"POK","_VDDR_CORE",1,1,"on",1,"on",0.01,"on",1,"on",1,"on"]
["3.0","suspend",0,1,null,null,null,null,null,null,null,null,null,null,"SXGA_|_1280x1024x60_fps_16b_|_1p8V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"N16FFC_POK_VMON_EXT_OV",{"$f":"_xlfn.IFNA(MATCH(BN89,PWRCALC!AS:AS,0),0)","v":81},1,"on",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,282,0,"POK","_VDDS_DDR",1,1,"on",1,"on",0.01,"on",1,"on",1,"on"]
["2.0 (dedicated)","suspend",0,2,null,null,null,null,null,null,null,null,null,null,"SXGA_|_1280x1024x60_fps_12b_|_3p3V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"N16FFC_POK_VMON_EXT_UV",{"$f":"_xlfn.IFNA(MATCH(BN90,PWRCALC!AS:AS,0),0)","v":82},1,"on",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,284,0,"POKSA","_VMON_ER_VSYS",1,1,"on",1,"on",0.01,"on",1,"on",1,"on"]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,"SXGA_|_1280x1024x60_fps_12b_|_1p8V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"PGD_MAIN_CORE",{"$f":"_xlfn.IFNA(MATCH(BN91,PWRCALC!AS:AS,0),0)","v":83},1,"on",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,286,0,"PGD","_MAIN_CORE",1,1,"on",1,"on",0.01,"on",1,"on",1,"on"]
["LVCMOS IO","Mode","Utilization","Instances",null,null,null,null,null,null,null,null,null,null,"SXGA_|_1280x1024x30_fps_24b_|_3p3V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"ddr32_3733_ios_0",{"$f":"_xlfn.IFNA(MATCH(BN92,PWRCALC!AS:AS,0),0)","v":84},1.1000000000000001,"lpddr4_2400_32",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,288,0,"LP/DDR4-32 IO 3733","_0",1,0.44000000000000006,"lpddr4_3733_32",0.5,"lpddr4_3733_32",0.01,"lpddr4_3733_32",0.5,"lpddr4_3733_32",0.5,"lpddr4_3733_32"]
["WKUP I2C","unused",0,1,null,null,null,null,null,null,null,null,null,null,"SXGA_|_1280x1024x30_fps_24b_|_1p8V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"ABJSTBL5_multiple",{"$f":"_xlfn.IFNA(MATCH(BN93,PWRCALC!AS:AS,0),0)","v":85},1,"on",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,290,0,"PVT Sensor","_0",1,1,"on",1,"on",0.01,"on",1,"on",1,"on"]
["WKUP UART","unused",0,1,null,null,null,null,null,null,null,null,null,null,"SXGA_|_1280x1024x30_fps_18b_|_3p3V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"ABJSTBL5_multiple",{"$f":"_xlfn.IFNA(MATCH(BN94,PWRCALC!AS:AS,0),0)","v":85},1,"on",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,292,0,"PVT Sensor","_1",1,1,"on",1,"on",0.01,"on",1,"on",1,"on"]
["MCU I2C","unused",0,1,null,null,null,null,null,null,null,null,null,null,"SXGA_|_1280x1024x30_fps_18b_|_1p8V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"ABJSTBL5_multiple",{"$f":"_xlfn.IFNA(MATCH(BN95,PWRCALC!AS:AS,0),0)","v":85},1,"on",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,294,0,"PVT Sensor","_2",1,1,"on",1,"on",0.01,"on",1,"on",1,"on"]
["MCU UART","unused",0,1,null,null,null,null,null,null,null,null,null,null,"SXGA_|_1280x1024x30_fps_16b_|_3p3V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"N16FFC_HFXOSC_0",{"$f":"_xlfn.IFNA(MATCH(BN96,PWRCALC!AS:AS,0),0)","v":88},1,"on",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,296,0,"HFOSC","_0",1,1,"on",1,"on",0.01,"on",1,"on",1,"on"]
["MCU McSPI","unused",0,2,null,null,null,null,null,null,null,null,null,null,"SXGA_|_1280x1024x30_fps_16b_|_1p8V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"N16FFC_LFXOSC_0",{"$f":"_xlfn.IFNA(MATCH(BN97,PWRCALC!AS:AS,0),0)","v":89},1,"on",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,298,0,"LFOSC","_0",1,1,"on",1,"on",0.01,"on",1,"on",1,"on"]
["MCU MCAN","unused",0,2,null,null,null,null,null,null,null,null,null,null,"SXGA_|_1280x1024x30_fps_12b_|_3p3V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"N16FFC_RCOSC_0",{"$f":"_xlfn.IFNA(MATCH(BN98,PWRCALC!AS:AS,0),0)","v":90},1,"on",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,300,0,"RCOSC","_0",1,1,"on",1,"on",0.01,"on",1,"on",1,"on"]
["MCU GPIO","unused",0,1,null,null,null,null,null,null,null,null,null,null,"SXGA_|_1280x1024x30_fps_12b_|_1p8V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"_xlfn.IFNA(MATCH(BN99,PWRCALC!AS:AS,0),0)","v":0},0,0,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,302,0,"SerDes 10G Common","_0_C0",1,1,"1pll","","","","","","","",""]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,"WXGA_|_1280x800x60_fps_24b_|_3p3V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"_xlfn.IFNA(MATCH(BN100,PWRCALC!AS:AS,0),0)","v":0},0,0,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,304,0,"SerDes 10G Common","_1_C0",1,0,"disable","","","","","","","",""]
["LVCMOS IO","Mode","Utilization","Instances",null,null,null,null,null,null,null,null,null,null,"WXGA_|_1280x800x60_fps_24b_|_1p8V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"_xlfn.IFNA(MATCH(BN101,PWRCALC!AS:AS,0),0)","v":0},0,0,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,306,0,"SerDes 10G Lane","_0_L0",1,1,"8g","","","","","","","",""]
["MAIN GPIO","unused",0,2,null,null,null,null,null,null,null,null,null,null,"WXGA_|_1280x800x60_fps_18b_|_3p3V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"_xlfn.IFNA(MATCH(BN102,PWRCALC!AS:AS,0),0)","v":0},0,0,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,308,0,"SerDes 10G Lane","_1_L0",1,0,"disable","","","","","","","",""]
["MAIN I2C","unused",0,5,null,null,null,null,null,null,null,null,null,null,"WXGA_|_1280x800x60_fps_18b_|_1p8V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"sd0901_rx4_0",{"$f":"_xlfn.IFNA(MATCH(BN103,PWRCALC!AS:AS,0),0)","v":95},0.1,"1p5g4l",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,310,0,"DPHY 1.2 RX - 4L","_0",1,0,"ulps",0.1,"1p5g4l",0.01,"2p5g4l",0.1,"1p5g4l",0.1,"1p5g4l"]
["MAIN UART","unused",0,7,null,null,null,null,null,null,null,null,null,null,"WXGA_|_1280x800x60_fps_16b_|_3p3V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"_xlfn.IFNA(MATCH(BN104,PWRCALC!AS:AS,0),0)","v":0},0,0,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,312,0,"DPHY 1.2 RX - 4L","_1",1,0,"ulps","","","","","","","",""]
["MAIN McSPI","unused",0,3,null,null,null,null,null,null,null,null,null,null,"WXGA_|_1280x800x60_fps_16b_|_1p8V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"_xlfn.IFNA(MATCH(BN105,PWRCALC!AS:AS,0),0)","v":0},0,0,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,314,0,"DPHY 1.2 RX - 4L","_2",1,0,"ulps","","","","","","","",""]
["MAIN McASP","unused",0,5,null,null,null,null,null,null,null,null,null,null,"WXGA_|_1280x800x60_fps_12b_|_3p3V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"_xlfn.IFNA(MATCH(BN106,PWRCALC!AS:AS,0),0)","v":0},0,0,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,316,0,"DPHY 1.2 RX - 4L","_3",1,0,"ulps","","","","","","","",""]
["MAIN ECAP","unused",0,3,null,null,null,null,null,null,null,null,null,null,"WXGA_|_1280x800x60_fps_12b_|_1p8V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"sd0901_tx4_0",{"$f":"_xlfn.IFNA(MATCH(BN107,PWRCALC!AS:AS,0),0)","v":99},0,"ulps",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,318,0,"DPHY 1.2 TX - 4L","_0",1,0,"ulps","","","","","","","",""]
["MAIN EPWM","unused",0,3,null,null,null,null,null,null,null,null,null,null,"WXGA_|_1280x800x30_fps_24b_|_3p3V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"LVDSTS16LLBI1E_multiple",{"$f":"_xlfn.IFNA(MATCH(BN108,PWRCALC!AS:AS,0),0)","v":100},1,"oldi_dual_24b_modes",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,320,0,"LVDS IO","_multiple",10,0,"disabled",1,"oldi_dual_24b_modes",0.01,"oldi_dual_24b_modes",1,"oldi_dual_24b_modes",1,"oldi_dual_24b_modes"]
["MAIN EQEP","unused",0,3,null,null,null,null,null,null,null,null,null,null,"WXGA_|_1280x800x30_fps_24b_|_1p8V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"N16FFC_POR_0",{"$f":"_xlfn.IFNA(MATCH(BN109,PWRCALC!AS:AS,0),0)","v":101},1,"on",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,322,0,"POR","_0",1,1,"on",1,"on",0.01,"on",1,"on",1,"on"]
["MAIN MCAN","unused",0,2,null,null,null,null,null,null,null,null,null,null,"WXGA_|_1280x800x30_fps_24b_|_3p3V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"N16FFC_TEMP_DIODE_TOP_0",{"$f":"_xlfn.IFNA(MATCH(BN110,PWRCALC!AS:AS,0),0)","v":102},1,"on",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,324,0,"Temp Sensing Diode","_0",1,1,"on",1,"on",0.01,"on",1,"on",1,"on"]
["MAIN MMCSD1","unused",0,2,null,null,null,null,null,null,null,null,null,null,"WXGA_|_1280x800x30_fps_24b_|_1p8V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"PDBODPMACRO_0",{"$f":"_xlfn.IFNA(MATCH(BN111,PWRCALC!AS:AS,0),0)","v":103},1,"on",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,326,0,"ODP IO","_0",1,1,"on",1,"on",0.01,"on",1,"on",1,"on"]
["MAIN DSS 0: DPI","unused",0,1,null,null,null,null,null,null,null,null,null,null,"WXGA_|_1280x800x30_fps_16b_|_3p3V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"emmc51phy_top_emmc_0",{"$f":"_xlfn.IFNA(MATCH(BN112,PWRCALC!AS:AS,0),0)","v":104},1,"hs400",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,328,0,"Arasan HS400 8 bit","_emmc_0",1,0,"off",0,"off",0.01,"hs400",0,"off",0,"off"]
["MAIN FSS OSPI1 (QSPI)","unused",0,1,null,null,null,null,null,null,null,null,null,null,"WXGA_|_1280x800x30_fps_16b_|_1p8V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"PRWDWUWSWEWCDGSDIO_mmc_1",{"$f":"_xlfn.IFNA(MATCH(BN113,PWRCALC!AS:AS,0),0)","v":105},1,"hs200_200mbs",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,330,0,"SDIO - 1 bit","_mmc_1",7,0,"unused",0,"unused",0.01,"hs200_200mbs",0,"unused",0,"unused"]
["MAIN Ethernet","unused",0,2,null,null,null,null,null,null,null,null,null,null,"WXGA_|_1280x800x30_fps_12b_|_3p3V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"PRWDWUWSWEWCDGSDIO_mmc_2",{"$f":"_xlfn.IFNA(MATCH(BN114,PWRCALC!AS:AS,0),0)","v":106},1,"hs200_200mbs",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,332,0,"SDIO - 1 bit","_mmc_2",7,0,"unused",0,"unused",0.01,"hs200_200mbs",0,"unused",0,"unused"]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,"WXGA_|_1280x800x30_fps_12b_|_1p8V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"sd1000_0",{"$f":"_xlfn.IFNA(MATCH(BN115,PWRCALC!AS:AS,0),0)","v":107},1,"host_hs",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,334,0,"USB2 - PHY","_0",1,0,"sleep",0.5,"sleep",0.01,"host_fs",0.5,"sleep",0.5,"sleep"]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,"HD_|_1280x720x60_fps_24b_|_3p3V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"sd1000_1",{"$f":"_xlfn.IFNA(MATCH(BN116,PWRCALC!AS:AS,0),0)","v":108},1,"host_hs",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,336,0,"USB2 - PHY","_1",1,0,"sleep",0,"sleep",0.01,"host_fs",0,"sleep",0,"sleep"]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,"HD_|_1280x720x60_fps_24b_|_1p8V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"TODP16FFC18_C170915_0",{"$f":"_xlfn.IFNA(MATCH(BN117,PWRCALC!AS:AS,0),0)","v":109},1,"on",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,338,0,"ODP","_0",1,1,"on",1,"on",0.01,"on",1,"on",1,"on"]
["Caution:",null,null,null,null,null,null,null,null,null,null,null,null,null,"HD_|_1280x720x60_fps_24b_|_3p3V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"PVDD18MODEDET_Main",{"$f":"_xlfn.IFNA(MATCH(BN118,PWRCALC!AS:AS,0),0)","v":110},1,"on",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,340,0,"LVCMOS SD","_Main",9,1,"on",1,"on",0.01,"on",1,"on",1,"on"]
["This power estimation spreadsheet is subject to change. SoC power estimates provide approximate power and current consumption based on measured and simulated data; they are provided “as is” and are not guaranteed within a specified precision. Power consumption depends on electrical parameters, silicon process variations, environmental conditions, and uses cases running on the processor during operation. Actual power consumption should be verified in the real system. An end product’s SoC power, PDN integrity & thermal performance can vary depending on final use cases, features supported, software characteristics and system thermal design.  ",null,null,null,null,null,null,null,null,null,null,null,null,null,"HD_|_1280x720x60_fps_24b_|_1p8V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"canfd_0",{"$f":"_xlfn.IFNA(MATCH(BN119,PWRCALC!AS:AS,0),0)","v":125},1,"1mbs_3p3v",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,342,0,"CANFD LVCMOS IO","_0",1,0.5,"8mbs_3p3v",0.2,"1mbs_3p3v",0.01,"12mbs_3p3v",0.2,"1mbs_3p3v",0.2,"1mbs_3p3v"]
[{"$f":"\"Conditions: \"&Process&\" Process\"","v":"Conditions: Strong Process"},null,null,null,null,null,null,null,null,null,null,null,null,null,"HD_|_1280x720x60_fps_16b_|_3p3V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"canfd_1",{"$f":"_xlfn.IFNA(MATCH(BN120,PWRCALC!AS:AS,0),0)","v":126},0,"unused",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,344,0,"CANFD LVCMOS IO","_1",1,0,"off",0.2,"1mbs_3p3v",0.01,"12mbs_3p3v",0.2,"1mbs_3p3v",0.2,"1mbs_3p3v"]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,"HD_|_1280x720x60_fps_16b_|_1p8V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"canfd_mcu_0",{"$f":"_xlfn.IFNA(MATCH(BN121,PWRCALC!AS:AS,0),0)","v":127},1,"5mbs_3p3v",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,346,0,"CANFD LVCMOS IO","_mcu_0",1,0,"off",0,"unused",0.01,"12mbs_3p3v",0,"unused",0,"unused"]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,"HD_|_1280x720x60_fps_12b_|_3p3V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"canfd_mcu_1",{"$f":"_xlfn.IFNA(MATCH(BN122,PWRCALC!AS:AS,0),0)","v":128},0,"unused",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,348,0,"CANFD LVCMOS IO","_mcu_1",1,0,"off",0,"unused",0.01,"12mbs_3p3v",0,"unused",0,"unused"]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,"HD_|_1280x720x60_fps_12b_|_1p8V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"dpi_0",{"$f":"_xlfn.IFNA(MATCH(BN123,PWRCALC!AS:AS,0),0)","v":129},1,"HD_|_1280x720x60_fps_24b_|_3p3V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,350,0,"DPI LVCMOS IO","_0",1,0,"unused",1,"2K_|_2048x1080x60_fps_24b_|_3p3V",0.01,"UXGA_|_1600x1200x30_fps_16b_|_3p3V",1,"2K_|_2048x1080x60_fps_24b_|_3p3V",1,"2K_|_2048x1080x60_fps_24b_|_3p3V"]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,"HD_|_1280x720x30_fps_24b_|_3p3V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"ecap_0",{"$f":"_xlfn.IFNA(MATCH(BN124,PWRCALC!AS:AS,0),0)","v":130},0,"unused",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,352,0,"eCAP LVCMOS IO","_0",1,0.5,"capture_in_5m_3p3v",0,"unused",0.01,"pwm_out_5m_3p3v",0,"unused",0,"unused"]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,"HD_|_1280x720x30_fps_24b_|_1p8V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"ecap_1",{"$f":"_xlfn.IFNA(MATCH(BN125,PWRCALC!AS:AS,0),0)","v":131},0,"unused",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,354,0,"eCAP LVCMOS IO","_1",1,0,"off",0,"unused",0.01,"pwm_out_5m_3p3v",0,"unused",0,"unused"]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,"HD_|_1280x720x30_fps_24b_|_3p3V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"ecap_2",{"$f":"_xlfn.IFNA(MATCH(BN126,PWRCALC!AS:AS,0),0)","v":132},0,"unused",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,356,0,"eCAP LVCMOS IO","_2",1,0,"off",0,"unused",0.01,"pwm_out_5m_3p3v",0,"unused",0,"unused"]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,"HD_|_1280x720x30_fps_24b_|_1p8V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"epwm_0",{"$f":"_xlfn.IFNA(MATCH(BN127,PWRCALC!AS:AS,0),0)","v":133},1,"on_1p8v",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,358,0,"ePWM LVCMOS IO","_0",1,0,"unused",0.05,"on_1p8v",0.01,"on_3p3v",0.05,"on_1p8v",0.05,"on_1p8v"]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,"HD_|_1280x720x30_fps_16b_|_3p3V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"epwm_1",{"$f":"_xlfn.IFNA(MATCH(BN128,PWRCALC!AS:AS,0),0)","v":134},1,"on_1p8v",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,360,0,"ePWM LVCMOS IO","_1",1,0,"unused",0.05,"on_1p8v",0.01,"on_3p3v",0.05,"on_1p8v",0.05,"on_1p8v"]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,"HD_|_1280x720x30_fps_16b_|_1p8V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"epwm_2",{"$f":"_xlfn.IFNA(MATCH(BN129,PWRCALC!AS:AS,0),0)","v":135},1,"on_1p8v",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,362,0,"ePWM LVCMOS IO","_2",1,0,"unused",0.05,"on_1p8v",0.01,"on_3p3v",0.05,"on_1p8v",0.05,"on_1p8v"]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,"HD_|_1280x720x30_fps_12b_|_3p3V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"eqep_0",{"$f":"_xlfn.IFNA(MATCH(BN130,PWRCALC!AS:AS,0),0)","v":136},0,"unused",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,364,0,"eQEP LVCMOS IO","_0",1,0,"unused",0,"off",0.01,"on_3p3v",0,"off",0,"off"]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,"HD_|_1280x720x30_fps_12b_|_1p8V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"eqep_1",{"$f":"_xlfn.IFNA(MATCH(BN131,PWRCALC!AS:AS,0),0)","v":137},0,"unused",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,366,0,"eQEP LVCMOS IO","_1",1,0,"unused",0,"off",0.01,"on_3p3v",0,"off",0,"off"]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,"XGA_|_1024x768x60_fps_24b_|_3p3V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"eqep_2",{"$f":"_xlfn.IFNA(MATCH(BN132,PWRCALC!AS:AS,0),0)","v":138},0,"unused",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,368,{"$f":"INDIRECT(ADDRESS(2,DA132))","v":0},"eQEP LVCMOS IO","_2",1,0,"unused",0,"off",0.01,"on_3p3v",0,"off",0,"off"]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,"XGA_|_1024x768x60_fps_24b_|_1p8V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"ethernet_port_0",{"$f":"_xlfn.IFNA(MATCH(BN133,PWRCALC!AS:AS,0),0)","v":139},1,"rgmii_1000_1p8v",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"2+DA132","v":370},0,"Ethernet LVCMOS IO","_port_0",1,0.25,"rgmii_1000_3p3v",0.2,"rgmii_1000_1p8v",0.01,"rgmii_1000_3p3v",0.2,"rgmii_1000_1p8v",0.2,"rgmii_1000_1p8v"]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,"XGA_|_1024x768x60_fps_24b_|_3p3V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"ethernet_port_1",{"$f":"_xlfn.IFNA(MATCH(BN134,PWRCALC!AS:AS,0),0)","v":140},1,"rgmii_1000_1p8v",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,372,0,"Ethernet LVCMOS IO","_port_1",1,0.25,"rgmii_1000_3p3v",0.2,"rgmii_1000_1p8v",0.01,"rgmii_1000_3p3v",0.2,"rgmii_1000_1p8v",0.2,"rgmii_1000_1p8v"]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,"XGA_|_1024x768x60_fps_24b_|_1p8V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"gpio_0",{"$f":"_xlfn.IFNA(MATCH(BN135,PWRCALC!AS:AS,0),0)","v":141},1,"1mbs_1p8v_20pf",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,374,0,"GPIO LVCMOS IO","_0",1,0,"unused",0.1,"1mbs_1p8v_20pf",0.01,"1mbs_3p3v_20pf",0.1,"1mbs_1p8v_20pf",0.1,"1mbs_1p8v_20pf"]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,"XGA_|_1024x768x60_fps_16b_|_3p3V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"gpio_1",{"$f":"_xlfn.IFNA(MATCH(BN136,PWRCALC!AS:AS,0),0)","v":142},1,"1mbs_1p8v_20pf",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,376,0,"GPIO LVCMOS IO","_1",1,0,"unused",0.1,"1mbs_3p3v_20pf",0.01,"1mbs_3p3v_20pf",0.1,"1mbs_3p3v_20pf",0.1,"1mbs_3p3v_20pf"]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,"XGA_|_1024x768x60_fps_16b_|_1p8V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"gpio_mcu",{"$f":"_xlfn.IFNA(MATCH(BN137,PWRCALC!AS:AS,0),0)","v":143},1,"1mbs_3p3v_20pf",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,378,0,"GPIO LVCMOS IO","_mcu",1,0,"unused",0.1,"1mbs_3p3v_20pf",0.01,"1mbs_3p3v_20pf",0.1,"1mbs_3p3v_20pf",0.1,"1mbs_3p3v_20pf"]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,"XGA_|_1024x768x60_fps_12b_|_3p3V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"gpmc_0",{"$f":"_xlfn.IFNA(MATCH(BN138,PWRCALC!AS:AS,0),0)","v":144},0,"unused",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,380,0,"GPMC LVCMOS IO","_0",1,0,"unused",0,"unused",0.01,"16b_133_MHz_3p3V",0,"unused",0,"unused"]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,"XGA_|_1024x768x60_fps_12b_|_1p8V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"i2c_0",{"$f":"_xlfn.IFNA(MATCH(BN139,PWRCALC!AS:AS,0),0)","v":145},1,"i2c_400k_3p3v",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,382,0,"I2C LVCMOS IO","_0",1,0.5,"i2c_400k_3p3v",0.05,"i2c_400k_3p3v",0.01,"i2c_400k_3p3v",0.05,"i2c_400k_3p3v",0.05,"i2c_400k_3p3v"]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,"WVGA_|_854x480x60_fps_24b_|_3p3V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"i2c_1",{"$f":"_xlfn.IFNA(MATCH(BN140,PWRCALC!AS:AS,0),0)","v":146},1,"i2c_400k_3p3v",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,384,0,"I2C LVCMOS IO","_1",1,0,"unused",0.05,"i2c_400k_3p3v",0.01,"i2c_400k_3p3v",0.05,"i2c_400k_3p3v",0.05,"i2c_400k_3p3v"]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,"WVGA_|_854x480x60_fps_24b_|_1p8V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"i2c_2",{"$f":"_xlfn.IFNA(MATCH(BN141,PWRCALC!AS:AS,0),0)","v":147},{"$f":"IFERROR(INDIRECT(ADDRESS($BO141,COLUMN(S$1),,,\"PWRCALC\")),0)","v":1},{"$f":"IFERROR(INDIRECT(ADDRESS($BO141,COLUMN(R$1),,,\"PWRCALC\")),0)","v":"i2c_400k_3p3v"},null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,386,0,"I2C LVCMOS IO","_2",1,0,"unused",0.05,"i2c_400k_3p3v",0.01,"i2c_400k_3p3v",0.05,"i2c_400k_3p3v",0.05,"i2c_400k_3p3v"]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,"WVGA_|_854x480x60_fps_24b_|_3p3V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"i2c_3",{"$f":"_xlfn.IFNA(MATCH(BN142,PWRCALC!AS:AS,0),0)","v":148},0,"unused",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,388,0,"I2C LVCMOS IO","_3",1,0,"unused",0,"off",0.01,"i2c_400k_3p3v",0,"off",0,"off"]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,"WVGA_|_854x480x60_fps_24b_|_1p8V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"_xlfn.IFNA(MATCH(BN143,PWRCALC!AS:AS,0),0)","v":0},0,0,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,390,0,"I2C LVCMOS IO","_4",1,null,null,"","","","","","","",""]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,"WVGA_|_854x480x60_fps_16b_|_3p3V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"i2c_od_mcu_0",{"$f":"_xlfn.IFNA(MATCH(BN144,PWRCALC!AS:AS,0),0)","v":150},1,"i2c_400k_3p3v",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,392,0,"I2C_OD LVCMOS IO","_mcu_0",1,0.5,"i2c_400k_3p3v",0,"off",0.01,"i2c_3p4m_1p8v",0,"off",0,"off"]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,"WVGA_|_854x480x60_fps_16b_|_1p8V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"i2c_od_wkp_0",{"$f":"_xlfn.IFNA(MATCH(BN145,PWRCALC!AS:AS,0),0)","v":151},1,"i2c_400k_3p3v",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,394,0,"I2C_OD LVCMOS IO","_wkp_0",1,0,"unused",0.05,"i2c_400k_3p3v",0.01,"i2c_3p4m_1p8v",0.05,"i2c_400k_3p3v",0.05,"i2c_400k_3p3v"]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,"WVGA_|_854x480x60_fps_12b_|_3p3V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"mcasp_0",{"$f":"_xlfn.IFNA(MATCH(BN146,PWRCALC!AS:AS,0),0)","v":152},1,"16Ch_TX_48_ksps_24b_3p3v",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,396,0,"McASP LVCMOS IO","_0",1,0,"unused",1,"16Ch_TX_48_ksps_24b_3p3v",0.01,"16Ch_TX_48_ksps_24b_3p3v",1,"16Ch_TX_48_ksps_24b_3p3v",1,"16Ch_TX_48_ksps_24b_3p3v"]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,"WVGA_|_854x480x60_fps_12b_|_1p8V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"mcasp_1",{"$f":"_xlfn.IFNA(MATCH(BN147,PWRCALC!AS:AS,0),0)","v":153},1,"16Ch_TX_48_ksps_24b_3p3v",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,398,0,"McASP LVCMOS IO","_1",1,0,"unused",1,"16Ch_TX_48_ksps_24b_3p3v",0.01,"16Ch_TX_48_ksps_24b_3p3v",1,"16Ch_TX_48_ksps_24b_3p3v",1,"16Ch_TX_48_ksps_24b_3p3v"]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,"SVGA_|_800x600x60_fps_24b_|_3p3V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"mcasp_2",{"$f":"_xlfn.IFNA(MATCH(BN148,PWRCALC!AS:AS,0),0)","v":154},1,"16Ch_TX_48_ksps_24b_3p3v",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,400,0,"McASP LVCMOS IO","_2",1,0,"unused",1,"16Ch_TX_48_ksps_24b_3p3v",0.01,"16Ch_TX_48_ksps_24b_3p3v",1,"16Ch_TX_48_ksps_24b_3p3v",1,"16Ch_TX_48_ksps_24b_3p3v"]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,"SVGA_|_800x600x60_fps_24b_|_1p8V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"_xlfn.IFNA(MATCH(BN149,PWRCALC!AS:AS,0),0)","v":0},0,0,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,402,0,"McASP LVCMOS IO","_3",1,0,"unused","","","","","","","",""]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,"SVGA_|_800x600x60_fps_24b_|_3p3V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,{"$f":"_xlfn.IFNA(MATCH(BN150,PWRCALC!AS:AS,0),0)","v":0},0,0,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,404,0,"McASP LVCMOS IO","_4",1,0,"unused","","","","","","","",""]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,"SVGA_|_800x600x60_fps_24b_|_1p8V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"fssul_0",{"$f":"_xlfn.IFNA(MATCH(BN151,PWRCALC!AS:AS,0),0)","v":157},1,"ospi_ddr_controller_133_3p3v",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,406,0,"FSSUL LVCMOS IO","_0",1,0.2,"ospi_sdr_controller_133_3p3v",1,"ospi_ddr_controller_133_3p3v",0.01,"ospi_ddr_controller_133_3p3v",1,"ospi_ddr_controller_133_3p3v",1,"ospi_ddr_controller_133_3p3v"]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,"SVGA_|_800x600x60_fps_16b_|_3p3V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"spi_0",{"$f":"_xlfn.IFNA(MATCH(BN152,PWRCALC!AS:AS,0),0)","v":158},1,"Controller_3.125_Mbaud_3p3v",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,408,0,"SPI LVCMOS IO","_0",1,0.5,"Controller_6.25_Mbaud_3p3v",0,"unused",0.01,"Controller_25_Mbaud_3p3v",0,"unused",0,"unused"]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,"SVGA_|_800x600x60_fps_16b_|_1p8V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"spi_1",{"$f":"_xlfn.IFNA(MATCH(BN153,PWRCALC!AS:AS,0),0)","v":159},1,"Controller_3.125_Mbaud_3p3v",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,410,0,"SPI LVCMOS IO","_1",1,0,"unused",0,"unused",0.01,"Controller_25_Mbaud_3p3v",0,"unused",0,"unused"]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,"SVGA_|_800x600x60_fps_12b_|_3p3V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"spi_2",{"$f":"_xlfn.IFNA(MATCH(BN154,PWRCALC!AS:AS,0),0)","v":160},1,"Controller_3.125_Mbaud_3p3v",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,412,0,"SPI LVCMOS IO","_2",1,0,"unused",0,"unused",0.01,"Controller_25_Mbaud_3p3v",0,"unused",0,"unused"]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,"SVGA_|_800x600x60_fps_12b_|_1p8V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"spi_mcu_0",{"$f":"_xlfn.IFNA(MATCH(BN155,PWRCALC!AS:AS,0),0)","v":161},1,"Controller_2.083_Mbaud_3p3v",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,414,0,"SPI LVCMOS IO","_mcu_0",1,0,"unused",0.1,"Controller_2.083_Mbaud_3p3v",0.01,"Controller_25_Mbaud_3p3v",0.1,"Controller_2.083_Mbaud_3p3v",0.1,"Controller_2.083_Mbaud_3p3v"]
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[null,null,null,null,null,null,null,null,null,null,null,null,null,null,"SD_|_640x480x60_fps_24b_|_3p3V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"uart_2",{"$f":"_xlfn.IFNA(MATCH(BN158,PWRCALC!AS:AS,0),0)","v":164},1,"3p6m_1p8v",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,420,0,"UART LVCMOS IO","_2",1,0,"unused",0.05,"3p6m_1p8v",0.01,"3p6m_1p8v",0.05,"3p6m_1p8v",0.05,"3p6m_1p8v"]
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[null,null,null,null,null,null,null,null,null,null,null,null,null,null,"SD_|_640x480x60_fps_16b_|_3p3V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"uart_4",{"$f":"_xlfn.IFNA(MATCH(BN160,PWRCALC!AS:AS,0),0)","v":166},1,"3p6m_1p8v",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,424,0,"UART LVCMOS IO","_4",1,0,"unused",0,"unused",0.01,"3p6m_1p8v",0,"unused",0,"unused"]
[null,null,null,null,null,null,null,null,null,null,null,null,null,null,"SD_|_640x480x60_fps_16b_|_1p8V",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"uart_5",{"$f":"_xlfn.IFNA(MATCH(BN161,PWRCALC!AS:AS,0),0)","v":167},0,"unused",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,426,0,"UART LVCMOS IO","_5",1,0,"unused",0,"unused",0.01,"3p6m_1p8v",0,"unused",0,"unused"]
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[null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,"sam67_wiz16b8m4cdt3_wrap_0",{"$f":"_xlfn.IFNA(MATCH(BN168,PWRCALC!AS:AS,0),0)","v":173},0,"ulps",null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,null,440,0,"sam67_wiz16b8m4cdt3_wrap",null,null,null,"unused",0,0,0.01,0,0,0,0,0]
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