diff --git a/arch/arm/mach-k3/include/mach/j721e_qos_params.h b/arch/arm/mach-k3/include/mach/j721e_qos_params.h
index 3f46a6bed5..41912f812c 100644
--- a/arch/arm/mach-k3/include/mach/j721e_qos_params.h
+++ b/arch/arm/mach-k3/include/mach/j721e_qos_params.h
@@ -27,6 +27,13 @@
 #define QOS_R5FSS0_CORE0_MEM_WR_ATYPE        (0U)
 #define QOS_R5FSS0_CORE1_MEM_RD_ATYPE        (0U)
 #define QOS_R5FSS0_CORE1_MEM_WR_ATYPE        (0U)
+#define QOS_R5FSS1_CORE0_MEM_RD_ATYPE        (0U)
+#define QOS_R5FSS1_CORE0_MEM_WR_ATYPE        (0U)
+#define QOS_R5FSS1_CORE1_MEM_RD_ATYPE        (0U)
+#define QOS_R5FSS1_CORE1_MEM_WR_ATYPE        (0U)
+#define QOS_MCU_R5FSS0_CORE0_MEM_RD_ATYPE    (0U)
+#define QOS_MCU_R5FSS0_CORE0_MEM_WR_ATYPE    (0U)
+
 
 #define QOS_VPAC0_LDC0_ORDER_ID              (1U)
 #define QOS_C66SS0_MDMA_ORDER_ID             (5U)
@@ -45,6 +52,12 @@
 #define QOS_R5FSS0_CORE0_MEM_WR_ORDER_ID     (11U)
 #define QOS_R5FSS0_CORE1_MEM_RD_ORDER_ID     (11U)
 #define QOS_R5FSS0_CORE1_MEM_WR_ORDER_ID     (11U)
+#define QOS_R5FSS1_CORE0_MEM_RD_ORDER_ID     (11U)
+#define QOS_R5FSS1_CORE0_MEM_WR_ORDER_ID     (11U)
+#define QOS_R5FSS1_CORE1_MEM_RD_ORDER_ID     (11U)
+#define QOS_R5FSS1_CORE1_MEM_WR_ORDER_ID     (11U)
+#define QOS_MCU_R5FSS0_CORE0_MEM_RD_ORDER_ID (11U)
+#define QOS_MCU_R5FSS0_CORE0_MEM_WR_ORDER_ID (11U)
 
 #define QOS_DSS0_DMA_PRIORITY                (1U)
 #define QOS_DSS0_FBDC_PRIORITY               (1U)
@@ -65,6 +78,12 @@
 #define QOS_R5FSS0_CORE0_MEM_WR_PRIORITY     (2U)
 #define QOS_R5FSS0_CORE1_MEM_RD_PRIORITY     (2U)
 #define QOS_R5FSS0_CORE1_MEM_WR_PRIORITY     (2U)
+#define QOS_R5FSS1_CORE0_MEM_RD_PRIORITY     (2U)
+#define QOS_R5FSS1_CORE0_MEM_WR_PRIORITY     (2U)
+#define QOS_R5FSS1_CORE1_MEM_RD_PRIORITY     (2U)
+#define QOS_R5FSS1_CORE1_MEM_WR_PRIORITY     (2U)
+#define QOS_MCU_R5FSS0_CORE0_MEM_RD_PRIORITY (2U)
+#define QOS_MCU_R5FSS0_CORE0_MEM_WR_PRIORITY (2U)
 
 #define QOS_ATYPE_MASK			0x30000000
 #define QOS_VIRTID_MASK			0x0fff0000
@@ -87,6 +106,20 @@
 #define QOS_C66SS1_MDMA_CBASS_GRP_MAP2(j)           (QOS_C66SS1_MDMA + 0x4 + (j) * 8)
 #define QOS_C66SS1_MDMA_CBASS_MAP(i)                (QOS_C66SS1_MDMA + 0x100 + (i) * 4)
 
+#define QOS_MCU_R5FSS0_CORE0_MEM_RD                     0x45d84000
+#define QOS_MCU_R5FSS0_CORE0_MEM_RD_NUM_J_CH            1
+#define QOS_MCU_R5FSS0_CORE0_MEM_RD_NUM_I_CH            1
+#define QOS_MCU_R5FSS0_CORE0_MEM_RD_CBASS_GRP_MAP1(j)   (QOS_MCU_R5FSS0_CORE0_MEM_RD + 0x0 + (j) * 8)
+#define QOS_MCU_R5FSS0_CORE0_MEM_RD_CBASS_GRP_MAP2(j)   (QOS_MCU_R5FSS0_CORE0_MEM_RD + 0x4 + (j) * 8)
+#define QOS_MCU_R5FSS0_CORE0_MEM_RD_CBASS_MAP(i)        (QOS_MCU_R5FSS0_CORE0_MEM_RD + 0x100 + (i) * 4)
+
+#define QOS_MCU_R5FSS0_CORE0_MEM_WR                     0x45d84800
+#define QOS_MCU_R5FSS0_CORE0_MEM_WR_NUM_J_CH            1
+#define QOS_MCU_R5FSS0_CORE0_MEM_WR_NUM_I_CH            1
+#define QOS_MCU_R5FSS0_CORE0_MEM_WR_CBASS_GRP_MAP1(j)   (QOS_MCU_R5FSS0_CORE0_MEM_WR + 0x0 + (j) * 8)
+#define QOS_MCU_R5FSS0_CORE0_MEM_WR_CBASS_GRP_MAP2(j)   (QOS_MCU_R5FSS0_CORE0_MEM_WR + 0x4 + (j) * 8)
+#define QOS_MCU_R5FSS0_CORE0_MEM_WR_CBASS_MAP(i)        (QOS_MCU_R5FSS0_CORE0_MEM_WR + 0x100 + (i) * 4)
+
 #define QOS_R5FSS0_CORE0_MEM_RD                     0x45d84000
 #define QOS_R5FSS0_CORE0_MEM_RD_NUM_J_CH            3
 #define QOS_R5FSS0_CORE0_MEM_RD_NUM_I_CH            1
@@ -115,6 +148,36 @@
 #define QOS_R5FSS0_CORE1_MEM_WR_CBASS_GRP_MAP2(j)   (QOS_R5FSS0_CORE1_MEM_WR + 0x4 + (j) * 8)
 #define QOS_R5FSS0_CORE1_MEM_WR_CBASS_MAP(i)        (QOS_R5FSS0_CORE1_MEM_WR + 0x100 + (i) * 4)
 
+#define QOS_R5FSS1_CORE0_MEM_RD                     0x45d85000
+#define QOS_R5FSS1_CORE0_MEM_RD_NUM_J_CH            3
+#define QOS_R5FSS1_CORE0_MEM_RD_NUM_I_CH            1
+#define QOS_R5FSS1_CORE0_MEM_RD_CBASS_GRP_MAP1(j)   (QOS_R5FSS1_CORE0_MEM_RD + 0x0 + (j) * 8)
+#define QOS_R5FSS1_CORE0_MEM_RD_CBASS_GRP_MAP2(j)   (QOS_R5FSS1_CORE0_MEM_RD + 0x4 + (j) * 8)
+#define QOS_R5FSS1_CORE0_MEM_RD_CBASS_MAP(i)        (QOS_R5FSS1_CORE0_MEM_RD + 0x100 + (i) * 4)
+
+#define QOS_R5FSS1_CORE1_MEM_RD                     0x45d85400
+#define QOS_R5FSS1_CORE1_MEM_RD_NUM_J_CH            3
+#define QOS_R5FSS1_CORE1_MEM_RD_NUM_I_CH            1
+#define QOS_R5FSS1_CORE1_MEM_RD_CBASS_GRP_MAP1(j)   (QOS_R5FSS1_CORE1_MEM_RD + 0x0 + (j) * 8)
+#define QOS_R5FSS1_CORE1_MEM_RD_CBASS_GRP_MAP2(j)   (QOS_R5FSS1_CORE1_MEM_RD + 0x4 + (j) * 8)
+#define QOS_R5FSS1_CORE1_MEM_RD_CBASS_MAP(i)        (QOS_R5FSS1_CORE1_MEM_RD + 0x100 + (i) * 4)
+
+#define QOS_R5FSS1_CORE0_MEM_WR                     0x45d85800
+#define QOS_R5FSS1_CORE0_MEM_WR_NUM_J_CH            3
+#define QOS_R5FSS1_CORE0_MEM_WR_NUM_I_CH            1
+#define QOS_R5FSS1_CORE0_MEM_WR_CBASS_GRP_MAP1(j)   (QOS_R5FSS1_CORE0_MEM_WR + 0x0 + (j) * 8)
+#define QOS_R5FSS1_CORE0_MEM_WR_CBASS_GRP_MAP2(j)   (QOS_R5FSS1_CORE0_MEM_WR + 0x4 + (j) * 8)
+#define QOS_R5FSS1_CORE0_MEM_WR_CBASS_MAP(i)        (QOS_R5FSS1_CORE0_MEM_WR + 0x100 + (i) * 4)
+
+#define QOS_R5FSS1_CORE1_MEM_WR                     0x45d85C00
+#define QOS_R5FSS1_CORE1_MEM_WR_NUM_J_CH            3
+#define QOS_R5FSS1_CORE1_MEM_WR_NUM_I_CH            1
+#define QOS_R5FSS1_CORE1_MEM_WR_CBASS_GRP_MAP1(j)   (QOS_R5FSS1_CORE1_MEM_WR + 0x0 + (j) * 8)
+#define QOS_R5FSS1_CORE1_MEM_WR_CBASS_GRP_MAP2(j)   (QOS_R5FSS1_CORE1_MEM_WR + 0x4 + (j) * 8)
+#define QOS_R5FSS1_CORE1_MEM_WR_CBASS_MAP(i)        (QOS_R5FSS1_CORE1_MEM_WR + 0x100 + (i) * 4)
+
+
+
 #define QOS_ENCODER0_WR                             0x45dc1000
 #define QOS_ENCODER0_WR_NUM_J_CH                    2
 #define QOS_ENCODER0_WR_NUM_I_CH                    5
@@ -218,4 +281,4 @@
 #define NAVSS0_NBSS_NB0_CFG_NB_THREADMAP            (NAVSS0_NBSS_NB0_CFG_MMRS + 0x10)
 #define NAVSS0_NBSS_NB1_CFG_NB_THREADMAP            (NAVSS0_NBSS_NB1_CFG_MMRS + 0x10)
 
-#endif
\ No newline at end of file
+#endif
diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c
index 2fb22a32ca..34550237e8 100644
--- a/arch/arm/mach-k3/j721e_init.c
+++ b/arch/arm/mach-k3/j721e_init.c
@@ -465,6 +465,72 @@ void setup_main_r5f_qos(void)
 		writel((QOS_R5FSS0_CORE1_MEM_WR_ATYPE << 28) | (QOS_R5FSS0_CORE1_MEM_WR_PRIORITY << 12) | (QOS_R5FSS0_CORE1_MEM_RD_ORDER_ID << 4), (uintptr_t)QOS_R5FSS0_CORE1_MEM_WR_CBASS_MAP(channel));
 	}
 
+	/* R5FSS1 core0 - read */
+	for (group = 0; group < QOS_R5FSS1_CORE0_MEM_RD_NUM_J_CH; ++group) {
+		writel(0x76543210, (uintptr_t)QOS_R5FSS1_CORE0_MEM_RD_CBASS_GRP_MAP1(group));
+		writel(0xfedcba98, (uintptr_t)QOS_R5FSS1_CORE0_MEM_RD_CBASS_GRP_MAP2(group));
+	}
+
+	for (channel = 0; channel < QOS_R5FSS1_CORE0_MEM_RD_NUM_I_CH; ++channel) {
+
+		writel((QOS_R5FSS1_CORE0_MEM_RD_ATYPE << 28) | (QOS_R5FSS1_CORE0_MEM_RD_PRIORITY << 12) | (QOS_R5FSS1_CORE0_MEM_RD_ORDER_ID << 4), (uintptr_t)QOS_R5FSS1_CORE0_MEM_RD_CBASS_MAP(channel));
+	}
+
+	/* R5FSS1 core0 - write */
+	for (group = 0; group < QOS_R5FSS1_CORE0_MEM_WR_NUM_J_CH; ++group) {
+		writel(0x76543210, (uintptr_t)QOS_R5FSS1_CORE0_MEM_WR_CBASS_GRP_MAP1(group));
+		writel(0xfedcba98, (uintptr_t)QOS_R5FSS1_CORE0_MEM_WR_CBASS_GRP_MAP2(group));
+	}
+
+	for (channel = 0; channel < QOS_R5FSS1_CORE0_MEM_WR_NUM_I_CH; ++channel) {
+
+		writel((QOS_R5FSS1_CORE0_MEM_WR_ATYPE << 28) | (QOS_R5FSS1_CORE0_MEM_WR_PRIORITY << 12) | (QOS_R5FSS1_CORE0_MEM_RD_ORDER_ID << 4), (uintptr_t)QOS_R5FSS1_CORE0_MEM_WR_CBASS_MAP(channel));
+	}
+
+	/* R5FSS1 core1 - read */
+	for (group = 0; group < QOS_R5FSS1_CORE1_MEM_RD_NUM_J_CH; ++group) {
+		writel(0x76543210, (uintptr_t)QOS_R5FSS1_CORE1_MEM_RD_CBASS_GRP_MAP1(group));
+		writel(0xfedcba98, (uintptr_t)QOS_R5FSS1_CORE1_MEM_RD_CBASS_GRP_MAP2(group));
+	}
+
+	for (channel = 0; channel < QOS_R5FSS1_CORE1_MEM_RD_NUM_I_CH; ++channel) {
+
+		writel((QOS_R5FSS1_CORE1_MEM_RD_ATYPE << 28) | (QOS_R5FSS1_CORE1_MEM_RD_PRIORITY << 12) | (QOS_R5FSS1_CORE0_MEM_RD_ORDER_ID << 4), (uintptr_t)QOS_R5FSS1_CORE1_MEM_RD_CBASS_MAP(channel));
+	}
+
+	/* R5FSS1 core1 - write */
+	for (group = 0; group < QOS_R5FSS1_CORE1_MEM_WR_NUM_J_CH; ++group) {
+		writel(0x76543210, (uintptr_t)QOS_R5FSS1_CORE1_MEM_WR_CBASS_GRP_MAP1(group));
+		writel(0xfedcba98, (uintptr_t)QOS_R5FSS1_CORE1_MEM_WR_CBASS_GRP_MAP2(group));
+	}
+
+	for (channel = 0; channel < QOS_R5FSS1_CORE1_MEM_WR_NUM_I_CH; ++channel) {
+
+		writel((QOS_R5FSS1_CORE1_MEM_WR_ATYPE << 28) | (QOS_R5FSS1_CORE1_MEM_WR_PRIORITY << 12) | (QOS_R5FSS1_CORE1_MEM_RD_ORDER_ID << 4), (uintptr_t)QOS_R5FSS1_CORE1_MEM_WR_CBASS_MAP(channel));
+	}
+
+	/* MCU_R5FSS0 core0 - read */
+	for (group = 0; group < QOS_MCU_R5FSS0_CORE0_MEM_RD_NUM_J_CH; ++group) {
+		writel(0x76543210, (uintptr_t)QOS_MCU_R5FSS0_CORE0_MEM_RD_CBASS_GRP_MAP1(group));
+		writel(0xfedcba98, (uintptr_t)QOS_MCU_R5FSS0_CORE0_MEM_RD_CBASS_GRP_MAP2(group));
+	}
+
+	for (channel = 0; channel < QOS_MCU_R5FSS0_CORE0_MEM_RD_NUM_I_CH; ++channel) {
+
+		writel((QOS_MCU_R5FSS0_CORE0_MEM_RD_ATYPE << 28) | (QOS_MCU_R5FSS0_CORE0_MEM_RD_PRIORITY << 12) | (QOS_MCU_R5FSS0_CORE0_MEM_RD_ORDER_ID << 4), (uintptr_t)QOS_MCU_R5FSS0_CORE0_MEM_RD_CBASS_MAP(channel));
+	}
+
+	/* MCU_R5FSS0 core0 - write */
+	for (group = 0; group < QOS_MCU_R5FSS0_CORE0_MEM_WR_NUM_J_CH; ++group) {
+		writel(0x76543210, (uintptr_t)QOS_MCU_R5FSS0_CORE0_MEM_WR_CBASS_GRP_MAP1(group));
+		writel(0xfedcba98, (uintptr_t)QOS_MCU_R5FSS0_CORE0_MEM_WR_CBASS_GRP_MAP2(group));
+	}
+
+	for (channel = 0; channel < QOS_MCU_R5FSS0_CORE0_MEM_WR_NUM_I_CH; ++channel) {
+
+		writel((QOS_MCU_R5FSS0_CORE0_MEM_WR_ATYPE << 28) | (QOS_MCU_R5FSS0_CORE0_MEM_WR_PRIORITY << 12) | (QOS_MCU_R5FSS0_CORE0_MEM_RD_ORDER_ID << 4), (uintptr_t)QOS_MCU_R5FSS0_CORE0_MEM_WR_CBASS_MAP(channel));
+	}
+
 }
 
 void board_init_f(ulong dummy)
