FILE COMPARISON Produced: 12/6/2021 6:53:53 PM Mode: Just Differences Left file: C:\Users\a0207867\TI Drive\AM64x\customers\Dominic\custom_lpddr4_0_03.dtsi Right file: C:\Users\a0207867\TI Drive\AM64x\customers\Dominic\custom_lpddr4_0_08_10_cloud.dtsi -+ * This file was generated with the * AM64x SysConfig DDR Subsystem Register Configuration Tool v0.08.10 * Mon Dec 06 2021 09:28:03 GMT+0100 (Mitteleuropäische Normalzeit) * DDR Type: LPDDR4 ------------------------------------------------------------------------ ------------------------------------------------------------------------ #define DDRSS_CTL_225_DATA 0x00000031 <> #define DDRSS_CTL_225_DATA 0x000000B1 #define DDRSS_CTL_226_DATA 0x00000031 #define DDRSS_CTL_226_DATA 0x000000B1 [James] This enables Write DBI in the LPDDR4 for FSP1. Enabling write DBI helps to improve power supply noise on the board to improve overall signal integrity ------------------------------------------------------------------------ ------------------------------------------------------------------------ #define DDRSS_CTL_228_DATA 0x00000031 <> #define DDRSS_CTL_228_DATA 0x000000B1 #define DDRSS_CTL_229_DATA 0x00000031 #define DDRSS_CTL_229_DATA 0x000000B1 [James] Similar to above, for FSP2 (both ranks). Note we only support one FSP at this time (FSP2), and only support one rank, but the change were made to keep consistency ------------------------------------------------------------------------ ------------------------------------------------------------------------ #define DDRSS_CTL_254_DATA 0x66006666 <> #define DDRSS_CTL_254_DATA 0x46004646 #define DDRSS_CTL_255_DATA 0x00002766 #define DDRSS_CTL_255_DATA 0x00002746 [James] This changes CA_ODT in the LPDDR4 device to 60ohm. The 4 changes are for both FSPs and both ranks. This was a result of additional SI simulations for our SK board which revealed this was a more optimal setting ------------------------------------------------------------------------ ------------------------------------------------------------------------ #define DDRSS_CTL_332_DATA 0x00000000 <> #define DDRSS_CTL_332_DATA 0x00000001 [James] This enables Write DBI in the controller ------------------------------------------------------------------------ ------------------------------------------------------------------------ #define DDRSS_PI_223_DATA 0x01000301 <> #define DDRSS_PI_223_DATA 0x01000101 [James] This change disables periodic write DQ leveling for F0 (init frequency). This periodic leveling was affecting realtime performance in some application tests, and we have determined that enabling it isn't necessary for AM64x ------------------------------------------------------------------------ ------------------------------------------------------------------------ #define DDRSS_PI_226_DATA 0x01000301 <> #define DDRSS_PI_226_DATA 0x01000101 [James] Disables periodic write DQ leveling for FSP1 ------------------------------------------------------------------------ ------------------------------------------------------------------------ #define DDRSS_PI_229_DATA 0x01000301 <> #define DDRSS_PI_229_DATA 0x01000101 [James] Disables periodic write DQ leveling for FSP2 ------------------------------------------------------------------------ ------------------------------------------------------------------------ #define DDRSS_PI_308_DATA 0x00000031 <> #define DDRSS_PI_308_DATA 0x000000B1 [James] The PI is used for init and training and will have similar settings to the controller. This is the new setting that enabled write DBI for FSP1 (as described above) ------------------------------------------------------------------------ ------------------------------------------------------------------------ #define DDRSS_PI_311_DATA 0x66000000 <> #define DDRSS_PI_311_DATA 0x46000000 [James] This is a result of the CA_ODT change as described above for FSP1 and rank0 ------------------------------------------------------------------------ ------------------------------------------------------------------------ #define DDRSS_PI_316_DATA 0x00000031 <> #define DDRSS_PI_316_DATA 0x000000B1 [James] Enabling write DBI for FSP2 rank0 ------------------------------------------------------------------------ ------------------------------------------------------------------------ #define DDRSS_PI_319_DATA 0x66000000 <> #define DDRSS_PI_319_DATA 0x46000000 [James] This is a result of the CA_ODT change as described above for FSP2 and rank0 ------------------------------------------------------------------------ ------------------------------------------------------------------------ #define DDRSS_PI_332_DATA 0x00000031 <> #define DDRSS_PI_332_DATA 0x000000B1 [James] Enabling write DBI for FSP1 rank1 ------------------------------------------------------------------------ ------------------------------------------------------------------------ #define DDRSS_PI_335_DATA 0x66000000 <> #define DDRSS_PI_335_DATA 0x46000000 [James] This is a result of the CA_ODT change as described above for FSP1 and rank1 ------------------------------------------------------------------------ ------------------------------------------------------------------------ #define DDRSS_PI_340_DATA 0x00000031 <> #define DDRSS_PI_340_DATA 0x000000B1 [James] Enabling write DBI for FSP2 rank1 ------------------------------------------------------------------------ ------------------------------------------------------------------------ #define DDRSS_PI_343_DATA 0x66000000 <> #define DDRSS_PI_343_DATA 0x46000000 [James] This is a result of the CA_ODT change as described above for FSP1 and rank1 ------------------------------------------------------------------------ ------------------------------------------------------------------------ #define DDRSS_PHY_91_DATA 0x0100C0C0 <> #define DDRSS_PHY_91_DATA 0x0000C0C0 [James] This was a power optimization. This disables the "always on" mode of the input enables for data byte 0 ------------------------------------------------------------------------ ------------------------------------------------------------------------ #define DDRSS_PHY_347_DATA 0x0100C0C0 <> #define DDRSS_PHY_347_DATA 0x0000C0C0 [James] Same as above for data byte 1 ------------------------------------------------------------------------ ------------------------------------------------------------------------ #define DDRSS_PHY_1375_DATA 0x030207AA <> #define DDRSS_PHY_1375_DATA 0x03020000 [James] This is also a power optimization. This disables VREF controller for addr/cmd signals. VREF is not used in the PHY for addr/ctrl ------------------------------------------------------------------------