/*
 *  Copyright (c) Texas Instruments Incorporated 2023
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#define UInt32                  unsigned int
#define UInt64                  unsigned long long
#define WR_MEM_32(addr, data)   *(UInt32*)(addr) = (UInt32)(data)
#define RD_MEM_32(addr)         *(UInt32*)(addr)
#define WR_MEM_64(addr, data)   *(UInt64*)(addr) = (UInt64)(data)
#define RD_MEM_64(addr)         *(UInt64*)(addr)

#define	COMPUTE_CLUSTER_J7AHP_MAIN_0_GIC_MEM_RD_VBUSM  	0x45D86000
#define	COMPUTE_CLUSTER_J7AHP_MAIN_0_GIC_MEM_WR_VBUSM  	0x45D86400
#define	DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMR  	0x45DA0000
#define	DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMW  	0x45DA0400
#define	DMPAC_TOP_MAIN_0_DATA_MST  	0x45DC0000
#define	EMMC8SS_16FFC_MAIN_0_EMMCSS_WR  	0x45D9B400
#define	EMMC8SS_16FFC_MAIN_0_EMMCSS_RD  	0x45D9B800
#define	EMMCSD4SS_MAIN_0_EMMCSDSS_RD  	0x45D82800
#define	EMMCSD4SS_MAIN_0_EMMCSDSS_WR  	0x45D82C00
#define	J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC  	0x45DC5000
#define	J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC  	0x45DC5800
#define	K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA  	0x45DC2000
#define	K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC  	0x45DC2400
#define	K3_VPU_WAVE521CL_MAIN_0_SEC_M_VBUSM_R_ASYNC  	0x45DC0C00
#define	K3_VPU_WAVE521CL_MAIN_0_SEC_M_VBUSM_W_ASYNC  	0x45DC1000
#define	K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_R_ASYNC  	0x45DC3400
#define	K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_W_ASYNC  	0x45DC3800
#define	K3_VPU_WAVE521CL_MAIN_1_SEC_M_VBUSM_R_ASYNC  	0x45DC3C00
#define	K3_VPU_WAVE521CL_MAIN_1_SEC_M_VBUSM_W_ASYNC  	0x45DC4000
#define	K3_VPU_WAVE521CL_MAIN_1_PRI_M_VBUSM_R_ASYNC  	0x45DC4400
#define	K3_VPU_WAVE521CL_MAIN_1_PRI_M_VBUSM_W_ASYNC  	0x45DC4800
#define	PCIE_G3X4_128_MAIN_0_PCIE_MST_RD  	0x45D98400
#define	PCIE_G3X4_128_MAIN_0_PCIE_MST_WR  	0x45D98C00
#define	PCIE_G3X4_128_MAIN_1_PCIE_MST_RD  	0x45D99400
#define	PCIE_G3X4_128_MAIN_1_PCIE_MST_WR  	0x45D99C00
#define	PULSAR_SL_MAIN_0_PBDG_RMST0  	0x45D78000
#define	PULSAR_SL_MAIN_0_PBDG_WMST0  	0x45D78400
#define	PULSAR_SL_MAIN_0_PBDG_RMST1  	0x45D78800
#define	PULSAR_SL_MAIN_0_PBDG_WMST1  	0x45D78C00
#define	PULSAR_SL_MAIN_0_CPU0_RMST  	0x45DC8000
#define	PULSAR_SL_MAIN_0_CPU0_WMST  	0x45DC8400
#define	PULSAR_SL_MAIN_0_CPU1_RMST  	0x45DC8800
#define	PULSAR_SL_MAIN_0_CPU1_WMST  	0x45DC8C00
#define	PULSAR_SL_MAIN_1_CPU0_RMST  	0x45DA8000
#define	PULSAR_SL_MAIN_1_CPU0_WMST  	0x45DA8400
#define	PULSAR_SL_MAIN_1_CPU1_RMST  	0x45DA8800
#define	PULSAR_SL_MAIN_1_CPU1_WMST  	0x45DA8C00
#define	PULSAR_SL_MAIN_1_PBDG_RMST0  	0x45DCA000
#define	PULSAR_SL_MAIN_1_PBDG_WMST0  	0x45DCA400
#define	PULSAR_SL_MAIN_1_PBDG_RMST1  	0x45DCA800
#define	PULSAR_SL_MAIN_1_PBDG_WMST1  	0x45DCAC00
#define	PULSAR_SL_MAIN_2_CPU0_RMST  	0x45DA9000
#define	PULSAR_SL_MAIN_2_CPU0_WMST  	0x45DA9400
#define	PULSAR_SL_MAIN_2_CPU1_RMST  	0x45DA9800
#define	PULSAR_SL_MAIN_2_CPU1_WMST  	0x45DA9C00
#define	PULSAR_SL_MAIN_2_PBDG_RMST0  	0x45DCB000
#define	PULSAR_SL_MAIN_2_PBDG_WMST0  	0x45DCB400
#define	PULSAR_SL_MAIN_2_PBDG_RMST1  	0x45DCB800
#define	PULSAR_SL_MAIN_2_PBDG_WMST1  	0x45DCBC00
#define	PULSAR_SL_MCU_0_CPU0_RMST  	0x45D10000
#define	PULSAR_SL_MCU_0_CPU0_WMST  	0x45D10400
#define	PULSAR_SL_MCU_0_CPU0_PMST  	0x45D10800
#define	PULSAR_SL_MCU_0_CPU1_RMST  	0x45D11000
#define	PULSAR_SL_MCU_0_CPU1_WMST  	0x45D11400
#define	PULSAR_SL_MCU_0_CPU1_PMST  	0x45D11800
#define	SA2_UL_MAIN_0_CTXCACH_EXT_DMA  	0x45D9BC00
#define	SA3SS_AM62_MCU_0_CTXCACH_EXT_DMA  	0x45D13000
#define	SMS_WKUP_0_TIFS_VBUSP_M  	0x45D00000
#define	SMS_WKUP_0_HSM_VBUSP_M  	0x45D00400
#define	UFSHCI2P1SS_16FFC_MAIN_0_UFSHCI_VBM_MST_RD  	0x45D9AC00
#define	UFSHCI2P1SS_16FFC_MAIN_0_UFSHCI_VBM_MST_WR  	0x45D9B000
#define	USB3P0SS_16FFC_MAIN_0_MSTR0  	0x45D9A000
#define	USB3P0SS_16FFC_MAIN_0_MSTW0  	0x45D9A400
#define	VPAC_TOP_MAIN_0_DATA_MST_0  	0x45DC1400
#define	VPAC_TOP_MAIN_0_DATA_MST_1  	0x45DC1800
#define	VPAC_TOP_MAIN_0_LDC0_M_MST  	0x45DC1C00
#define	VPAC_TOP_MAIN_1_LDC0_M_MST  	0x45DC2800
#define	VPAC_TOP_MAIN_1_DATA_MST_0  	0x45DC2C00
#define	VPAC_TOP_MAIN_1_DATA_MST_1  	0x45DC3000
#define	VUSR_DUAL_MAIN_0_V0_M  	0x45D9C000
#define	VUSR_DUAL_MAIN_0_V1_M  	0x45D9C400
#define NAVSS0_UDMASS_UDMAP0_CFG_TCHAN_BASE 0x30B00000
#define NAVSS0_UDMASS_UDMAP0_CFG_RCHAN_BASE 0x30C00000
#define MCU_NAVSS0_UDMASS_UDMAP0_TCHAN_BASE        0x284a0000
#define MCU_NAVSS0_UDMASS_UDMAP0_RCHAN_BASE        0x284c0000

#define COMPUTE_CLUSTER0_DRU_MMR_DRU0_MMR_CFG_DRU_QUEUE 0x6D008000
#define COMPUTE_CLUSTER0_DRU_MMR_DRU0_MMR_CFG_DRU_CHNRT 0x6D040000
#define VPAC0_DRU_UTC_VPAC0_DRU_MMR_CFG_DRU_DRU_QUEUE   0x3A08000
#define VPAC0_DRU_UTC_VPAC0_DRU_MMR_CFG_DRU_DRU_CHNRT 0x3A40000
#define VPAC0_DRU_UTC_VPAC1_DRU_MMR_CFG_DRU_DRU_QUEUE   0x3B08000
#define VPAC0_DRU_UTC_VPAC1_DRU_MMR_CFG_DRU_DRU_CHNRT 0x3B40000
#define DMPAC0_DRU_0_DRU_UTC_DMPAC0_DRU_MMR_CFG_DRU_DRU_QUEUE 0xF608000
#define DMPAC0_DRU_0_DRU_UTC_DMPAC0_DRU_MMR_CFG_DRU_DRU_CHNRT 0xF640000

Read64(UInt64 addr)
{
   UInt64 regVal,regAddr;
   regAddr = addr;
   regVal = RD_MEM_64(regAddr);
   GEL_TextOut("Reg_%x : %x\n",,,,,regAddr, regVal);
}

Read32(UInt32 addr)
{
   UInt32 regVal,regAddr;
   regAddr = addr;
   regVal = RD_MEM_32(regAddr);
   GEL_TextOut("Reg_%x : %x\n",,,,,regAddr, regVal);
}

menuitem "TDA4VM Qos dump"

hotmenu tda4vm_Qos_dump()
{
  Dump_DRU_Qos();
  Dump_UDMASS_UDMAP0_RCHAN();
  Dump_UDMASS_UDMAP0_TCHAN();
  Dump_VPAC_Qos();
  Dump_DMPAC_Qos();
  Dump_core_QOS();
}

Dump_DRU_Qos()
{
  UInt64 regAddr,i;

  GEL_TextOut("DRU_CFG_y:\n") ;
  for (i=0;i<5;i++)
  {
   regAddr = COMPUTE_CLUSTER0_DRU_MMR_DRU0_MMR_CFG_DRU_QUEUE + (i * 0x8);
   Read64(regAddr);
  }
 
   GEL_TextOut("DRU_CFG_j:\n") ;
   for (i=0;i<0x40;i++)
  {
   regAddr = COMPUTE_CLUSTER0_DRU_MMR_DRU0_MMR_CFG_DRU_CHNRT + (i * 0x100);
   Read64(regAddr);
  }
}

Dump_VPAC_Qos()
{
  UInt64 regAddr,i;

  GEL_TextOut("DRU_UTC_VPAC0__DRU_MMR_CFG__DRU_DRU_DRU_QUEUE_cfg:\n") ;
  for (i=0;i<5;i++)
  {
   regAddr = VPAC0_DRU_UTC_VPAC0_DRU_MMR_CFG_DRU_DRU_QUEUE + (i * 0x8);
   Read64(regAddr);
  }
 
   GEL_TextOut("DRU_UTC_VPAC0__DRU_MMR_CFG__DRU_DRU_DRU_CHNRT_cfg:\n") ;
   for (i=0;i<0x20;i++)
  {
   regAddr = VPAC0_DRU_UTC_VPAC0_DRU_MMR_CFG_DRU_DRU_CHNRT + (i * 0x100);
   Read64(regAddr);
  }

  GEL_TextOut("DRU_UTC_VPAC1__DRU_MMR_CFG__DRU_DRU_DRU_QUEUE_cfg:\n") ;
  for (i=0;i<5;i++)
  {
   regAddr = DMPAC0_DRU_0_DRU_UTC_DMPAC0_DRU_MMR_CFG_DRU_DRU_QUEUE + (i * 0x8);
   Read64(regAddr);
  }
 
   GEL_TextOut("DRU_UTC_VPAC1__DRU_MMR_CFG__DRU_DRU_DRU_CHNRT_cfg:\n") ;
   for (i=0;i<0x20;i++)
  {
   regAddr = DMPAC0_DRU_0_DRU_UTC_DMPAC0_DRU_MMR_CFG_DRU_DRU_CHNRT + (i * 0x100);
   Read64(regAddr);
  }
}

Dump_DMPAC_Qos()
{
  UInt64 regAddr,i;

  GEL_TextOut("DRU_UTC_DMPAC0__DRU_MMR_CFG__DRU_DRU_DRU_QUEUE_cfg:\n") ;
  for (i=0;i<5;i++)
  {
   regAddr = COMPUTE_CLUSTER0_DRU_MMR_DRU0_MMR_CFG_DRU_QUEUE + (i * 0x8);
   Read64(regAddr);
  }
 
   GEL_TextOut("DRU_UTC_DMPAC__DRU_MMR_CFG__DRU_DRU_DRU_CHNRT_cfg:\n") ;
   for (i=0;i<0x20;i++)
  {
   regAddr = COMPUTE_CLUSTER0_DRU_MMR_DRU0_MMR_CFG_DRU_CHNRT + (i * 0x100);
   Read64(regAddr);
  }

}
Dump_UDMASS_UDMAP0_RCHAN()
{

  UInt32 regAddr,i;
  GEL_TextOut("UDMAP0__CFG__RCHAN_RCFG:\n") ;
  for (i=0;i < 82;i++)
  {
   regAddr = NAVSS0_UDMASS_UDMAP0_CFG_RCHAN_BASE  + (i * 0x100);
   Read32(regAddr);
  }

  GEL_TextOut("UDMAP0__CFG__RCHAN_RPRI_CTRL:\n") ;
  for (i=0;i< 82;i++)
  {
   regAddr = NAVSS0_UDMASS_UDMAP0_CFG_RCHAN_BASE + 0x64 + (i * 0x100);
   Read32(regAddr);
  }
  
  GEL_TextOut("MCU_UDMAP0__CFG__RCHAN_RCFG:\n") ;
  for (i=0;i<0x30;i++)
  {
  regAddr = MCU_NAVSS0_UDMASS_UDMAP0_RCHAN_BASE +  (i * 0x100);
   Read32(regAddr);
  }
 
  GEL_TextOut("MCU_UDMAP0__CFG__RCHAN_RPRI_CTRLj:\n") ;
  for (i=0;i<0x30;i++)
  {
   regAddr = MCU_NAVSS0_UDMASS_UDMAP0_RCHAN_BASE + 0x64 + (i * 0x100);
   Read32(regAddr);
  } 
} 

Dump_UDMASS_UDMAP0_TCHAN()
{
  UInt32 regAddr,i;
  GEL_TextOut("UDMA_TCFG_j: \n") ;
  for (i=0;i< 85;i++)
  {
   regAddr = NAVSS0_UDMASS_UDMAP0_CFG_TCHAN_BASE  + (i * 0x100);
   Read32(regAddr);
  }

  GEL_TextOut("UDMA_TPRI_CTRL_j: \n") ;
  for (i=0;i<85;i++)
  {
   regAddr = NAVSS0_UDMASS_UDMAP0_CFG_TCHAN_BASE + 0x64 + (i * 0x100);
   Read32(regAddr);
  }
  
  GEL_TextOut("MCU_UDMA_TCFG_j: \n") ;
  for (i=0;i<0x30;i++)
  {
  regAddr = MCU_NAVSS0_UDMASS_UDMAP0_TCHAN_BASE +  (i * 0x100);
   Read32(regAddr);
  }
 
  GEL_TextOut("MCU_UDMA_TPRI_CTRL_j:\n") ;
  for (i=0;i<0x30;i++)
  {
   regAddr = MCU_NAVSS0_UDMASS_UDMAP0_TCHAN_BASE + 0x64 + (i * 0x100);
   Read32(regAddr);
  }
}


Dump_core_QOS()
{
  UInt32 regAddr,i;
  
  regAddr =COMPUTE_CLUSTER_J7AHP_MAIN_0_GIC_MEM_RD_VBUSM + 0x100;
   Read32(regAddr);

   regAddr =COMPUTE_CLUSTER_J7AHP_MAIN_0_GIC_MEM_WR_VBUSM + 0x100;
   Read32(regAddr);

   regAddr =DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMR + 0x100;
    Read32(regAddr);

    regAddr =DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMW + 0x100;
    Read32(regAddr);

   for (i=0 ;i<32;i++)
   {
    regAddr =DMPAC_TOP_MAIN_0_DATA_MST + 0x100 + i *4;
     Read32(regAddr);
   }
   
    regAddr =EMMC8SS_16FFC_MAIN_0_EMMCSS_WR + 0x100;
    Read32(regAddr);

   regAddr =EMMC8SS_16FFC_MAIN_0_EMMCSS_RD + 0x100;
    Read32(regAddr);

   regAddr =EMMCSD4SS_MAIN_0_EMMCSDSS_RD + 0x100;
    Read32(regAddr);


   regAddr =EMMCSD4SS_MAIN_0_EMMCSDSS_WR + 0x100;
    Read32(regAddr);

   for (i=0 ;i<160;i++)
   {
    regAddr =J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_R_SYNC + 0x100 + i *4;
    Read32(regAddr);
   }

   for (i=0 ;i<160;i++)
   {
   regAddr = J7AEP_GPU_BXS464_WRAP_MAIN_0_M_VBUSM_W_SYNC + 0x100 + i *4;
    Read32(regAddr);
   }

   for (i=0 ;i<10;i++)
   {
     regAddr =K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA + 0x100 + i *4;
      Read32(regAddr);
   }

   for (i=0 ;i<10;i++)
   {
      regAddr =K3_DSS_MAIN_0_DSS_INST0_VBUSM_FBDC + 0x100 + i *4;
      Read32(regAddr);
    }

    regAddr =K3_VPU_WAVE521CL_MAIN_0_SEC_M_VBUSM_R_ASYNC + 0x100;
     Read32(regAddr);

    regAddr =K3_VPU_WAVE521CL_MAIN_0_SEC_M_VBUSM_W_ASYNC + 0x100 ;
     Read32(regAddr);

  for (i=0 ;i<5;i++)
  {
    regAddr =K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_R_ASYNC + 0x100 + i *4;
     Read32(regAddr);
  }

  for (i=0 ;i<5;i++)
  {
    regAddr =K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_W_ASYNC + 0x100 + i *4;
     Read32(regAddr);
  }

    regAddr =K3_VPU_WAVE521CL_MAIN_1_SEC_M_VBUSM_R_ASYNC + 0x100;
     Read32(regAddr);

    regAddr =K3_VPU_WAVE521CL_MAIN_1_SEC_M_VBUSM_W_ASYNC + 0x100 ;
     Read32(regAddr);

  for (i=0 ;i<5;i++)
  {
    regAddr =K3_VPU_WAVE521CL_MAIN_1_PRI_M_VBUSM_R_ASYNC + 0x100 + i *4;
     Read32(regAddr);
  }

  for (i=0 ;i<5;i++)
  {
    regAddr =K3_VPU_WAVE521CL_MAIN_1_PRI_M_VBUSM_W_ASYNC + 0x100 + i *4;
     Read32(regAddr);
  }

  for (i=0 ;i<8;i++)
  {
    regAddr =PCIE_G3X4_128_MAIN_0_PCIE_MST_RD + 0x100 + i *4;
     Read32(regAddr);
  }
  
   for (i=0 ;i<8;i++)
  {
    regAddr =PCIE_G3X4_128_MAIN_0_PCIE_MST_WR + 0x100 + i *4;
     Read32(regAddr);
  }
    for (i=0 ;i<8;i++)
  {
    regAddr =PCIE_G3X4_128_MAIN_1_PCIE_MST_RD + 0x100 + i *4;
     Read32(regAddr);
  }
   
   for (i=0 ;i<8;i++)
  {
    regAddr =PCIE_G3X4_128_MAIN_1_PCIE_MST_WR + 0x100 + i *4;
     Read32(regAddr);
  }

  regAddr =PULSAR_SL_MAIN_0_PBDG_RMST0 + 0x100;
   Read32(regAddr);

  regAddr =PULSAR_SL_MAIN_0_PBDG_WMST0 + 0x100;
   Read32(regAddr);


  regAddr =PULSAR_SL_MAIN_0_PBDG_RMST1 + 0x100;
   Read32(regAddr);


  regAddr =PULSAR_SL_MAIN_0_PBDG_WMST1 + 0x100;
   Read32(regAddr);

  regAddr =PULSAR_SL_MAIN_0_CPU0_RMST + 0x100;
   Read32(regAddr);


  regAddr =PULSAR_SL_MAIN_0_CPU0_WMST + 0x100;
   Read32(regAddr);


  regAddr =PULSAR_SL_MAIN_0_CPU1_RMST + 0x100;
   Read32(regAddr);


  regAddr =PULSAR_SL_MAIN_0_CPU1_WMST + 0x100;
   Read32(regAddr);


  regAddr =PULSAR_SL_MAIN_1_CPU0_RMST + 0x100;
   Read32(regAddr);


  regAddr =PULSAR_SL_MAIN_1_CPU0_WMST + 0x100;
   Read32(regAddr);

  regAddr =PULSAR_SL_MAIN_1_CPU1_RMST + 0x100;
   Read32(regAddr);


  regAddr =PULSAR_SL_MAIN_1_CPU1_WMST + 0x100;
   Read32(regAddr);


  regAddr =PULSAR_SL_MAIN_1_PBDG_RMST0 + 0x100;
   Read32(regAddr);


  regAddr =PULSAR_SL_MAIN_1_PBDG_WMST0 + 0x100;
   Read32(regAddr);


  regAddr =PULSAR_SL_MAIN_1_PBDG_RMST1 + 0x100;
   Read32(regAddr);


  regAddr =PULSAR_SL_MAIN_1_PBDG_WMST1 + 0x100;
   Read32(regAddr);

  regAddr =PULSAR_SL_MAIN_2_CPU0_RMST + 0x100;
  Read32(regAddr);


  regAddr =PULSAR_SL_MAIN_2_CPU0_WMST + 0x100;
  Read32(regAddr);


  regAddr =PULSAR_SL_MAIN_2_CPU1_RMST + 0x100;
  Read32(regAddr);


  regAddr =PULSAR_SL_MAIN_2_CPU1_WMST + 0x100;
  Read32(regAddr);

  regAddr =PULSAR_SL_MAIN_2_PBDG_RMST0 + 0x100;
  Read32(regAddr);


  regAddr =PULSAR_SL_MAIN_2_PBDG_WMST0 + 0x100;
  Read32(regAddr);

  regAddr =PULSAR_SL_MAIN_2_PBDG_RMST1 + 0x100;
  Read32(regAddr);


  regAddr =PULSAR_SL_MAIN_2_PBDG_WMST1 + 0x100;
  Read32(regAddr);


  regAddr =PULSAR_SL_MCU_0_CPU0_RMST + 0x100;
  Read32(regAddr);

  regAddr =PULSAR_SL_MCU_0_CPU0_WMST + 0x100;
  Read32(regAddr);


  regAddr =PULSAR_SL_MCU_0_CPU0_PMST + 0x100;
  Read32(regAddr);

  regAddr =PULSAR_SL_MCU_0_CPU1_RMST + 0x100;
  Read32(regAddr);

  regAddr =PULSAR_SL_MCU_0_CPU1_WMST + 0x100;
  Read32(regAddr);


  regAddr =PULSAR_SL_MCU_0_CPU1_PMST + 0x100;
  Read32(regAddr);


  regAddr =SA2_UL_MAIN_0_CTXCACH_EXT_DMA + 0x100;
  Read32(regAddr);


  regAddr =SA3SS_AM62_MCU_0_CTXCACH_EXT_DMA + 0x100;
  Read32(regAddr);

  regAddr =SMS_WKUP_0_TIFS_VBUSP_M + 0x100;
  Read32(regAddr);

  regAddr =SMS_WKUP_0_HSM_VBUSP_M + 0x100;
  Read32(regAddr);

  for (i=0 ;i<2;i++)
  {
    regAddr =UFSHCI2P1SS_16FFC_MAIN_0_UFSHCI_VBM_MST_RD + 0x100 + i *4;
    Read32(regAddr);
  }


  for (i=0 ;i<4;i++)
  {
    regAddr =UFSHCI2P1SS_16FFC_MAIN_0_UFSHCI_VBM_MST_WR + 0x100 + i *4;
    Read32(regAddr);
  }
 

  for (i=0 ;i<8;i++)
  {
    regAddr =USB3P0SS_16FFC_MAIN_0_MSTR0 + 0x100 + i *4;
     Read32(regAddr);
  }

  for (i=0 ;i<8;i++)
  {
    regAddr =USB3P0SS_16FFC_MAIN_0_MSTW0 + 0x100 + i *4;
     Read32(regAddr);
  }
 
  for (i=0 ;i<32;i++)
  {
    regAddr =VPAC_TOP_MAIN_0_DATA_MST_0 + 0x100 + i *4;
     Read32(regAddr);
  }

  for (i=0 ;i<64;i++)
  {
    regAddr =VPAC_TOP_MAIN_0_DATA_MST_1 + 0x100 + i *4;
    Read32(regAddr);
  }

  for (i=0 ;i<3;i++)
  {
  regAddr =VPAC_TOP_MAIN_0_LDC0_M_MST + 0x100 + i *4;
   Read32(regAddr);
  }

   for (i=0 ;i<3;i++)
  {
  regAddr =VPAC_TOP_MAIN_1_LDC0_M_MST + 0x100 + i *4;
   Read32(regAddr);
  }

  for (i=0 ;i<32;i++)
 {
  regAddr =VPAC_TOP_MAIN_1_DATA_MST_0 + 0x100 + i *4;
   Read32(regAddr);
 }

   for (i=0 ;i<64;i++)
  {
   regAddr =VPAC_TOP_MAIN_1_DATA_MST_1 + 0x100 + i *4;
   Read32(regAddr);
  }

  regAddr =VUSR_DUAL_MAIN_0_V0_M + 0x100 ; 
   Read32(regAddr);

  regAddr =VUSR_DUAL_MAIN_0_V1_M + 0x100 ; 
   Read32(regAddr);
}