/******************************************************************************
*
* CSLR_SOC_BASEADDRESS.h - SOC memory map header file
*
* Copyright (c) 2013, Texas Instruments Incorporated - http://www.ti.com/
* Software License Agreement
* Redistribution and use in source and binary forms, with or without
* * Redistributions of source code must retain the above copyright
*   notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
*   notice, this list of conditions and the following disclaimer in the
*   documentation and/or other materials provided with the distribution.
* * Neither the name of the Texas Instruments Incorporated nor the
*   names of its contributors may be used to endorse or promote products
*   derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* DAMAGES, FOR ANY REASON WHATSOEVER.
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#include <ti/csl/cslr.h>
#include <ti/csl/tistdtypes.h>
#ifndef CSLR_SOC_BASEADDRESS_H
#define CSLR_SOC_BASEADDRESS_H

#ifdef __cplusplus
extern "C"
{
#endif

#define CSL_ARM_ROM_0_DATA                                                      (0x0U)
#define CSL_ARM_ROM_0_DATA_SIZE                                                 (0x40000)
#define CSL_C66X_COREPAC_LOCAL_L2_SRAM_REGS                                     (0x800000U)
#define CSL_C66X_COREPAC_LOCAL_L2_SRAM_REGS_SIZE                                (0x100000)
#define CSL_C66X_COREPAC_LOCAL_L1P_SRAM_REGS                                    (0xe00000U)
#define CSL_C66X_COREPAC_LOCAL_L1P_SRAM_REGS_SIZE                               (0x8000)
#define CSL_C66X_COREPAC_LOCAL_L1D_SRAM_REGS                                    (0xf00000U)
#define CSL_C66X_COREPAC_LOCAL_L1D_SRAM_REGS_SIZE                               (0x8000)
#define CSL_C66X_COREPAC_REG_BASE_ADDRESS_REGS                                  (0x1800000U)
#define CSL_C66X_COREPAC_REG_BASE_ADDRESS_REGS_SIZE                             (0x10000)
#define CSL_C66X_COREPAC_POWER_DOWN_CFG_REGS                                    (0x1810000U)
#define CSL_C66X_COREPAC_POWER_DOWN_CFG_REGS_SIZE                               (0x1000)
#define CSL_C66X_COREPAC_SECURITY_ID_REGS                                       (0x1811000U)
#define CSL_C66X_COREPAC_SECURITY_ID_REGS_SIZE                                  (0x1000)
#define CSL_C66X_COREPAC_REVISION_ID_REGS                                       (0x1812000U)
#define CSL_C66X_COREPAC_REVISION_ID_REGS_SIZE                                  (0x1000)
#define CSL_C66X_COREPAC_EMC_REGS                                               (0x1820000U)
#define CSL_C66X_COREPAC_EMC_REGS_SIZE                                          (0x20000)
#define CSL_C66X_COREPAC_L1_L2_CFG_REGS                                         (0x1840000U)
#define CSL_C66X_COREPAC_L1_L2_CFG_REGS_SIZE                                    (0x20000)
#define CSL_C66X_COREPAC_EMULATION_REGS                                         (0x1bc0000U)
#define CSL_C66X_COREPAC_EMULATION_REGS_SIZE                                    (0x10000)
#define CSL_TRACER_0_REGS                                                       (0x1d00000U)
#define CSL_TRACER_0_REGS_SIZE                                                  (0x80)
#define CSL_TRACER_8_REGS                                                       (0x1d08000U)
#define CSL_TRACER_8_REGS_SIZE                                                  (0x80)
#define CSL_TRACER_2_REGS                                                       (0x1d10000U)
#define CSL_TRACER_2_REGS_SIZE                                                  (0x80)
#define CSL_TRACER_3_REGS                                                       (0x1d18000U)
#define CSL_TRACER_3_REGS_SIZE                                                  (0x80)
#define CSL_TRACER_4_REGS                                                       (0x1d20000U)
#define CSL_TRACER_4_REGS_SIZE                                                  (0x80)
#define CSL_TRACER_5_REGS                                                       (0x1d28000U)
#define CSL_TRACER_5_REGS_SIZE                                                  (0x80)
#define CSL_TRACER_6_REGS                                                       (0x1d30000U)
#define CSL_TRACER_6_REGS_SIZE                                                  (0x80)
#define CSL_TRACER_7_REGS                                                       (0x1d38000U)
#define CSL_TRACER_7_REGS_SIZE                                                  (0x80)
#define CSL_TRACER_15_REGS                                                      (0x1d40000U)
#define CSL_TRACER_15_REGS_SIZE                                                 (0x80)
#define CSL_TRACER_9_REGS                                                       (0x1d48000U)
#define CSL_TRACER_9_REGS_SIZE                                                  (0x80)
#define CSL_TRACER_10_REGS                                                      (0x1d50000U)
#define CSL_TRACER_10_REGS_SIZE                                                 (0x80)
#define CSL_TRACER_11_REGS                                                      (0x1d58000U)
#define CSL_TRACER_11_REGS_SIZE                                                 (0x80)
#define CSL_TRACER_12_REGS                                                      (0x1d60000U)
#define CSL_TRACER_12_REGS_SIZE                                                 (0x80)
#define CSL_TRACER_13_REGS                                                      (0x1d68000U)
#define CSL_TRACER_13_REGS_SIZE                                                 (0x80)
#define CSL_TRACER_14_REGS                                                      (0x1d70000U)
#define CSL_TRACER_14_REGS_SIZE                                                 (0x80)
#define CSL_TETRIS_REGS                                                         (0x1e80000U)
#define CSL_TETRIS_REGS_SIZE                                                    (0x4000)
#define CSL_MSMC_PBIST_REGS                                                     (0x1e84000U)
#define CSL_MSMC_PBIST_REGS_SIZE                                                (0x400)
#define CSL_EQEP_0_CFG_REGS                                                     (0x21c0000U)
#define CSL_EQEP_0_CFG_REGS_SIZE                                                (0x400)
#define CSL_EQEP_1_CFG_REGS                                                     (0x21c0400U)
#define CSL_EQEP_1_CFG_REGS_SIZE                                                (0x400)
#define CSL_EQEP_2_CFG_REGS                                                     (0x21c0800U)
#define CSL_EQEP_2_CFG_REGS_SIZE                                                (0x400)
#define CSL_MLB_0_TOP_REGS                                                      (0x21c6000U)
#define CSL_MLB_0_TOP_REGS_SIZE                                                 (0x3fd)
#define CSL_MLB_0_CFG_REGS                                                      (0x21c6400U)
#define CSL_MLB_0_CFG_REGS_SIZE                                                 (0x3fd)
#define CSL_ELM_0_CFG_REGS                                                      (0x21c8000U)
#define CSL_ELM_0_CFG_REGS_SIZE                                                 (0x8000)
#define CSL_PWM_0_CFG_REGS                                                      (0x21d0000U)
#define CSL_PWM_0_CFG_REGS_SIZE                                                 (0x80)
#define CSL_PWM_0_EHR_CFG_REGS                                                  (0x21d0080U)
#define CSL_PWM_0_EHR_CFG_REGS_SIZE                                             (0x80)
#define CSL_PWM_1_CFG_REGS                                                      (0x21d0400U)
#define CSL_PWM_1_CFG_REGS_SIZE                                                 (0x80)
#define CSL_PWM_1_EHR_CFG_REGS                                                  (0x21d0480U)
#define CSL_PWM_1_EHR_CFG_REGS_SIZE                                             (0x80)
#define CSL_PWM_2_CFG_REGS                                                      (0x21d0800U)
#define CSL_PWM_2_CFG_REGS_SIZE                                                 (0x80)
#define CSL_PWM_2_EHR_CFG_REGS                                                  (0x21d0880U)
#define CSL_PWM_2_EHR_CFG_REGS_SIZE                                             (0x80)
#define CSL_PWM_3_CFG_REGS                                                      (0x21d0c00U)
#define CSL_PWM_3_CFG_REGS_SIZE                                                 (0x80)
#define CSL_PWM_3_EHR_CFG_REGS                                                  (0x21d0c80U)
#define CSL_PWM_3_EHR_CFG_REGS_SIZE                                             (0x80)
#define CSL_PWM_4_CFG_REGS                                                      (0x21d1000U)
#define CSL_PWM_4_CFG_REGS_SIZE                                                 (0x80)
#define CSL_PWM_4_EHR_CFG_REGS                                                  (0x21d1080U)
#define CSL_PWM_4_EHR_CFG_REGS_SIZE                                             (0x80)
#define CSL_PWM_5_CFG_REGS                                                      (0x21d1400U)
#define CSL_PWM_5_CFG_REGS_SIZE                                                 (0x80)
#define CSL_PWM_5_EHR_CFG_REGS                                                  (0x21d1480U)
#define CSL_PWM_5_EHR_CFG_REGS_SIZE                                             (0x80)
#define CSL_ECAP_0_CFG_REGS                                                     (0x21d1800U)
#define CSL_ECAP_0_CFG_REGS_SIZE                                                (0x400)
#define CSL_ECAP_1_CFG_REGS                                                     (0x21d1c00U)
#define CSL_ECAP_1_CFG_REGS_SIZE                                                (0x400)
#define CSL_OTP_0_CFG_REGS                                                      (0x21d2000U)
#define CSL_OTP_0_CFG_REGS_SIZE                                                 (0x100)
#define CSL_ASRC_0_CFG_REGS                                                     (0x21e0000U)
#define CSL_ASRC_0_CFG_REGS_SIZE                                                (0x800)
#define CSL_TIMER_0_CFG_REGS                                                    (0x2200000U)
#define CSL_TIMER_0_CFG_REGS_SIZE                                               (0x80)
#define CSL_TIMER_1_CFG_REGS                                                    (0x2210000U)
#define CSL_TIMER_1_CFG_REGS_SIZE                                               (0x80)
#define CSL_TIMER_2_CFG_REGS                                                    (0x2220000U)
#define CSL_TIMER_2_CFG_REGS_SIZE                                               (0x80)
#define CSL_TIMER_3_CFG_REGS                                                    (0x2230000U)
#define CSL_TIMER_3_CFG_REGS_SIZE                                               (0x80)
#define CSL_TIMER_4_CFG_REGS                                                    (0x2240000U)
#define CSL_TIMER_4_CFG_REGS_SIZE                                               (0x80)
#define CSL_TIMER_5_CFG_REGS                                                    (0x2250000U)
#define CSL_TIMER_5_CFG_REGS_SIZE                                               (0x80)
#define CSL_TIMER_6_CFG_REGS                                                    (0x2260000U)
#define CSL_TIMER_6_CFG_REGS_SIZE                                               (0x80)
#define CSL_PLLC_CFG_REGS                                                       (0x2310000U)
#define CSL_PLLC_CFG_REGS_SIZE                                                  (0x200)
#define CSL_PCIE_0_PHY_CFG_REGS                                                 (0x2320000U)
#define CSL_PCIE_0_PHY_CFG_REGS_SIZE                                            (0x4000)
#ifndef CSL_MODIFICATION 
#define CSL_PCIE_0_SERDES_CFG_REGS                                              (CSL_PCIE_0_PHY_CFG_REGS)
#endif
#define CSL_DDR_0_PHY_CFG_REGS                                                  (0x2329000U)
#define CSL_DDR_0_PHY_CFG_REGS_SIZE                                             (0x1000)
#define CSL_SR_0_REGS                                                           (0x232f000U)
#define CSL_SR_0_REGS_SIZE                                                      (0x800)
#define CSL_PCIE_0_ECC_CFG_REGS                                                 (0x2330400U)
#define CSL_PCIE_0_ECC_CFG_REGS_SIZE                                            (0x4000)
#define CSL_MCASP_0_CFG_REGS                                                    (0x2340000U)
#define CSL_MCASP_0_CFG_REGS_SIZE                                               (0x400)
#define CSL_MCASP_0_FIFO_CFG_REGS                                               (0x2341000U)
#define CSL_MCASP_0_FIFO_CFG_REGS_SIZE                                          (0x400)
#define CSL_MCASP_1_CFG_REGS                                                    (0x2342000U)
#define CSL_MCASP_1_CFG_REGS_SIZE                                               (0x400)
#define CSL_MCASP_1_FIFO_CFG_REGS                                               (0x2343000U)
#define CSL_MCASP_1_FIFO_CFG_REGS_SIZE                                          (0x400)
#define CSL_MCASP_2_CFG_REGS                                                    (0x2344000U)
#define CSL_MCASP_2_CFG_REGS_SIZE                                               (0x400)
#define CSL_MCASP_2_FIFO_CFG_REGS                                               (0x2345000U)
#define CSL_MCASP_2_FIFO_CFG_REGS_SIZE                                          (0x400)
#define CSL_MCBSP_0_CFG_REGS                                                    (0x2346000U)
#define CSL_MCBSP_0_CFG_REGS_SIZE                                               (0x80)
#define CSL_MCBSP_0_FIFO_CFG_REGS                                               (0x2346080U)
#define CSL_MCBSP_0_FIFO_CFG_REGS_SIZE                                          (0x80)
#define CSL_PSC_REGS                                                            (0x2350000U)
#define CSL_PSC_REGS_SIZE                                                       (0x1000)
#define CSL_MPU_0_REGS                                                          (0x2360000U)
#define CSL_MPU_0_REGS_SIZE                                                     (0x400)
#define CSL_MPU_1_REGS                                                          (0x2368000U)
#define CSL_MPU_1_REGS_SIZE                                                     (0x400)
#define CSL_MPU_2_REGS                                                          (0x2370000U)
#define CSL_MPU_2_REGS_SIZE                                                     (0x400)
#define CSL_MPU_3_REGS                                                          (0x2378000U)
#define CSL_MPU_3_REGS_SIZE                                                     (0x400)
#define CSL_MPU_4_REGS                                                          (0x2380000U)
#define CSL_MPU_4_REGS_SIZE                                                     (0x400)
#define CSL_MPU_5_REGS                                                          (0x2388000U)
#define CSL_MPU_5_REGS_SIZE                                                     (0x400)
#define CSL_MPU_6_REGS                                                          (0x2388400U)
#define CSL_MPU_6_REGS_SIZE                                                     (0x400)
#define CSL_MPU_7_REGS                                                          (0x2388800U)
#define CSL_MPU_7_REGS_SIZE                                                     (0x400)
#define CSL_MPU_8_REGS                                                          (0x2388c00U)
#define CSL_MPU_8_REGS_SIZE                                                     (0x400)
#define CSL_MPU_9_REGS                                                          (0x2389000U)
#define CSL_MPU_9_REGS_SIZE                                                     (0x400)
#define CSL_MPU_10_REGS                                                         (0x2389400U)
#define CSL_MPU_10_REGS_SIZE                                                    (0x400)
#define CSL_MPU_11_REGS                                                         (0x2389800U)
#define CSL_MPU_11_REGS_SIZE                                                    (0x400)
#define CSL_MPU_12_REGS                                                         (0x2389c00U)
#define CSL_MPU_12_REGS_SIZE                                                    (0x400)
#define CSL_MPU_13_REGS                                                         (0x238a000U)
#define CSL_MPU_13_REGS_SIZE                                                    (0x400)
#define CSL_MPU_14_REGS                                                         (0x238a400U)
#define CSL_MPU_14_REGS_SIZE                                                    (0x400)
#define CSL_MPU_15_REGS                                                         (0x238a800U)
#define CSL_MPU_15_REGS_SIZE                                                    (0x400)
#define CSL_MPU_16_REGS                                                         (0x238ac00U)
#define CSL_MPU_16_REGS_SIZE                                                    (0x400)
#define CSL_DBG_ADTF_0_REGS                                                     (0x2440000U)
#define CSL_DBG_ADTF_0_REGS_SIZE                                                (0x4000)
#define CSL_PBIST_COM_0_REGS                                                    (0x24c0000U)
#define CSL_PBIST_COM_0_REGS_SIZE                                               (0x200)
#define CSL_PBIST_CTL_0_REGS                                                    (0x24c0400U)
#define CSL_PBIST_CTL_0_REGS_SIZE                                               (0x400)
#define CSL_SEC_CTL_REGS                                                        (0x2500000U)
#define CSL_SEC_CTL_REGS_SIZE                                                   (0x8000)
#define CSL_I2C_0_DATA_CFG_REGS                                                 (0x2530000U)
#define CSL_I2C_0_DATA_CFG_REGS_SIZE                                            (0x80)
#define CSL_I2C_1_DATA_CFG_REGS                                                 (0x2530400U)
#define CSL_I2C_1_DATA_CFG_REGS_SIZE                                            (0x80)
#define CSL_I2C_2_DATA_CFG_REGS                                                 (0x2530800U)
#define CSL_I2C_2_DATA_CFG_REGS_SIZE                                            (0x80)
#define CSL_UART_0_REGS                                                         (0x2530c00U)
#define CSL_UART_0_REGS_SIZE                                                    (0x40)
#define CSL_UART_1_REGS                                                         (0x2531000U)
#define CSL_UART_1_REGS_SIZE                                                    (0x40)
#define CSL_UART_2_REGS                                                         (0x2531400U)
#define CSL_UART_2_REGS_SIZE                                                    (0x40)
#define CSL_DSSUL_0_CFG_REGS                                                    (0x2540000U)
#define CSL_DSSUL_0_CFG_REGS_SIZE                                               (0x20000)
#define CSL_ARM_GIC_CFG_REGS                                                    (0x2560000U)
#define CSL_ARM_GIC_CFG_REGS_SIZE                                               (0x8000)
#ifndef CSL_MODIFICATION
#define CSL_MPU_INTC_MPU_PHYS_CPU_IF_REGS                                       (0x02562000U)
#define CSL_MPU_INTC_MPU_DISTRIBUTOR_REGS                                       (0x02561000U)
#endif
#define CSL_USB_1_CFG_REGS                                                      (0x2580000U)
#define CSL_USB_1_CFG_REGS_SIZE                                                 (0x20000)
#define CSL_CIC_0_REGS                                                          (0x2600000U)
#define CSL_CIC_0_REGS_SIZE                                                     (0x2000)
#define CSL_GPIO_0_REGS                                                         (0x2603000U)
#define CSL_GPIO_0_REGS_SIZE                                                    (0x100)
#define CSL_DCAN_0_DATA                                                         (0x2604000U)
#define CSL_DCAN_0_DATA_SIZE                                                    (0x2000)
#define CSL_DCAN_1_DATA                                                         (0x2608000U)
#define CSL_DCAN_1_DATA_SIZE                                                    (0x2000)
#define CSL_GPIO_1_REGS                                                         (0x260a000U)
#define CSL_GPIO_1_REGS_SIZE                                                    (0x100)
#define CSL_DCAN_0_CFG_REGS                                                     (0x260b200U)
#define CSL_DCAN_0_CFG_REGS_SIZE                                                (0x2000)
#define CSL_DCAN_1_CFG_REGS                                                     (0x260b400U)
#define CSL_DCAN_1_CFG_REGS_SIZE                                                (0x2000)
#define CSL_BOOT_CFG_REGS                                                       (0x2620000U)
#define CSL_BOOT_CFG_REGS_SIZE                                                  (0x2000)
#define CSL_USB_0_PHY_CFG_REGS                                                  (0x2630000U)
#define CSL_USB_0_PHY_CFG_REGS_SIZE                                             (0x10000)
#define CSL_SEMAPHORE_REGS                                                      (0x2640000U)
#define CSL_SEMAPHORE_REGS_SIZE                                                 (0x800)
#define CSL_USB_1_PHY_CFG_REGS                                                  (0x2650000U)
#define CSL_USB_1_PHY_CFG_REGS_SIZE                                             (0x20000)
#define CSL_USB_0_CFG_REGS                                                      (0x2680000U)
#define CSL_USB_0_CFG_REGS_SIZE                                                 (0x10000)
#define CSL_EDMACC_0_REGS                                                       (0x2700000U)
#define CSL_EDMACC_0_REGS_SIZE                                                  (0x8000)
#define CSL_EDMACC_1_REGS                                                       (0x2728000U)
#define CSL_EDMACC_1_REGS_SIZE                                                  (0x8000)
#define CSL_EDMATC_0_REGS                                                       (0x2760000U)
#define CSL_EDMATC_0_REGS_SIZE                                                  (0x400)
#define CSL_EDMATC_1_REGS                                                       (0x2768000U)
#define CSL_EDMATC_1_REGS_SIZE                                                  (0x400)
#define CSL_EDMATC_2_REGS                                                       (0x27b0000U)
#define CSL_EDMATC_2_REGS_SIZE                                                  (0x400)
#define CSL_EDMATC_3_REGS                                                       (0x27b8000U)
#define CSL_EDMATC_3_REGS_SIZE                                                  (0x400)
#define CSL_MESSAGEMANAGER_0_CFG1_REGS                                          (0x2880000U)
#define CSL_MESSAGEMANAGER_0_CFG1_REGS_SIZE                                     (0x20000)
#define CSL_MESSAGEMANAGER_0_CFG2_REGS                                          (0x28a0000U)
#define CSL_MESSAGEMANAGER_0_CFG2_REGS_SIZE                                     (0x20000)
#define CSL_MESSAGEMANAGER_0_CFG0_REGS                                          (0x28c0000U)
#define CSL_MESSAGEMANAGER_0_CFG0_REGS_SIZE                                     (0x20000)
#define CSL_MESSAGEMANAGER_0_CFG4_REGS                                          (0x28c1000U)
#define CSL_MESSAGEMANAGER_0_CFG4_REGS_SIZE                                     (0x20000)
#define CSL_MESSAGEMANAGER_0_CFG5_REGS                                          (0x28c2000U)
#define CSL_MESSAGEMANAGER_0_CFG5_REGS_SIZE                                     (0x20000)
#define CSL_MESSAGEMANAGER_0_CFG7_REGS                                          (0x28c3000U)
#define CSL_MESSAGEMANAGER_0_CFG7_REGS_SIZE                                     (0x20000)
#define CSL_MESSAGEMANAGER_0_CFG6_REGS                                          (0x28c3400U)
#define CSL_MESSAGEMANAGER_0_CFG6_REGS_SIZE                                     (0x20000)
#define CSL_PMMC_0_CFG_REGS                                                     (0x2900000U)
#define CSL_PMMC_0_CFG_REGS_SIZE                                                (0x40000)
#define CSL_QSPI_0_CFG_REGS                                                     (0x2940000U)
#define CSL_QSPI_0_CFG_REGS_SIZE                                                (0x1000)
#define CSL_MESSAGEMANAGER_0_CFG3_REGS                                          (0x2a00000U)
#define CSL_MESSAGEMANAGER_0_CFG3_REGS_SIZE                                     (0x20000)
#define CSL_DEBUG_CFG_REGS                                                      (0x3000000U)
#define CSL_DEBUG_CFG_REGS_SIZE                                                 (0x100000)
#define CSL_NSS_0_NAVSS_REGS                                                    (0x4000000U)
#define CSL_NSS_0_NAVSS_REGS_SIZE                                               (0x100)
#define CSL_NSS_0_ECC_REGS                                                      (0x4000100U)
#define CSL_NSS_0_ECC_REGS_SIZE                                                 (0x400)
#define CSL_NSS_0_INTD_REGS                                                     (0x4001000U)
#define CSL_NSS_0_INTD_REGS_SIZE                                                (0x1000)
#define CSL_NSS_0_CPPIDMA0_CONFIG_REGS                                          (0x4010000U)
#define CSL_NSS_0_CPPIDMA0_CONFIG_REGS_SIZE                                     (0x100)
#define CSL_NSS_0_CPPIDMA0_TX_SCHEDULER_REGS                                    (0x4010100U)
#define CSL_NSS_0_CPPIDMA0_TX_SCHEDULER_REGS_SIZE                               (0x80)
#define CSL_NSS_0_CPPIDMA0_TX_CHANNEL_CFG_REGS                                  (0x4011000U)
#define CSL_NSS_0_CPPIDMA0_TX_CHANNEL_CFG_REGS_SIZE                             (0x1000)
#define CSL_NSS_0_CPPIDMA0_RX_CHANNEL_CFG_REGS                                  (0x4012000U)
#define CSL_NSS_0_CPPIDMA0_RX_CHANNEL_CFG_REGS_SIZE                             (0x1000)
#define CSL_NSS_0_CPPIDMA0_RX_FLOW_CFG_REGS                                     (0x4013000U)
#define CSL_NSS_0_CPPIDMA0_RX_FLOW_CFG_REGS_SIZE                                (0x1000)
#define CSL_NSS_0_QMGR_LINKING_RAM_REGS                                         (0x4020000U)
#define CSL_NSS_0_QMGR_LINKING_RAM_REGS_SIZE                                    (0x800)
#define CSL_NSS_0_QMGR0_CFG_REGS                                                (0x4040000U)
#define CSL_NSS_0_QMGR0_CFG_REGS_SIZE                                           (0x100)
#define CSL_NSS_0_QUEUEPROXY0_CFG_REGS                                          (0x4040200U)
#define CSL_NSS_0_QUEUEPROXY0_CFG_REGS_SIZE                                     (0x100)
#define CSL_NSS_0_QUEUEPROXY1_CFG_REGS                                          (0x4040200U)
#define CSL_NSS_0_QUEUEPROXY1_CFG_REGS_SIZE                                     (0x100)
#define CSL_NSS_0_QMGR0_DESCRIPTOR_REGIONS_REGS                                 (0x4080000U)
#define CSL_NSS_0_QMGR0_DESCRIPTOR_REGIONS_REGS_SIZE                            (0x800)
#define CSL_NSS_0_QMGR0_QUEUE_REGS                                              (0x40c0000U)
#define CSL_NSS_0_QMGR0_QUEUE_REGS_SIZE                                         (0x800)
#define CSL_NSS_0_QMGR0_QUEUE_STATUS_REGS                                       (0x4100000U)
#define CSL_NSS_0_QMGR0_QUEUE_STATUS_REGS_SIZE                                  (0x800)
#define CSL_NSS_0_QUEUEPROXY0_QUEUE_REGS                                        (0x4140000U)
#define CSL_NSS_0_QUEUEPROXY0_QUEUE_REGS_SIZE                                   (0x800)
#define CSL_NSS_0_QUEUEPROXY1_QUEUE_REGS                                        (0x4140000U)
#define CSL_NSS_0_QUEUEPROXY1_QUEUE_REGS_SIZE                                   (0x800)
#define CSL_NSS_0_CPSW_REGS                                                     (0x4200000U)
#define CSL_NSS_0_CPSW_REGS_SIZE                                                (0x80000)
#define CSL_NSS_0_SA_UL_REGS                                                    (0x4400000U)
#define CSL_NSS_0_SA_UL_REGS_SIZE                                               (0x80000)
#define CSL_XMC_CFG_REGS                                                        (0x8000000U)
#define CSL_XMC_CFG_REGS_SIZE                                                   (0x20000)
#define CSL_MSMC_CFG_REGS                                                       (0xbc00000U)
#define CSL_MSMC_CFG_REGS_SIZE                                                  (0x100000)
#define CSL_MSMC_SRAM_REGS                                                      (0xc000000U)
#define CSL_MSMC_SRAM_REGS_SIZE                                                 (0x100000)
#define CSL_C66X_COREPAC_0_L2_SRAM_REGS                                         (0x10800000U)
#define CSL_C66X_COREPAC_0_L2_SRAM_REGS_SIZE                                    (0x100000)
#define CSL_C66X_COREPAC_0_L1P_SRAM_REGS                                        (0x10e00000U)
#define CSL_C66X_COREPAC_0_L1P_SRAM_REGS_SIZE                                   (0x8000)
#define CSL_GEM_INTERNAL_DSP0_L1D_SRAM_RAM_REGS                                 (0x10f00000U)
#define CSL_GEM_INTERNAL_DSP0_L1D_SRAM_RAM_REGS_SIZE                            (0x8000)
#define CSL_DBG_STM_REGS                                                        (0x20000000U)
#define CSL_DBG_STM_REGS_SIZE                                                   (0x100000)
#define CSL_ASRC_0_S1_REGS                                                      (0x20100000U)
#define CSL_ASRC_0_S1_REGS_SIZE                                                 (0x800)
#define CSL_ASRC_0_S0_REGS                                                      (0x20104000U)
#define CSL_ASRC_0_S0_REGS_SIZE                                                 (0x800)
#define CSL_DBG_TBR_SYS_REGS                                                    (0x20600000U)
#define CSL_DBG_TBR_SYS_REGS_SIZE                                               (0x100000)
#define CSL_TETRIS_0_TBR_SYS_REGS                                               (0x20700000U)
#define CSL_TETRIS_0_TBR_SYS_REGS_SIZE                                          (0x4000)
#define CSL_TETB_0_CFG_REGS                                                     (0x20800000U)
#define CSL_TETB_0_CFG_REGS_SIZE                                                (0x1000)
#define CSL_M3_TBR_SYS_REGS                                                     (0x20900000U)
#define CSL_M3_TBR_SYS_REGS_SIZE                                                (0x100000)
#define CSL_ICSS_0_DATA_RAM_8KB_0_REGS                                          (0x20a80000U)
#define CSL_ICSS_0_DATA_RAM_8KB_0_REGS_SIZE                                     (0x2000)
#define CSL_ICSS_0_DATA_RAM_8KB_1_REGS                                          (0x20a82000U)
#define CSL_ICSS_0_DATA_RAM_8KB_1_REGS_SIZE                                     (0x2000)
#define CSL_ICSS_0_DATA_RAM_64KB_REGS                                           (0x20a90000U)
#define CSL_ICSS_0_DATA_RAM_64KB_REGS_SIZE                                      (0x10000)
#define CSL_ICSS_0_INTC_REGS                                                    (0x20aa0000U)
#define CSL_ICSS_0_INTC_REGS_SIZE                                               (0x5404)
#define CSL_ICSS_0_PRU_CTRL_0_REGS                                              (0x20aa2000U)
#define CSL_ICSS_0_PRU_CTRL_0_REGS_SIZE                                         (0xb4)
#define CSL_ICSS_0_PRU_DEBUG_0_REGS                                             (0x20aa2400U)
#define CSL_ICSS_0_PRU_DEBUG_0_REGS_SIZE                                        (0x3f4)
#define CSL_ICSS_0_PRU_CTRL_1_REGS                                              (0x20aa4000U)
#define CSL_ICSS_0_PRU_CTRL_1_REGS_SIZE                                         (0xb4)
#define CSL_ICSS_0_PRU_DEBUG_1_REGS                                             (0x20aa4400U)
#define CSL_ICSS_0_PRU_DEBUG_1_REGS_SIZE                                        (0x3f4)
#define CSL_ICSS_0_CFG_REGS                                                     (0x20aa6000U)
#define CSL_ICSS_0_CFG_REGS_SIZE                                                (0x474)
#define CSL_ICSS_0_UART_REGS                                                    (0x20aa8000U)
#define CSL_ICSS_0_UART_REGS_SIZE                                               (0xd4)
#define CSL_ICSS_0_IEP_REGS                                                     (0x20aae000U)
#define CSL_ICSS_0_IEP_REGS_SIZE                                                (0xc64)
#define CSL_ICSS_0_ECAP_REGS                                                    (0x20ab0000U)
#define CSL_ICSS_0_ECAP_REGS_SIZE                                               (0x174)
#define CSL_ICSS_0_MII_RT_CFG_REGS                                              (0x20ab2000U)
#define CSL_ICSS_0_MII_RT_CFG_REGS_SIZE                                         (0x154)
#define CSL_ICSS_0_MII_MDIO_REGS                                                (0x20ab2400U)
#define CSL_ICSS_0_MII_MDIO_REGS_SIZE                                           (0x234)
#define CSL_ICSS_0_INST_RAM_16KB_0_REGS                                         (0x20ab4000U)
#define CSL_ICSS_0_INST_RAM_16KB_0_REGS_SIZE                                    (0x4000)
#define CSL_ICSS_0_INST_RAM_16KB_1_REGS                                         (0x20ab8000U)
#define CSL_ICSS_0_INST_RAM_16KB_1_REGS_SIZE                                    (0x4000)
#define CSL_ICSS_1_DATA_RAM_8KB_0_REGS                                          (0x20ac0000U)
#define CSL_ICSS_1_DATA_RAM_8KB_0_REGS_SIZE                                     (0x2000)
#define CSL_ICSS_1_DATA_RAM_8KB_1_REGS                                          (0x20ac2000U)
#define CSL_ICSS_1_DATA_RAM_8KB_1_REGS_SIZE                                     (0x2000)
#define CSL_ICSS_1_DATA_RAM_64KB_REGS                                           (0x20ad0000U)
#define CSL_ICSS_1_DATA_RAM_64KB_REGS_SIZE                                      (0x10000)
#define CSL_ICSS_1_INTC_REGS                                                    (0x20ae0000U)
#define CSL_ICSS_1_INTC_REGS_SIZE                                               (0x5404)
#define CSL_ICSS_1_PRU_CTRL_0_REGS                                              (0x20ae2000U)
#define CSL_ICSS_1_PRU_CTRL_0_REGS_SIZE                                         (0xb4)
#define CSL_ICSS_1_PRU_DEBUG_0_REGS                                             (0x20ae2400U)
#define CSL_ICSS_1_PRU_DEBUG_0_REGS_SIZE                                        (0x3f4)
#define CSL_ICSS_1_PRU_CTRL_1_REGS                                              (0x20ae4000U)
#define CSL_ICSS_1_PRU_CTRL_1_REGS_SIZE                                         (0xb4)
#define CSL_ICSS_1_PRU_DEBUG_1_REGS                                             (0x20ae4400U)
#define CSL_ICSS_1_PRU_DEBUG_1_REGS_SIZE                                        (0x3f4)
#define CSL_ICSS_1_CFG_REGS                                                     (0x20ae6000U)
#define CSL_ICSS_1_CFG_REGS_SIZE                                                (0x474)
#define CSL_ICSS_1_UART_REGS                                                    (0x20ae8000U)
#define CSL_ICSS_1_UART_REGS_SIZE                                               (0xd4)
#define CSL_ICSS_1_IEP_REGS                                                     (0x20aee000U)
#define CSL_ICSS_1_IEP_REGS_SIZE                                                (0xc64)
#define CSL_ICSS_1_ECAP_REGS                                                    (0x20af0000U)
#define CSL_ICSS_1_ECAP_REGS_SIZE                                               (0x174)
#define CSL_ICSS_1_MII_RT_CFG_REGS                                              (0x20af2000U)
#define CSL_ICSS_1_MII_RT_CFG_REGS_SIZE                                         (0x154)
#define CSL_ICSS_1_MII_MDIO_REGS                                                (0x20af2400U)
#define CSL_ICSS_1_MII_MDIO_REGS_SIZE                                           (0x234)
#define CSL_ICSS_1_INST_RAM_16KB_0_REGS                                         (0x20af4000U)
#define CSL_ICSS_1_INST_RAM_16KB_0_REGS_SIZE                                    (0x4000)
#define CSL_ICSS_1_INST_RAM_16KB_1_REGS                                         (0x20af8000U)
#define CSL_ICSS_1_INST_RAM_16KB_1_REGS_SIZE                                    (0x4000)
#define CSL_DSP_ROM_0_SLV_REGS                                                  (0x20b00000U)
#define CSL_DSP_ROM_0_SLV_REGS_SIZE                                             (0x40000)
#define CSL_DDR3_0_SLV_CFG_REGS                                                 (0x21010000U)
#define CSL_DDR3_0_SLV_CFG_REGS_SIZE                                            (0x1000)
#define CSL_PCIE_0_SLV_CFG_REGS                                                 (0x21800000U)
#define CSL_PCIE_0_SLV_CFG_REGS_SIZE                                            (0x4000)
#define CSL_MCASP_0_SLV_REGS                                                    (0x21804000U)
#define CSL_MCASP_0_SLV_REGS_SIZE                                               (0x100)
#define CSL_MCASP_1_SLV_REGS                                                    (0x21804400U)
#define CSL_MCASP_1_SLV_REGS_SIZE                                               (0x100)
#define CSL_MCASP_2_SLV_REGS                                                    (0x21804800U)
#define CSL_MCASP_2_SLV_REGS_SIZE                                               (0x100)
#define CSL_MCBSP_0_SLV_REGS                                                    (0x21805000U)
#define CSL_MCBSP_0_SLV_REGS_SIZE                                               (0x80)
#define CSL_SPI_0_SLV_REGS                                                      (0x21805400U)
#define CSL_SPI_0_SLV_REGS_SIZE                                                 (0x200)
#define CSL_SPI_1_SLV_REGS                                                      (0x21805800U)
#define CSL_SPI_1_SLV_REGS_SIZE                                                 (0x200)
#define CSL_SPI_2_SLV_REGS                                                      (0x21805c00U)
#define CSL_SPI_2_SLV_REGS_SIZE                                                 (0x200)
#define CSL_SPI_3_SLV_REGS                                                      (0x21806000U)
#define CSL_SPI_3_SLV_REGS_SIZE                                                 (0x200)
#define CSL_GPMC_0_CFG_REGS                                                     (0x21818000U)
#define CSL_GPMC_0_CFG_REGS_SIZE                                                (0x400)
#define CSL_MMCSD_0_S_REGS                                                      (0x23000000U)
#define CSL_MMCSD_0_S_REGS_SIZE                                                 (0x10000)
#define CSL_MMCSD_1_S_REGS                                                      (0x23100000U)
#define CSL_MMCSD_1_S_REGS_SIZE                                                 (0x10000)
#define CSL_QSPI_0_DATA                                                         (0x24000000U)
#define CSL_QSPI_0_DATA_SIZE                                                    (0x1000)
#define CSL_DXB_0_S_REGS                                                        (0x28000000U)
#define CSL_DXB_0_S_REGS_SIZE                                                   (0x8000000)
#define CSL_GPMC_0_DATA                                                         (0x30000000U)
#define CSL_GPMC_0_DATA_SIZE                                                    (0x400)
#define CSL_PCIE_0_DATA                                                         (0x70000000U)
#define CSL_PCIE_0_DATA_SIZE                                                    (0x4000)
#ifndef CSL_MODIFICATION 
#define CSL_PCIE_0_SLV_DATA                                                     (CSL_PCIE_0_DATA)
#endif
#define CSL_DDR_0_DATA                                                          (0x80000000U)
#define CSL_DDR_0_DATA_SIZE                                                     (0x1000)
#define CSL_C66X_COREPAC_REGS                                                   (0x800000U)
#define CSL_MCASP_0_REGS                                                        (0x2340000U)
#define CSL_MCASP_1_REGS                                                        (0x2342000U)
#define CSL_MCASP_2_REGS                                                        (0x2344000U)
#define CSL_NSS_0_CFG_REGS                                                      (0x4000000U)
#define CSL_ICSS_0_REGS                                                         (0x20a80000U)
#define CSL_ICSS_1_REGS                                                         (0x20ac0000U)
#define CSL_MLB_0_REGS                                                          (0x21c6000U)
/* Auto-Generated Instance ID List*/

#define CSL_ARM_ROM_0                                                           (0U)
#define CSL_C66X_COREPAC_LOCAL_L2_SRAM                                          (0U)
#define CSL_C66X_COREPAC_LOCAL_L1P_SRAM                                         (0U)
#define CSL_C66X_COREPAC_LOCAL_L1D_SRAM                                         (0U)
#define CSL_C66X_COREPAC_REG_BASE_ADDRESS                                       (0U)
#define CSL_C66X_COREPAC_POWER_DOWN                                             (0U)
#define CSL_C66X_COREPAC_SECURITY_ID                                            (0U)
#define CSL_C66X_COREPAC_REVISION_ID                                            (0U)
#define CSL_C66X_COREPAC_EMC                                                    (0U)
#define CSL_C66X_COREPAC_L1_L2                                                  (0U)
#define CSL_C66X_COREPAC_EMULATION                                              (0U)
#define CSL_TRACER_0                                                            (0U)
#define CSL_TRACER_8                                                            (8U)
#define CSL_TRACER_2                                                            (2U)
#define CSL_TRACER_3                                                            (3U)
#define CSL_TRACER_4                                                            (4U)
#define CSL_TRACER_5                                                            (5U)
#define CSL_TRACER_6                                                            (6U)
#define CSL_TRACER_7                                                            (7U)
#define CSL_TRACER_15                                                           (15U)
#define CSL_TRACER_9                                                            (9U)
#define CSL_TRACER_10                                                           (10U)
#define CSL_TRACER_11                                                           (11U)
#define CSL_TRACER_12                                                           (12U)
#define CSL_TRACER_13                                                           (13U)
#define CSL_TRACER_14                                                           (14U)
#define CSL_TETRIS                                                              (0U)
#define CSL_MSMC_PBIST                                                          (0U)
#define CSL_EQEP_0                                                              (0U)
#define CSL_EQEP_1                                                              (1U)
#define CSL_EQEP_2                                                              (2U)
#define CSL_MLB_0_CFG                                                           (0U)
#define CSL_MLB_0_TOP                                                           (0U)
#define CSL_MLB_0                                                               (0U)
#define CSL_ELM_0                                                               (0U)
#define CSL_PWM_0                                                               (0U)
#define CSL_PWM_1                                                               (1U)
#define CSL_PWM_2                                                               (2U)
#define CSL_PWM_3                                                               (3U)
#define CSL_PWM_4                                                               (4U)
#define CSL_PWM_5                                                               (5U)
#define CSL_ECAP_0                                                              (0U)
#define CSL_ECAP_1                                                              (1U)
#define CSL_OTP_0                                                               (0U)
#define CSL_ASRC_0                                                              (0U)
#define CSL_TIMER_0                                                             (0U)
#define CSL_TIMER_1                                                             (1U)
#define CSL_TIMER_2                                                             (2U)
#define CSL_TIMER_3                                                             (3U)
#define CSL_TIMER_4                                                             (4U)
#define CSL_TIMER_5                                                             (5U)
#define CSL_TIMER_6                                                             (6U)
#define CSL_PLLC                                                                (0U)
#define CSL_PCIE_0                                                              (0U)
#define CSL_DDR_0                                                               (0U)
#define CSL_SR_0                                                                (0U)
#define CSL_MCASP_0_CFG                                                         (0U)
#define CSL_MCASP_0_FIFO_CFG                                                    (0U)
#define CSL_MCASP_1_CFG                                                         (0U)
#define CSL_MCASP_1_FIFO_CFG                                                    (0U)
#define CSL_MCASP_2_CFG                                                         (0U)
#define CSL_MCASP_2_FIFO_CFG                                                    (0U)
#define CSL_MCBSP_0                                                             (0U)
#define CSL_PSC                                                                 (0U)
#define CSL_MPU_0                                                               (0U)
#define CSL_MPU_1                                                               (1U)
#define CSL_MPU_2                                                               (2U)
#define CSL_MPU_3                                                               (3U)
#define CSL_MPU_4                                                               (4U)
#define CSL_MPU_5                                                               (5U)
#define CSL_MPU_6                                                               (6U)
#define CSL_MPU_7                                                               (7U)
#define CSL_MPU_8                                                               (8U)
#define CSL_MPU_9                                                               (9U)
#define CSL_MPU_10                                                              (10U)
#define CSL_MPU_11                                                              (11U)
#define CSL_MPU_12                                                              (12U)
#define CSL_MPU_13                                                              (13U)
#define CSL_MPU_14                                                              (14U)
#define CSL_MPU_15                                                              (15U)
#define CSL_MPU_16                                                              (16U)
#define CSL_DBG_ADTF_0                                                          (0U)
#define CSL_PBIST_COM_0                                                         (0U)
#define CSL_PBIST_CTL_0                                                         (0U)
#define CSL_SEC_CTL                                                             (0U)
#define CSL_I2C_0                                                               (0U)
#define CSL_I2C_1                                                               (1U)
#define CSL_I2C_2                                                               (2U)
#define CSL_UART_0                                                              (0U)
#define CSL_UART_1                                                              (1U)
#define CSL_UART_2                                                              (2U)
#define CSL_DSSUL_0                                                             (0U)
#define CSL_ARM_GIC                                                             (0U)
#define CSL_USB_1                                                               (1U)
#define CSL_CIC_0                                                               (0U)
#define CSL_GPIO_0                                                              (0U)
#define CSL_DCAN_0                                                              (0U)
#define CSL_DCAN_1                                                              (1U)
#define CSL_GPIO_1                                                              (1U)
#define CSL_BOOT                                                                (0U)
#define CSL_USB_0                                                               (0U)
#define CSL_SEMAPHORE                                                           (0U)
#define CSL_EDMACC_0                                                            (0U)
#define CSL_EDMACC_1                                                            (1U)
#define CSL_EDMATC_0                                                            (0U)
#define CSL_EDMATC_1                                                            (1U)
#define CSL_EDMATC_2                                                            (2U)
#define CSL_EDMATC_3                                                            (3U)
#define CSL_MESSAGEMANAGER_0                                                    (0U)
#define CSL_PMMC_0                                                              (0U)
#define CSL_QSPI_0                                                              (0U)
#define CSL_DEBUG                                                               (0U)
#define CSL_NSS_0_NAVSS                                                         (0U)
#define CSL_NSS_0_ECC                                                           (0U)
#define CSL_NSS_0_INTD                                                          (0U)
#define CSL_NSS_0_CPPIDMA0_CONFIG                                               (0U)
#define CSL_NSS_0_CPPIDMA0_TX_SCHEDULER                                         (0U)
#define CSL_NSS_0_CPPIDMA0_TX_CHANNEL                                           (0U)
#define CSL_NSS_0_CPPIDMA0_RX_CHANNEL                                           (0U)
#define CSL_NSS_0_CPPIDMA0_RX_FLOW                                              (0U)
#define CSL_NSS_0_QMGR_LINKING_RAM                                              (0U)
#define CSL_NSS_0_QMGR0                                                         (0U)
#define CSL_NSS_0_QUEUEPROXY0                                                   (0U)
#define CSL_NSS_0_QUEUEPROXY1                                                   (0U)
#define CSL_NSS_0_QMGR0_DESCRIPTOR_REGIONS                                      (0U)
#define CSL_NSS_0_QMGR0_QUEUE                                                   (0U)
#define CSL_NSS_0_QMGR0_QUEUE_STATUS                                            (0U)
#define CSL_NSS_0_QUEUEPROXY0_QUEUE                                             (0U)
#define CSL_NSS_0_QUEUEPROXY1_QUEUE                                             (0U)
#define CSL_NSS_0_CPSW                                                          (0U)
#define CSL_NSS_0_SA_UL                                                         (0U)
#define CSL_XMC                                                                 (0U)
#define CSL_MSMC                                                                (0U)
#define CSL_MSMC_SRAM                                                           (0U)
#define CSL_C66X_COREPAC_0                                                      (0U)
#define CSL_GEM_INTERNAL_DSP0_L1D_SRAM_RAM                                      (0U)
#define CSL_DBG_STM                                                             (0U)
#define CSL_DBG_TBR_SYS                                                         (0U)
#define CSL_TETRIS_0                                                            (0U)
#define CSL_TETB_0                                                              (0U)
#define CSL_M3_TBR_SYS                                                          (0U)
#define CSL_ICSS_0_RAM_8KB_0                                                    (0U)
#define CSL_ICSS_0_RAM_8KB_1                                                    (1U)
#define CSL_ICSS_0_RAM_64KB                                                     (0U)
#define CSL_ICSS_0_INTC                                                         (0U)
#define CSL_ICSS_0_PRU_CTRL_0                                                   (0U)
#define CSL_ICSS_0_PRU_DEBUG_0                                                  (0U)
#define CSL_ICSS_0_PRU_CTRL_1                                                   (1U)
#define CSL_ICSS_0_PRU_DEBUG_1                                                  (1U)
#define CSL_ICSS_0_CFG                                                          (0U)
#define CSL_ICSS_0_UART                                                         (0U)
#define CSL_ICSS_0_IEP                                                          (0U)
#define CSL_ICSS_0_ECAP                                                         (0U)
#define CSL_ICSS_0_MII_RT_CFG                                                   (0U)
#define CSL_ICSS_0_MII_MDIO                                                     (0U)
#define CSL_ICSS_0_INST_RAM_16KB_0                                              (0U)
#define CSL_ICSS_0_INST_RAM_16KB_1                                              (1U)
#define CSL_ICSS_1_RAM_8KB_0                                                    (0U)
#define CSL_ICSS_1_RAM_8KB_1                                                    (1U)
#define CSL_ICSS_1_RAM_64KB                                                     (0U)
#define CSL_ICSS_1_INTC                                                         (0U)
#define CSL_ICSS_1_PRU_CTRL_0                                                   (0U)
#define CSL_ICSS_1_PRU_DEBUG_0                                                  (0U)
#define CSL_ICSS_1_PRU_CTRL_1                                                   (1U)
#define CSL_ICSS_1_PRU_DEBUG_1                                                  (1U)
#define CSL_ICSS_1_CFG                                                          (0U)
#define CSL_ICSS_1_UART                                                         (0U)
#define CSL_ICSS_1_IEP                                                          (0U)
#define CSL_ICSS_1_ECAP                                                         (0U)
#define CSL_ICSS_1_MII_RT_CFG                                                   (0U)
#define CSL_ICSS_1_MII_MDIO                                                     (0U)
#define CSL_ICSS_1_INST_RAM_16KB_0                                              (0U)
#define CSL_ICSS_1_INST_RAM_16KB_1                                              (1U)
#define CSL_DSP_ROM_0                                                           (0U)
#define CSL_DDR3_0                                                              (0U)
#define CSL_PCIE                                                                (0U)
#define CSL_MCASP_0                                                             (0U)
#define CSL_MCASP_1                                                             (1U)
#define CSL_MCASP_2                                                             (2U)
#define CSL_SPI_0                                                               (0U)
#define CSL_SPI_1                                                               (1U)
#define CSL_SPI_2                                                               (2U)
#define CSL_SPI_3                                                               (3U)
#define CSL_GPMC_0                                                              (0U)
#define CSL_MMCSD_0                                                             (0U)
#define CSL_MMCSD_1                                                             (1U)
#define CSL_DXB_0                                                               (0U)
#define CSL_C66X_COREPAC                                                        (0U)
#define CSL_NSS_0                                                               (0U)
#define CSL_ICSS_0                                                              (0U)
#define CSL_ICSS_1                                                              (1U)
/* Auto-Generated Instance CNT List*/

#define CSL_ARM_ROM_CNT                                                         (1U)
#define CSL_C66X_COREPAC_LOCAL_L2_SRAM_CNT                                      (1U)
#define CSL_C66X_COREPAC_LOCAL_L1P_SRAM_CNT                                     (1U)
#define CSL_C66X_COREPAC_LOCAL_L1D_SRAM_CNT                                     (1U)
#define CSL_C66X_COREPAC_REG_BASE_ADDRESS_CNT                                   (1U)
#define CSL_C66X_COREPAC_POWER_DOWN_CNT                                         (1U)
#define CSL_C66X_COREPAC_SECURITY_ID_CNT                                        (1U)
#define CSL_C66X_COREPAC_REVISION_ID_CNT                                        (1U)
#define CSL_C66X_COREPAC_EMC_CNT                                                (1U)
#define CSL_C66X_COREPAC_L1_L2_CNT                                              (1U)
#define CSL_C66X_COREPAC_EMULATION_CNT                                          (1U)
#define CSL_TRACER_CNT                                                          (16U)
#define CSL_MSMC_PBIST_CNT                                                      (1U)
#define CSL_EQEP_CNT                                                            (3U)
#define CSL_MLB_CNT                                                             (1U)
#define CSL_MLB_0_CFG_CNT                                                       (1U)
#define CSL_MLB_0_TOP_CNT                                                       (1U)
#define CSL_ELM_CNT                                                             (1U)
#define CSL_PWM_CNT                                                             (6U)
#define CSL_ECAP_CNT                                                            (2U)
#define CSL_OTP_CNT                                                             (1U)
#define CSL_ASRC_CNT                                                            (1U)
#define CSL_TIMER_CNT                                                           (7U)
#define CSL_PLLC_CNT                                                            (1U)
#define CSL_PCIE_CNT                                                            (1U)
#define CSL_DDR_CNT                                                             (1U)
#define CSL_SR_CNT                                                              (1U)
#define CSL_MCASP_0_CFG_CNT                                                     (1U)
#define CSL_MCASP_0_FIFO_CFG_CNT                                                (1U)
#define CSL_MCASP_1_CFG_CNT                                                     (1U)
#define CSL_MCASP_1_FIFO_CFG_CNT                                                (1U)
#define CSL_MCASP_2_CFG_CNT                                                     (1U)
#define CSL_MCASP_2_FIFO_CFG_CNT                                                (1U)
#define CSL_MCBSP_CNT                                                           (1U)
#define CSL_MPU_CNT                                                             (17U)
#define CSL_DBG_ADTF_CNT                                                        (1U)
#define CSL_PBIST_COM_CNT                                                       (1U)
#define CSL_PBIST_CTL_CNT                                                       (1U)
#define CSL_SEC_CTL_CNT                                                         (1U)
#define CSL_I2C_CNT                                                             (3U)
#define CSL_UART_CNT                                                            (3U)
#define CSL_DSSUL_CNT                                                           (1U)
#define CSL_ARM_GIC_CNT                                                         (1U)
#define CSL_CIC_CNT                                                             (1U)
#define CSL_GPIO_CNT                                                            (2U)
#define CSL_DCAN_CNT                                                            (2U)
#define CSL_BOOT_CNT                                                            (1U)
#define CSL_USB_CNT                                                             (2U)
#define CSL_EDMACC_CNT                                                          (2U)
#define CSL_EDMATC_CNT                                                          (4U)
#define CSL_MESSAGEMANAGER_CNT                                                  (1U)
#define CSL_PMMC_CNT                                                            (1U)
#define CSL_QSPI_CNT                                                            (1U)
#define CSL_DEBUG_CNT                                                           (1U)
#define CSL_NSS_0_NAVSS_CNT                                                     (1U)
#define CSL_NSS_0_ECC_CNT                                                       (1U)
#define CSL_NSS_0_INTD_CNT                                                      (1U)
#define CSL_NSS_0_CPPIDMA0_CONFIG_CNT                                           (1U)
#define CSL_NSS_0_CPPIDMA0_TX_SCHEDULER_CNT                                     (1U)
#define CSL_NSS_0_CPPIDMA0_TX_CHANNEL_CNT                                       (1U)
#define CSL_NSS_0_CPPIDMA0_RX_CHANNEL_CNT                                       (1U)
#define CSL_NSS_0_CPPIDMA0_RX_FLOW_CNT                                          (1U)
#define CSL_NSS_0_QMGR_LINKING_RAM_CNT                                          (1U)
#define CSL_NSS_0_QMGR0_CNT                                                     (1U)
#define CSL_NSS_0_QUEUEPROXY0_CNT                                               (1U)
#define CSL_NSS_0_QUEUEPROXY1_CNT                                               (1U)
#define CSL_NSS_0_QMGR0_DESCRIPTOR_REGIONS_CNT                                  (1U)
#define CSL_NSS_0_QMGR0_QUEUE_CNT                                               (1U)
#define CSL_NSS_0_QMGR0_QUEUE_STATUS_CNT                                        (1U)
#define CSL_NSS_0_QUEUEPROXY0_QUEUE_CNT                                         (1U)
#define CSL_NSS_0_QUEUEPROXY1_QUEUE_CNT                                         (1U)
#define CSL_NSS_0_CPSW_CNT                                                      (1U)
#define CSL_NSS_0_SA_UL_CNT                                                     (1U)
#define CSL_XMC_CNT                                                             (1U)
#define CSL_MSMC_CNT                                                            (1U)
#define CSL_MSMC_SRAM_CNT                                                       (1U)
#define CSL_C66X_COREPAC_CNT                                                    (1U)
#define CSL_GEM_INTERNAL_DSP0_L1D_SRAM_RAM_CNT                                  (1U)
#define CSL_DBG_STM_CNT                                                         (1U)
#define CSL_DBG_TBR_SYS_CNT                                                     (1U)
#define CSL_TETRIS_CNT                                                          (1U)
#define CSL_TETB_CNT                                                            (1U)
#define CSL_M3_TBR_SYS_CNT                                                      (1U)
#define CSL_ICSS_0_RAM_8KB_CNT                                                  (2U)
#define CSL_ICSS_0_RAM_64KB_CNT                                                 (1U)
#define CSL_ICSS_0_INTC_CNT                                                     (1U)
#define CSL_ICSS_0_PRU_CTRL_CNT                                                 (2U)
#define CSL_ICSS_0_PRU_DEBUG_CNT                                                (2U)
#define CSL_ICSS_0_CNT                                                          (1U)
#define CSL_ICSS_0_UART_CNT                                                     (1U)
#define CSL_ICSS_0_IEP_CNT                                                      (1U)
#define CSL_ICSS_0_ECAP_CNT                                                     (1U)
#define CSL_ICSS_0_MII_RT_CNT                                                   (1U)
#define CSL_ICSS_0_MII_MDIO_CNT                                                 (1U)
#define CSL_ICSS_0_INST_RAM_16KB_CNT                                            (2U)
#define CSL_ICSS_1_RAM_8KB_CNT                                                  (2U)
#define CSL_ICSS_1_RAM_64KB_CNT                                                 (1U)
#define CSL_ICSS_1_INTC_CNT                                                     (1U)
#define CSL_ICSS_1_PRU_CTRL_CNT                                                 (2U)
#define CSL_ICSS_1_PRU_DEBUG_CNT                                                (2U)
#define CSL_ICSS_1_CNT                                                          (1U)
#define CSL_ICSS_1_UART_CNT                                                     (1U)
#define CSL_ICSS_1_IEP_CNT                                                      (1U)
#define CSL_ICSS_1_ECAP_CNT                                                     (1U)
#define CSL_ICSS_1_MII_RT_CNT                                                   (1U)
#define CSL_ICSS_1_MII_MDIO_CNT                                                 (1U)
#define CSL_ICSS_1_INST_RAM_16KB_CNT                                            (2U)
#define CSL_DSP_ROM_CNT                                                         (1U)
#define CSL_DDR3_CNT                                                            (1U)
#define CSL_PCIE_CNT                                                            (1U)
#define CSL_MCASP_CNT                                                           (3U)
#define CSL_SPI_CNT                                                             (4U)
#define CSL_GPMC_CNT                                                            (1U)
#define CSL_MMCSD_CNT                                                           (2U)
#define CSL_DXB_CNT                                                             (1U)
#define CSL_NSS_CNT                                                             (1U)
#define CSL_ICSS_CNT                                                            (2U)

#define CSL_EDMACC_0_NUM_DMACH  (64U)
#define CSL_EDMACC_0_NUM_QDMACH  (8U)
#define CSL_EDMACC_0_NUM_INTCH  (64U)
#define CSL_EDMACC_0_NUM_PARAMSETS  (512U)
#define CSL_EDMACC_0_NUM_EVQUE  (2U)
#define CSL_EDMACC_0_NUM_TC  (2U)
#define CSL_EDMACC_0_MEMPROTECT  (1U)
#define CSL_EDMACC_0_NUM_REGIONS  (8U)
#define CSL_EDMACC_0_CHMAPEXIST  (1U)
#define CSL_EDMACC_1_NUM_DMACH  (64U)
#define CSL_EDMACC_1_NUM_QDMACH  (8U)
#define CSL_EDMACC_1_NUM_INTCH  (64U)
#define CSL_EDMACC_1_NUM_PARAMSETS  (512U)
#define CSL_EDMACC_1_NUM_EVQUE  (2U)
#define CSL_EDMACC_1_NUM_TC  (2U)
#define CSL_EDMACC_1_MEMPROTECT  (1U)
#define CSL_EDMACC_1_NUM_REGIONS  (8U)
#define CSL_EDMACC_1_CHMAPEXIST  (1U)

#ifndef CSL_MODIFICATION
#define SOC_INTC_MPU_PHYS_CPU_IF_BASE                                           (CSL_MPU_INTC_MPU_PHYS_CPU_IF_REGS)
#define SOC_INTC_MPU_DISTRIBUTOR_BASE                                           (CSL_MPU_INTC_MPU_DISTRIBUTOR_REGS)
#endif

#ifdef __cplusplus
}
#endif
#endif /* CSLR_SOC_BASEADDRESS_H */
