/*
 * edma3_rl_tc.h
 *
 * EDMA3 Transfer Controller Register Desciption.
 *
 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
 *
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
*/

#ifndef EDMA3_RL_TC_H_
#define EDMA3_RL_TC_H_

#ifdef __cplusplus
extern "C" {
#endif

/**************************************************************************\
* Register Overlay Structure for DFIREG
\**************************************************************************/
typedef struct  {
    volatile uint32_t DFOPT;
    volatile uint32_t DFSRC;
    volatile uint32_t DFCNT;
    volatile uint32_t DFDST;
    volatile uint32_t DFBIDX;
    volatile uint32_t DFMPPRXY;
    volatile uint8_t RSVD0[40];
} EDMA3_TCRL_DfiregRegs;

/**************************************************************************\
* Register Overlay Structure
\**************************************************************************/
typedef struct  {
    volatile uint32_t REV;
    volatile uint32_t TCCFG;
    volatile uint8_t RSVD0[248];
    volatile uint32_t TCSTAT;
    volatile uint32_t INTSTAT;
    volatile uint32_t INTEN;
    volatile uint32_t INTCLR;
    volatile uint32_t INTCMD;
    volatile uint8_t RSVD1[12];
    volatile uint32_t ERRSTAT;
    volatile uint32_t ERREN;
    volatile uint32_t ERRCLR;
    volatile uint32_t ERRDET;
    volatile uint32_t ERRCMD;
    volatile uint8_t RSVD2[12];
    volatile uint32_t RDRATE;
    volatile uint8_t RSVD3[188];
    volatile uint32_t POPT;
    volatile uint32_t PSRC;
    volatile uint32_t PCNT;
    volatile uint32_t PDST;
    volatile uint32_t PBIDX;
    volatile uint32_t PMPPRXY;
    volatile uint8_t RSVD4[40];
    volatile uint32_t SAOPT;
    volatile uint32_t SASRC;
    volatile uint32_t SACNT;
    volatile uint32_t SADST;
    volatile uint32_t SABIDX;
    volatile uint32_t SAMPPRXY;
    volatile uint32_t SACNTRLD;
    volatile uint32_t SASRCBREF;
    volatile uint32_t SADSTBREF;
    volatile uint8_t RSVD5[28];
    volatile uint32_t DFCNTRLD;
    volatile uint32_t DFSRCBREF;
    volatile uint32_t DFDSTBREF;
    volatile uint8_t RSVD6[116];
    EDMA3_TCRL_DfiregRegs DFIREG[4];
} EDMA3_TCRL_Regs;

/**************************************************************************\
* Field Definition Macros
\**************************************************************************/

/* REV */

#define EDMA3_TCRL_REV_TYPE_MASK         (0x00FF0000U)
#define EDMA3_TCRL_REV_TYPE_SHIFT        (0x00000010U)
#define EDMA3_TCRL_REV_TYPE_RESETVAL     (0x00000006U)

#define EDMA3_TCRL_REV_CLASS_MASK        (0x0000FF00U)
#define EDMA3_TCRL_REV_CLASS_SHIFT       (0x00000008U)
#define EDMA3_TCRL_REV_CLASS_RESETVAL    (0x00000004U)

#define EDMA3_TCRL_REV_REV_MASK          (0x000000FFU)
#define EDMA3_TCRL_REV_REV_SHIFT         (0x00000000U)
#define EDMA3_TCRL_REV_REV_RESETVAL      (0x00000001U)

#define EDMA3_TCRL_REV_RESETVAL          (0x00060401U)

/* TCCFG */

#define EDMA3_TCRL_TCCFG_DREGDEPTH_MASK  (0x00000300U)
#define EDMA3_TCRL_TCCFG_DREGDEPTH_SHIFT (0x00000008U)
#define EDMA3_TCRL_TCCFG_DREGDEPTH_RESETVAL (0x00000000U)

/*----DREGDEPTH Tokens----*/
#define EDMA3_TCRL_TCCFG_DREGDEPTH_1ENTRY (0x00000000U)
#define EDMA3_TCRL_TCCFG_DREGDEPTH_2ENTRY (0x00000001U)
#define EDMA3_TCRL_TCCFG_DREGDEPTH_4ENTRY (0x00000002U)

#define EDMA3_TCRL_TCCFG_BUSWIDTH_MASK   (0x00000030U)
#define EDMA3_TCRL_TCCFG_BUSWIDTH_SHIFT  (0x00000004U)
#define EDMA3_TCRL_TCCFG_BUSWIDTH_RESETVAL (0x00000000U)

/*----BUSWIDTH Tokens----*/
#define EDMA3_TCRL_TCCFG_BUSWIDTH_32BIT  (0x00000000U)
#define EDMA3_TCRL_TCCFG_BUSWIDTH_64BIY  (0x00000001U)
#define EDMA3_TCRL_TCCFG_BUSWIDTH_128BIT (0x00000002U)

#define EDMA3_TCRL_TCCFG_FIFOSIZE_MASK   (0x00000007U)
#define EDMA3_TCRL_TCCFG_FIFOSIZE_SHIFT  (0x00000000U)
#define EDMA3_TCRL_TCCFG_FIFOSIZE_RESETVAL (0x00000000U)

/*----FIFOSIZE Tokens----*/
#define EDMA3_TCRL_TCCFG_FIFOSIZE_32BYTE (0x00000000U)
#define EDMA3_TCRL_TCCFG_FIFOSIZE_64BYTE (0x00000001U)
#define EDMA3_TCRL_TCCFG_FIFOSIZE_128BYTE (0x00000002U)
#define EDMA3_TCRL_TCCFG_FIFOSIZE_256BYTE (0x00000003U)
#define EDMA3_TCRL_TCCFG_FIFOSIZE_512BYTE (0x00000004U)

#define EDMA3_TCRL_TCCFG_RESETVAL        (0x00000000U)

/* TCSTAT */

#define EDMA3_TCRL_TCSTAT_DFSTRT_MASK  (0x00003000U)
#define EDMA3_TCRL_TCSTAT_DFSTRT_SHIFT (0x0000000CU)
#define EDMA3_TCRL_TCSTAT_DFSTRT_RESETVAL (0x00000000U)

#define EDMA3_TCRL_TCSTAT_ATCV_MASK    (0x00000100U)
#define EDMA3_TCRL_TCSTAT_ATCV_SHIFT   (0x00000008U)
#define EDMA3_TCRL_TCSTAT_ATCV_RESETVAL (0x00000000U)

/*----ATCV Tokens----*/
#define EDMA3_TCRL_TCSTAT_ATCV_IDLE    (0x00000000U)
#define EDMA3_TCRL_TCSTAT_ATCV_BUSY    (0x00000001U)

#define EDMA3_TCRL_TCSTAT_DSTACT_MASK  (0x00000070U)
#define EDMA3_TCRL_TCSTAT_DSTACT_SHIFT (0x00000004U)
#define EDMA3_TCRL_TCSTAT_DSTACT_RESETVAL (0x00000000U)

/*----DSTACT Tokens----*/
#define EDMA3_TCRL_TCSTAT_DSTACT_EMPTY (0x00000000U)
#define EDMA3_TCRL_TCSTAT_DSTACT_1TR   (0x00000001U)
#define EDMA3_TCRL_TCSTAT_DSTACT_2TR   (0x00000002U)
#define EDMA3_TCRL_TCSTAT_DSTACT_3TR   (0x00000003U)
#define EDMA3_TCRL_TCSTAT_DSTACT_4TR   (0x00000004U)

#define EDMA3_TCRL_TCSTAT_WSACTV_MASK  (0x00000004U)
#define EDMA3_TCRL_TCSTAT_WSACTV_SHIFT (0x00000002U)
#define EDMA3_TCRL_TCSTAT_WSACTV_RESETVAL (0x00000000U)

/*----WSACTV Tokens----*/
#define EDMA3_TCRL_TCSTAT_WSACTV_NONE  (0x00000000U)
#define EDMA3_TCRL_TCSTAT_WSACTV_PEND  (0x00000001U)

#define EDMA3_TCRL_TCSTAT_SRCACTV_MASK (0x00000002U)
#define EDMA3_TCRL_TCSTAT_SRCACTV_SHIFT (0x00000001U)
#define EDMA3_TCRL_TCSTAT_SRCACTV_RESETVAL (0x00000000U)

/*----SRCACTV Tokens----*/
#define EDMA3_TCRL_TCSTAT_SRCACTV_IDLE (0x00000000U)
#define EDMA3_TCRL_TCSTAT_SRCACTV_BUSY (0x00000001U)

#define EDMA3_TCRL_TCSTAT_PROGBUSY_MASK (0x00000001U)
#define EDMA3_TCRL_TCSTAT_PROGBUSY_SHIFT (0x00000000U)
#define EDMA3_TCRL_TCSTAT_PROGBUSY_RESETVAL (0x00000000U)

/*----PROGBUSY Tokens----*/
#define EDMA3_TCRL_TCSTAT_PROGBUSY_IDLE (0x00000000U)
#define EDMA3_TCRL_TCSTAT_PROGBUSY_BUSY (0x00000001U)

#define EDMA3_TCRL_TCSTAT_RESETVAL     (0x00000000U)

/* INTSTAT */

#define EDMA3_TCRL_INTSTAT_TRDONE_MASK   (0x00000002U)
#define EDMA3_TCRL_INTSTAT_TRDONE_SHIFT  (0x00000001U)
#define EDMA3_TCRL_INTSTAT_TRDONE_RESETVAL (0x00000000U)

/*----TRDONE Tokens----*/
#define EDMA3_TCRL_INTSTAT_TRDONE_NONE   (0x00000000U)
#define EDMA3_TCRL_INTSTAT_TRDONE_DONE   (0x00000001U)

#define EDMA3_TCRL_INTSTAT_PROGEMPTY_MASK (0x00000001U)
#define EDMA3_TCRL_INTSTAT_PROGEMPTY_SHIFT (0x00000000U)
#define EDMA3_TCRL_INTSTAT_PROGEMPTY_RESETVAL (0x00000000U)

/*----PROGEMPTY Tokens----*/
#define EDMA3_TCRL_INTSTAT_PROGEMPTY_NONE (0x00000000U)
#define EDMA3_TCRL_INTSTAT_PROGEMPTY_EMPTY (0x00000001U)

#define EDMA3_TCRL_INTSTAT_RESETVAL      (0x00000000U)

/* INTEN */

#define EDMA3_TCRL_INTEN_TRDONE_MASK     (0x00000002U)
#define EDMA3_TCRL_INTEN_TRDONE_SHIFT    (0x00000001U)
#define EDMA3_TCRL_INTEN_TRDONE_RESETVAL (0x00000000U)

/*----TRDONE Tokens----*/
#define EDMA3_TCRL_INTEN_TRDONE_DISABLE  (0x00000000U)
#define EDMA3_TCRL_INTEN_TRDONE_ENABLE   (0x00000001U)

#define EDMA3_TCRL_INTEN_PROGEMPTY_MASK  (0x00000001U)
#define EDMA3_TCRL_INTEN_PROGEMPTY_SHIFT (0x00000000U)
#define EDMA3_TCRL_INTEN_PROGEMPTY_RESETVAL (0x00000000U)

/*----PROGEMPTY Tokens----*/
#define EDMA3_TCRL_INTEN_PROGEMPTY_DISABLE (0x00000000U)
#define EDMA3_TCRL_INTEN_PROGEMPTY_ENABLE (0x00000001U)

#define EDMA3_TCRL_INTEN_RESETVAL        (0x00000000U)

/* INTCLR */

#define EDMA3_TCRL_INTCLR_TRDONE_MASK    (0x00000002U)
#define EDMA3_TCRL_INTCLR_TRDONE_SHIFT   (0x00000001U)
#define EDMA3_TCRL_INTCLR_TRDONE_RESETVAL (0x00000000U)

/*----TRDONE Tokens----*/
#define EDMA3_TCRL_INTCLR_TRDONE_CLEAR   (0x00000001U)

#define EDMA3_TCRL_INTCLR_PROGEMPTY_MASK (0x00000001U)
#define EDMA3_TCRL_INTCLR_PROGEMPTY_SHIFT (0x00000000U)
#define EDMA3_TCRL_INTCLR_PROGEMPTY_RESETVAL (0x00000000U)

/*----PROGEMPTY Tokens----*/
#define EDMA3_TCRL_INTCLR_PROGEMPTY_CLEAR (0x00000001U)

#define EDMA3_TCRL_INTCLR_RESETVAL       (0x00000000U)

/* INTCMD */

#define EDMA3_TCRL_INTCMD_SET_MASK       (0x00000002U)
#define EDMA3_TCRL_INTCMD_SET_SHIFT      (0x00000001U)
#define EDMA3_TCRL_INTCMD_SET_RESETVAL   (0x00000000U)

/*----SET Tokens----*/
#define EDMA3_TCRL_INTCMD_SET_SET        (0x00000001U)

#define EDMA3_TCRL_INTCMD_EVAL_MASK      (0x00000001U)
#define EDMA3_TCRL_INTCMD_EVAL_SHIFT     (0x00000000U)
#define EDMA3_TCRL_INTCMD_EVAL_RESETVAL  (0x00000000U)

/*----EVAL Tokens----*/
#define EDMA3_TCRL_INTCMD_EVAL_EVAL      (0x00000001U)

#define EDMA3_TCRL_INTCMD_RESETVAL       (0x00000000U)

/* ERRSTAT */

#define EDMA3_TCRL_ERRSTAT_MMRAERR_MASK  (0x00000008U)
#define EDMA3_TCRL_ERRSTAT_MMRAERR_SHIFT (0x00000003U)
#define EDMA3_TCRL_ERRSTAT_MMRAERR_RESETVAL (0x00000000U)

/*----MMRAERR Tokens----*/
#define EDMA3_TCRL_ERRSTAT_MMRAERR_NONE  (0x00000000U)
#define EDMA3_TCRL_ERRSTAT_MMRAERR_ERROR (0x00000001U)

#define EDMA3_TCRL_ERRSTAT_TRERR_MASK    (0x00000004U)
#define EDMA3_TCRL_ERRSTAT_TRERR_SHIFT   (0x00000002U)
#define EDMA3_TCRL_ERRSTAT_TRERR_RESETVAL (0x00000000U)

/*----TRERR Tokens----*/
#define EDMA3_TCRL_ERRSTAT_TRERR_NONE    (0x00000000U)
#define EDMA3_TCRL_ERRSTAT_TRERR_ERROR   (0x00000001U)

#define EDMA3_TCRL_ERRSTAT_BUSERR_MASK   (0x00000001U)
#define EDMA3_TCRL_ERRSTAT_BUSERR_SHIFT  (0x00000000U)
#define EDMA3_TCRL_ERRSTAT_BUSERR_RESETVAL (0x00000000U)

/*----BUSERR Tokens----*/
#define EDMA3_TCRL_ERRSTAT_BUSERR_NONE   (0x00000000U)
#define EDMA3_TCRL_ERRSTAT_BUSERR_ERROR  (0x00000001U)

#define EDMA3_TCRL_ERRSTAT_RESETVAL      (0x00000000U)

/* ERREN */

#define EDMA3_TCRL_ERREN_MMRAERR_MASK    (0x00000008U)
#define EDMA3_TCRL_ERREN_MMRAERR_SHIFT   (0x00000003U)
#define EDMA3_TCRL_ERREN_MMRAERR_RESETVAL (0x00000000U)

/*----MMRAERR Tokens----*/
#define EDMA3_TCRL_ERREN_MMRAERR_ENABLE  (0x00000001U)
#define EDMA3_TCRL_ERREN_MMRAERR_DISABLE (0x00000000U)

#define EDMA3_TCRL_ERREN_TRERR_MASK      (0x00000004U)
#define EDMA3_TCRL_ERREN_TRERR_SHIFT     (0x00000002U)
#define EDMA3_TCRL_ERREN_TRERR_RESETVAL  (0x00000000U)

/*----TRERR Tokens----*/
#define EDMA3_TCRL_ERREN_TRERR_ENABLE    (0x00000001U)
#define EDMA3_TCRL_ERREN_TRERR_DISABLE   (0x00000000U)

#define EDMA3_TCRL_ERREN_BUSERR_MASK     (0x00000001U)
#define EDMA3_TCRL_ERREN_BUSERR_SHIFT    (0x00000000U)
#define EDMA3_TCRL_ERREN_BUSERR_RESETVAL (0x00000000U)

/*----BUSERR Tokens----*/
#define EDMA3_TCRL_ERREN_BUSERR_ENABLE   (0x00000001U)
#define EDMA3_TCRL_ERREN_BUSERR_DISABLE  (0x00000000U)

#define EDMA3_TCRL_ERREN_RESETVAL        (0x00000000U)

/* ERRCLR */

#define EDMA3_TCRL_ERRCLR_MMRAERR_MASK   (0x00000008U)
#define EDMA3_TCRL_ERRCLR_MMRAERR_SHIFT  (0x00000003U)
#define EDMA3_TCRL_ERRCLR_MMRAERR_RESETVAL (0x00000000U)

/*----MMRAERR Tokens----*/
#define EDMA3_TCRL_ERRCLR_MMRAERR_CLEAR  (0x00000001U)

#define EDMA3_TCRL_ERRCLR_TRERR_MASK     (0x00000004U)
#define EDMA3_TCRL_ERRCLR_TRERR_SHIFT    (0x00000002U)
#define EDMA3_TCRL_ERRCLR_TRERR_RESETVAL (0x00000000U)

/*----TRERR Tokens----*/
#define EDMA3_TCRL_ERRCLR_TRERR_CLEAR    (0x00000001U)

#define EDMA3_TCRL_ERRCLR_BUSERR_MASK    (0x00000001U)
#define EDMA3_TCRL_ERRCLR_BUSERR_SHIFT   (0x00000000U)
#define EDMA3_TCRL_ERRCLR_BUSERR_RESETVAL (0x00000000U)

/*----BUSERR Tokens----*/
#define EDMA3_TCRL_ERRCLR_BUSERR_CLEAR   (0x00000001U)

#define EDMA3_TCRL_ERRCLR_RESETVAL       (0x00000000U)

/* ERRDET */

#define EDMA3_TCRL_ERRDET_TCCHEN_MASK    (0x00020000U)
#define EDMA3_TCRL_ERRDET_TCCHEN_SHIFT   (0x00000011U)
#define EDMA3_TCRL_ERRDET_TCCHEN_RESETVAL (0x00000000U)

#define EDMA3_TCRL_ERRDET_TCINTEN_MASK   (0x00010000U)
#define EDMA3_TCRL_ERRDET_TCINTEN_SHIFT  (0x00000010U)
#define EDMA3_TCRL_ERRDET_TCINTEN_RESETVAL (0x00000000U)

#define EDMA3_TCRL_ERRDET_TCC_MASK       (0x00003F00U)
#define EDMA3_TCRL_ERRDET_TCC_SHIFT      (0x00000008U)
#define EDMA3_TCRL_ERRDET_TCC_RESETVAL   (0x00000000U)

#define EDMA3_TCRL_ERRDET_STAT_MASK      (0x0000000FU)
#define EDMA3_TCRL_ERRDET_STAT_SHIFT     (0x00000000U)
#define EDMA3_TCRL_ERRDET_STAT_RESETVAL  (0x00000000U)

/*----STAT Tokens----*/
#define EDMA3_TCRL_ERRDET_STAT_NONE      (0x00000000U)
#define EDMA3_TCRL_ERRDET_STAT_READ_ADDRESS (0x00000001U)
#define EDMA3_TCRL_ERRDET_STAT_READ_PRIVILEGE (0x00000002U)
#define EDMA3_TCRL_ERRDET_STAT_READ_TIMEOUT (0x00000003U)
#define EDMA3_TCRL_ERRDET_STAT_READ_DATA (0x00000004U)
#define EDMA3_TCRL_ERRDET_STAT_READ_EXCLUSIVE (0x00000007U)
#define EDMA3_TCRL_ERRDET_STAT_WRITE_ADDRESS (0x00000009U)
#define EDMA3_TCRL_ERRDET_STAT_WRITE_PRIVILEGE (0x0000000AU)
#define EDMA3_TCRL_ERRDET_STAT_WRITE_TIMEOUT (0x0000000BU)
#define EDMA3_TCRL_ERRDET_STAT_WRITE_DATA (0x0000000CU)
#define EDMA3_TCRL_ERRDET_STAT_WRITE_EXCLUSIVE (0x0000000FU)

#define EDMA3_TCRL_ERRDET_RESETVAL       (0x00000000U)

/* ERRCMD */

#define EDMA3_TCRL_ERRCMD_SET_MASK       (0x00000002U)
#define EDMA3_TCRL_ERRCMD_SET_SHIFT      (0x00000001U)
#define EDMA3_TCRL_ERRCMD_SET_RESETVAL   (0x00000000U)

/*----SET Tokens----*/
#define EDMA3_TCRL_ERRCMD_SET_SET        (0x00000001U)

#define EDMA3_TCRL_ERRCMD_EVAL_MASK      (0x00000001U)
#define EDMA3_TCRL_ERRCMD_EVAL_SHIFT     (0x00000000U)
#define EDMA3_TCRL_ERRCMD_EVAL_RESETVAL  (0x00000000U)

/*----EVAL Tokens----*/
#define EDMA3_TCRL_ERRCMD_EVAL_EVAL      (0x00000001U)

#define EDMA3_TCRL_ERRCMD_RESETVAL       (0x00000000U)

/* RDRATE */

#define EDMA3_TCRL_RDRATE_RDRATE_MASK    (0x00000007U)
#define EDMA3_TCRL_RDRATE_RDRATE_SHIFT   (0x00000000U)
#define EDMA3_TCRL_RDRATE_RDRATE_RESETVAL (0x00000000U)

/*----RDRATE Tokens----*/
#define EDMA3_TCRL_RDRATE_RDRATE_AFAP    (0x00000000U)
#define EDMA3_TCRL_RDRATE_RDRATE_4CYCLE  (0x00000001U)
#define EDMA3_TCRL_RDRATE_RDRATE_8CYCLE  (0x00000002U)
#define EDMA3_TCRL_RDRATE_RDRATE_16CYCLE (0x00000003U)
#define EDMA3_TCRL_RDRATE_RDRATE_32CYCLE (0x00000004U)

#define EDMA3_TCRL_RDRATE_RESETVAL       (0x00000000U)

/* POPT */

#define EDMA3_TCRL_POPT_TCCHEN_MASK      (0x00400000U)
#define EDMA3_TCRL_POPT_TCCHEN_SHIFT     (0x00000016U)
#define EDMA3_TCRL_POPT_TCCHEN_RESETVAL  (0x00000000U)

/*----TCCHEN Tokens----*/
#define EDMA3_TCRL_POPT_TCCHEN_DISABLE   (0x00000000U)
#define EDMA3_TCRL_POPT_TCCHEN_ENABLE    (0x00000001U)

#define EDMA3_TCRL_POPT_TCINTEN_MASK     (0x00100000U)
#define EDMA3_TCRL_POPT_TCINTEN_SHIFT    (0x00000014U)
#define EDMA3_TCRL_POPT_TCINTEN_RESETVAL (0x00000000U)

/*----TCINTEN Tokens----*/
#define EDMA3_TCRL_POPT_TCINTEN_DISABLE  (0x00000000U)
#define EDMA3_TCRL_POPT_TCINTEN_ENABLE   (0x00000001U)

#define EDMA3_TCRL_POPT_TCC_MASK         (0x0003F000U)
#define EDMA3_TCRL_POPT_TCC_SHIFT        (0x0000000CU)
#define EDMA3_TCRL_POPT_TCC_RESETVAL     (0x00000000U)

#define EDMA3_TCRL_POPT_FWID_MASK        (0x00000700U)
#define EDMA3_TCRL_POPT_FWID_SHIFT       (0x00000008U)
#define EDMA3_TCRL_POPT_FWID_RESETVAL    (0x00000000U)

/*----FWID Tokens----*/
#define EDMA3_TCRL_POPT_FWID_8BIT        (0x00000000U)
#define EDMA3_TCRL_POPT_FWID_16BIT       (0x00000001U)
#define EDMA3_TCRL_POPT_FWID_32BIT       (0x00000002U)
#define EDMA3_TCRL_POPT_FWID_64BIT       (0x00000003U)
#define EDMA3_TCRL_POPT_FWID_128BIT      (0x00000004U)
#define EDMA3_TCRL_POPT_FWID_256BIT      (0x00000005U)

#define EDMA3_TCRL_POPT_PRI_MASK         (0x00000070U)
#define EDMA3_TCRL_POPT_PRI_SHIFT        (0x00000004U)
#define EDMA3_TCRL_POPT_PRI_RESETVAL     (0x00000000U)

#define EDMA3_TCRL_POPT_DAM_MASK         (0x00000002U)
#define EDMA3_TCRL_POPT_DAM_SHIFT        (0x00000001U)
#define EDMA3_TCRL_POPT_DAM_RESETVAL     (0x00000000U)

/*----DAM Tokens----*/
#define EDMA3_TCRL_POPT_DAM_INCR         (0x00000000U)
#define EDMA3_TCRL_POPT_DAM_FIFO         (0x00000001U)

#define EDMA3_TCRL_POPT_SAM_MASK         (0x00000001U)
#define EDMA3_TCRL_POPT_SAM_SHIFT        (0x00000000U)
#define EDMA3_TCRL_POPT_SAM_RESETVAL     (0x00000000U)

/*----SAM Tokens----*/
#define EDMA3_TCRL_POPT_SAM_INCR         (0x00000000U)
#define EDMA3_TCRL_POPT_SAM_FIFO         (0x00000001U)

#define EDMA3_TCRL_POPT_RESETVAL         (0x00000000U)

/* PSRC */

#define EDMA3_TCRL_PSRC_SADDR_MASK       (0xFFFFFFFFU)
#define EDMA3_TCRL_PSRC_SADDR_SHIFT      (0x00000000U)
#define EDMA3_TCRL_PSRC_SADDR_RESETVAL   (0x00000000U)

#define EDMA3_TCRL_PSRC_RESETVAL         (0x00000000U)

/* PCNT */

#define EDMA3_TCRL_PCNT_BCNT_MASK        (0xFFFF0000U)
#define EDMA3_TCRL_PCNT_BCNT_SHIFT       (0x00000010U)
#define EDMA3_TCRL_PCNT_BCNT_RESETVAL    (0x00000000U)

#define EDMA3_TCRL_PCNT_ACNT_MASK        (0x0000FFFFU)
#define EDMA3_TCRL_PCNT_ACNT_SHIFT       (0x00000000U)
#define EDMA3_TCRL_PCNT_ACNT_RESETVAL    (0x00000000U)

#define EDMA3_TCRL_PCNT_RESETVAL         (0x00000000U)

/* PDST */

#define EDMA3_TCRL_PDST_DADDR_MASK       (0xFFFFFFFFU)
#define EDMA3_TCRL_PDST_DADDR_SHIFT      (0x00000000U)
#define EDMA3_TCRL_PDST_DADDR_RESETVAL   (0x00000000U)

#define EDMA3_TCRL_PDST_RESETVAL         (0x00000000U)

/* PBIDX */

#define EDMA3_TCRL_PBIDX_DBIDX_MASK      (0xFFFF0000U)
#define EDMA3_TCRL_PBIDX_DBIDX_SHIFT     (0x00000010U)
#define EDMA3_TCRL_PBIDX_DBIDX_RESETVAL  (0x00000000U)

#define EDMA3_TCRL_PBIDX_SBIDX_MASK      (0x0000FFFFU)
#define EDMA3_TCRL_PBIDX_SBIDX_SHIFT     (0x00000000U)
#define EDMA3_TCRL_PBIDX_SBIDX_RESETVAL  (0x00000000U)

#define EDMA3_TCRL_PBIDX_RESETVAL        (0x00000000U)

/* PMPPRXY */

#define EDMA3_TCRL_PMPPRXY_PRIV_MASK     (0x00000100U)
#define EDMA3_TCRL_PMPPRXY_PRIV_SHIFT    (0x00000008U)
#define EDMA3_TCRL_PMPPRXY_PRIV_RESETVAL (0x00000000U)

/*----PRIV Tokens----*/
#define EDMA3_TCRL_PMPPRXY_PRIV_USER     (0x00000000U)
#define EDMA3_TCRL_PMPPRXY_PRIV_SUPERVISOR (0x00000001U)

#define EDMA3_TCRL_PMPPRXY_PRIVID_MASK   (0x0000000FU)
#define EDMA3_TCRL_PMPPRXY_PRIVID_SHIFT  (0x00000000U)
#define EDMA3_TCRL_PMPPRXY_PRIVID_RESETVAL (0x00000000U)

#define EDMA3_TCRL_PMPPRXY_RESETVAL      (0x00000000U)

/* SAOPT */

#define EDMA3_TCRL_SAOPT_TCCHEN_MASK     (0x00400000U)
#define EDMA3_TCRL_SAOPT_TCCHEN_SHIFT    (0x00000016U)
#define EDMA3_TCRL_SAOPT_TCCHEN_RESETVAL (0x00000000U)

/*----TCCHEN Tokens----*/
#define EDMA3_TCRL_SAOPT_TCCHEN_DISABLE  (0x00000000U)
#define EDMA3_TCRL_SAOPT_TCCHEN_ENABLE   (0x00000001U)

#define EDMA3_TCRL_SAOPT_TCINTEN_MASK    (0x00100000U)
#define EDMA3_TCRL_SAOPT_TCINTEN_SHIFT   (0x00000014U)
#define EDMA3_TCRL_SAOPT_TCINTEN_RESETVAL (0x00000000U)

/*----TCINTEN Tokens----*/
#define EDMA3_TCRL_SAOPT_TCINTEN_DISABLE (0x00000000U)
#define EDMA3_TCRL_SAOPT_TCINTEN_ENABLE  (0x00000001U)

#define EDMA3_TCRL_SAOPT_TCC_MASK        (0x0003F000U)
#define EDMA3_TCRL_SAOPT_TCC_SHIFT       (0x0000000CU)
#define EDMA3_TCRL_SAOPT_TCC_RESETVAL    (0x00000000U)

#define EDMA3_TCRL_SAOPT_FWID_MASK       (0x00000700U)
#define EDMA3_TCRL_SAOPT_FWID_SHIFT      (0x00000008U)
#define EDMA3_TCRL_SAOPT_FWID_RESETVAL   (0x00000000U)

/*----FWID Tokens----*/
#define EDMA3_TCRL_SAOPT_FWID_8BIT       (0x00000000U)
#define EDMA3_TCRL_SAOPT_FWID_16BIT      (0x00000001U)
#define EDMA3_TCRL_SAOPT_FWID_32BIT      (0x00000002U)
#define EDMA3_TCRL_SAOPT_FWID_64BIT      (0x00000003U)
#define EDMA3_TCRL_SAOPT_FWID_128BIT     (0x00000004U)
#define EDMA3_TCRL_SAOPT_FWID_256BIT     (0x00000005U)

#define EDMA3_TCRL_SAOPT_PRI_MASK        (0x00000070U)
#define EDMA3_TCRL_SAOPT_PRI_SHIFT       (0x00000004U)
#define EDMA3_TCRL_SAOPT_PRI_RESETVAL    (0x00000000U)

#define EDMA3_TCRL_SAOPT_DAM_MASK        (0x00000002U)
#define EDMA3_TCRL_SAOPT_DAM_SHIFT       (0x00000001U)
#define EDMA3_TCRL_SAOPT_DAM_RESETVAL    (0x00000000U)

/*----DAM Tokens----*/
#define EDMA3_TCRL_SAOPT_DAM_INCR        (0x00000000U)
#define EDMA3_TCRL_SAOPT_DAM_FIFO        (0x00000001U)

#define EDMA3_TCRL_SAOPT_SAM_MASK        (0x00000001U)
#define EDMA3_TCRL_SAOPT_SAM_SHIFT       (0x00000000U)
#define EDMA3_TCRL_SAOPT_SAM_RESETVAL    (0x00000000U)

/*----SAM Tokens----*/
#define EDMA3_TCRL_SAOPT_SAM_INCR        (0x00000000U)
#define EDMA3_TCRL_SAOPT_SAM_FIFO        (0x00000001U)

#define EDMA3_TCRL_SAOPT_RESETVAL        (0x00000000U)

/* SASRC */

#define EDMA3_TCRL_SASRC_SADDR_MASK      (0xFFFFFFFFU)
#define EDMA3_TCRL_SASRC_SADDR_SHIFT     (0x00000000U)
#define EDMA3_TCRL_SASRC_SADDR_RESETVAL  (0x00000000U)

#define EDMA3_TCRL_SASRC_RESETVAL        (0x00000000U)

/* SACNT */

#define EDMA3_TCRL_SACNT_BCNT_MASK       (0xFFFF0000U)
#define EDMA3_TCRL_SACNT_BCNT_SHIFT      (0x00000010U)
#define EDMA3_TCRL_SACNT_BCNT_RESETVAL   (0x00000000U)

#define EDMA3_TCRL_SACNT_ACNT_MASK       (0x0000FFFFU)
#define EDMA3_TCRL_SACNT_ACNT_SHIFT      (0x00000000U)
#define EDMA3_TCRL_SACNT_ACNT_RESETVAL   (0x00000000U)

#define EDMA3_TCRL_SACNT_RESETVAL        (0x00000000U)

/* SADST */

#define EDMA3_TCRL_SADST_RESETVAL        (0x00000000U)

/* SABIDX */

#define EDMA3_TCRL_SABIDX_DBIDX_MASK     (0xFFFF0000U)
#define EDMA3_TCRL_SABIDX_DBIDX_SHIFT    (0x00000010U)
#define EDMA3_TCRL_SABIDX_DBIDX_RESETVAL (0x00000000U)

#define EDMA3_TCRL_SABIDX_SBIDX_MASK     (0x0000FFFFU)
#define EDMA3_TCRL_SABIDX_SBIDX_SHIFT    (0x00000000U)
#define EDMA3_TCRL_SABIDX_SBIDX_RESETVAL (0x00000000U)

#define EDMA3_TCRL_SABIDX_RESETVAL       (0x00000000U)

/* SAMPPRXY */

#define EDMA3_TCRL_SAMPPRXY_PRIV_MASK    (0x00000100U)
#define EDMA3_TCRL_SAMPPRXY_PRIV_SHIFT   (0x00000008U)
#define EDMA3_TCRL_SAMPPRXY_PRIV_RESETVAL (0x00000000U)

/*----PRIV Tokens----*/
#define EDMA3_TCRL_SAMPPRXY_PRIV_USER    (0x00000000U)
#define EDMA3_TCRL_SAMPPRXY_PRIV_SUPERVISOR (0x00000001U)

#define EDMA3_TCRL_SAMPPRXY_PRIVID_MASK  (0x0000000FU)
#define EDMA3_TCRL_SAMPPRXY_PRIVID_SHIFT (0x00000000U)
#define EDMA3_TCRL_SAMPPRXY_PRIVID_RESETVAL (0x00000000U)

#define EDMA3_TCRL_SAMPPRXY_RESETVAL     (0x00000000U)

/* SACNTRLD */

#define EDMA3_TCRL_SACNTRLD_ACNTRLD_MASK (0x0000FFFFU)
#define EDMA3_TCRL_SACNTRLD_ACNTRLD_SHIFT (0x00000000U)
#define EDMA3_TCRL_SACNTRLD_ACNTRLD_RESETVAL (0x00000000U)

#define EDMA3_TCRL_SACNTRLD_RESETVAL     (0x00000000U)

/* SASRCBREF */

#define EDMA3_TCRL_SASRCBREF_SADDRBREFG_MASK (0xFFFFFFFFU)
#define EDMA3_TCRL_SASRCBREF_SADDRBREFG_SHIFT (0x00000000U)
#define EDMA3_TCRL_SASRCBREF_SADDRBREFG_RESETVAL (0x00000000U)

#define EDMA3_TCRL_SASRCBREF_RESETVAL    (0x00000000U)

/* SADSTBREF */

#define EDMA3_TCRL_SADSTBREF_RESETVAL    (0x00000000U)

/* DFCNTRLD */

#define EDMA3_TCRL_DFCNTRLD_ACNTRLD_MASK (0x0000FFFFU)
#define EDMA3_TCRL_DFCNTRLD_ACNTRLD_SHIFT (0x00000000U)
#define EDMA3_TCRL_DFCNTRLD_ACNTRLD_RESETVAL (0x00000000U)

#define EDMA3_TCRL_DFCNTRLD_RESETVAL     (0x00000000U)

/* DFSRCBREF */

#define EDMA3_TCRL_DFSRCBREF_RESETVAL    (0x00000000U)

/* DFDSTBREF */

#define EDMA3_TCRL_DFDSTBREF_DADDRBREF_MASK (0xFFFFFFFFU)
#define EDMA3_TCRL_DFDSTBREF_DADDRBREF_SHIFT (0x00000000U)
#define EDMA3_TCRL_DFDSTBREF_DADDRBREF_RESETVAL (0x00000000U)

#define EDMA3_TCRL_DFDSTBREF_RESETVAL    (0x00000000U)

/* DFOPT */

#define EDMA3_TCRL_DFOPT_TCCHEN_MASK     (0x00400000U)
#define EDMA3_TCRL_DFOPT_TCCHEN_SHIFT    (0x00000016U)
#define EDMA3_TCRL_DFOPT_TCCHEN_RESETVAL (0x00000000U)

/*----TCCHEN Tokens----*/
#define EDMA3_TCRL_DFOPT_TCCHEN_DISABLE  (0x00000000U)
#define EDMA3_TCRL_DFOPT_TCCHEN_ENABLE   (0x00000001U)

#define EDMA3_TCRL_DFOPT_TCINTEN_MASK    (0x00100000U)
#define EDMA3_TCRL_DFOPT_TCINTEN_SHIFT   (0x00000014U)
#define EDMA3_TCRL_DFOPT_TCINTEN_RESETVAL (0x00000000U)

/*----TCINTEN Tokens----*/
#define EDMA3_TCRL_DFOPT_TCINTEN_DISABLE (0x00000000U)
#define EDMA3_TCRL_DFOPT_TCINTEN_ENABLE  (0x00000001U)

#define EDMA3_TCRL_DFOPT_TCC_MASK        (0x0003F000U)
#define EDMA3_TCRL_DFOPT_TCC_SHIFT       (0x0000000CU)
#define EDMA3_TCRL_DFOPT_TCC_RESETVAL    (0x00000000U)

#define EDMA3_TCRL_DFOPT_FWID_MASK       (0x00000700U)
#define EDMA3_TCRL_DFOPT_FWID_SHIFT      (0x00000008U)
#define EDMA3_TCRL_DFOPT_FWID_RESETVAL   (0x00000000U)

/*----FWID Tokens----*/
#define EDMA3_TCRL_DFOPT_FWID_8BIT       (0x00000000U)
#define EDMA3_TCRL_DFOPT_FWID_16BIT      (0x00000001U)
#define EDMA3_TCRL_DFOPT_FWID_32BIT      (0x00000002U)
#define EDMA3_TCRL_DFOPT_FWID_64BIT      (0x00000003U)
#define EDMA3_TCRL_DFOPT_FWID_128BIT     (0x00000004U)
#define EDMA3_TCRL_DFOPT_FWID_256BIT     (0x00000005U)

#define EDMA3_TCRL_DFOPT_PRI_MASK        (0x00000070U)
#define EDMA3_TCRL_DFOPT_PRI_SHIFT       (0x00000004U)
#define EDMA3_TCRL_DFOPT_PRI_RESETVAL    (0x00000000U)

#define EDMA3_TCRL_DFOPT_DAM_MASK        (0x00000002U)
#define EDMA3_TCRL_DFOPT_DAM_SHIFT       (0x00000001U)
#define EDMA3_TCRL_DFOPT_DAM_RESETVAL    (0x00000000U)

/*----DAM Tokens----*/
#define EDMA3_TCRL_DFOPT_DAM_INCR        (0x00000000U)
#define EDMA3_TCRL_DFOPT_DAM_FIFO        (0x00000001U)

#define EDMA3_TCRL_DFOPT_SAM_MASK        (0x00000001U)
#define EDMA3_TCRL_DFOPT_SAM_SHIFT       (0x00000000U)
#define EDMA3_TCRL_DFOPT_SAM_RESETVAL    (0x00000000U)

/*----SAM Tokens----*/
#define EDMA3_TCRL_DFOPT_SAM_INCR        (0x00000000U)
#define EDMA3_TCRL_DFOPT_SAM_FIFO        (0x00000001U)

#define EDMA3_TCRL_DFOPT_RESETVAL        (0x00000000U)

/* DFSRC */

#define EDMA3_TCRL_DFSRC_RESETVAL        (0x00000000U)

/* DFCNT */

#define EDMA3_TCRL_DFCNT_BCNT_MASK       (0xFFFF0000U)
#define EDMA3_TCRL_DFCNT_BCNT_SHIFT      (0x00000010U)
#define EDMA3_TCRL_DFCNT_BCNT_RESETVAL   (0x00000000U)

#define EDMA3_TCRL_DFCNT_ACNT_MASK       (0x0000FFFFU)
#define EDMA3_TCRL_DFCNT_ACNT_SHIFT      (0x00000000U)
#define EDMA3_TCRL_DFCNT_ACNT_RESETVAL   (0x00000000U)

#define EDMA3_TCRL_DFCNT_RESETVAL        (0x00000000U)

/* DFDST */

#define EDMA3_TCRL_DFDST_DADDR_MASK      (0xFFFFFFFFU)
#define EDMA3_TCRL_DFDST_DADDR_SHIFT     (0x00000000U)
#define EDMA3_TCRL_DFDST_DADDR_RESETVAL  (0x00000000U)

#define EDMA3_TCRL_DFDST_RESETVAL        (0x00000000U)

/* DFBIDX */

#define EDMA3_TCRL_DFBIDX_DBIDX_MASK     (0xFFFF0000U)
#define EDMA3_TCRL_DFBIDX_DBIDX_SHIFT    (0x00000010U)
#define EDMA3_TCRL_DFBIDX_DBIDX_RESETVAL (0x00000000U)

#define EDMA3_TCRL_DFBIDX_SBIDX_MASK     (0x0000FFFFU)
#define EDMA3_TCRL_DFBIDX_SBIDX_SHIFT    (0x00000000U)
#define EDMA3_TCRL_DFBIDX_SBIDX_RESETVAL (0x00000000U)

#define EDMA3_TCRL_DFBIDX_RESETVAL       (0x00000000U)

/* DFMPPRXY */

#define EDMA3_TCRL_DFMPPRXY_PRIV_MASK    (0x00000100U)
#define EDMA3_TCRL_DFMPPRXY_PRIV_SHIFT   (0x00000008U)
#define EDMA3_TCRL_DFMPPRXY_PRIV_RESETVAL (0x00000000U)

/*----PRIV Tokens----*/
#define EDMA3_TCRL_DFMPPRXY_PRIV_USER    (0x00000000U)
#define EDMA3_TCRL_DFMPPRXY_PRIV_SUPERVISOR (0x00000001U)

#define EDMA3_TCRL_DFMPPRXY_PRIVID_MASK  (0x0000000FU)
#define EDMA3_TCRL_DFMPPRXY_PRIVID_SHIFT (0x00000000U)
#define EDMA3_TCRL_DFMPPRXY_PRIVID_RESETVAL (0x00000000U)

#define EDMA3_TCRL_DFMPPRXY_RESETVAL     (0x00000000U)

#ifdef __cplusplus
}
#endif /* extern "C" */

#endif  /* _EDMA3_RL_TC_H_ */
