/*
 * Auto-generated CSL section
 */
/*
 *
 * Copyright (C) 2013 - 2018 Texas Instruments Incorporated - http://www.ti.com/
 *
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
*/

#ifndef CSL_RL_K2G_H
#define CSL_RL_K2G_H

#include <ti/csl/cslr.h>
#include <ti/csl/tistdtypes.h>

#ifdef __cplusplus
extern "C" {
#endif

/*
 * Auto-generated CSL section
 */
#define ARM_GIC_EVENT_CNT 479
#define CSL_ARM_GIC_RSTMUX_INT8 (0x00000000)
#define CSL_ARM_GIC_IPC_GR8 (0x00000001)
#define CSL_ARM_GIC_SEM_INT8 (0x00000002)
#define CSL_ARM_GIC_SEM_ERR8 (0x00000003)
#define CSL_ARM_GIC_ARM_NPMUIRQ0 (0x00000004)
#define CSL_ARM_GIC_ARM_NINTERRIRQ (0x00000005)
#define CSL_ARM_GIC_ARM_NAXIERRIRQ (0x00000006)
#define CSL_ARM_GIC_ARM_NCTIIRQ0 (0x00000007)
#define CSL_ARM_GIC_ARM_TBR_DMA (0x00000008)
#define CSL_ARM_GIC_ARM_TBR_ACQ (0x00000009)
#define CSL_ARM_GIC_BOOTCFG_INT (0x0000000A)
#define CSL_ARM_GIC_RESERVED_11 (0x0000000B)
#define CSL_ARM_GIC_RESERVED_12 (0x0000000C)
#define CSL_ARM_GIC_RESERVED_13 (0x0000000D)
#define CSL_ARM_GIC_RESERVED_14 (0x0000000E)
#define CSL_ARM_GIC_RESERVED_15 (0x0000000F)
#define CSL_ARM_GIC_TIMER_0_INTL (0x00000010)
#define CSL_ARM_GIC_TIMER_0_INTH (0x00000011)
#define CSL_ARM_GIC_TIMER_1_INTL (0x00000012)
#define CSL_ARM_GIC_TIMER_1_INTH (0x00000013)
#define CSL_ARM_GIC_TIMER_2_INTL (0x00000014)
#define CSL_ARM_GIC_TIMER_2_INTH (0x00000015)
#define CSL_ARM_GIC_TIMER_3_INTL (0x00000016)
#define CSL_ARM_GIC_TIMER_3_INTH (0x00000017)
#define CSL_ARM_GIC_TIMER_4_INTL (0x00000018)
#define CSL_ARM_GIC_TIMER_4_INTH (0x00000019)
#define CSL_ARM_GIC_TIMER_5_INTL (0x0000001A)
#define CSL_ARM_GIC_TIMER_5_INTH (0x0000001B)
#define CSL_ARM_GIC_TIMER_6_INTL (0x0000001C)
#define CSL_ARM_GIC_TIMER_6_INTH (0x0000001D)
#define CSL_ARM_GIC_RESERVED_30 (0x0000001E)
#define CSL_ARM_GIC_RESERVED_31 (0x0000001F)
#define CSL_ARM_GIC_RESERVED_32 (0x00000020)
#define CSL_ARM_GIC_RESERVED_33 (0x00000021)
#define CSL_ARM_GIC_RESERVED_34 (0x00000022)
#define CSL_ARM_GIC_RESERVED_35 (0x00000023)
#define CSL_ARM_GIC_RESERVED_36 (0x00000024)
#define CSL_ARM_GIC_RESERVED_37 (0x00000025)
#define CSL_ARM_GIC_RESERVED_38 (0x00000026)
#define CSL_ARM_GIC_RESERVED_39 (0x00000027)
#define CSL_ARM_GIC_RESERVED_40 (0x00000028)
#define CSL_ARM_GIC_RESERVED_41 (0x00000029)
#define CSL_ARM_GIC_RESERVED_42 (0x0000002A)
#define CSL_ARM_GIC_RESERVED_43 (0x0000002B)
#define CSL_ARM_GIC_RESERVED_44 (0x0000002C)
#define CSL_ARM_GIC_RESERVED_45 (0x0000002D)
#define CSL_ARM_GIC_RESERVED_46 (0x0000002E)
#define CSL_ARM_GIC_RESERVED_47 (0x0000002F)
#define CSL_ARM_GIC_PCIE_INT0 (0x00000030)
#define CSL_ARM_GIC_PCIE_INT1 (0x00000031)
#define CSL_ARM_GIC_PCIE_INT2 (0x00000032)
#define CSL_ARM_GIC_PCIE_INT3 (0x00000033)
#define CSL_ARM_GIC_PCIE_INT4 (0x00000034)
#define CSL_ARM_GIC_PCIE_INT5 (0x00000035)
#define CSL_ARM_GIC_PCIE_INT6 (0x00000036)
#define CSL_ARM_GIC_PCIE_INT7 (0x00000037)
#define CSL_ARM_GIC_PCIE_INT8 (0x00000038)
#define CSL_ARM_GIC_PCIE_INT9 (0x00000039)
#define CSL_ARM_GIC_PCIE_INT10 (0x0000003A)
#define CSL_ARM_GIC_PCIE_INT11 (0x0000003B)
#define CSL_ARM_GIC_PCIE_INT12 (0x0000003C)
#define CSL_ARM_GIC_PCIE_INT13 (0x0000003D)
#define CSL_ARM_GIC_PCIE_ECC_ERROR (0x0000003E)
#define CSL_ARM_GIC_RESERVED_63 (0x0000003F)
#define CSL_ARM_GIC_SPI_0_INT0 (0x00000040)
#define CSL_ARM_GIC_SPI_0_INT1 (0x00000041)
#define CSL_ARM_GIC_SPI_1_INT0 (0x00000042)
#define CSL_ARM_GIC_SPI_1_INT1 (0x00000043)
#define CSL_ARM_GIC_SPI_2_INT0 (0x00000044)
#define CSL_ARM_GIC_SPI_2_INT1 (0x00000045)
#define CSL_ARM_GIC_SPI_3_INT0 (0x00000046)
#define CSL_ARM_GIC_SPI_3_INT1 (0x00000047)
#define CSL_ARM_GIC_RESERVED_72 (0x00000048)
#define CSL_ARM_GIC_RESERVED_73 (0x00000049)
#define CSL_ARM_GIC_RESERVED_74 (0x0000004A)
#define CSL_ARM_GIC_RESERVED_75 (0x0000004B)
#define CSL_ARM_GIC_RESERVED_76 (0x0000004C)
#define CSL_ARM_GIC_RESERVED_77 (0x0000004D)
#define CSL_ARM_GIC_RESERVED_78 (0x0000004E)
#define CSL_ARM_GIC_RESERVED_79 (0x0000004F)
#define CSL_ARM_GIC_McASP_0_XINT (0x00000050)
#define CSL_ARM_GIC_McASP_0_RINT (0x00000051)
#define CSL_ARM_GIC_McASP_1_XINT (0x00000052)
#define CSL_ARM_GIC_McASP_1_RINT (0x00000053)
#define CSL_ARM_GIC_McASP_2_XINT (0x00000054)
#define CSL_ARM_GIC_McASP_2_RINT (0x00000055)
#define CSL_ARM_GIC_RESERVED_86 (0x00000056)
#define CSL_ARM_GIC_RESERVED_87 (0x00000057)
#define CSL_ARM_GIC_I2C_0_INT (0x00000058)
#define CSL_ARM_GIC_I2C_1_INT (0x00000059)
#define CSL_ARM_GIC_I2C_2_INT (0x0000005A)
#define CSL_ARM_GIC_RESERVED_91 (0x0000005B)
#define CSL_ARM_GIC_RESERVED_92 (0x0000005C)
#define CSL_ARM_GIC_RESERVED_93 (0x0000005D)
#define CSL_ARM_GIC_RESERVED_94 (0x0000005E)
#define CSL_ARM_GIC_RESERVED_95 (0x0000005F)
#define CSL_ARM_GIC_MMC_SD_0_INT (0x00000060)
#define CSL_ARM_GIC_MMC_SD_1_INT (0x00000061)
#define CSL_ARM_GIC_RESERVED_98 (0x00000062)
#define CSL_ARM_GIC_RESERVED_99 (0x00000063)
#define CSL_ARM_GIC_McBSP_XINT (0x00000064)
#define CSL_ARM_GIC_McBSP_RINT (0x00000065)
#define CSL_ARM_GIC_RESERVED_102 (0x00000066)
#define CSL_ARM_GIC_RESERVED_103 (0x00000067)
#define CSL_ARM_GIC_NSS_CDMA_STARVE_INT (0x00000068)
#define CSL_ARM_GIC_NSS_SWITCH_STAT_INT0 (0x00000069)
#define CSL_ARM_GIC_NSS_SWITCH_STAT_INT1 (0x0000006A)
#define CSL_ARM_GIC_NSS_NAVSS_ECC_INT (0x0000006B)
#define CSL_ARM_GIC_NSS_SA_UL_ECC_INT (0x0000006C)
#define CSL_ARM_GIC_NSS_SWITCH_ECC_INT (0x0000006D)
#define CSL_ARM_GIC_NSS_MDIO_LINK_INT0 (0x0000006E)
#define CSL_ARM_GIC_NSS_CPTS_EVENT_INT (0x0000006F)
#define CSL_ARM_GIC_NSS_MDIO_USER_INT0 (0x00000070)
#define CSL_ARM_GIC_NSS_MDIO_USER_INT1 (0x00000071)
#define CSL_ARM_GIC_PKA_INT (0x00000072)
#define CSL_ARM_GIC_RNG_INT (0x00000073)
#define CSL_ARM_GIC_RESERVED_116 (0x00000074)
#define CSL_ARM_GIC_RESERVED_117 (0x00000075)
#define CSL_ARM_GIC_RESERVED_118 (0x00000076)
#define CSL_ARM_GIC_RESERVED_119 (0x00000077)
#define CSL_ARM_GIC_MLB_DMA_CH_INT0 (0x00000078)
#define CSL_ARM_GIC_MLB_DMA_CH_INT1 (0x00000079)
#define CSL_ARM_GIC_MLB_SYS_INT (0x0000007A)
#define CSL_ARM_GIC_DDR3_ERR (0x0000007B)
#define CSL_ARM_GIC_SR_0_SR_I2CINT (0x0000007C)
#define CSL_ARM_GIC_RESERVED_125 (0x0000007D)
#define CSL_ARM_GIC_RESERVED_126 (0x0000007E)
#define CSL_ARM_GIC_RESERVED_127 (0x0000007F)
#define CSL_ARM_GIC_USB_0_INT00 (0x00000080)
#define CSL_ARM_GIC_USB_0_INT01 (0x00000081)
#define CSL_ARM_GIC_USB_0_INT02 (0x00000082)
#define CSL_ARM_GIC_USB_0_INT03 (0x00000083)
#define CSL_ARM_GIC_USB_0_INT04 (0x00000084)
#define CSL_ARM_GIC_USB_0_INT05 (0x00000085)
#define CSL_ARM_GIC_USB_0_INT06 (0x00000086)
#define CSL_ARM_GIC_USB_0_INT07 (0x00000087)
#define CSL_ARM_GIC_USB_0_INT08 (0x00000088)
#define CSL_ARM_GIC_USB_0_INT09 (0x00000089)
#define CSL_ARM_GIC_USB_0_INT10 (0x0000008A)
#define CSL_ARM_GIC_USB_0_INT11 (0x0000008B)
#define CSL_ARM_GIC_USB_0_INT12 (0x0000008C)
#define CSL_ARM_GIC_USB_0_INT13 (0x0000008D)
#define CSL_ARM_GIC_USB_0_INT14 (0x0000008E)
#define CSL_ARM_GIC_USB_0_INT15 (0x0000008F)
#define CSL_ARM_GIC_USB_1_INT00 (0x00000090)
#define CSL_ARM_GIC_USB_1_INT01 (0x00000091)
#define CSL_ARM_GIC_USB_1_INT02 (0x00000092)
#define CSL_ARM_GIC_USB_1_INT03 (0x00000093)
#define CSL_ARM_GIC_USB_1_INT04 (0x00000094)
#define CSL_ARM_GIC_USB_1_INT05 (0x00000095)
#define CSL_ARM_GIC_USB_1_INT06 (0x00000096)
#define CSL_ARM_GIC_USB_1_INT07 (0x00000097)
#define CSL_ARM_GIC_USB_1_INT08 (0x00000098)
#define CSL_ARM_GIC_USB_1_INT09 (0x00000099)
#define CSL_ARM_GIC_USB_1_INT10 (0x0000009A)
#define CSL_ARM_GIC_USB_1_INT11 (0x0000009B)
#define CSL_ARM_GIC_USB_1_INT12 (0x0000009C)
#define CSL_ARM_GIC_USB_1_INT13 (0x0000009D)
#define CSL_ARM_GIC_USB_1_INT14 (0x0000009E)
#define CSL_ARM_GIC_USB_1_INT15 (0x0000009F)
#define CSL_ARM_GIC_USB_0_OABSINT (0x000000A0)
#define CSL_ARM_GIC_USB_0_MISCINT (0x000000A1)
#define CSL_ARM_GIC_USB_1_OABSINT (0x000000A2)
#define CSL_ARM_GIC_USB_1_MISCINT (0x000000A3)
#define CSL_ARM_GIC_UART_0_UARTINT (0x000000A4)
#define CSL_ARM_GIC_UART_1_UARTINT (0x000000A5)
#define CSL_ARM_GIC_UART_2_UARTINT (0x000000A6)
#define CSL_ARM_GIC_RESERVED_167 (0x000000A7)
#define CSL_ARM_GIC_RESERVED_168 (0x000000A8)
#define CSL_ARM_GIC_RESERVED_169 (0x000000A9)
#define CSL_ARM_GIC_RESERVED_170 (0x000000AA)
#define CSL_ARM_GIC_RESERVED_171 (0x000000AB)
#define CSL_ARM_GIC_EPWM_0_INT (0x000000AC)
#define CSL_ARM_GIC_EPWM_1_INT (0x000000AD)
#define CSL_ARM_GIC_EPWM_2_INT (0x000000AE)
#define CSL_ARM_GIC_EPWM_3_INT (0x000000AF)
#define CSL_ARM_GIC_EPWM_4_INT (0x000000B0)
#define CSL_ARM_GIC_EPWM_5_INT (0x000000B1)
#define CSL_ARM_GIC_EPWM_0_TRIP_ZONE (0x000000B2)
#define CSL_ARM_GIC_EPWM_1_TRIP_ZONE (0x000000B3)
#define CSL_ARM_GIC_EPWM_2_TRIP_ZONE (0x000000B4)
#define CSL_ARM_GIC_EPWM_3_TRIP_ZONE (0x000000B5)
#define CSL_ARM_GIC_EPWM_4_TRIP_ZONE (0x000000B6)
#define CSL_ARM_GIC_EPWM_5_TRIP_ZONE (0x000000B7)
#define CSL_ARM_GIC_EQEP_0_INT (0x000000B8)
#define CSL_ARM_GIC_EQEP_1_INT (0x000000B9)
#define CSL_ARM_GIC_EQEP_2_INT (0x000000BA)
#define CSL_ARM_GIC_ECAP_0_INT (0x000000BB)
#define CSL_ARM_GIC_ECAP_1_INT (0x000000BC)
#define CSL_ARM_GIC_RESERVED_189 (0x000000BD)
#define CSL_ARM_GIC_DCAN_0_INT0 (0x000000BE)
#define CSL_ARM_GIC_DCAN_0_INT1 (0x000000BF)
#define CSL_ARM_GIC_DCAN_0_ERR_INT (0x000000C0)
#define CSL_ARM_GIC_DCAN_1_INT0 (0x000000C1)
#define CSL_ARM_GIC_DCAN_1_INT1 (0x000000C2)
#define CSL_ARM_GIC_DCAN_1_ERR_INT (0x000000C3)
#define CSL_ARM_GIC_GPMC_INT (0x000000C4)
#define CSL_ARM_GIC_ELM_INT (0x000000C5)
#define CSL_ARM_GIC_QSPI_INT (0x000000C6)
#define CSL_ARM_GIC_QSPI_ECC_ERR (0x000000C7)
#define CSL_ARM_GIC_EDMACC_0_REGION_0_INT (0x000000C8)
#define CSL_ARM_GIC_EDMACC_0_REGION_1_INT (0x000000C9)
#define CSL_ARM_GIC_EDMACC_0_REGION_2_INT (0x000000CA)
#define CSL_ARM_GIC_EDMACC_0_REGION_3_INT (0x000000CB)
#define CSL_ARM_GIC_EDMACC_0_REGION_4_INT (0x000000CC)
#define CSL_ARM_GIC_EDMACC_0_REGION_5_INT (0x000000CD)
#define CSL_ARM_GIC_EDMACC_0_REGION_6_INT (0x000000CE)
#define CSL_ARM_GIC_EDMACC_0_REGION_7_INT (0x000000CF)
#define CSL_ARM_GIC_EDMACC_1_REGION_0_INT (0x000000D0)
#define CSL_ARM_GIC_EDMACC_1_REGION_1_INT (0x000000D1)
#define CSL_ARM_GIC_EDMACC_1_REGION_2_INT (0x000000D2)
#define CSL_ARM_GIC_EDMACC_1_REGION_3_INT (0x000000D3)
#define CSL_ARM_GIC_EDMACC_1_REGION_4_INT (0x000000D4)
#define CSL_ARM_GIC_EDMACC_1_REGION_5_INT (0x000000D5)
#define CSL_ARM_GIC_EDMACC_1_REGION_6_INT (0x000000D6)
#define CSL_ARM_GIC_EDMACC_1_REGION_7_INT (0x000000D7)
#define CSL_ARM_GIC_EDMACC_0_MPINT (0x000000D8)
#define CSL_ARM_GIC_EDMACC_0_ERRINT (0x000000D9)
#define CSL_ARM_GIC_EDMACC_0_GINT (0x000000DA)
#define CSL_ARM_GIC_EDMACC_1_MPINT (0x000000DB)
#define CSL_ARM_GIC_EDMACC_1_ERRINT (0x000000DC)
#define CSL_ARM_GIC_EDMACC_1_GINT (0x000000DD)
#define CSL_ARM_GIC_RESERVED_222 (0x000000DE)
#define CSL_ARM_GIC_RESERVED_223 (0x000000DF)
#define CSL_ARM_GIC_ICSSM0_HOST_INT0 (0x000000E0)
#define CSL_ARM_GIC_ICSSM0_HOST_INT1 (0x000000E1)
#define CSL_ARM_GIC_ICSSM0_HOST_INT2 (0x000000E2)
#define CSL_ARM_GIC_ICSSM0_HOST_INT3 (0x000000E3)
#define CSL_ARM_GIC_ICSSM0_HOST_INT4 (0x000000E4)
#define CSL_ARM_GIC_RESERVED_229 (0x000000E5)
#define CSL_ARM_GIC_ICSSM0_HOST_INT6 (0x000000E6)
#define CSL_ARM_GIC_ICSSM0_HOST_INT7 (0x000000E7)
#define CSL_ARM_GIC_ICSSM1_HOST_INT0 (0x000000E8)
#define CSL_ARM_GIC_ICSSM1_HOST_INT1 (0x000000E9)
#define CSL_ARM_GIC_ICSSM1_HOST_INT2 (0x000000EA)
#define CSL_ARM_GIC_ICSSM1_HOST_INT3 (0x000000EB)
#define CSL_ARM_GIC_ICSSM1_HOST_INT4 (0x000000EC)
#define CSL_ARM_GIC_RESERVED_237 (0x000000ED)
#define CSL_ARM_GIC_ICSSM1_HOST_INT6 (0x000000EE)
#define CSL_ARM_GIC_ICSSM1_HOST_INT7 (0x000000EF)
#define CSL_ARM_GIC_ASRC_STREAM_IN_INT (0x000000F0)
#define CSL_ARM_GIC_ASRC_STREAM_OUT_INT (0x000000F1)
#define CSL_ARM_GIC_ASRC_STREAM_ERR_INT (0x000000F2)
#define CSL_ARM_GIC_ASRC_GROUP_IN_INT (0x000000F3)
#define CSL_ARM_GIC_ASRC_GROUP_OUT_INT (0x000000F4)
#define CSL_ARM_GIC_RESERVED_245 (0x000000F5)
#define CSL_ARM_GIC_RESERVED_246 (0x000000F6)
#define CSL_ARM_GIC_DSS_INT (0x000000F7)
#define CSL_ARM_GIC_DBGTBR_DMAINT (0x000000F8)
#define CSL_ARM_GIC_DBGTBR_ACQCOMP (0x000000F9)
#define CSL_ARM_GIC_MSMC_MPF_ERROR1 (0x000000FA)
#define CSL_ARM_GIC_PMMC_INT0 (0x000000FB)
#define CSL_ARM_GIC_PMMC_FAULTDET_INT (0x000000FC)
#define CSL_ARM_GIC_SECMGRINT (0x000000FD)
#define CSL_ARM_GIC_PMMCTBR_ACQCOMP (0x000000FE)
#define CSL_ARM_GIC_PMMCTBR_DMAINT (0x000000FF)
#define CSL_ARM_GIC_SR_0_PO_VCON_SMPSERR_INT (0x00000100)
#define CSL_ARM_GIC_SR_0_SMARTREFLEX_INTREQ0 (0x00000101)
#define CSL_ARM_GIC_SR_0_SMARTREFLEX_INTREQ1 (0x00000102)
#define CSL_ARM_GIC_SR_0_SMARTREFLEX_INTREQ2 (0x00000103)
#define CSL_ARM_GIC_SR_0_SMARTREFLEX_INTREQ3 (0x00000104)
#define CSL_ARM_GIC_SR_0_VPNOSMPSACK (0x00000105)
#define CSL_ARM_GIC_SR_0_VPEQVALUE (0x00000106)
#define CSL_ARM_GIC_SR_0_VPMAXVDD (0x00000107)
#define CSL_ARM_GIC_SR_0_VPMINVDD (0x00000108)
#define CSL_ARM_GIC_SR_0_VPINIDLE (0x00000109)
#define CSL_ARM_GIC_SR_0_VPOPPCHANGEDONE (0x0000010A)
#define CSL_ARM_GIC_SR_0_VPSMPSACK (0x0000010B)
#define CSL_ARM_GIC_SR_0_SR_TEMPSENSOR (0x0000010C)
#define CSL_ARM_GIC_SR_0_SR_TIMERINT (0x0000010D)
#define CSL_ARM_GIC_SR_0_SR_MAX_TEMP_INT (0x0000010E)
#define CSL_ARM_GIC_SR_0_SR_SMBALERT (0x0000010F)
#define CSL_ARM_GIC_NSS_QPEND0 (0x00000110)
#define CSL_ARM_GIC_NSS_QPEND1 (0x00000111)
#define CSL_ARM_GIC_NSS_QPEND2 (0x00000112)
#define CSL_ARM_GIC_NSS_QPEND3 (0x00000113)
#define CSL_ARM_GIC_NSS_QPEND4 (0x00000114)
#define CSL_ARM_GIC_NSS_QPEND5 (0x00000115)
#define CSL_ARM_GIC_NSS_QPEND6 (0x00000116)
#define CSL_ARM_GIC_NSS_QPEND7 (0x00000117)
#define CSL_ARM_GIC_NSS_QPEND8 (0x00000118)
#define CSL_ARM_GIC_NSS_QPEND9 (0x00000119)
#define CSL_ARM_GIC_NSS_QPEND10 (0x0000011A)
#define CSL_ARM_GIC_NSS_QPEND11 (0x0000011B)
#define CSL_ARM_GIC_NSS_QPEND12 (0x0000011C)
#define CSL_ARM_GIC_NSS_QPEND13 (0x0000011D)
#define CSL_ARM_GIC_NSS_QPEND14 (0x0000011E)
#define CSL_ARM_GIC_NSS_QPEND15 (0x0000011F)
#define CSL_ARM_GIC_NSS_QPEND16 (0x00000120)
#define CSL_ARM_GIC_NSS_QPEND17 (0x00000121)
#define CSL_ARM_GIC_NSS_QPEND18 (0x00000122)
#define CSL_ARM_GIC_NSS_QPEND19 (0x00000123)
#define CSL_ARM_GIC_NSS_QPEND20 (0x00000124)
#define CSL_ARM_GIC_NSS_QPEND21 (0x00000125)
#define CSL_ARM_GIC_NSS_QPEND22 (0x00000126)
#define CSL_ARM_GIC_NSS_QPEND23 (0x00000127)
#define CSL_ARM_GIC_NSS_QPEND24 (0x00000128)
#define CSL_ARM_GIC_NSS_QPEND25 (0x00000129)
#define CSL_ARM_GIC_NSS_QPEND26 (0x0000012A)
#define CSL_ARM_GIC_NSS_QPEND27 (0x0000012B)
#define CSL_ARM_GIC_NSS_QPEND28 (0x0000012C)
#define CSL_ARM_GIC_NSS_QPEND29 (0x0000012D)
#define CSL_ARM_GIC_NSS_QPEND30 (0x0000012E)
#define CSL_ARM_GIC_NSS_QPEND31 (0x0000012F)
#define CSL_ARM_GIC_NSS_QPEND32 (0x00000130)
#define CSL_ARM_GIC_NSS_QPEND33 (0x00000131)
#define CSL_ARM_GIC_NSS_QPEND34 (0x00000132)
#define CSL_ARM_GIC_NSS_QPEND35 (0x00000133)
#define CSL_ARM_GIC_NSS_QPEND56 (0x00000134)
#define CSL_ARM_GIC_NSS_QPEND57 (0x00000135)
#define CSL_ARM_GIC_NSS_QPEND58 (0x00000136)
#define CSL_ARM_GIC_NSS_QPEND59 (0x00000137)
#define CSL_ARM_GIC_NSS_QPEND60 (0x00000138)
#define CSL_ARM_GIC_NSS_QPEND61 (0x00000139)
#define CSL_ARM_GIC_NSS_QPEND62 (0x0000013A)
#define CSL_ARM_GIC_NSS_QPEND63 (0x0000013B)
#define CSL_ARM_GIC_RESERVED_316 (0x0000013C)
#define CSL_ARM_GIC_RESERVED_317 (0x0000013D)
#define CSL_ARM_GIC_RESERVED_318 (0x0000013E)
#define CSL_ARM_GIC_RESERVED_319 (0x0000013F)
#define CSL_ARM_GIC_MSGMGR_PROXY_ERROR (0x00000140)
#define CSL_ARM_GIC_MSGMGR_FREEINDEX_ERROR (0x00000141)
#define CSL_ARM_GIC_MSGMGR_ECC_ERROR (0x00000142)
#define CSL_ARM_GIC_RESERVED_323 (0x00000143)
#define CSL_ARM_GIC_MSGMGR_QUE_PEND_5 (0x00000144)
#define CSL_ARM_GIC_MSGMGR_QUE_PEND_37 (0x00000145)
#define CSL_ARM_GIC_MSGMGR_QUE_PEND_49 (0x00000146)
#define CSL_ARM_GIC_MSGMGR_QUE_PEND_57 (0x00000147)
#define CSL_ARM_GIC_RESERVED_328 (0x00000148)
#define CSL_ARM_GIC_RESERVED_329 (0x00000149)
#define CSL_ARM_GIC_RESERVED_330 (0x0000014A)
#define CSL_ARM_GIC_RESERVED_331 (0x0000014B)
#define CSL_ARM_GIC_RESERVED_332 (0x0000014C)
#define CSL_ARM_GIC_RESERVED_333 (0x0000014D)
#define CSL_ARM_GIC_RESERVED_334 (0x0000014E)
#define CSL_ARM_GIC_RESERVED_335 (0x0000014F)
#define CSL_ARM_GIC_CIC_0_OUT0 (0x00000150)
#define CSL_ARM_GIC_CIC_0_OUT1 (0x00000151)
#define CSL_ARM_GIC_CIC_0_OUT2 (0x00000152)
#define CSL_ARM_GIC_CIC_0_OUT3 (0x00000153)
#define CSL_ARM_GIC_CIC_0_OUT4 (0x00000154)
#define CSL_ARM_GIC_CIC_0_OUT5 (0x00000155)
#define CSL_ARM_GIC_CIC_0_OUT6 (0x00000156)
#define CSL_ARM_GIC_CIC_0_OUT7 (0x00000157)
#define CSL_ARM_GIC_CIC_0_OUT8 (0x00000158)
#define CSL_ARM_GIC_CIC_0_OUT9 (0x00000159)
#define CSL_ARM_GIC_CIC_0_OUT10 (0x0000015A)
#define CSL_ARM_GIC_CIC_0_OUT11 (0x0000015B)
#define CSL_ARM_GIC_CIC_0_OUT12 (0x0000015C)
#define CSL_ARM_GIC_CIC_0_OUT13 (0x0000015D)
#define CSL_ARM_GIC_CIC_0_OUT14 (0x0000015E)
#define CSL_ARM_GIC_CIC_0_OUT15 (0x0000015F)
#define CSL_ARM_GIC_CIC_0_OUT16 (0x00000160)
#define CSL_ARM_GIC_CIC_0_OUT17 (0x00000161)
#define CSL_ARM_GIC_CIC_0_OUT18 (0x00000162)
#define CSL_ARM_GIC_CIC_0_OUT19 (0x00000163)
#define CSL_ARM_GIC_CIC_0_OUT20 (0x00000164)
#define CSL_ARM_GIC_CIC_0_OUT21 (0x00000165)
#define CSL_ARM_GIC_CIC_0_OUT22 (0x00000166)
#define CSL_ARM_GIC_CIC_0_OUT23 (0x00000167)
#define CSL_ARM_GIC_CIC_0_OUT24 (0x00000168)
#define CSL_ARM_GIC_CIC_0_OUT25 (0x00000169)
#define CSL_ARM_GIC_CIC_0_OUT26 (0x0000016A)
#define CSL_ARM_GIC_CIC_0_OUT27 (0x0000016B)
#define CSL_ARM_GIC_CIC_0_OUT28 (0x0000016C)
#define CSL_ARM_GIC_CIC_0_OUT29 (0x0000016D)
#define CSL_ARM_GIC_CIC_0_OUT30 (0x0000016E)
#define CSL_ARM_GIC_CIC_0_OUT31 (0x0000016F)
#define CSL_ARM_GIC_CIC_0_OUT32 (0x00000170)
#define CSL_ARM_GIC_CIC_0_OUT33 (0x00000171)
#define CSL_ARM_GIC_CIC_0_OUT34 (0x00000172)
#define CSL_ARM_GIC_CIC_0_OUT35 (0x00000173)
#define CSL_ARM_GIC_CIC_0_OUT36 (0x00000174)
#define CSL_ARM_GIC_CIC_0_OUT37 (0x00000175)
#define CSL_ARM_GIC_CIC_0_OUT38 (0x00000176)
#define CSL_ARM_GIC_CIC_0_OUT39 (0x00000177)
#define CSL_ARM_GIC_CIC_0_OUT80 (0x00000178)
#define CSL_ARM_GIC_CIC_0_OUT81 (0x00000179)
#define CSL_ARM_GIC_CIC_0_OUT82 (0x0000017A)
#define CSL_ARM_GIC_CIC_0_OUT83 (0x0000017B)
#define CSL_ARM_GIC_CIC_0_OUT84 (0x0000017C)
#define CSL_ARM_GIC_CIC_0_OUT85 (0x0000017D)
#define CSL_ARM_GIC_CIC_0_OUT86 (0x0000017E)
#define CSL_ARM_GIC_CIC_0_OUT87 (0x0000017F)
#define CSL_ARM_GIC_RESERVED_384 (0x00000180)
#define CSL_ARM_GIC_RESERVED_385 (0x00000181)
#define CSL_ARM_GIC_RESERVED_386 (0x00000182)
#define CSL_ARM_GIC_RESERVED_387 (0x00000183)
#define CSL_ARM_GIC_RESERVED_388 (0x00000184)
#define CSL_ARM_GIC_RESERVED_389 (0x00000185)
#define CSL_ARM_GIC_RESERVED_390 (0x00000186)
#define CSL_ARM_GIC_RESERVED_391 (0x00000187)
#define CSL_ARM_GIC_RESERVED_392 (0x00000188)
#define CSL_ARM_GIC_RESERVED_393 (0x00000189)
#define CSL_ARM_GIC_RESERVED_394 (0x0000018A)
#define CSL_ARM_GIC_RESERVED_395 (0x0000018B)
#define CSL_ARM_GIC_RESERVED_396 (0x0000018C)
#define CSL_ARM_GIC_RESERVED_397 (0x0000018D)
#define CSL_ARM_GIC_RESERVED_398 (0x0000018E)
#define CSL_ARM_GIC_RESERVED_399 (0x0000018F)
#define CSL_ARM_GIC_RESERVED_400 (0x00000190)
#define CSL_ARM_GIC_RESERVED_401 (0x00000191)
#define CSL_ARM_GIC_RESERVED_402 (0x00000192)
#define CSL_ARM_GIC_RESERVED_403 (0x00000193)
#define CSL_ARM_GIC_RESERVED_404 (0x00000194)
#define CSL_ARM_GIC_RESERVED_405 (0x00000195)
#define CSL_ARM_GIC_RESERVED_406 (0x00000196)
#define CSL_ARM_GIC_RESERVED_407 (0x00000197)
#define CSL_ARM_GIC_RESERVED_408 (0x00000198)
#define CSL_ARM_GIC_RESERVED_409 (0x00000199)
#define CSL_ARM_GIC_RESERVED_410 (0x0000019A)
#define CSL_ARM_GIC_RESERVED_411 (0x0000019B)
#define CSL_ARM_GIC_RESERVED_412 (0x0000019C)
#define CSL_ARM_GIC_RESERVED_413 (0x0000019D)
#define CSL_ARM_GIC_RESERVED_414 (0x0000019E)
#define CSL_ARM_GIC_RESERVED_415 (0x0000019F)
#define CSL_ARM_GIC_RESERVED_416 (0x000001A0)
#define CSL_ARM_GIC_RESERVED_417 (0x000001A1)
#define CSL_ARM_GIC_RESERVED_418 (0x000001A2)
#define CSL_ARM_GIC_RESERVED_419 (0x000001A3)
#define CSL_ARM_GIC_RESERVED_420 (0x000001A4)
#define CSL_ARM_GIC_RESERVED_421 (0x000001A5)
#define CSL_ARM_GIC_RESERVED_422 (0x000001A6)
#define CSL_ARM_GIC_RESERVED_423 (0x000001A7)
#define CSL_ARM_GIC_RESERVED_424 (0x000001A8)
#define CSL_ARM_GIC_RESERVED_425 (0x000001A9)
#define CSL_ARM_GIC_RESERVED_426 (0x000001AA)
#define CSL_ARM_GIC_RESERVED_427 (0x000001AB)
#define CSL_ARM_GIC_RESERVED_428 (0x000001AC)
#define CSL_ARM_GIC_RESERVED_429 (0x000001AD)
#define CSL_ARM_GIC_RESERVED_430 (0x000001AE)
#define CSL_ARM_GIC_RESERVED_431 (0x000001AF)
#define CSL_ARM_GIC_GPIO_0_BANK0_INT (0x000001B0)
#define CSL_ARM_GIC_GPIO_0_BANK1_INT (0x000001B1)
#define CSL_ARM_GIC_GPIO_0_BANK2_INT (0x000001B2)
#define CSL_ARM_GIC_GPIO_0_BANK3_INT (0x000001B3)
#define CSL_ARM_GIC_GPIO_0_BANK4_INT (0x000001B4)
#define CSL_ARM_GIC_GPIO_0_BANK5_INT (0x000001B5)
#define CSL_ARM_GIC_GPIO_0_BANK6_INT (0x000001B6)
#define CSL_ARM_GIC_GPIO_0_BANK7_INT (0x000001B7)
#define CSL_ARM_GIC_GPIO_0_BANK8_INT (0x000001B8)
#define CSL_ARM_GIC_RESERVED_441 (0x000001B9)
#define CSL_ARM_GIC_GPIO_1_BANK0_INT (0x000001BA)
#define CSL_ARM_GIC_GPIO_1_BANK1_INT (0x000001BB)
#define CSL_ARM_GIC_GPIO_1_BANK2_INT (0x000001BC)
#define CSL_ARM_GIC_GPIO_1_BANK3_INT (0x000001BD)
#define CSL_ARM_GIC_GPIO_1_BANK4_INT (0x000001BE)
#define CSL_ARM_GIC_RESERVED_447 (0x000001BF)
#define CSL_ARM_GIC_GPIOMUX_INT0 (0x000001C0)
#define CSL_ARM_GIC_GPIOMUX_INT1 (0x000001C1)
#define CSL_ARM_GIC_GPIOMUX_INT2 (0x000001C2)
#define CSL_ARM_GIC_GPIOMUX_INT3 (0x000001C3)
#define CSL_ARM_GIC_GPIOMUX_INT4 (0x000001C4)
#define CSL_ARM_GIC_GPIOMUX_INT5 (0x000001C5)
#define CSL_ARM_GIC_GPIOMUX_INT6 (0x000001C6)
#define CSL_ARM_GIC_GPIOMUX_INT7 (0x000001C7)
#define CSL_ARM_GIC_GPIOMUX_INT8 (0x000001C8)
#define CSL_ARM_GIC_GPIOMUX_INT9 (0x000001C9)
#define CSL_ARM_GIC_GPIOMUX_INT10 (0x000001CA)
#define CSL_ARM_GIC_GPIOMUX_INT11 (0x000001CB)
#define CSL_ARM_GIC_GPIOMUX_INT12 (0x000001CC)
#define CSL_ARM_GIC_GPIOMUX_INT13 (0x000001CD)
#define CSL_ARM_GIC_GPIOMUX_INT14 (0x000001CE)
#define CSL_ARM_GIC_GPIOMUX_INT15 (0x000001CF)
#define CSL_ARM_GIC_GPIOMUX_INT16 (0x000001D0)
#define CSL_ARM_GIC_GPIOMUX_INT17 (0x000001D1)
#define CSL_ARM_GIC_GPIOMUX_INT18 (0x000001D2)
#define CSL_ARM_GIC_GPIOMUX_INT19 (0x000001D3)
#define CSL_ARM_GIC_GPIOMUX_INT20 (0x000001D4)
#define CSL_ARM_GIC_GPIOMUX_INT21 (0x000001D5)
#define CSL_ARM_GIC_GPIOMUX_INT22 (0x000001D6)
#define CSL_ARM_GIC_GPIOMUX_INT23 (0x000001D7)
#define CSL_ARM_GIC_GPIOMUX_INT24 (0x000001D8)
#define CSL_ARM_GIC_GPIOMUX_INT25 (0x000001D9)
#define CSL_ARM_GIC_GPIOMUX_INT26 (0x000001DA)
#define CSL_ARM_GIC_GPIOMUX_INT27 (0x000001DB)
#define CSL_ARM_GIC_GPIOMUX_INT28 (0x000001DC)
#define CSL_ARM_GIC_GPIOMUX_INT29 (0x000001DD)
#define CSL_ARM_GIC_GPIOMUX_INT30 (0x000001DE)
#define CSL_ARM_GIC_GPIOMUX_INT31 (0x000001DF)

/*
 * Auto-generated CSL section
 */
#define CIC_EVENT_CNT 415
#define CSL_CIC_ICSSM0_HOST_INT0 (0x00000000)
#define CSL_CIC_ICSSM0_HOST_INT1 (0x00000001)
#define CSL_CIC_ICSSM0_HOST_INT2 (0x00000002)
#define CSL_CIC_ICSSM0_HOST_INT3 (0x00000003)
#define CSL_CIC_ICSSM0_HOST_INT4 (0x00000004)
#define CSL_CIC_RESERVED_5 (0x00000005)
#define CSL_CIC_ICSSM0_HOST_INT6 (0x00000006)
#define CSL_CIC_ICSSM0_HOST_INT7 (0x00000007)
#define CSL_CIC_ICSSM1_HOST_INT0 (0x00000008)
#define CSL_CIC_ICSSM1_HOST_INT1 (0x00000009)
#define CSL_CIC_ICSSM1_HOST_INT2 (0x0000000A)
#define CSL_CIC_ICSSM1_HOST_INT3 (0x0000000B)
#define CSL_CIC_ICSSM1_HOST_INT4 (0x0000000C)
#define CSL_CIC_RESERVED_13 (0x0000000D)
#define CSL_CIC_ICSSM1_HOST_INT6 (0x0000000E)
#define CSL_CIC_ICSSM1_HOST_INT7 (0x0000000F)
#define CSL_CIC_MSMC_MPF_ERROR0 (0x00000010)
#define CSL_CIC_MSMC_MPF_ERROR1 (0x00000011)
#define CSL_CIC_MSMC_MPF_ERROR2 (0x00000012)
#define CSL_CIC_MSMC_MPF_ERROR3 (0x00000013)
#define CSL_CIC_MSMC_MPF_ERROR4 (0x00000014)
#define CSL_CIC_MSMC_MPF_ERROR5 (0x00000015)
#define CSL_CIC_MSMC_MPF_ERROR6 (0x00000016)
#define CSL_CIC_MSMC_MPF_ERROR7 (0x00000017)
#define CSL_CIC_MSMC_MPF_ERROR8 (0x00000018)
#define CSL_CIC_MSMC_MPF_ERROR9 (0x00000019)
#define CSL_CIC_MSMC_MPF_ERROR10 (0x0000001A)
#define CSL_CIC_MSMC_MPF_ERROR11 (0x0000001B)
#define CSL_CIC_MSMC_MPF_ERROR12 (0x0000001C)
#define CSL_CIC_MSMC_MPF_ERROR13 (0x0000001D)
#define CSL_CIC_MSMC_MPF_ERROR14 (0x0000001E)
#define CSL_CIC_MSMC_MPF_ERROR15 (0x0000001F)
#define CSL_CIC_MSMC_DEDC_CERROR (0x00000020)
#define CSL_CIC_MSMC_SCRUB_CERROR (0x00000021)
#define CSL_CIC_MSMC_DEDC_NC_ERROR (0x00000022)
#define CSL_CIC_MSMC_SCRUB_NC_ERROR (0x00000023)
#define CSL_CIC_DBGTBR_DMAINT (0x00000024)
#define CSL_CIC_DBGTBR_ACQCOMP (0x00000025)
#define CSL_CIC_BOOTCFG_INT (0x00000026)
#define CSL_CIC_DFT_PBIST_CPU_INT (0x00000027)
#define CSL_CIC_MPU_0_INT (0x00000028)
#define CSL_CIC_MPU_1_INT (0x00000029)
#define CSL_CIC_MPU_2_INT (0x0000002A)
#define CSL_CIC_MPU_3_INT (0x0000002B)
#define CSL_CIC_MPU_4_INT (0x0000002C)
#define CSL_CIC_MPU_5_INT (0x0000002D)
#define CSL_CIC_MPU_6_INT (0x0000002E)
#define CSL_CIC_MPU_7_INT (0x0000002F)
#define CSL_CIC_MPU_8_INT (0x00000030)
#define CSL_CIC_MPU_9_INT (0x00000031)
#define CSL_CIC_MPU_10_INT (0x00000032)
#define CSL_CIC_MPU_11_INT (0x00000033)
#define CSL_CIC_MPU_12_INT (0x00000034)
#define CSL_CIC_MPU_13_INT (0x00000035)
#define CSL_CIC_MPU_14_INT (0x00000036)
#define CSL_CIC_MPU_15_INT (0x00000037)
#define CSL_CIC_TRACER_MSMC_0_INT (0x00000038)
#define CSL_CIC_TRACER_DDR_INT (0x00000039)
#define CSL_CIC_TRACER_CORE_INT (0x0000003A)
#define CSL_CIC_TRACER_PCIE_EVT (0x0000003B)
#define CSL_CIC_TRACER_DXB_INT (0x0000003C)
#define CSL_CIC_TRACER_MCASP_MCBSP_INT (0x0000003D)
#define CSL_CIC_TRACER_GPMC_MMC_QSPI_INT (0x0000003E)
#define CSL_CIC_TRACER_EMDACC_01_INT (0x0000003F)
#define CSL_CIC_TRACER_CFG_INT (0x00000040)
#define CSL_CIC_TRACER_ALWAYSON_CFG_INT (0x00000041)
#define CSL_CIC_TRACER_GIC_INT (0x00000042)
#define CSL_CIC_TRACER_CIC_INT (0x00000043)
#define CSL_CIC_TRACER_ROM_SPI_INT (0x00000044)
#define CSL_CIC_TRACER_ALWAYSON_INT (0x00000045)
#define CSL_CIC_TRACER_ICSS_ASRC (0x00000046)
#define CSL_CIC_RESERVED_71 (0x00000047)
#define CSL_CIC_TIMER_0_INTL (0x00000048)
#define CSL_CIC_TIMER_0_INTH (0x00000049)
#define CSL_CIC_TIMER_1_INTL (0x0000004A)
#define CSL_CIC_TIMER_1_INTH (0x0000004B)
#define CSL_CIC_TIMER_2_INTL (0x0000004C)
#define CSL_CIC_TIMER_2_INTH (0x0000004D)
#define CSL_CIC_TIMER_3_INTL (0x0000004E)
#define CSL_CIC_TIMER_3_INTH (0x0000004F)
#define CSL_CIC_TIMER_4_INTL (0x00000050)
#define CSL_CIC_TIMER_4_INTH (0x00000051)
#define CSL_CIC_TIMER_5_INTL (0x00000052)
#define CSL_CIC_TIMER_5_INTH (0x00000053)
#define CSL_CIC_TIMER_6_INTL (0x00000054)
#define CSL_CIC_TIMER_6_INTH (0x00000055)
#define CSL_CIC_RESERVED_86 (0x00000056)
#define CSL_CIC_RESERVED_87 (0x00000057)
#define CSL_CIC_DCAN_0_INT0 (0x00000058)
#define CSL_CIC_DCAN_0_INT1 (0x00000059)
#define CSL_CIC_DCAN_0_ERR_INT (0x0000005A)
#define CSL_CIC_DCAN_1_INT0 (0x0000005B)
#define CSL_CIC_DCAN_1_INT1 (0x0000005C)
#define CSL_CIC_DCAN_1_ERR_INT (0x0000005D)
#define CSL_CIC_QSPI_INT (0x0000005E)
#define CSL_CIC_DSS_INT (0x0000005F)
#define CSL_CIC_USB_0_INT00 (0x00000060)
#define CSL_CIC_USB_0_INT01 (0x00000061)
#define CSL_CIC_USB_0_INT02 (0x00000062)
#define CSL_CIC_USB_0_INT03 (0x00000063)
#define CSL_CIC_USB_0_INT04 (0x00000064)
#define CSL_CIC_USB_0_INT05 (0x00000065)
#define CSL_CIC_USB_0_INT06 (0x00000066)
#define CSL_CIC_USB_0_INT07 (0x00000067)
#define CSL_CIC_USB_0_INT08 (0x00000068)
#define CSL_CIC_USB_0_INT09 (0x00000069)
#define CSL_CIC_USB_0_INT10 (0x0000006A)
#define CSL_CIC_USB_0_INT11 (0x0000006B)
#define CSL_CIC_USB_0_INT12 (0x0000006C)
#define CSL_CIC_USB_0_INT13 (0x0000006D)
#define CSL_CIC_USB_0_INT14 (0x0000006E)
#define CSL_CIC_USB_0_INT15 (0x0000006F)
#define CSL_CIC_USB_1_INT00 (0x00000070)
#define CSL_CIC_USB_1_INT01 (0x00000071)
#define CSL_CIC_USB_1_INT02 (0x00000072)
#define CSL_CIC_USB_1_INT03 (0x00000073)
#define CSL_CIC_USB_1_INT04 (0x00000074)
#define CSL_CIC_USB_1_INT05 (0x00000075)
#define CSL_CIC_USB_1_INT06 (0x00000076)
#define CSL_CIC_USB_1_INT07 (0x00000077)
#define CSL_CIC_USB_1_INT08 (0x00000078)
#define CSL_CIC_USB_1_INT09 (0x00000079)
#define CSL_CIC_USB_1_INT10 (0x0000007A)
#define CSL_CIC_USB_1_INT11 (0x0000007B)
#define CSL_CIC_USB_1_INT12 (0x0000007C)
#define CSL_CIC_USB_1_INT13 (0x0000007D)
#define CSL_CIC_USB_1_INT14 (0x0000007E)
#define CSL_CIC_USB_1_INT15 (0x0000007F)
#define CSL_CIC_USB_0_OABSINT (0x00000080)
#define CSL_CIC_USB_0_MISCINT (0x00000081)
#define CSL_CIC_USB_1_OABSINT (0x00000082)
#define CSL_CIC_USB_1_MISCINT (0x00000083)
#define CSL_CIC_UART_0_UARTINT (0x00000084)
#define CSL_CIC_UART_1_UARTINT (0x00000085)
#define CSL_CIC_UART_2_UARTINT (0x00000086)
#define CSL_CIC_RESERVED_135 (0x00000087)
#define CSL_CIC_EDMACC_0_REGION_0_INT (0x00000088)
#define CSL_CIC_EDMACC_0_REGION_1_INT (0x00000089)
#define CSL_CIC_EDMACC_0_REGION_2_INT (0x0000008A)
#define CSL_CIC_EDMACC_0_REGION_3_INT (0x0000008B)
#define CSL_CIC_EDMACC_0_REGION_4_INT (0x0000008C)
#define CSL_CIC_EDMACC_0_REGION_5_INT (0x0000008D)
#define CSL_CIC_EDMACC_0_REGION_6_INT (0x0000008E)
#define CSL_CIC_EDMACC_0_REGION_7_INT (0x0000008F)
#define CSL_CIC_EDMACC_1_REGION_0_INT (0x00000090)
#define CSL_CIC_EDMACC_1_REGION_1_INT (0x00000091)
#define CSL_CIC_EDMACC_1_REGION_2_INT (0x00000092)
#define CSL_CIC_EDMACC_1_REGION_3_INT (0x00000093)
#define CSL_CIC_EDMACC_1_REGION_4_INT (0x00000094)
#define CSL_CIC_EDMACC_1_REGION_5_INT (0x00000095)
#define CSL_CIC_EDMACC_1_REGION_6_INT (0x00000096)
#define CSL_CIC_EDMACC_1_REGION_7_INT (0x00000097)
#define CSL_CIC_EDMACC_0_MPINT (0x00000098)
#define CSL_CIC_EDMACC_0_ERRINT (0x00000099)
#define CSL_CIC_EDMACC_0_GINT (0x0000009A)
#define CSL_CIC_EDMACC_1_MPINT (0x0000009B)
#define CSL_CIC_EDMACC_1_ERRINT (0x0000009C)
#define CSL_CIC_EDMACC_1_GINT (0x0000009D)
#define CSL_CIC_EDMACC_0_TC_0_INT (0x0000009E)
#define CSL_CIC_EDMACC_0_TC_1_INT (0x0000009F)
#define CSL_CIC_EDMACC_0_TC_0_ERRINT (0x000000A0)
#define CSL_CIC_EDMACC_0_TC_1_ERRINT (0x000000A1)
#define CSL_CIC_EDMACC_1_TC_0_INT (0x000000A2)
#define CSL_CIC_EDMACC_1_TC_1_INT (0x000000A3)
#define CSL_CIC_EDMACC_1_TC_0_ERRINT (0x000000A4)
#define CSL_CIC_EDMACC_1_TC_1_ERRINT (0x000000A5)
#define CSL_CIC_ARM_TBR_DMA (0x000000A6)
#define CSL_CIC_ARM_TBR_ACQ (0x000000A7)
#define CSL_CIC_ARM_NCNTPNSIRQ0 (0x000000A8)
#define CSL_CIC_ARM_NCNTVIRQ0 (0x000000A9)
#define CSL_CIC_RESERVED_170 (0x000000AA)
#define CSL_CIC_MPU_16_INT (0x000000AB)
#define CSL_CIC_McASP_0_XINT (0x000000AC)
#define CSL_CIC_McASP_0_RINT (0x000000AD)
#define CSL_CIC_McASP_1_XINT (0x000000AE)
#define CSL_CIC_McASP_1_RINT (0x000000AF)
#define CSL_CIC_McASP_2_XINT (0x000000B0)
#define CSL_CIC_McASP_2_RINT (0x000000B1)
#define CSL_CIC_McBSP_XINT (0x000000B2)
#define CSL_CIC_McBSP_RINT (0x000000B3)
#define CSL_CIC_I2C_0_INT (0x000000B4)
#define CSL_CIC_I2C_1_INT (0x000000B5)
#define CSL_CIC_I2C_2_INT (0x000000B6)
#define CSL_CIC_RESERVED_183 (0x000000B7)
#define CSL_CIC_ASRC_STREAM_IN_INT (0x000000B8)
#define CSL_CIC_ASRC_STREAM_OUT_INT (0x000000B9)
#define CSL_CIC_ASRC_STREAM_ERR_INT (0x000000BA)
#define CSL_CIC_ASRC_GROUP_IN_INT (0x000000BB)
#define CSL_CIC_ASRC_GROUP_OUT_INT (0x000000BC)
#define CSL_CIC_MLB_DMA_CH_INT0 (0x000000BD)
#define CSL_CIC_MLB_DMA_CH_INT1 (0x000000BE)
#define CSL_CIC_MLB_SYS_INT (0x000000BF)
#define CSL_CIC_MMC_SD_0_INT (0x000000C0)
#define CSL_CIC_MMC_SD_1_INT (0x000000C1)
#define CSL_CIC_RESERVED_194 (0x000000C2)
#define CSL_CIC_RESERVED_195 (0x000000C3)
#define CSL_CIC_GPMC_INT (0x000000C4)
#define CSL_CIC_ELM_INT (0x000000C5)
#define CSL_CIC_DDR3_ERR (0x000000C6)
#define CSL_CIC_SR_0_SR_I2CINT (0x000000C7)
#define CSL_CIC_EPWM_0_INT (0x000000C8)
#define CSL_CIC_EPWM_1_INT (0x000000C9)
#define CSL_CIC_EPWM_2_INT (0x000000CA)
#define CSL_CIC_EPWM_3_INT (0x000000CB)
#define CSL_CIC_EPWM_4_INT (0x000000CC)
#define CSL_CIC_EPWM_5_INT (0x000000CD)
#define CSL_CIC_EPWM_0_TRIP_ZONE (0x000000CE)
#define CSL_CIC_EPWM_1_TRIP_ZONE (0x000000CF)
#define CSL_CIC_EPWM_2_TRIP_ZONE (0x000000D0)
#define CSL_CIC_EPWM_3_TRIP_ZONE (0x000000D1)
#define CSL_CIC_EPWM_4_TRIP_ZONE (0x000000D2)
#define CSL_CIC_EPWM_5_TRIP_ZONE (0x000000D3)
#define CSL_CIC_EQEP_0_INT (0x000000D4)
#define CSL_CIC_EQEP_1_INT (0x000000D5)
#define CSL_CIC_EQEP_2_INT (0x000000D6)
#define CSL_CIC_ECAP_0_INT (0x000000D7)
#define CSL_CIC_ECAP_1_INT (0x000000D8)
#define CSL_CIC_RESERVED_217 (0x000000D9)
#define CSL_CIC_TETB_HFULLINT0 (0x000000DA)
#define CSL_CIC_TETB_FULLINT0 (0x000000DB)
#define CSL_CIC_TETB_ACQINT0 (0x000000DC)
#define CSL_CIC_TETB_OVFLINT0 (0x000000DD)
#define CSL_CIC_TETB_UNFLINT0 (0x000000DE)
#define CSL_CIC_PSC_ALLINT (0x000000DF)
#define CSL_CIC_PCIE_INT0 (0x000000E0)
#define CSL_CIC_PCIE_INT1 (0x000000E1)
#define CSL_CIC_PCIE_INT2 (0x000000E2)
#define CSL_CIC_PCIE_INT3 (0x000000E3)
#define CSL_CIC_PCIE_INT4 (0x000000E4)
#define CSL_CIC_PCIE_INT5 (0x000000E5)
#define CSL_CIC_PCIE_INT6 (0x000000E6)
#define CSL_CIC_PCIE_INT7 (0x000000E7)
#define CSL_CIC_PCIE_INT8 (0x000000E8)
#define CSL_CIC_PCIE_INT9 (0x000000E9)
#define CSL_CIC_PCIE_INT10 (0x000000EA)
#define CSL_CIC_PCIE_INT11 (0x000000EB)
#define CSL_CIC_PCIE_INT12 (0x000000EC)
#define CSL_CIC_PCIE_INT13 (0x000000ED)
#define CSL_CIC_PCIE_ECC_ERROR (0x000000EE)
#define CSL_CIC_QSPI_ECC_ERR (0x000000EF)
#define CSL_CIC_SR_0_PO_VCON_SMPSERR_INT (0x000000F0)
#define CSL_CIC_SR_0_SMARTREFLEX_INTREQ0 (0x000000F1)
#define CSL_CIC_SR_0_SMARTREFLEX_INTREQ1 (0x000000F2)
#define CSL_CIC_SR_0_SMARTREFLEX_INTREQ2 (0x000000F3)
#define CSL_CIC_SR_0_SMARTREFLEX_INTREQ3 (0x000000F4)
#define CSL_CIC_SR_0_VPNOSMPSACK (0x000000F5)
#define CSL_CIC_SR_0_VPEQVALUE (0x000000F6)
#define CSL_CIC_SR_0_VPMAXVDD (0x000000F7)
#define CSL_CIC_SR_0_VPMINVDD (0x000000F8)
#define CSL_CIC_SR_0_VPINIDLE (0x000000F9)
#define CSL_CIC_SR_0_VPOPPCHANGEDONE (0x000000FA)
#define CSL_CIC_SR_0_VPSMPSACK (0x000000FB)
#define CSL_CIC_SR_0_SR_TEMPSENSOR (0x000000FC)
#define CSL_CIC_SR_0_SR_TIMERINT (0x000000FD)
#define CSL_CIC_SR_0_SR_MAX_TEMP_INT (0x000000FE)
#define CSL_CIC_SR_0_SR_SMBALERT (0x000000FF)
#define CSL_CIC_SPI_0_INT0 (0x00000100)
#define CSL_CIC_SPI_0_INT1 (0x00000101)
#define CSL_CIC_SPI_1_INT0 (0x00000102)
#define CSL_CIC_SPI_1_INT1 (0x00000103)
#define CSL_CIC_SPI_2_INT0 (0x00000104)
#define CSL_CIC_SPI_2_INT1 (0x00000105)
#define CSL_CIC_SPI_3_INT0 (0x00000106)
#define CSL_CIC_SPI_3_INT1 (0x00000107)
#define CSL_CIC_NSS_CDMA_STARVE_INT (0x00000108)
#define CSL_CIC_NSS_SWITCH_STAT_INT0 (0x00000109)
#define CSL_CIC_NSS_SWITCH_STAT_INT1 (0x0000010A)
#define CSL_CIC_NSS_NAVSS_ECC_INT (0x0000010B)
#define CSL_CIC_NSS_SA_UL_ECC_INT (0x0000010C)
#define CSL_CIC_NSS_SWITCH_ECC_INT (0x0000010D)
#define CSL_CIC_NSS_MDIO_LINK_INT0 (0x0000010E)
#define CSL_CIC_NSS_CPTS_EVENT_INT (0x0000010F)
#define CSL_CIC_NSS_MDIO_USER_INT0 (0x00000110)
#define CSL_CIC_NSS_MDIO_USER_INT1 (0x00000111)
#define CSL_CIC_PKA_INT (0x00000112)
#define CSL_CIC_RNG_INT (0x00000113)
#define CSL_CIC_PMMC_INT0 (0x00000114)
#define CSL_CIC_PMMC_INT1 (0x00000115)
#define CSL_CIC_PMMC_FAULTDET_INT (0x00000116)
#define CSL_CIC_SECMGRINT (0x00000117)
#define CSL_CIC_PMMCTBR_ACQCOMP (0x00000118)
#define CSL_CIC_PMMCTBR_DMAINT (0x00000119)
#define CSL_CIC_RESERVED_282 (0x0000011A)
#define CSL_CIC_MSGMGR_PROXY_ERROR (0x0000011B)
#define CSL_CIC_MSGMGR_FREEINDEX_ERROR (0x0000011C)
#define CSL_CIC_MSGMGR_ECC_ERROR (0x0000011D)
#define CSL_CIC_NSS_QPEND0 (0x0000011E)
#define CSL_CIC_NSS_QPEND1 (0x0000011F)
#define CSL_CIC_NSS_QPEND2 (0x00000120)
#define CSL_CIC_NSS_QPEND3 (0x00000121)
#define CSL_CIC_NSS_QPEND4 (0x00000122)
#define CSL_CIC_NSS_QPEND5 (0x00000123)
#define CSL_CIC_NSS_QPEND6 (0x00000124)
#define CSL_CIC_NSS_QPEND7 (0x00000125)
#define CSL_CIC_NSS_QPEND8 (0x00000126)
#define CSL_CIC_NSS_QPEND9 (0x00000127)
#define CSL_CIC_NSS_QPEND10 (0x00000128)
#define CSL_CIC_NSS_QPEND11 (0x00000129)
#define CSL_CIC_NSS_QPEND12 (0x0000012A)
#define CSL_CIC_NSS_QPEND13 (0x0000012B)
#define CSL_CIC_NSS_QPEND14 (0x0000012C)
#define CSL_CIC_NSS_QPEND15 (0x0000012D)
#define CSL_CIC_NSS_QPEND16 (0x0000012E)
#define CSL_CIC_NSS_QPEND17 (0x0000012F)
#define CSL_CIC_NSS_QPEND18 (0x00000130)
#define CSL_CIC_NSS_QPEND19 (0x00000131)
#define CSL_CIC_NSS_QPEND20 (0x00000132)
#define CSL_CIC_NSS_QPEND21 (0x00000133)
#define CSL_CIC_NSS_QPEND22 (0x00000134)
#define CSL_CIC_NSS_QPEND23 (0x00000135)
#define CSL_CIC_NSS_QPEND24 (0x00000136)
#define CSL_CIC_NSS_QPEND25 (0x00000137)
#define CSL_CIC_NSS_QPEND26 (0x00000138)
#define CSL_CIC_NSS_QPEND27 (0x00000139)
#define CSL_CIC_NSS_QPEND28 (0x0000013A)
#define CSL_CIC_NSS_QPEND29 (0x0000013B)
#define CSL_CIC_NSS_QPEND30 (0x0000013C)
#define CSL_CIC_NSS_QPEND31 (0x0000013D)
#define CSL_CIC_NSS_QPEND56 (0x0000013E)
#define CSL_CIC_NSS_QPEND57 (0x0000013F)
#define CSL_CIC_NSS_QPEND58 (0x00000140)
#define CSL_CIC_NSS_QPEND59 (0x00000141)
#define CSL_CIC_NSS_QPEND60 (0x00000142)
#define CSL_CIC_NSS_QPEND61 (0x00000143)
#define CSL_CIC_NSS_QPEND62 (0x00000144)
#define CSL_CIC_NSS_QPEND63 (0x00000145)
#define CSL_CIC_NSS_QPEND64 (0x00000146)
#define CSL_CIC_NSS_QPEND65 (0x00000147)
#define CSL_CIC_NSS_QPEND66 (0x00000148)
#define CSL_CIC_NSS_QPEND67 (0x00000149)
#define CSL_CIC_NSS_QPEND68 (0x0000014A)
#define CSL_CIC_NSS_QPEND69 (0x0000014B)
#define CSL_CIC_NSS_QPEND70 (0x0000014C)
#define CSL_CIC_NSS_QPEND71 (0x0000014D)
#define CSL_CIC_RESERVED_334 (0x0000014E)
#define CSL_CIC_RESERVED_335 (0x0000014F)
#define CSL_CIC_RESERVED_336 (0x00000150)
#define CSL_CIC_RESERVED_337 (0x00000151)
#define CSL_CIC_PWM_SOCA (0x00000152)
#define CSL_CIC_PWM_SOCB (0x00000153)
#define CSL_CIC_SEM_INT11 (0x00000154)
#define CSL_CIC_SEM_INT12 (0x00000155)
#define CSL_CIC_SEM_INT13 (0x00000156)
#define CSL_CIC_SEM_INT14 (0x00000157)
#define CSL_CIC_SEM_ERR11 (0x00000158)
#define CSL_CIC_SEM_ERR12 (0x00000159)
#define CSL_CIC_SEM_ERR13 (0x0000015A)
#define CSL_CIC_SEM_ERR14 (0x0000015B)
#define CSL_CIC_RESERVED_348 (0x0000015C)
#define CSL_CIC_RESERVED_349 (0x0000015D)
#define CSL_CIC_RESERVED_350 (0x0000015E)
#define CSL_CIC_RESERVED_351 (0x0000015F)
#define CSL_CIC_RESERVED_352 (0x00000160)
#define CSL_CIC_RESERVED_353 (0x00000161)
#define CSL_CIC_RESERVED_354 (0x00000162)
#define CSL_CIC_RESERVED_355 (0x00000163)
#define CSL_CIC_RESERVED_356 (0x00000164)
#define CSL_CIC_RESERVED_357 (0x00000165)
#define CSL_CIC_RESERVED_358 (0x00000166)
#define CSL_CIC_RESERVED_359 (0x00000167)
#define CSL_CIC_RESERVED_360 (0x00000168)
#define CSL_CIC_RESERVED_361 (0x00000169)
#define CSL_CIC_RESERVED_362 (0x0000016A)
#define CSL_CIC_RESERVED_363 (0x0000016B)
#define CSL_CIC_RESERVED_364 (0x0000016C)
#define CSL_CIC_RESERVED_365 (0x0000016D)
#define CSL_CIC_RESERVED_366 (0x0000016E)
#define CSL_CIC_RESERVED_367 (0x0000016F)
#define CSL_CIC_RESERVED_368 (0x00000170)
#define CSL_CIC_RESERVED_369 (0x00000171)
#define CSL_CIC_GPIO_0_BANK0_INT (0x00000172)
#define CSL_CIC_GPIO_0_BANK1_INT (0x00000173)
#define CSL_CIC_GPIO_0_BANK2_INT (0x00000174)
#define CSL_CIC_GPIO_0_BANK3_INT (0x00000175)
#define CSL_CIC_GPIO_0_BANK4_INT (0x00000176)
#define CSL_CIC_GPIO_0_BANK5_INT (0x00000177)
#define CSL_CIC_GPIO_0_BANK6_INT (0x00000178)
#define CSL_CIC_GPIO_0_BANK7_INT (0x00000179)
#define CSL_CIC_GPIO_0_BANK8_INT (0x0000017A)
#define CSL_CIC_GPIO_1_BANK0_INT (0x0000017B)
#define CSL_CIC_GPIO_1_BANK1_INT (0x0000017C)
#define CSL_CIC_GPIO_1_BANK2_INT (0x0000017D)
#define CSL_CIC_GPIO_1_BANK3_INT (0x0000017E)
#define CSL_CIC_GPIO_1_BANK4_INT (0x0000017F)
#define CSL_CIC_GPIOMUX_INT0 (0x00000180)
#define CSL_CIC_GPIOMUX_INT1 (0x00000181)
#define CSL_CIC_GPIOMUX_INT2 (0x00000182)
#define CSL_CIC_GPIOMUX_INT3 (0x00000183)
#define CSL_CIC_GPIOMUX_INT4 (0x00000184)
#define CSL_CIC_GPIOMUX_INT5 (0x00000185)
#define CSL_CIC_GPIOMUX_INT6 (0x00000186)
#define CSL_CIC_GPIOMUX_INT7 (0x00000187)
#define CSL_CIC_GPIOMUX_INT8 (0x00000188)
#define CSL_CIC_GPIOMUX_INT9 (0x00000189)
#define CSL_CIC_GPIOMUX_INT10 (0x0000018A)
#define CSL_CIC_GPIOMUX_INT11 (0x0000018B)
#define CSL_CIC_GPIOMUX_INT12 (0x0000018C)
#define CSL_CIC_GPIOMUX_INT13 (0x0000018D)
#define CSL_CIC_GPIOMUX_INT14 (0x0000018E)
#define CSL_CIC_GPIOMUX_INT15 (0x0000018F)
#define CSL_CIC_GPIOMUX_INT16 (0x00000190)
#define CSL_CIC_GPIOMUX_INT17 (0x00000191)
#define CSL_CIC_GPIOMUX_INT18 (0x00000192)
#define CSL_CIC_GPIOMUX_INT19 (0x00000193)
#define CSL_CIC_GPIOMUX_INT20 (0x00000194)
#define CSL_CIC_GPIOMUX_INT21 (0x00000195)
#define CSL_CIC_GPIOMUX_INT22 (0x00000196)
#define CSL_CIC_GPIOMUX_INT23 (0x00000197)
#define CSL_CIC_GPIOMUX_INT24 (0x00000198)
#define CSL_CIC_GPIOMUX_INT25 (0x00000199)
#define CSL_CIC_GPIOMUX_INT26 (0x0000019A)
#define CSL_CIC_GPIOMUX_INT27 (0x0000019B)
#define CSL_CIC_GPIOMUX_INT28 (0x0000019C)
#define CSL_CIC_GPIOMUX_INT29 (0x0000019D)
#define CSL_CIC_GPIOMUX_INT30 (0x0000019E)
#define CSL_CIC_GPIOMUX_INT31 (0x0000019F)

/*
 * Auto-generated CSL section
 */
#define C66X_COREPAC_EVENT_CNT 127
#define CSL_C66X_COREPAC_EVT0 (0x00000000)
#define CSL_C66X_COREPAC_EVT1 (0x00000001)
#define CSL_C66X_COREPAC_EVT2 (0x00000002)
#define CSL_C66X_COREPAC_EVT3 (0x00000003)
#define CSL_C66X_COREPAC_ICSSM0_HOST_INT0 (0x00000004)
#define CSL_C66X_COREPAC_ICSSM1_HOST_INT0 (0x00000005)
#define CSL_C66X_COREPAC_EDMACC_0_REGION_0_INT (0x00000006)
#define CSL_C66X_COREPAC_EDMACC_1_REGION_0_INT (0x00000007)
#define CSL_C66X_COREPAC_IPC_GR0 (0x00000008)
#define CSL_C66X_COREPAC_EMU_DTDMA (0x00000009)
#define CSL_C66X_COREPAC_MSMC_MPF_ERROR0 (0x0000000A)
#define CSL_C66X_COREPAC_EMU_RTDXRX (0x0000000B)
#define CSL_C66X_COREPAC_EMU_RTDXTX (0x0000000C)
#define CSL_C66X_COREPAC_IDMA0 (0x0000000D)
#define CSL_C66X_COREPAC_IDMA1 (0x0000000E)
#define CSL_C66X_COREPAC_SEM_ERR0 (0x0000000F)
#define CSL_C66X_COREPAC_SEM_INT0 (0x00000010)
#define CSL_C66X_COREPAC_PCIE_INT4 (0x00000011)
#define CSL_C66X_COREPAC_RESERVED_18 (0x00000012)
#define CSL_C66X_COREPAC_RESERVED_19 (0x00000013)
#define CSL_C66X_COREPAC_MSGMGR_QUE_PEND_4 (0x00000014)
#define CSL_C66X_COREPAC_MSGMGR_QUE_PEND_36 (0x00000015)
#define CSL_C66X_COREPAC_MSGMGR_QUE_PEND_48 (0x00000016)
#define CSL_C66X_COREPAC_MSGMGR_QUE_PEND_56 (0x00000017)
#define CSL_C66X_COREPAC_NSS_QPEND36 (0x00000018)
#define CSL_C66X_COREPAC_NSS_QPEND37 (0x00000019)
#define CSL_C66X_COREPAC_NSS_QPEND38 (0x0000001A)
#define CSL_C66X_COREPAC_NSS_QPEND39 (0x0000001B)
#define CSL_C66X_COREPAC_NSS_QPEND0 (0x0000001C)
#define CSL_C66X_COREPAC_NSS_QPEND1 (0x0000001D)
#define CSL_C66X_COREPAC_NSS_QPEND2 (0x0000001E)
#define CSL_C66X_COREPAC_NSS_QPEND3 (0x0000001F)
#define CSL_C66X_COREPAC_TIMER_0_INTL (0x00000020)
#define CSL_C66X_COREPAC_TIMER_0_INTH (0x00000021)
#define CSL_C66X_COREPAC_TIMER_1_INTL (0x00000022)
#define CSL_C66X_COREPAC_TIMER_1_INTH (0x00000023)
#define CSL_C66X_COREPAC_TIMER_2_INTL (0x00000024)
#define CSL_C66X_COREPAC_TIMER_2_INTH (0x00000025)
#define CSL_C66X_COREPAC_TIMER_3_INTL (0x00000026)
#define CSL_C66X_COREPAC_TIMER_3_INTH (0x00000027)
#define CSL_C66X_COREPAC_TIMER_4_INTL (0x00000028)
#define CSL_C66X_COREPAC_TIMER_4_INTH (0x00000029)
#define CSL_C66X_COREPAC_TIMER_5_INTL (0x0000002A)
#define CSL_C66X_COREPAC_TIMER_5_INTH (0x0000002B)
#define CSL_C66X_COREPAC_RESERVED_44 (0x0000002C)
#define CSL_C66X_COREPAC_RESERVED_45 (0x0000002D)
#define CSL_C66X_COREPAC_RESERVED_46 (0x0000002E)
#define CSL_C66X_COREPAC_RESERVED_47 (0x0000002F)
#define CSL_C66X_COREPAC_CIC_0_OUT32 (0x00000030)
#define CSL_C66X_COREPAC_CIC_0_OUT33 (0x00000031)
#define CSL_C66X_COREPAC_CIC_0_OUT34 (0x00000032)
#define CSL_C66X_COREPAC_CIC_0_OUT35 (0x00000033)
#define CSL_C66X_COREPAC_CIC_0_OUT36 (0x00000034)
#define CSL_C66X_COREPAC_CIC_0_OUT37 (0x00000035)
#define CSL_C66X_COREPAC_CIC_0_OUT38 (0x00000036)
#define CSL_C66X_COREPAC_CIC_0_OUT39 (0x00000037)
#define CSL_C66X_COREPAC_CIC_0_OUT40 (0x00000038)
#define CSL_C66X_COREPAC_CIC_0_OUT41 (0x00000039)
#define CSL_C66X_COREPAC_CIC_0_OUT42 (0x0000003A)
#define CSL_C66X_COREPAC_CIC_0_OUT43 (0x0000003B)
#define CSL_C66X_COREPAC_CIC_0_OUT44 (0x0000003C)
#define CSL_C66X_COREPAC_CIC_0_OUT45 (0x0000003D)
#define CSL_C66X_COREPAC_CIC_0_OUT46 (0x0000003E)
#define CSL_C66X_COREPAC_CIC_0_OUT47 (0x0000003F)
#define CSL_C66X_COREPAC_CIC_0_OUT48 (0x00000040)
#define CSL_C66X_COREPAC_CIC_0_OUT49 (0x00000041)
#define CSL_C66X_COREPAC_CIC_0_OUT50 (0x00000042)
#define CSL_C66X_COREPAC_CIC_0_OUT51 (0x00000043)
#define CSL_C66X_COREPAC_CIC_0_OUT52 (0x00000044)
#define CSL_C66X_COREPAC_CIC_0_OUT53 (0x00000045)
#define CSL_C66X_COREPAC_CIC_0_OUT54 (0x00000046)
#define CSL_C66X_COREPAC_CIC_0_OUT55 (0x00000047)
#define CSL_C66X_COREPAC_CIC_0_OUT56 (0x00000048)
#define CSL_C66X_COREPAC_CIC_0_OUT57 (0x00000049)
#define CSL_C66X_COREPAC_CIC_0_OUT58 (0x0000004A)
#define CSL_C66X_COREPAC_CIC_0_OUT59 (0x0000004B)
#define CSL_C66X_COREPAC_CIC_0_OUT60 (0x0000004C)
#define CSL_C66X_COREPAC_CIC_0_OUT61 (0x0000004D)
#define CSL_C66X_COREPAC_CIC_0_OUT62 (0x0000004E)
#define CSL_C66X_COREPAC_CIC_0_OUT63 (0x0000004F)
#define CSL_C66X_COREPAC_CIC_0_OUT64 (0x00000050)
#define CSL_C66X_COREPAC_CIC_0_OUT65 (0x00000051)
#define CSL_C66X_COREPAC_CIC_0_OUT66 (0x00000052)
#define CSL_C66X_COREPAC_CIC_0_OUT67 (0x00000053)
#define CSL_C66X_COREPAC_CIC_0_OUT68 (0x00000054)
#define CSL_C66X_COREPAC_CIC_0_OUT69 (0x00000055)
#define CSL_C66X_COREPAC_CIC_0_OUT70 (0x00000056)
#define CSL_C66X_COREPAC_CIC_0_OUT71 (0x00000057)
#define CSL_C66X_COREPAC_CIC_0_OUT72 (0x00000058)
#define CSL_C66X_COREPAC_CIC_0_OUT73 (0x00000059)
#define CSL_C66X_COREPAC_CIC_0_OUT74 (0x0000005A)
#define CSL_C66X_COREPAC_CIC_0_OUT75 (0x0000005B)
#define CSL_C66X_COREPAC_CIC_0_OUT76 (0x0000005C)
#define CSL_C66X_COREPAC_CIC_0_OUT77 (0x0000005D)
#define CSL_C66X_COREPAC_CIC_0_OUT78 (0x0000005E)
#define CSL_C66X_COREPAC_CIC_0_OUT79 (0x0000005F)
#define CSL_C66X_COREPAC_INTERR (0x00000060)
#define CSL_C66X_COREPAC_EMC_IDMAERR (0x00000061)
#define CSL_C66X_COREPAC_PBISTINT (0x00000062)
#define CSL_C66X_COREPAC_RESERVED_99 (0x00000063)
#define CSL_C66X_COREPAC_EFIINT0 (0x00000064)
#define CSL_C66X_COREPAC_EFIINT1 (0x00000065)
#define CSL_C66X_COREPAC_GPIOMUX_INT16 (0x00000066)
#define CSL_C66X_COREPAC_GPIOMUX_INT17 (0x00000067)
#define CSL_C66X_COREPAC_GPIOMUX_INT18 (0x00000068)
#define CSL_C66X_COREPAC_GPIOMUX_INT19 (0x00000069)
#define CSL_C66X_COREPAC_GPIOMUX_INT20 (0x0000006A)
#define CSL_C66X_COREPAC_GPIOMUX_INT21 (0x0000006B)
#define CSL_C66X_COREPAC_GPIOMUX_INT22 (0x0000006C)
#define CSL_C66X_COREPAC_GPIOMUX_INT23 (0x0000006D)
#define CSL_C66X_COREPAC_MDMAERREVT (0x0000006E)
#define CSL_C66X_COREPAC_EDC_NCERR (0x0000006F)
#define CSL_C66X_COREPAC_EDC_CORRERR (0x00000070)
#define CSL_C66X_COREPAC_PMC_ED (0x00000071)
#define CSL_C66X_COREPAC_EDMACC_0_TC_AET_INT (0x00000072)
#define CSL_C66X_COREPAC_EDMACC_1_TC_AET_INT (0x00000073)
#define CSL_C66X_COREPAC_UMC_ED1 (0x00000074)
#define CSL_C66X_COREPAC_UMC_ED2 (0x00000075)
#define CSL_C66X_COREPAC_PDC_INT (0x00000076)
#define CSL_C66X_COREPAC_SYS_CMPA (0x00000077)
#define CSL_C66X_COREPAC_PMC_CMPA (0x00000078)
#define CSL_C66X_COREPAC_PMC_DMPA (0x00000079)
#define CSL_C66X_COREPAC_DMC_CMPA (0x0000007A)
#define CSL_C66X_COREPAC_DMC_DMPA (0x0000007B)
#define CSL_C66X_COREPAC_UMC_CMPA (0x0000007C)
#define CSL_C66X_COREPAC_UMC_DMPA (0x0000007D)
#define CSL_C66X_COREPAC_EMC_CMPA (0x0000007E)
#define CSL_C66X_COREPAC_EMC_BUSERR (0x0000007F)

/*
 * Auto-generated CSL section
 */
#define ICSS0_EVENT_CNT 31
#define CSL_ICSS0_QSPI_INT (0x00000020)
#define CSL_ICSS0_SPI_0_INT0 (0x00000021)
#define CSL_ICSS0_SPI_1_INT0 (0x00000022)
#define CSL_ICSS0_I2C_0_INT (0x00000023)
#define CSL_ICSS0_CIC_0_OUT80 (0x00000024)
#define CSL_ICSS0_CIC_0_OUT81 (0x00000025)
#define CSL_ICSS0_CIC_0_OUT82 (0x00000026)
#define CSL_ICSS0_CIC_0_OUT83 (0x00000027)
#define CSL_ICSS0_CIC_0_OUT88 (0x00000028)
#define CSL_ICSS0_CIC_0_OUT89 (0x00000029)
#define CSL_ICSS0_CIC_0_OUT90 (0x0000002A)
#define CSL_ICSS0_CIC_0_OUT91 (0x0000002B)
#define CSL_ICSS0_CIC_0_OUT92 (0x0000002C)
#define CSL_ICSS0_CIC_0_OUT93 (0x0000002D)
#define CSL_ICSS0_CIC_0_OUT94 (0x0000002E)
#define CSL_ICSS0_CIC_0_OUT95 (0x0000002F)
#define CSL_ICSS0_CIC_0_OUT96 (0x00000030)
#define CSL_ICSS0_CIC_0_OUT97 (0x00000031)
#define CSL_ICSS0_CIC_0_OUT98 (0x00000032)
#define CSL_ICSS0_CIC_0_OUT99 (0x00000033)
#define CSL_ICSS0_CIC_0_OUT100 (0x00000034)
#define CSL_ICSS0_CIC_0_OUT101 (0x00000035)
#define CSL_ICSS0_CIC_0_OUT102 (0x00000036)
#define CSL_ICSS0_IPC_GR11 (0x00000037)
#define CSL_ICSS0_ICSS1_HOST_INT (0x00000038)
#define CSL_ICSS0_IPC_GR12 (0x00000039)
#define CSL_ICSS0_MSGMGR_QUE_PEND_6 (0x0000003A)
#define CSL_ICSS0_MSGMGR_QUE_PEND_7 (0x0000003B)
#define CSL_ICSS0_MSGMGR_QUE_PEND_58 (0x0000003C)
#define CSL_ICSS0_MSGMGR_QUE_PEND_59 (0x0000003D)
#define CSL_ICSS0_EDMACC_0_REGION_6_INT (0x0000003E)
#define CSL_ICSS0_EDMACC_1_REGION_6_INT (0x0000003F)

/*
 * Auto-generated CSL section
 */
#define ICSS1_EVENT_CNT 31
#define CSL_ICSS1_ECAP_0_INT (0x00000020)
#define CSL_ICSS1_ECAP_1_INT (0x00000021)
#define CSL_ICSS1_EPWM_0_INT (0x00000022)
#define CSL_ICSS1_EPWM_1_INT (0x00000023)
#define CSL_ICSS1_EPWM_2_INT (0x00000024)
#define CSL_ICSS1_EPWM_3_INT (0x00000025)
#define CSL_ICSS1_EPWM_4_INT (0x00000026)
#define CSL_ICSS1_EPWM_5_INT (0x00000027)
#define CSL_ICSS1_EPWM_0_TRIP_ZONE (0x00000028)
#define CSL_ICSS1_EPWM_3_TRIP_ZONE (0x00000029)
#define CSL_ICSS1_EQEP_0_INT (0x0000002A)
#define CSL_ICSS1_EQEP_1_INT (0x0000002B)
#define CSL_ICSS1_EQEP_2_INT (0x0000002C)
#define CSL_ICSS1_CIC_0_OUT80 (0x0000002D)
#define CSL_ICSS1_CIC_0_OUT81 (0x0000002E)
#define CSL_ICSS1_CIC_0_OUT82 (0x0000002F)
#define CSL_ICSS1_CIC_0_OUT83 (0x00000030)
#define CSL_ICSS1_CIC_0_OUT84 (0x00000031)
#define CSL_ICSS1_CIC_0_OUT85 (0x00000032)
#define CSL_ICSS1_CIC_0_OUT86 (0x00000033)
#define CSL_ICSS1_CIC_0_OUT87 (0x00000034)
#define CSL_ICSS1_PWM_SOCA (0x00000035)
#define CSL_ICSS1_PWM_SOCB (0x00000036)
#define CSL_ICSS1_IPC_GR13 (0x00000037)
#define CSL_ICSS1_ICSS0_HOST_INT (0x00000038)
#define CSL_ICSS1_IPC_GR14 (0x00000039)
#define CSL_ICSS1_MSGMGR_QUE_PEND_8 (0x0000003A)
#define CSL_ICSS1_MSGMGR_QUE_PEND_9 (0x0000003B)
#define CSL_ICSS1_MSGMGR_QUE_PEND_60 (0x0000003C)
#define CSL_ICSS1_MSGMGR_QUE_PEND_61 (0x0000003D)
#define CSL_ICSS1_EDMACC_0_REGION_7_INT (0x0000003E)
#define CSL_ICSS1_EDMACC_1_REGION_7_INT (0x0000003F)

/*
 * Auto-generated CSL section
 */
#define PMMC_EVENT_CNT 215
#define CSL_PMMC_RESERVED_0 (0x00000000)
#define CSL_PMMC_RESERVED_1 (0x00000001)
#define CSL_PMMC_RESERVED_2 (0x00000002)
#define CSL_PMMC_TIMER_6_INTL (0x00000003)
#define CSL_PMMC_TIMER_6_INTH (0x00000004)
#define CSL_PMMC_I2C_0_INT (0x00000005)
#define CSL_PMMC_RESERVED_6 (0x00000006)
#define CSL_PMMC_RESERVED_7 (0x00000007)
#define CSL_PMMC_SEM_INT15 (0x00000008)
#define CSL_PMMC_SEM_ERR15 (0x00000009)
#define CSL_PMMC_PSC_ALLINT (0x0000000A)
#define CSL_PMMC_ARM_CLKSTOP (0x0000000B)
#define CSL_PMMC_GEM_0_CLKSTOP (0x0000000C)
#define CSL_PMMC_MSMC_MPF_ERROR9 (0x0000000D)
#define CSL_PMMC_ARM_WFI (0x0000000E)
#define CSL_PMMC_ARM_PWRDWN (0x0000000F)
#define CSL_PMMC_MSGMGR_QUE_PEND_0 (0x00000010)
#define CSL_PMMC_MSGMGR_QUE_PEND_1 (0x00000011)
#define CSL_PMMC_MSGMGR_QUE_PEND_2 (0x00000012)
#define CSL_PMMC_MSGMGR_QUE_PEND_3 (0x00000013)
#define CSL_PMMC_MSGMGR_QUE_PEND_32 (0x00000014)
#define CSL_PMMC_MSGMGR_QUE_PEND_33 (0x00000015)
#define CSL_PMMC_MSGMGR_QUE_PEND_34 (0x00000016)
#define CSL_PMMC_MSGMGR_QUE_PEND_35 (0x00000017)
#define CSL_PMMC_RESERVED_24 (0x00000018)
#define CSL_PMMC_RESERVED_25 (0x00000019)
#define CSL_PMMC_RESERVED_26 (0x0000001A)
#define CSL_PMMC_RESERVED_27 (0x0000001B)
#define CSL_PMMC_RESERVED_28 (0x0000001C)
#define CSL_PMMC_MSGMGR_ECC_ERROR (0x0000001D)
#define CSL_PMMC_MSGMGR_FREEINDEX_ERROR (0x0000001E)
#define CSL_PMMC_MSGMGR_PROXY_ERROR (0x0000001F)
#define CSL_PMMC_SR_0_SMARTREFLEX_INTREQ0 (0x00000020)
#define CSL_PMMC_SR_0_SMARTREFLEX_INTREQ1 (0x00000021)
#define CSL_PMMC_SR_0_SMARTREFLEX_INTREQ2 (0x00000022)
#define CSL_PMMC_SR_0_SMARTREFLEX_INTREQ3 (0x00000023)
#define CSL_PMMC_SR_0_VPNOSMPSACK (0x00000024)
#define CSL_PMMC_SR_0_VPEQVALUE (0x00000025)
#define CSL_PMMC_SR_0_VPMAXVDD (0x00000026)
#define CSL_PMMC_SR_0_VPMINVDD (0x00000027)
#define CSL_PMMC_SR_0_VPINIDLE (0x00000028)
#define CSL_PMMC_SR_0_VPOPPCHANGEDONE (0x00000029)
#define CSL_PMMC_SR_0_PO_VCON_SMPSERR_INT (0x0000002A)
#define CSL_PMMC_SR_0_VPSMPSACK (0x0000002B)
#define CSL_PMMC_SR_0_SR_TEMPSENSOR (0x0000002C)
#define CSL_PMMC_SR_0_SR_TIMERINT (0x0000002D)
#define CSL_PMMC_SR_0_SR_I2CINT (0x0000002E)
#define CSL_PMMC_SR_0_SR_MAX_TEMP_INT (0x0000002F)
#define CSL_PMMC_SR_0_SR_SMBALERT (0x00000030)
#define CSL_PMMC_RESERVED_49 (0x00000031)
#define CSL_PMMC_RESERVED_50 (0x00000032)
#define CSL_PMMC_RESERVED_51 (0x00000033)
#define CSL_PMMC_RESERVED_52 (0x00000034)
#define CSL_PMMC_RESERVED_53 (0x00000035)
#define CSL_PMMC_RESERVED_54 (0x00000036)
#define CSL_PMMC_RESERVED_55 (0x00000037)
#define CSL_PMMC_RESERVED_56 (0x00000038)
#define CSL_PMMC_RESERVED_57 (0x00000039)
#define CSL_PMMC_RESERVED_58 (0x0000003A)
#define CSL_PMMC_RESERVED_59 (0x0000003B)
#define CSL_PMMC_NSS_QPEND44 (0x0000003C)
#define CSL_PMMC_NSS_QPEND45 (0x0000003D)
#define CSL_PMMC_NSS_QPEND46 (0x0000003E)
#define CSL_PMMC_NSS_QPEND47 (0x0000003F)
#define CSL_PMMC_GPIOMUX_INT24 (0x00000040)
#define CSL_PMMC_GPIOMUX_INT25 (0x00000041)
#define CSL_PMMC_GPIOMUX_INT26 (0x00000042)
#define CSL_PMMC_GPIOMUX_INT27 (0x00000043)
#define CSL_PMMC_GPIOMUX_INT28 (0x00000044)
#define CSL_PMMC_GPIOMUX_INT29 (0x00000045)
#define CSL_PMMC_GPIOMUX_INT30 (0x00000046)
#define CSL_PMMC_GPIOMUX_INT31 (0x00000047)
#define CSL_PMMC_RESERVED_72 (0x00000048)
#define CSL_PMMC_RESERVED_73 (0x00000049)
#define CSL_PMMC_RESERVED_74 (0x0000004A)
#define CSL_PMMC_RESERVED_75 (0x0000004B)
#define CSL_PMMC_RESERVED_76 (0x0000004C)
#define CSL_PMMC_RESERVED_77 (0x0000004D)
#define CSL_PMMC_RESERVED_78 (0x0000004E)
#define CSL_PMMC_RESERVED_79 (0x0000004F)
#define CSL_PMMC_DCAN_0_INT0 (0x00000050)
#define CSL_PMMC_DCAN_0_INT1 (0x00000051)
#define CSL_PMMC_DCAN_0_ERR_INT (0x00000052)
#define CSL_PMMC_RESERVED_83 (0x00000053)
#define CSL_PMMC_DCAN_1_INT0 (0x00000054)
#define CSL_PMMC_DCAN_1_INT1 (0x00000055)
#define CSL_PMMC_DCAN_1_ERR_INT (0x00000056)
#define CSL_PMMC_RESERVED_87 (0x00000057)
#define CSL_PMMC_RESERVED_88 (0x00000058)
#define CSL_PMMC_RESERVED_89 (0x00000059)
#define CSL_PMMC_RESERVED_90 (0x0000005A)
#define CSL_PMMC_RESERVED_91 (0x0000005B)
#define CSL_PMMC_RESERVED_92 (0x0000005C)
#define CSL_PMMC_RESERVED_93 (0x0000005D)
#define CSL_PMMC_RESERVED_94 (0x0000005E)
#define CSL_PMMC_RESERVED_95 (0x0000005F)
#define CSL_PMMC_RESERVED_96 (0x00000060)
#define CSL_PMMC_RESERVED_97 (0x00000061)
#define CSL_PMMC_RESERVED_98 (0x00000062)
#define CSL_PMMC_RESERVED_99 (0x00000063)
#define CSL_PMMC_RESERVED_100 (0x00000064)
#define CSL_PMMC_RESERVED_101 (0x00000065)
#define CSL_PMMC_RESERVED_102 (0x00000066)
#define CSL_PMMC_RESERVED_103 (0x00000067)
#define CSL_PMMC_RESERVED_104 (0x00000068)
#define CSL_PMMC_RESERVED_105 (0x00000069)
#define CSL_PMMC_RESERVED_106 (0x0000006A)
#define CSL_PMMC_RESERVED_107 (0x0000006B)
#define CSL_PMMC_RESERVED_108 (0x0000006C)
#define CSL_PMMC_RESERVED_109 (0x0000006D)
#define CSL_PMMC_RESERVED_110 (0x0000006E)
#define CSL_PMMC_RESERVED_111 (0x0000006F)
#define CSL_PMMC_RESERVED_112 (0x00000070)
#define CSL_PMMC_RESERVED_113 (0x00000071)
#define CSL_PMMC_RESERVED_114 (0x00000072)
#define CSL_PMMC_RESERVED_115 (0x00000073)
#define CSL_PMMC_RESERVED_116 (0x00000074)
#define CSL_PMMC_RESERVED_117 (0x00000075)
#define CSL_PMMC_RESERVED_118 (0x00000076)
#define CSL_PMMC_RESERVED_119 (0x00000077)
#define CSL_PMMC_RESERVED_120 (0x00000078)
#define CSL_PMMC_RESERVED_121 (0x00000079)
#define CSL_PMMC_RESERVED_122 (0x0000007A)
#define CSL_PMMC_RESERVED_123 (0x0000007B)
#define CSL_PMMC_RESERVED_124 (0x0000007C)
#define CSL_PMMC_RESERVED_125 (0x0000007D)
#define CSL_PMMC_RESERVED_126 (0x0000007E)
#define CSL_PMMC_RESERVED_127 (0x0000007F)
#define CSL_PMMC_RESERVED_128 (0x00000080)
#define CSL_PMMC_RESERVED_129 (0x00000081)
#define CSL_PMMC_RESERVED_130 (0x00000082)
#define CSL_PMMC_RESERVED_131 (0x00000083)
#define CSL_PMMC_RESERVED_132 (0x00000084)
#define CSL_PMMC_RESERVED_133 (0x00000085)
#define CSL_PMMC_RESERVED_134 (0x00000086)
#define CSL_PMMC_RESERVED_135 (0x00000087)
#define CSL_PMMC_RESERVED_136 (0x00000088)
#define CSL_PMMC_RESERVED_137 (0x00000089)
#define CSL_PMMC_RESERVED_138 (0x0000008A)
#define CSL_PMMC_RESERVED_139 (0x0000008B)
#define CSL_PMMC_RESERVED_140 (0x0000008C)
#define CSL_PMMC_RESERVED_141 (0x0000008D)
#define CSL_PMMC_RESERVED_142 (0x0000008E)
#define CSL_PMMC_RESERVED_143 (0x0000008F)
#define CSL_PMMC_RESERVED_144 (0x00000090)
#define CSL_PMMC_RESERVED_145 (0x00000091)
#define CSL_PMMC_RESERVED_146 (0x00000092)
#define CSL_PMMC_RESERVED_147 (0x00000093)
#define CSL_PMMC_RESERVED_148 (0x00000094)
#define CSL_PMMC_RESERVED_149 (0x00000095)
#define CSL_PMMC_RESERVED_150 (0x00000096)
#define CSL_PMMC_RESERVED_151 (0x00000097)
#define CSL_PMMC_RESERVED_152 (0x00000098)
#define CSL_PMMC_RESERVED_153 (0x00000099)
#define CSL_PMMC_RESERVED_154 (0x0000009A)
#define CSL_PMMC_RESERVED_155 (0x0000009B)
#define CSL_PMMC_RESERVED_156 (0x0000009C)
#define CSL_PMMC_RESERVED_157 (0x0000009D)
#define CSL_PMMC_RESERVED_158 (0x0000009E)
#define CSL_PMMC_RESERVED_159 (0x0000009F)
#define CSL_PMMC_RESERVED_160 (0x000000A0)
#define CSL_PMMC_RESERVED_161 (0x000000A1)
#define CSL_PMMC_RESERVED_162 (0x000000A2)
#define CSL_PMMC_RESERVED_163 (0x000000A3)
#define CSL_PMMC_RESERVED_164 (0x000000A4)
#define CSL_PMMC_RESERVED_165 (0x000000A5)
#define CSL_PMMC_RESERVED_166 (0x000000A6)
#define CSL_PMMC_RESERVED_167 (0x000000A7)
#define CSL_PMMC_RESERVED_168 (0x000000A8)
#define CSL_PMMC_RESERVED_169 (0x000000A9)
#define CSL_PMMC_RESERVED_170 (0x000000AA)
#define CSL_PMMC_RESERVED_171 (0x000000AB)
#define CSL_PMMC_RESERVED_172 (0x000000AC)
#define CSL_PMMC_RESERVED_173 (0x000000AD)
#define CSL_PMMC_RESERVED_174 (0x000000AE)
#define CSL_PMMC_RESERVED_175 (0x000000AF)
#define CSL_PMMC_RESERVED_176 (0x000000B0)
#define CSL_PMMC_RESERVED_177 (0x000000B1)
#define CSL_PMMC_RESERVED_178 (0x000000B2)
#define CSL_PMMC_RESERVED_179 (0x000000B3)
#define CSL_PMMC_RESERVED_180 (0x000000B4)
#define CSL_PMMC_RESERVED_181 (0x000000B5)
#define CSL_PMMC_RESERVED_182 (0x000000B6)
#define CSL_PMMC_RESERVED_183 (0x000000B7)
#define CSL_PMMC_RESERVED_184 (0x000000B8)
#define CSL_PMMC_RESERVED_185 (0x000000B9)
#define CSL_PMMC_RESERVED_186 (0x000000BA)
#define CSL_PMMC_RESERVED_187 (0x000000BB)
#define CSL_PMMC_RESERVED_188 (0x000000BC)
#define CSL_PMMC_RESERVED_189 (0x000000BD)
#define CSL_PMMC_RESERVED_190 (0x000000BE)
#define CSL_PMMC_RESERVED_191 (0x000000BF)
#define CSL_PMMC_RESERVED_192 (0x000000C0)
#define CSL_PMMC_RESERVED_193 (0x000000C1)
#define CSL_PMMC_RESERVED_194 (0x000000C2)
#define CSL_PMMC_RESERVED_195 (0x000000C3)
#define CSL_PMMC_RESERVED_196 (0x000000C4)
#define CSL_PMMC_RESERVED_197 (0x000000C5)
#define CSL_PMMC_RESERVED_198 (0x000000C6)
#define CSL_PMMC_RESERVED_199 (0x000000C7)
#define CSL_PMMC_RESERVED_200 (0x000000C8)
#define CSL_PMMC_RESERVED_201 (0x000000C9)
#define CSL_PMMC_RESERVED_202 (0x000000CA)
#define CSL_PMMC_RESERVED_203 (0x000000CB)
#define CSL_PMMC_RESERVED_204 (0x000000CC)
#define CSL_PMMC_RESERVED_205 (0x000000CD)
#define CSL_PMMC_RESERVED_206 (0x000000CE)
#define CSL_PMMC_RESERVED_207 (0x000000CF)
#define CSL_PMMC_RESERVED_208 (0x000000D0)
#define CSL_PMMC_RESERVED_209 (0x000000D1)
#define CSL_PMMC_RESERVED_210 (0x000000D2)
#define CSL_PMMC_RESERVED_211 (0x000000D3)
#define CSL_PMMC_RESERVED_212 (0x000000D4)
#define CSL_PMMC_RESERVED_213 (0x000000D5)
#define CSL_PMMC_RESERVED_214 (0x000000D6)
#define CSL_PMMC_RESERVED_215 (0x000000D7)

/*
 * Auto-generated CSL section
 */
#define EDMACC_0_EVENT_CNT 63
#define CSL_EDMACC_0_TIMER_2_INTL (0x00000000)
#define CSL_EDMACC_0_TIMER_2_INTH (0x00000001)
#define CSL_EDMACC_0_TIMER_3_INTL (0x00000002)
#define CSL_EDMACC_0_TIMER_3_INTH (0x00000003)
#define CSL_EDMACC_0_SPI_0_XEVT (0x00000004)
#define CSL_EDMACC_0_SPI_0_REVT (0x00000005)
#define CSL_EDMACC_0_SPI_1_XEVT (0x00000006)
#define CSL_EDMACC_0_SPI_1_REVT (0x00000007)
#define CSL_EDMACC_0_I2C_0_XEVT (0x00000008)
#define CSL_EDMACC_0_I2C_0_REVT (0x00000009)
#define CSL_EDMACC_0_QSPI_INT (0x0000000A)
#define CSL_EDMACC_0_PMMCTBR_DMAINT (0x0000000B)
#define CSL_EDMACC_0_ARM_TBR_DMA (0x0000000C)
#define CSL_EDMACC_0_DBGTBR_DMAINT (0x0000000D)
#define CSL_EDMACC_0_TETB_HFULLINT0 (0x0000000E)
#define CSL_EDMACC_0_TETB_FULLINT0 (0x0000000F)
#define CSL_EDMACC_0_UART_0_UTXEVT (0x00000010)
#define CSL_EDMACC_0_UART_0_URXEVT (0x00000011)
#define CSL_EDMACC_0_UART_1_UTXEVT (0x00000012)
#define CSL_EDMACC_0_UART_1_URXEVT (0x00000013)
#define CSL_EDMACC_0_UART_2_UTXEVT (0x00000014)
#define CSL_EDMACC_0_UART_2_URXEVT (0x00000015)
#define CSL_EDMACC_0_DSS_DISPCDMA_REQ (0x00000016)
#define CSL_EDMACC_0_DSS_RFBIDMA_REQ (0x00000017)
#define CSL_EDMACC_0_McASP_0_XEVT (0x00000018)
#define CSL_EDMACC_0_McASP_0_REVT (0x00000019)
#define CSL_EDMACC_0_McBSP_XEVT (0x0000001A)
#define CSL_EDMACC_0_McBSP_REVT (0x0000001B)
#define CSL_EDMACC_0_CIC_0_OUT32 (0x0000001C)
#define CSL_EDMACC_0_CIC_0_OUT33 (0x0000001D)
#define CSL_EDMACC_0_CIC_0_OUT34 (0x0000001E)
#define CSL_EDMACC_0_CIC_0_OUT35 (0x0000001F)
#define CSL_EDMACC_0_ASRC_GROUP_IN_0_EVT (0x00000020)
#define CSL_EDMACC_0_ASRC_GROUP_IN_1_EVT (0x00000021)
#define CSL_EDMACC_0_ASRC_GROUP_OUT_0_EVT (0x00000022)
#define CSL_EDMACC_0_ASRC_GROUP_OUT_1_EVT (0x00000023)
#define CSL_EDMACC_0_CIC_0_OUT28 (0x00000024)
#define CSL_EDMACC_0_CIC_0_OUT29 (0x00000025)
#define CSL_EDMACC_0_CIC_0_OUT30 (0x00000026)
#define CSL_EDMACC_0_CIC_0_OUT31 (0x00000027)
#define CSL_EDMACC_0_NSS_QPEND48 (0x00000028)
#define CSL_EDMACC_0_NSS_QPEND49 (0x00000029)
#define CSL_EDMACC_0_NSS_QPEND50 (0x0000002A)
#define CSL_EDMACC_0_NSS_QPEND51 (0x0000002B)
#define CSL_EDMACC_0_NSS_QPEND64 (0x0000002C)
#define CSL_EDMACC_0_NSS_QPEND65 (0x0000002D)
#define CSL_EDMACC_0_NSS_QPEND66 (0x0000002E)
#define CSL_EDMACC_0_NSS_QPEND67 (0x0000002F)
#define CSL_EDMACC_0_GPIOMUX_INT48 (0x00000030)
#define CSL_EDMACC_0_GPIOMUX_INT49 (0x00000031)
#define CSL_EDMACC_0_GPIOMUX_INT50 (0x00000032)
#define CSL_EDMACC_0_GPIOMUX_INT51 (0x00000033)
#define CSL_EDMACC_0_GPIOMUX_INT52 (0x00000034)
#define CSL_EDMACC_0_GPIOMUX_INT53 (0x00000035)
#define CSL_EDMACC_0_GPIOMUX_INT54 (0x00000036)
#define CSL_EDMACC_0_GPIOMUX_INT55 (0x00000037)
#define CSL_EDMACC_0_GPIOMUX_INT32 (0x00000038)
#define CSL_EDMACC_0_GPIOMUX_INT33 (0x00000039)
#define CSL_EDMACC_0_GPIOMUX_INT34 (0x0000003A)
#define CSL_EDMACC_0_GPIOMUX_INT35 (0x0000003B)
#define CSL_EDMACC_0_GPIOMUX_INT36 (0x0000003C)
#define CSL_EDMACC_0_GPIOMUX_INT37 (0x0000003D)
#define CSL_EDMACC_0_GPIOMUX_INT38 (0x0000003E)
#define CSL_EDMACC_0_GPIOMUX_INT39 (0x0000003F)

/*
 * Auto-generated CSL section
 */
#define EDMACC_1_EVENT_CNT 63
#define CSL_EDMACC_1_TIMER_4_INTL (0x00000000)
#define CSL_EDMACC_1_TIMER_4_INTH (0x00000001)
#define CSL_EDMACC_1_TIMER_1_INTL (0x00000002)
#define CSL_EDMACC_1_TIMER_1_INTH (0x00000003)
#define CSL_EDMACC_1_SPI_2_XEVT (0x00000004)
#define CSL_EDMACC_1_SPI_2_REVT (0x00000005)
#define CSL_EDMACC_1_SPI_3_XEVT (0x00000006)
#define CSL_EDMACC_1_SPI_3_REVT (0x00000007)
#define CSL_EDMACC_1_I2C_1_XEVT (0x00000008)
#define CSL_EDMACC_1_I2C_1_REVT (0x00000009)
#define CSL_EDMACC_1_I2C_2_XEVT (0x0000000A)
#define CSL_EDMACC_1_I2C_2_REVT (0x0000000B)
#define CSL_EDMACC_1_RESERVED_12 (0x0000000C)
#define CSL_EDMACC_1_RESERVED_13 (0x0000000D)
#define CSL_EDMACC_1_SR_0_SR_I2C_XEVT (0x0000000E)
#define CSL_EDMACC_1_SR_0_SR_I2C_REVT (0x0000000F)
#define CSL_EDMACC_1_DCAN_0_INTERFACE1_EVT (0x00000010)
#define CSL_EDMACC_1_DCAN_0_INTERFACE2_EVT (0x00000011)
#define CSL_EDMACC_1_DCAN_0_INTERFACE3_EVT (0x00000012)
#define CSL_EDMACC_1_DCAN_1_INTERFACE1_EVT (0x00000013)
#define CSL_EDMACC_1_DCAN_1_INTERFACE2_EVT (0x00000014)
#define CSL_EDMACC_1_DCAN_1_INTERFACE3_EVT (0x00000015)
#define CSL_EDMACC_1_CIC_0_OUT24 (0x00000016)
#define CSL_EDMACC_1_CIC_0_OUT25 (0x00000017)
#define CSL_EDMACC_1_MMC_SD_0_TX_EVT (0x00000018)
#define CSL_EDMACC_1_MMC_SD_0_RX_EVT (0x00000019)
#define CSL_EDMACC_1_MMC_SD_1_TX_EVT (0x0000001A)
#define CSL_EDMACC_1_MMC_SD_1_RX_EVT (0x0000001B)
#define CSL_EDMACC_1_EQEP_0_INT (0x0000001C)
#define CSL_EDMACC_1_EQEP_1_INT (0x0000001D)
#define CSL_EDMACC_1_EQEP_2_INT (0x0000001E)
#define CSL_EDMACC_1_GPMC_DMA_REQ (0x0000001F)
#define CSL_EDMACC_1_EPWM_0_INT (0x00000020)
#define CSL_EDMACC_1_EPWM_1_INT (0x00000021)
#define CSL_EDMACC_1_EPWM_2_INT (0x00000022)
#define CSL_EDMACC_1_EPWM_3_INT (0x00000023)
#define CSL_EDMACC_1_EPWM_4_INT (0x00000024)
#define CSL_EDMACC_1_EPWM_5_INT (0x00000025)
#define CSL_EDMACC_1_EPWM_0_TRIP_ZONE (0x00000026)
#define CSL_EDMACC_1_EPWM_1_TRIP_ZONE (0x00000027)
#define CSL_EDMACC_1_EPWM_2_TRIP_ZONE (0x00000028)
#define CSL_EDMACC_1_EPWM_3_TRIP_ZONE (0x00000029)
#define CSL_EDMACC_1_EPWM_4_TRIP_ZONE (0x0000002A)
#define CSL_EDMACC_1_EPWM_5_TRIP_ZONE (0x0000002B)
#define CSL_EDMACC_1_ECAP_0_INT (0x0000002C)
#define CSL_EDMACC_1_ECAP_1_INT (0x0000002D)
#define CSL_EDMACC_1_CIC_0_OUT26 (0x0000002E)
#define CSL_EDMACC_1_CIC_0_OUT27 (0x0000002F)
#define CSL_EDMACC_1_McASP_1_XEVT (0x00000030)
#define CSL_EDMACC_1_McASP_1_REVT (0x00000031)
#define CSL_EDMACC_1_McASP_2_XEVT (0x00000032)
#define CSL_EDMACC_1_McASP_2_REVT (0x00000033)
#define CSL_EDMACC_1_ASRC_GROUP_IN_2_EVT (0x00000034)
#define CSL_EDMACC_1_ASRC_GROUP_IN_3_EVT (0x00000035)
#define CSL_EDMACC_1_ASRC_GROUP_OUT_2_EVT (0x00000036)
#define CSL_EDMACC_1_ASRC_GROUP_OUT_3_EVT (0x00000037)
#define CSL_EDMACC_1_GPIOMUX_INT40 (0x00000038)
#define CSL_EDMACC_1_GPIOMUX_INT41 (0x00000039)
#define CSL_EDMACC_1_GPIOMUX_INT42 (0x0000003A)
#define CSL_EDMACC_1_GPIOMUX_INT43 (0x0000003B)
#define CSL_EDMACC_1_GPIOMUX_INT44 (0x0000003C)
#define CSL_EDMACC_1_GPIOMUX_INT45 (0x0000003D)
#define CSL_EDMACC_1_GPIOMUX_INT46 (0x0000003E)
#define CSL_EDMACC_1_GPIOMUX_INT47 (0x0000003F)

/*
 * Auto-generated CSL section
 */
#define CSL_MPU_EOI_VALUE (0)
#define CSL_TRACER_EOI_VALUE (0)
#define CSL_ASRC_STREAM_IN_EOI_VALUE (0)
#define CSL_ASRC_STREAM_OUT_EOI_VALUE (1)
#define CSL_ASRC_GROUP_IN_EOI_VALUE (2)
#define CSL_ASRC_GROUP_OUT_EOI_VALUE (3)
#define CSL_ASRC_STREAM_ERR_EOI_VALUE (4)
#define CSL_NSS_CDMA_STARVE_EOI_VALUE (0)
#define CSL_NSS_ESW_STAT_PEND0_EOI_VALUE (1)
#define CSL_NSS_ESW_STAT_PEND1_EOI_VALUE (2)
#define CSL_NSS_ESW_EVT_PEND_EOI_VALUE (3)
#define CSL_NSS_MDIO_LINK0_EOI_VALUE (4)
#define CSL_NSS_MDIO_LINK1_EOI_VALUE (5)
#define CSL_NSS_MDIO_USER0_EOI_VALUE (6)
#define CSL_NSS_MDIO_USER1_EOI_VALUE (7)
#define CSL_NSS_TRNG_EOI_VALUE (8)
#define CSL_NSS_PKA_EOI_VALUE (9)

/*
 * Auto-generated CSL section
 */
#define QMSS_NSS_QUEUE_BASE  0
#define QMSS_MAX_NSS_QUEUE  21
#define QMSS_RECEIVE_QUEUE_QUEUE_BASE  21
#define QMSS_MAX_RECEIVE_QUEUE_QUEUE  32
#define QMSS_ARM_GIC_QUEUE_BASE  53
#define QMSS_MAX_ARM_GIC_QUEUE  4
#define QMSS_DSP_QUEUE_BASE  57
#define QMSS_MAX_DSP_QUEUE  4
#define QMSS_UNASSIGNED_SET_0_QUEUE_BASE  61
#define QMSS_MAX_UNASSIGNED_SET_0_QUEUE  4
#define QMSS_PMMC_QUEUE_BASE  65
#define QMSS_MAX_PMMC_QUEUE  4
#define QMSS_EDMA0_QUEUE_BASE  69
#define QMSS_MAX_EDMA0_QUEUE  4
#define QMSS_UNASSIGNED_SET_1_QUEUE_BASE  73
#define QMSS_MAX_UNASSIGNED_SET_1_QUEUE  4
#define QMSS_SOC_SET_0_QUEUE_BASE  77
#define QMSS_MAX_SOC_SET_0_QUEUE  8
#define QMSS_CIC_EDMA_SET_0_QUEUE_BASE  85
#define QMSS_MAX_CIC_EDMA_SET_0_QUEUE  4
#define QMSS_UNASSIGNED_SET_2_QUEUE_BASE  89
#define QMSS_MAX_UNASSIGNED_SET_2_QUEUE  4
#define QMSS_GENERAL_PURPOSE_QUEUE_BASE  89
#define QMSS_MAX_GENERAL_PURPOSE_QUEUE  39
#define MSGMGR_PMMC_NONSEC_FWD_QUEUE_BASE  0
#define MSGMGR_MAX_PMMC_NONSEC_FWD_QUEUE  4
#define MSGMGR_PMMC_NONSEC_RTN_DSP_QUEUE_BASE  4
#define MSGMGR_MAX_PMMC_NONSEC_RTN_DSP_QUEUE  1
#define MSGMGR_PMMC_NONSEC_RTN_ARM_QUEUE_BASE  5
#define MSGMGR_MAX_PMMC_NONSEC_RTN_ARM_QUEUE  1
#define MSGMGR_PMMC_NONSEC_RTN_ICSS0_PRU0_QUEUE_BASE  6
#define MSGMGR_MAX_PMMC_NONSEC_RTN_ICSS0_PRU0_QUEUE  1
#define MSGMGR_PMMC_NONSEC_RTN_ICSS0_PRU1_QUEUE_BASE  7
#define MSGMGR_MAX_PMMC_NONSEC_RTN_ICSS0_PRU1_QUEUE  1
#define MSGMGR_PMMC_NONSEC_RTN_ICSS1_PRU0_QUEUE_BASE  8
#define MSGMGR_MAX_PMMC_NONSEC_RTN_ICSS1_PRU0_QUEUE  1
#define MSGMGR_PMMC_NONSEC_RTN_ICSS1_PRU1_QUEUE_BASE  9
#define MSGMGR_MAX_PMMC_NONSEC_RTN_ICSS1_PRU1_QUEUE  1
#define MSGMGR_UNASSIGNED_SET_0_QUEUE_BASE  10
#define MSGMGR_MAX_UNASSIGNED_SET_0_QUEUE  22
#define MSGMGR_PMMC_SEC_FWD_QUEUE_BASE  32
#define MSGMGR_MAX_PMMC_SEC_FWD_QUEUE  4
#define MSGMGR_PMMC_SEC_RTN_DSP_QUEUE_BASE  36
#define MSGMGR_MAX_PMMC_SEC_RTN_DSP_QUEUE  1
#define MSGMGR_PMMC_SEC_RTN_ARM_QUEUE_BASE  37
#define MSGMGR_MAX_PMMC_SEC_RTN_ARM_QUEUE  1
#define MSGMGR_UNASSIGNED_SET_1_QUEUE_BASE  38
#define MSGMGR_MAX_UNASSIGNED_SET_1_QUEUE  10
#define MSGMGR_IPC_SEC_DSP_QUEUE_BASE  48
#define MSGMGR_MAX_IPC_SEC_DSP_QUEUE  1
#define MSGMGR_IPC_SEC_ARM_QUEUE_BASE  49
#define MSGMGR_MAX_IPC_SEC_ARM_QUEUE  1
#define MSGMGR_UNASSIGNED_SET_2_QUEUE_BASE  50
#define MSGMGR_MAX_UNASSIGNED_SET_2_QUEUE  6
#define MSGMGR_IPC_NONSEC_DSP_QUEUE_BASE  56
#define MSGMGR_MAX_IPC_NONSEC_DSP_QUEUE  1
#define MSGMGR_IPC_NONSEC_ARM_QUEUE_BASE  57
#define MSGMGR_MAX_IPC_NONSEC_ARM_QUEUE  1
#define MSGMGR_IPC_NONSEC_ICSS0_PRU0_QUEUE_BASE  58
#define MSGMGR_MAX_IPC_NONSEC_ICSS0_PRU0_QUEUE  1
#define MSGMGR_IPC_NONSEC_ICSS0_PRU1_QUEUE_BASE  59
#define MSGMGR_MAX_IPC_NONSEC_ICSS0_PRU1_QUEUE  1
#define MSGMGR_IPC_NONSEC_ICSS1_PRU0_QUEUE_BASE  60
#define MSGMGR_MAX_IPC_NONSEC_ICSS1_PRU0_QUEUE  1
#define MSGMGR_IPC_NONSEC_ICSS1_PRU1_QUEUE_BASE  61
#define MSGMGR_MAX_IPC_NONSEC_ICSS1_PRU1_QUEUE  1
#define MSGMGR_UNASSIGNED_SET_3_QUEUE_BASE  62
#define MSGMGR_MAX_UNASSIGNED_SET_3_QUEUE  2

/*
 * Auto-generated CSL section
 */
#ifndef CSL_MODIFICATION   

/* ========================================================================= */
/* ========================================================================= */

/* Followings defines are used for maintaining backward compatibility */

#define QMSS_INFRASTRUCTURE_QUEUE_BASE              (QMSS_NSS_QUEUE_BASE)
#define QMSS_MAX_INFRASTRUCTURE_QUEUE               4

#define QMSS_PASS_QUEUE_BASE                        (QMSS_NSS_QUEUE_BASE + 4)
#define QMSS_MAX_PASS_QUEUE                         (QMSS_MAX_NSS_QUEUE - 4)

/* ========================================================================= */
/* ========================================================================= */
#endif


#ifdef __cplusplus
}
#endif

#endif


