/********************************************************************
 * Copyright (C) 2013-2014 Texas Instruments Incorporated.
 * 
 *  Redistribution and use in source and binary forms, with or without 
 *  modification, are permitted provided that the following conditions 
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright 
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the 
 *    documentation and/or other materials provided with the   
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
*/
#ifndef CSLR_EMIF4FV_H
#define CSLR_EMIF4FV_H

#ifdef __cplusplus
extern "C"
{
#endif
#include <ti/csl/cslr.h>
#include <ti/csl/tistdtypes.h>


/**************************************************************************
* Register Overlay Structure for __ALL__
**************************************************************************/
typedef struct {
    volatile Uint32 EMIF_MOD_ID_REV;
    volatile Uint32 STATUS;
    volatile Uint32 SDRAM_CONFIG;
    volatile Uint8  RSVD0[4];
    volatile Uint32 SDRAM_REF_CTRL;
    volatile Uint8  RSVD1[4];
    volatile Uint32 SDRAM_TIM_1;
    volatile Uint32 SDRAM_TIM_2;
    volatile Uint32 SDRAM_TIM_3;
    volatile Uint8  RSVD2[4];
    volatile Uint32 SDRAM_TIM_4;
    volatile Uint8  RSVD3[12];
    volatile Uint32 PWR_MGMT_CTRL;
    volatile Uint8  RSVD4[24];
    volatile Uint32 VBUSM_CONFIG;
    volatile Uint32 VBUSM_CFG_VAL_1;
    volatile Uint32 VBUSM_CFG_VAL_2;
    volatile Uint32 IODFT_TLGC;
    volatile Uint32 IODFT_CTRL_MISR_RSLT;
    volatile Uint32 IODFT_ADDR_MISR_RSLT;
    volatile Uint32 IODFT_DATA_MISR_RSLT_1;
    volatile Uint32 IODFT_DATA_MISR_RSLT_2;
    volatile Uint32 IODFT_DATA_MISR_RSLT_3;
    volatile Uint32 IODFT_DATA_MISR_RSLT_4;
    volatile Uint32 IODFT_DATA_MISR_RSLT_5;
    volatile Uint32 PERF_CNT_1;
    volatile Uint32 PERF_CNT_2;
    volatile Uint32 PERF_CNT_CFG;
    volatile Uint32 PERF_CNT_SEL;
    volatile Uint32 PERF_CNT_TIM;
    volatile Uint8  RSVD5[12];
    volatile Uint32 IRQ_EOI;
    volatile Uint32 IRQSTATUS_RAW_SYS;
    volatile Uint8  RSVD6[4];
    volatile Uint32 IRQSTATUS_SYS;
    volatile Uint8  RSVD7[4];
    volatile Uint32 IRQENABLE_SET_SYS;
    volatile Uint8  RSVD8[4];
    volatile Uint32 IRQENABLE_CLR_SYS;
    volatile Uint8  RSVD9[8];
    volatile Uint32 ZQ_CONFIG;
    volatile Uint8  RSVD10[4];
    volatile Uint32 VBUSM_ERR_LOG;
    volatile Uint8  RSVD11[44];
    volatile Uint32 PRI_COS_MAP;
    volatile Uint32 MSTID_COS_1_MAP;
    volatile Uint32 MSTID_COS_2_MAP;
    volatile Uint8  RSVD12[4];
    volatile Uint32 ECC_CTRL;
    volatile Uint32 ECC_ADDR_RNG_1;
    volatile Uint32 ECC_ADDR_RNG_2;
    volatile Uint8  RSVD13[4];
    volatile Uint32 RD_WR_EXEC_THRSH;
    volatile Uint8  RSVD14[12];
    volatile Uint32 ONE_BIT_ECC_ERR_CNT;
    volatile Uint32 ONE_BIT_ECC_ERR_THRSH;
    volatile Uint32 ONE_BIT_ECC_ERR_DIST_1;
    volatile Uint32 ONE_BIT_ECC_ERR_ADDR_LOG;
    volatile Uint32 TWO_BIT_ECC_ERR_ADDR_LOG;
    volatile Uint32 ONE_BIT_ECC_ERR_DIST_2;
    volatile Uint8  RSVD15[972];
} CSL_Emif4fvRegs;


/**************************************************************************
* Register Macros
**************************************************************************/
#define CSL_EMIF4FV_EMIF_MOD_ID_REV                             (0x0U)
#define CSL_EMIF4FV_STATUS                                      (0x4U)
#define CSL_EMIF4FV_SDRAM_CONFIG                                (0x8U)
#define CSL_EMIF4FV_SDRAM_REF_CTRL                              (0x10U)
#define CSL_EMIF4FV_SDRAM_TIM_1                                 (0x18U)
#define CSL_EMIF4FV_SDRAM_TIM_2                                 (0x1CU)
#define CSL_EMIF4FV_SDRAM_TIM_3                                 (0x20U)
#define CSL_EMIF4FV_SDRAM_TIM_4                                 (0x28U)
#define CSL_EMIF4FV_PWR_MGMT_CTRL                               (0x38U)
#define CSL_EMIF4FV_VBUSM_CONFIG                                (0x54U)
#define CSL_EMIF4FV_VBUSM_CFG_VAL_1                             (0x58U)
#define CSL_EMIF4FV_VBUSM_CFG_VAL_2                             (0x5CU)
#define CSL_EMIF4FV_IODFT_TLGC                                  (0x60U)
#define CSL_EMIF4FV_IODFT_CTRL_MISR_RSLT                        (0x64U)
#define CSL_EMIF4FV_IODFT_ADDR_MISR_RSLT                        (0x68U)
#define CSL_EMIF4FV_IODFT_DATA_MISR_RSLT_1                      (0x6CU)
#define CSL_EMIF4FV_IODFT_DATA_MISR_RSLT_2                      (0x70U)
#define CSL_EMIF4FV_IODFT_DATA_MISR_RSLT_3                      (0x74U)
#define CSL_EMIF4FV_IODFT_DATA_MISR_RSLT_4                      (0x78U)
#define CSL_EMIF4FV_IODFT_DATA_MISR_RSLT_5                      (0x7CU)
#define CSL_EMIF4FV_PERF_CNT_1                                  (0x80U)
#define CSL_EMIF4FV_PERF_CNT_2                                  (0x84U)
#define CSL_EMIF4FV_PERF_CNT_CFG                                (0x88U)
#define CSL_EMIF4FV_PERF_CNT_SEL                                (0x8CU)
#define CSL_EMIF4FV_PERF_CNT_TIM                                (0x90U)
#define CSL_EMIF4FV_IRQ_EOI                                     (0xA0U)
#define CSL_EMIF4FV_IRQSTATUS_RAW_SYS                           (0xA4U)
#define CSL_EMIF4FV_IRQSTATUS_SYS                               (0xACU)
#define CSL_EMIF4FV_IRQENABLE_SET_SYS                           (0xB4U)
#define CSL_EMIF4FV_IRQENABLE_CLR_SYS                           (0xBCU)
#define CSL_EMIF4FV_ZQ_CONFIG                                   (0xC8U)
#define CSL_EMIF4FV_VBUSM_ERR_LOG                               (0xD0U)
#define CSL_EMIF4FV_PRI_COS_MAP                                 (0x100U)
#define CSL_EMIF4FV_MSTID_COS_1_MAP                             (0x104U)
#define CSL_EMIF4FV_MSTID_COS_2_MAP                             (0x108U)
#define CSL_EMIF4FV_ECC_CTRL                                    (0x110U)
#define CSL_EMIF4FV_ECC_ADDR_RNG_1                              (0x114U)
#define CSL_EMIF4FV_ECC_ADDR_RNG_2                              (0x118U)
#define CSL_EMIF4FV_RD_WR_EXEC_THRSH                            (0x120U)
#define CSL_EMIF4FV_ONE_BIT_ECC_ERR_CNT                         (0x130U)
#define CSL_EMIF4FV_ONE_BIT_ECC_ERR_THRSH                       (0x134U)
#define CSL_EMIF4FV_ONE_BIT_ECC_ERR_DIST_1                      (0x138U)
#define CSL_EMIF4FV_ONE_BIT_ECC_ERR_ADDR_LOG                    (0x13CU)
#define CSL_EMIF4FV_TWO_BIT_ECC_ERR_ADDR_LOG                    (0x140U)
#define CSL_EMIF4FV_ONE_BIT_ECC_ERR_DIST_2                      (0x144U)


/**************************************************************************
* Field Definition Macros
**************************************************************************/

/* EMIF_MOD_ID_REV */

#define CSL_EMIF4FV_EMIF_MOD_ID_REV_REG_MINOR_REVISION_MASK     (0x0000003FU)
#define CSL_EMIF4FV_EMIF_MOD_ID_REV_REG_MINOR_REVISION_SHIFT    (0U)
#define CSL_EMIF4FV_EMIF_MOD_ID_REV_REG_MINOR_REVISION_RESETVAL  (0x00000002U)
#define CSL_EMIF4FV_EMIF_MOD_ID_REV_REG_MINOR_REVISION_MAX      (0x0000003fU)

#define CSL_EMIF4FV_EMIF_MOD_ID_REV_REG_MAJOR_REVISION_MASK     (0x00000700U)
#define CSL_EMIF4FV_EMIF_MOD_ID_REV_REG_MAJOR_REVISION_SHIFT    (8U)
#define CSL_EMIF4FV_EMIF_MOD_ID_REV_REG_MAJOR_REVISION_RESETVAL  (0x00000004U)
#define CSL_EMIF4FV_EMIF_MOD_ID_REV_REG_MAJOR_REVISION_MAX      (0x00000007U)

#define CSL_EMIF4FV_EMIF_MOD_ID_REV_REG_RTL_VERSION_MASK        (0x0000F800U)
#define CSL_EMIF4FV_EMIF_MOD_ID_REV_REG_RTL_VERSION_SHIFT       (11U)
#define CSL_EMIF4FV_EMIF_MOD_ID_REV_REG_RTL_VERSION_RESETVAL    (0x00000003U)
#define CSL_EMIF4FV_EMIF_MOD_ID_REV_REG_RTL_VERSION_MAX         (0x0000001fU)

#define CSL_EMIF4FV_EMIF_MOD_ID_REV_REG_MODULE_ID_MASK          (0x0FFF0000U)
#define CSL_EMIF4FV_EMIF_MOD_ID_REV_REG_MODULE_ID_SHIFT         (16U)
#define CSL_EMIF4FV_EMIF_MOD_ID_REV_REG_MODULE_ID_RESETVAL      (0x00000046U)
#define CSL_EMIF4FV_EMIF_MOD_ID_REV_REG_MODULE_ID_MAX           (0x00000fffU)

#define CSL_EMIF4FV_EMIF_MOD_ID_REV_REG_SCHEME_MASK             (0xC0000000U)
#define CSL_EMIF4FV_EMIF_MOD_ID_REV_REG_SCHEME_SHIFT            (30U)
#define CSL_EMIF4FV_EMIF_MOD_ID_REV_REG_SCHEME_RESETVAL         (0x00000001U)
#define CSL_EMIF4FV_EMIF_MOD_ID_REV_REG_SCHEME_MAX              (0x00000003U)

#define CSL_EMIF4FV_EMIF_MOD_ID_REV_RESETVAL                    (0x40461c02U)

/* STATUS */

#define CSL_EMIF4FV_STATUS_REG_PHY_DLL_READY_MASK               (0x00000004U)
#define CSL_EMIF4FV_STATUS_REG_PHY_DLL_READY_SHIFT              (2U)
#define CSL_EMIF4FV_STATUS_REG_PHY_DLL_READY_RESETVAL           (0x00000000U)
#define CSL_EMIF4FV_STATUS_REG_PHY_DLL_READY_MAX                (0x00000001U)

#define CSL_EMIF4FV_STATUS_REG_DEEP_PWRDN_MASK                  (0x01000000U)
#define CSL_EMIF4FV_STATUS_REG_DEEP_PWRDN_SHIFT                 (24U)
#define CSL_EMIF4FV_STATUS_REG_DEEP_PWRDN_RESETVAL              (0x00000000U)
#define CSL_EMIF4FV_STATUS_REG_DEEP_PWRDN_MAX                   (0x00000001U)

#define CSL_EMIF4FV_STATUS_REG_CLK_STOP_MASK                    (0x02000000U)
#define CSL_EMIF4FV_STATUS_REG_CLK_STOP_SHIFT                   (25U)
#define CSL_EMIF4FV_STATUS_REG_CLK_STOP_RESETVAL                (0x00000000U)
#define CSL_EMIF4FV_STATUS_REG_CLK_STOP_MAX                     (0x00000001U)

#define CSL_EMIF4FV_STATUS_REG_PWRDN_MASK                       (0x04000000U)
#define CSL_EMIF4FV_STATUS_REG_PWRDN_SHIFT                      (26U)
#define CSL_EMIF4FV_STATUS_REG_PWRDN_RESETVAL                   (0x00000000U)
#define CSL_EMIF4FV_STATUS_REG_PWRDN_MAX                        (0x00000001U)

#define CSL_EMIF4FV_STATUS_REG_SELF_REF_MASK                    (0x08000000U)
#define CSL_EMIF4FV_STATUS_REG_SELF_REF_SHIFT                   (27U)
#define CSL_EMIF4FV_STATUS_REG_SELF_REF_RESETVAL                (0x00000000U)
#define CSL_EMIF4FV_STATUS_REG_SELF_REF_MAX                     (0x00000001U)

#define CSL_EMIF4FV_STATUS_REG_OBF_STAT_MASK                    (0x10000000U)
#define CSL_EMIF4FV_STATUS_REG_OBF_STAT_SHIFT                   (28U)
#define CSL_EMIF4FV_STATUS_REG_OBF_STAT_RESETVAL                (0x00000000U)
#define CSL_EMIF4FV_STATUS_REG_OBF_STAT_MAX                     (0x00000001U)

#define CSL_EMIF4FV_STATUS_REG_DUAL_CLK_MODE_MASK               (0x40000000U)
#define CSL_EMIF4FV_STATUS_REG_DUAL_CLK_MODE_SHIFT              (30U)
#define CSL_EMIF4FV_STATUS_REG_DUAL_CLK_MODE_RESETVAL           (0x00000000U)
#define CSL_EMIF4FV_STATUS_REG_DUAL_CLK_MODE_MAX                (0x00000001U)

#define CSL_EMIF4FV_STATUS_REG_BE_MASK                          (0x80000000U)
#define CSL_EMIF4FV_STATUS_REG_BE_SHIFT                         (31U)
#define CSL_EMIF4FV_STATUS_REG_BE_RESETVAL                      (0x00000000U)
#define CSL_EMIF4FV_STATUS_REG_BE_MAX                           (0x00000001U)

#define CSL_EMIF4FV_STATUS_RESETVAL                             (0x00000000U)

/* SDRAM_CONFIG */

#define CSL_EMIF4FV_SDRAM_CONFIG_REG_PAGESIZE_MASK              (0x00000003U)
#define CSL_EMIF4FV_SDRAM_CONFIG_REG_PAGESIZE_SHIFT             (0U)
#define CSL_EMIF4FV_SDRAM_CONFIG_REG_PAGESIZE_RESETVAL          (0x00000000U)
#define CSL_EMIF4FV_SDRAM_CONFIG_REG_PAGESIZE_MAX               (0x00000003U)

#define CSL_EMIF4FV_SDRAM_CONFIG_REG_EBANK_MASK                 (0x00000008U)
#define CSL_EMIF4FV_SDRAM_CONFIG_REG_EBANK_SHIFT                (3U)
#define CSL_EMIF4FV_SDRAM_CONFIG_REG_EBANK_RESETVAL             (0x00000000U)
#define CSL_EMIF4FV_SDRAM_CONFIG_REG_EBANK_MAX                  (0x00000001U)

#define CSL_EMIF4FV_SDRAM_CONFIG_REG_IBANK_MASK                 (0x00000060U)
#define CSL_EMIF4FV_SDRAM_CONFIG_REG_IBANK_SHIFT                (5U)
#define CSL_EMIF4FV_SDRAM_CONFIG_REG_IBANK_RESETVAL             (0x00000000U)
#define CSL_EMIF4FV_SDRAM_CONFIG_REG_IBANK_MAX                  (0x00000003U)

#define CSL_EMIF4FV_SDRAM_CONFIG_REG_CL_MASK                    (0x00000F00U)
#define CSL_EMIF4FV_SDRAM_CONFIG_REG_CL_SHIFT                   (8U)
#define CSL_EMIF4FV_SDRAM_CONFIG_REG_CL_RESETVAL                (0x00000002U)
#define CSL_EMIF4FV_SDRAM_CONFIG_REG_CL_MAX                     (0x0000000fU)

#define CSL_EMIF4FV_SDRAM_CONFIG_REG_NARROW_MODE_MASK           (0x00003000U)
#define CSL_EMIF4FV_SDRAM_CONFIG_REG_NARROW_MODE_SHIFT          (12U)
#define CSL_EMIF4FV_SDRAM_CONFIG_REG_NARROW_MODE_RESETVAL       (0x00000000U)
#define CSL_EMIF4FV_SDRAM_CONFIG_REG_NARROW_MODE_MAX            (0x00000003U)

#define CSL_EMIF4FV_SDRAM_CONFIG_REG_CWL_MASK                   (0x0001C000U)
#define CSL_EMIF4FV_SDRAM_CONFIG_REG_CWL_SHIFT                  (14U)
#define CSL_EMIF4FV_SDRAM_CONFIG_REG_CWL_RESETVAL               (0x00000000U)
#define CSL_EMIF4FV_SDRAM_CONFIG_REG_CWL_MAX                    (0x00000007U)

#define CSL_EMIF4FV_SDRAM_CONFIG_REG_DYN_ODT_MASK               (0x00C00000U)
#define CSL_EMIF4FV_SDRAM_CONFIG_REG_DYN_ODT_SHIFT              (22U)
#define CSL_EMIF4FV_SDRAM_CONFIG_REG_DYN_ODT_RESETVAL           (0x00000000U)
#define CSL_EMIF4FV_SDRAM_CONFIG_REG_DYN_ODT_MAX                (0x00000003U)

#define CSL_EMIF4FV_SDRAM_CONFIG_REG_DDR2_DDQS_MASK             (0x01000000U)
#define CSL_EMIF4FV_SDRAM_CONFIG_REG_DDR2_DDQS_SHIFT            (24U)
#define CSL_EMIF4FV_SDRAM_CONFIG_REG_DDR2_DDQS_RESETVAL         (0x00000000U)
#define CSL_EMIF4FV_SDRAM_CONFIG_REG_DDR2_DDQS_MAX              (0x00000001U)

#define CSL_EMIF4FV_SDRAM_CONFIG_REG_DDR_TERM_MASK              (0x0E000000U)
#define CSL_EMIF4FV_SDRAM_CONFIG_REG_DDR_TERM_SHIFT             (25U)
#define CSL_EMIF4FV_SDRAM_CONFIG_REG_DDR_TERM_RESETVAL          (0x00000000U)
#define CSL_EMIF4FV_SDRAM_CONFIG_REG_DDR_TERM_MAX               (0x00000007U)

#define CSL_EMIF4FV_SDRAM_CONFIG_REG_SDRAM_TYPE_MASK            (0xE0000000U)
#define CSL_EMIF4FV_SDRAM_CONFIG_REG_SDRAM_TYPE_SHIFT           (29U)
#define CSL_EMIF4FV_SDRAM_CONFIG_REG_SDRAM_TYPE_RESETVAL        (0x00000000U)
#define CSL_EMIF4FV_SDRAM_CONFIG_REG_SDRAM_TYPE_MAX             (0x00000007U)

#define CSL_EMIF4FV_SDRAM_CONFIG_RESETVAL                       (0x00000200U)

/* SDRAM_REF_CTRL */

#define CSL_EMIF4FV_SDRAM_REF_CTRL_REG_REFRESH_RATE_MASK        (0x0000FFFFU)
#define CSL_EMIF4FV_SDRAM_REF_CTRL_REG_REFRESH_RATE_SHIFT       (0U)
#define CSL_EMIF4FV_SDRAM_REF_CTRL_REG_REFRESH_RATE_RESETVAL    (0x00000000U)
#define CSL_EMIF4FV_SDRAM_REF_CTRL_REG_REFRESH_RATE_MAX         (0x0000ffffU)

#define CSL_EMIF4FV_SDRAM_REF_CTRL_REG_INITREF_DIS_MASK         (0x80000000U)
#define CSL_EMIF4FV_SDRAM_REF_CTRL_REG_INITREF_DIS_SHIFT        (31U)
#define CSL_EMIF4FV_SDRAM_REF_CTRL_REG_INITREF_DIS_RESETVAL     (0x00000001U)
#define CSL_EMIF4FV_SDRAM_REF_CTRL_REG_INITREF_DIS_MAX          (0x00000001U)

#define CSL_EMIF4FV_SDRAM_REF_CTRL_RESETVAL                     (0x80000000U)

/* SDRAM_TIM_1 */

#define CSL_EMIF4FV_SDRAM_TIM_1_REG_T_WTR_MASK                  (0x0000000FU)
#define CSL_EMIF4FV_SDRAM_TIM_1_REG_T_WTR_SHIFT                 (0U)
#define CSL_EMIF4FV_SDRAM_TIM_1_REG_T_WTR_RESETVAL              (0x0000000fU)
#define CSL_EMIF4FV_SDRAM_TIM_1_REG_T_WTR_MAX                   (0x0000000fU)

#define CSL_EMIF4FV_SDRAM_TIM_1_REG_T_RRD_MASK                  (0x000003F0U)
#define CSL_EMIF4FV_SDRAM_TIM_1_REG_T_RRD_SHIFT                 (4U)
#define CSL_EMIF4FV_SDRAM_TIM_1_REG_T_RRD_RESETVAL              (0x0000003fU)
#define CSL_EMIF4FV_SDRAM_TIM_1_REG_T_RRD_MAX                   (0x0000003fU)

#define CSL_EMIF4FV_SDRAM_TIM_1_REG_T_RC_MASK                   (0x0003FC00U)
#define CSL_EMIF4FV_SDRAM_TIM_1_REG_T_RC_SHIFT                  (10U)
#define CSL_EMIF4FV_SDRAM_TIM_1_REG_T_RC_RESETVAL               (0x000000ffU)
#define CSL_EMIF4FV_SDRAM_TIM_1_REG_T_RC_MAX                    (0x000000ffU)

#define CSL_EMIF4FV_SDRAM_TIM_1_REG_T_RAS_MASK                  (0x01FC0000U)
#define CSL_EMIF4FV_SDRAM_TIM_1_REG_T_RAS_SHIFT                 (18U)
#define CSL_EMIF4FV_SDRAM_TIM_1_REG_T_RAS_RESETVAL              (0x0000007fU)
#define CSL_EMIF4FV_SDRAM_TIM_1_REG_T_RAS_MAX                   (0x0000007fU)

#define CSL_EMIF4FV_SDRAM_TIM_1_REG_T_WR_MASK                   (0x3E000000U)
#define CSL_EMIF4FV_SDRAM_TIM_1_REG_T_WR_SHIFT                  (25U)
#define CSL_EMIF4FV_SDRAM_TIM_1_REG_T_WR_RESETVAL               (0x0000001fU)
#define CSL_EMIF4FV_SDRAM_TIM_1_REG_T_WR_MAX                    (0x0000001fU)

#define CSL_EMIF4FV_SDRAM_TIM_1_RESETVAL                        (0x3fffffffU)

/* SDRAM_TIM_2 */

#define CSL_EMIF4FV_SDRAM_TIM_2_REG_T_RCD_MASK                  (0x0000001FU)
#define CSL_EMIF4FV_SDRAM_TIM_2_REG_T_RCD_SHIFT                 (0U)
#define CSL_EMIF4FV_SDRAM_TIM_2_REG_T_RCD_RESETVAL              (0x0000001fU)
#define CSL_EMIF4FV_SDRAM_TIM_2_REG_T_RCD_MAX                   (0x0000001fU)

#define CSL_EMIF4FV_SDRAM_TIM_2_REG_T_RP_MASK                   (0x000003E0U)
#define CSL_EMIF4FV_SDRAM_TIM_2_REG_T_RP_SHIFT                  (5U)
#define CSL_EMIF4FV_SDRAM_TIM_2_REG_T_RP_RESETVAL               (0x0000001fU)
#define CSL_EMIF4FV_SDRAM_TIM_2_REG_T_RP_MAX                    (0x0000001fU)

#define CSL_EMIF4FV_SDRAM_TIM_2_REG_T_RTW_MASK                  (0x00001C00U)
#define CSL_EMIF4FV_SDRAM_TIM_2_REG_T_RTW_SHIFT                 (10U)
#define CSL_EMIF4FV_SDRAM_TIM_2_REG_T_RTW_RESETVAL              (0x00000007U)
#define CSL_EMIF4FV_SDRAM_TIM_2_REG_T_RTW_MAX                   (0x00000007U)

#define CSL_EMIF4FV_SDRAM_TIM_2_RESETVAL                        (0x00001fffU)

/* SDRAM_TIM_3 */

#define CSL_EMIF4FV_SDRAM_TIM_3_REG_T_CKE_MASK                  (0x0000000FU)
#define CSL_EMIF4FV_SDRAM_TIM_3_REG_T_CKE_SHIFT                 (0U)
#define CSL_EMIF4FV_SDRAM_TIM_3_REG_T_CKE_RESETVAL              (0x0000000fU)
#define CSL_EMIF4FV_SDRAM_TIM_3_REG_T_CKE_MAX                   (0x0000000fU)

#define CSL_EMIF4FV_SDRAM_TIM_3_REG_T_RTP_MASK                  (0x000000F0U)
#define CSL_EMIF4FV_SDRAM_TIM_3_REG_T_RTP_SHIFT                 (4U)
#define CSL_EMIF4FV_SDRAM_TIM_3_REG_T_RTP_RESETVAL              (0x0000000fU)
#define CSL_EMIF4FV_SDRAM_TIM_3_REG_T_RTP_MAX                   (0x0000000fU)

#define CSL_EMIF4FV_SDRAM_TIM_3_REG_T_XSRD_MASK                 (0x0003FF00U)
#define CSL_EMIF4FV_SDRAM_TIM_3_REG_T_XSRD_SHIFT                (8U)
#define CSL_EMIF4FV_SDRAM_TIM_3_REG_T_XSRD_RESETVAL             (0x000003ffU)
#define CSL_EMIF4FV_SDRAM_TIM_3_REG_T_XSRD_MAX                  (0x000003ffU)

#define CSL_EMIF4FV_SDRAM_TIM_3_REG_T_XSNR_MASK                 (0x0FFC0000U)
#define CSL_EMIF4FV_SDRAM_TIM_3_REG_T_XSNR_SHIFT                (18U)
#define CSL_EMIF4FV_SDRAM_TIM_3_REG_T_XSNR_RESETVAL             (0x000003ffU)
#define CSL_EMIF4FV_SDRAM_TIM_3_REG_T_XSNR_MAX                  (0x000003ffU)

#define CSL_EMIF4FV_SDRAM_TIM_3_REG_T_XP_MASK                   (0xF0000000U)
#define CSL_EMIF4FV_SDRAM_TIM_3_REG_T_XP_SHIFT                  (28U)
#define CSL_EMIF4FV_SDRAM_TIM_3_REG_T_XP_RESETVAL               (0x0000000fU)
#define CSL_EMIF4FV_SDRAM_TIM_3_REG_T_XP_MAX                    (0x0000000fU)

#define CSL_EMIF4FV_SDRAM_TIM_3_RESETVAL                        (0xffffffffU)

/* SDRAM_TIM_4 */

#define CSL_EMIF4FV_SDRAM_TIM_4_REG_T_RAS_MAX_MASK              (0x0000000FU)
#define CSL_EMIF4FV_SDRAM_TIM_4_REG_T_RAS_MAX_SHIFT             (0U)
#define CSL_EMIF4FV_SDRAM_TIM_4_REG_T_RAS_MAX_RESETVAL          (0x0000000fU)
#define CSL_EMIF4FV_SDRAM_TIM_4_REG_T_RAS_MAX_MAX               (0x0000000fU)

#define CSL_EMIF4FV_SDRAM_TIM_4_REG_T_RFC_MASK                  (0x00003FF0U)
#define CSL_EMIF4FV_SDRAM_TIM_4_REG_T_RFC_SHIFT                 (4U)
#define CSL_EMIF4FV_SDRAM_TIM_4_REG_T_RFC_RESETVAL              (0x000003ffU)
#define CSL_EMIF4FV_SDRAM_TIM_4_REG_T_RFC_MAX                   (0x000003ffU)

#define CSL_EMIF4FV_SDRAM_TIM_4_REG_ZQ_ZQCS_MASK                (0x00FF0000U)
#define CSL_EMIF4FV_SDRAM_TIM_4_REG_ZQ_ZQCS_SHIFT               (16U)
#define CSL_EMIF4FV_SDRAM_TIM_4_REG_ZQ_ZQCS_RESETVAL            (0x000000ffU)
#define CSL_EMIF4FV_SDRAM_TIM_4_REG_ZQ_ZQCS_MAX                 (0x000000ffU)

#define CSL_EMIF4FV_SDRAM_TIM_4_REG_T_CKESR_MASK                (0x0F000000U)
#define CSL_EMIF4FV_SDRAM_TIM_4_REG_T_CKESR_SHIFT               (24U)
#define CSL_EMIF4FV_SDRAM_TIM_4_REG_T_CKESR_RESETVAL            (0x0000000fU)
#define CSL_EMIF4FV_SDRAM_TIM_4_REG_T_CKESR_MAX                 (0x0000000fU)

#define CSL_EMIF4FV_SDRAM_TIM_4_REG_T_CSTA_MASK                 (0xF0000000U)
#define CSL_EMIF4FV_SDRAM_TIM_4_REG_T_CSTA_SHIFT                (28U)
#define CSL_EMIF4FV_SDRAM_TIM_4_REG_T_CSTA_RESETVAL             (0x0000000fU)
#define CSL_EMIF4FV_SDRAM_TIM_4_REG_T_CSTA_MAX                  (0x0000000fU)

#define CSL_EMIF4FV_SDRAM_TIM_4_RESETVAL                        (0xffff3fffU)

/* PWR_MGMT_CTRL */

#define CSL_EMIF4FV_PWR_MGMT_CTRL_REG_CS_TIM_MASK               (0x0000000FU)
#define CSL_EMIF4FV_PWR_MGMT_CTRL_REG_CS_TIM_SHIFT              (0U)
#define CSL_EMIF4FV_PWR_MGMT_CTRL_REG_CS_TIM_RESETVAL           (0x00000000U)
#define CSL_EMIF4FV_PWR_MGMT_CTRL_REG_CS_TIM_MAX                (0x0000000fU)

#define CSL_EMIF4FV_PWR_MGMT_CTRL_REG_SR_TIM_MASK               (0x000000F0U)
#define CSL_EMIF4FV_PWR_MGMT_CTRL_REG_SR_TIM_SHIFT              (4U)
#define CSL_EMIF4FV_PWR_MGMT_CTRL_REG_SR_TIM_RESETVAL           (0x00000000U)
#define CSL_EMIF4FV_PWR_MGMT_CTRL_REG_SR_TIM_MAX                (0x0000000fU)

#define CSL_EMIF4FV_PWR_MGMT_CTRL_REG_LP_MODE_MASK              (0x00000700U)
#define CSL_EMIF4FV_PWR_MGMT_CTRL_REG_LP_MODE_SHIFT             (8U)
#define CSL_EMIF4FV_PWR_MGMT_CTRL_REG_LP_MODE_RESETVAL          (0x00000000U)
#define CSL_EMIF4FV_PWR_MGMT_CTRL_REG_LP_MODE_MAX               (0x00000007U)

#define CSL_EMIF4FV_PWR_MGMT_CTRL_REG_DPD_EN_MASK               (0x00000800U)
#define CSL_EMIF4FV_PWR_MGMT_CTRL_REG_DPD_EN_SHIFT              (11U)
#define CSL_EMIF4FV_PWR_MGMT_CTRL_REG_DPD_EN_RESETVAL           (0x00000000U)
#define CSL_EMIF4FV_PWR_MGMT_CTRL_REG_DPD_EN_MAX                (0x00000001U)

#define CSL_EMIF4FV_PWR_MGMT_CTRL_REG_PD_TIM_MASK               (0x0000F000U)
#define CSL_EMIF4FV_PWR_MGMT_CTRL_REG_PD_TIM_SHIFT              (12U)
#define CSL_EMIF4FV_PWR_MGMT_CTRL_REG_PD_TIM_RESETVAL           (0x00000000U)
#define CSL_EMIF4FV_PWR_MGMT_CTRL_REG_PD_TIM_MAX                (0x0000000fU)

#define CSL_EMIF4FV_PWR_MGMT_CTRL_RESETVAL                      (0x00000000U)

/* VBUSM_CONFIG */

#define CSL_EMIF4FV_VBUSM_CONFIG_REG_PR_OLD_COUNT_MASK          (0x000000FFU)
#define CSL_EMIF4FV_VBUSM_CONFIG_REG_PR_OLD_COUNT_SHIFT         (0U)
#define CSL_EMIF4FV_VBUSM_CONFIG_REG_PR_OLD_COUNT_RESETVAL      (0x000000ffU)
#define CSL_EMIF4FV_VBUSM_CONFIG_REG_PR_OLD_COUNT_MAX           (0x000000ffU)

#define CSL_EMIF4FV_VBUSM_CONFIG_REG_COS_COUNT_2_MASK           (0x0000FF00U)
#define CSL_EMIF4FV_VBUSM_CONFIG_REG_COS_COUNT_2_SHIFT          (8U)
#define CSL_EMIF4FV_VBUSM_CONFIG_REG_COS_COUNT_2_RESETVAL       (0x000000ffU)
#define CSL_EMIF4FV_VBUSM_CONFIG_REG_COS_COUNT_2_MAX            (0x000000ffU)

#define CSL_EMIF4FV_VBUSM_CONFIG_REG_COS_COUNT_1_MASK           (0x00FF0000U)
#define CSL_EMIF4FV_VBUSM_CONFIG_REG_COS_COUNT_1_SHIFT          (16U)
#define CSL_EMIF4FV_VBUSM_CONFIG_REG_COS_COUNT_1_RESETVAL       (0x000000ffU)
#define CSL_EMIF4FV_VBUSM_CONFIG_REG_COS_COUNT_1_MAX            (0x000000ffU)

#define CSL_EMIF4FV_VBUSM_CONFIG_RESETVAL                       (0x00ffffffU)

/* VBUSM_CFG_VAL_1 */

#define CSL_EMIF4FV_VBUSM_CFG_VAL_1_REG_CMD_FIFO_DEPTH_MASK     (0x000000FFU)
#define CSL_EMIF4FV_VBUSM_CFG_VAL_1_REG_CMD_FIFO_DEPTH_SHIFT    (0U)
#define CSL_EMIF4FV_VBUSM_CFG_VAL_1_REG_CMD_FIFO_DEPTH_RESETVAL  (0x00000010U)
#define CSL_EMIF4FV_VBUSM_CFG_VAL_1_REG_CMD_FIFO_DEPTH_MAX      (0x000000ffU)

#define CSL_EMIF4FV_VBUSM_CFG_VAL_1_REG_WR_FIFO_DEPTH_MASK      (0x0000FF00U)
#define CSL_EMIF4FV_VBUSM_CFG_VAL_1_REG_WR_FIFO_DEPTH_SHIFT     (8U)
#define CSL_EMIF4FV_VBUSM_CFG_VAL_1_REG_WR_FIFO_DEPTH_RESETVAL  (0x00000014U)
#define CSL_EMIF4FV_VBUSM_CFG_VAL_1_REG_WR_FIFO_DEPTH_MAX       (0x000000ffU)

#define CSL_EMIF4FV_VBUSM_CFG_VAL_1_REG_STAT_FIFO_DEPTH_MASK    (0x00FF0000U)
#define CSL_EMIF4FV_VBUSM_CFG_VAL_1_REG_STAT_FIFO_DEPTH_SHIFT   (16U)
#define CSL_EMIF4FV_VBUSM_CFG_VAL_1_REG_STAT_FIFO_DEPTH_RESETVAL  (0x00000007U)
#define CSL_EMIF4FV_VBUSM_CFG_VAL_1_REG_STAT_FIFO_DEPTH_MAX     (0x000000ffU)

#define CSL_EMIF4FV_VBUSM_CFG_VAL_1_REG_SYS_BUS_WIDTH_MASK      (0xC0000000U)
#define CSL_EMIF4FV_VBUSM_CFG_VAL_1_REG_SYS_BUS_WIDTH_SHIFT     (30U)
#define CSL_EMIF4FV_VBUSM_CFG_VAL_1_REG_SYS_BUS_WIDTH_RESETVAL  (0x00000003U)
#define CSL_EMIF4FV_VBUSM_CFG_VAL_1_REG_SYS_BUS_WIDTH_MAX       (0x00000003U)

#define CSL_EMIF4FV_VBUSM_CFG_VAL_1_RESETVAL                    (0xc0071410U)

/* VBUSM_CFG_VAL_2 */

#define CSL_EMIF4FV_VBUSM_CFG_VAL_2_REG_RCMD_FIFO_DEPTH_MASK    (0x000000FFU)
#define CSL_EMIF4FV_VBUSM_CFG_VAL_2_REG_RCMD_FIFO_DEPTH_SHIFT   (0U)
#define CSL_EMIF4FV_VBUSM_CFG_VAL_2_REG_RCMD_FIFO_DEPTH_RESETVAL  (0x0000001cU)
#define CSL_EMIF4FV_VBUSM_CFG_VAL_2_REG_RCMD_FIFO_DEPTH_MAX     (0x000000ffU)

#define CSL_EMIF4FV_VBUSM_CFG_VAL_2_REG_RSD_FIFO_DEPTH_MASK     (0x0000FF00U)
#define CSL_EMIF4FV_VBUSM_CFG_VAL_2_REG_RSD_FIFO_DEPTH_SHIFT    (8U)
#define CSL_EMIF4FV_VBUSM_CFG_VAL_2_REG_RSD_FIFO_DEPTH_RESETVAL  (0x0000001cU)
#define CSL_EMIF4FV_VBUSM_CFG_VAL_2_REG_RSD_FIFO_DEPTH_MAX      (0x000000ffU)

#define CSL_EMIF4FV_VBUSM_CFG_VAL_2_REG_RREG_FIFO_DEPTH_MASK    (0x00FF0000U)
#define CSL_EMIF4FV_VBUSM_CFG_VAL_2_REG_RREG_FIFO_DEPTH_SHIFT   (16U)
#define CSL_EMIF4FV_VBUSM_CFG_VAL_2_REG_RREG_FIFO_DEPTH_RESETVAL  (0x00000002U)
#define CSL_EMIF4FV_VBUSM_CFG_VAL_2_REG_RREG_FIFO_DEPTH_MAX     (0x000000ffU)

#define CSL_EMIF4FV_VBUSM_CFG_VAL_2_RESETVAL                    (0x00021c1cU)

/* IODFT_TLGC */

#define CSL_EMIF4FV_IODFT_TLGC_REG_PC_MASK                      (0x0000000EU)
#define CSL_EMIF4FV_IODFT_TLGC_REG_PC_SHIFT                     (1U)
#define CSL_EMIF4FV_IODFT_TLGC_REG_PC_RESETVAL                  (0x00000000U)
#define CSL_EMIF4FV_IODFT_TLGC_REG_PC_MAX                       (0x00000007U)

#define CSL_EMIF4FV_IODFT_TLGC_REG_MC_MASK                      (0x00000030U)
#define CSL_EMIF4FV_IODFT_TLGC_REG_MC_SHIFT                     (4U)
#define CSL_EMIF4FV_IODFT_TLGC_REG_MC_RESETVAL                  (0x00000001U)
#define CSL_EMIF4FV_IODFT_TLGC_REG_MC_MAX                       (0x00000003U)

#define CSL_EMIF4FV_IODFT_TLGC_REG_MMS_MASK                     (0x00000100U)
#define CSL_EMIF4FV_IODFT_TLGC_REG_MMS_SHIFT                    (8U)
#define CSL_EMIF4FV_IODFT_TLGC_REG_MMS_RESETVAL                 (0x00000000U)
#define CSL_EMIF4FV_IODFT_TLGC_REG_MMS_MAX                      (0x00000001U)

#define CSL_EMIF4FV_IODFT_TLGC_REG_OPG_LD_MASK                  (0x00001000U)
#define CSL_EMIF4FV_IODFT_TLGC_REG_OPG_LD_SHIFT                 (12U)
#define CSL_EMIF4FV_IODFT_TLGC_REG_OPG_LD_RESETVAL              (0x00000000U)
#define CSL_EMIF4FV_IODFT_TLGC_REG_OPG_LD_MAX                   (0x00000001U)

#define CSL_EMIF4FV_IODFT_TLGC_REG_ACT_CAP_EN_MASK              (0x00002000U)
#define CSL_EMIF4FV_IODFT_TLGC_REG_ACT_CAP_EN_SHIFT             (13U)
#define CSL_EMIF4FV_IODFT_TLGC_REG_ACT_CAP_EN_RESETVAL          (0x00000001U)
#define CSL_EMIF4FV_IODFT_TLGC_REG_ACT_CAP_EN_MAX               (0x00000001U)

#define CSL_EMIF4FV_IODFT_TLGC_REG_MT_MASK                      (0x00004000U)
#define CSL_EMIF4FV_IODFT_TLGC_REG_MT_SHIFT                     (14U)
#define CSL_EMIF4FV_IODFT_TLGC_REG_MT_RESETVAL                  (0x00000000U)
#define CSL_EMIF4FV_IODFT_TLGC_REG_MT_MAX                       (0x00000001U)

#define CSL_EMIF4FV_IODFT_TLGC_REG_TLEC_MASK                    (0xFFFF0000U)
#define CSL_EMIF4FV_IODFT_TLGC_REG_TLEC_SHIFT                   (16U)
#define CSL_EMIF4FV_IODFT_TLGC_REG_TLEC_RESETVAL                (0x00000000U)
#define CSL_EMIF4FV_IODFT_TLGC_REG_TLEC_MAX                     (0x0000ffffU)

#define CSL_EMIF4FV_IODFT_TLGC_RESETVAL                         (0x00002010U)

/* IODFT_CTRL_MISR_RSLT */

#define CSL_EMIF4FV_IODFT_CTRL_MISR_RSLT_REG_CTL_TLMR_MASK      (0x000007FFU)
#define CSL_EMIF4FV_IODFT_CTRL_MISR_RSLT_REG_CTL_TLMR_SHIFT     (0U)
#define CSL_EMIF4FV_IODFT_CTRL_MISR_RSLT_REG_CTL_TLMR_RESETVAL  (0x00000000U)
#define CSL_EMIF4FV_IODFT_CTRL_MISR_RSLT_REG_CTL_TLMR_MAX       (0x000007ffU)

#define CSL_EMIF4FV_IODFT_CTRL_MISR_RSLT_REG_DQM_TLMR_MASK      (0xFFFFF000U)
#define CSL_EMIF4FV_IODFT_CTRL_MISR_RSLT_REG_DQM_TLMR_SHIFT     (12U)
#define CSL_EMIF4FV_IODFT_CTRL_MISR_RSLT_REG_DQM_TLMR_RESETVAL  (0x00000000U)
#define CSL_EMIF4FV_IODFT_CTRL_MISR_RSLT_REG_DQM_TLMR_MAX       (0x000fffffU)

#define CSL_EMIF4FV_IODFT_CTRL_MISR_RSLT_RESETVAL               (0x00000000U)

/* IODFT_ADDR_MISR_RSLT */

#define CSL_EMIF4FV_IODFT_ADDR_MISR_RSLT_REG_ADDR_TLMR_MASK     (0x001FFFFFU)
#define CSL_EMIF4FV_IODFT_ADDR_MISR_RSLT_REG_ADDR_TLMR_SHIFT    (0U)
#define CSL_EMIF4FV_IODFT_ADDR_MISR_RSLT_REG_ADDR_TLMR_RESETVAL  (0x00000000U)
#define CSL_EMIF4FV_IODFT_ADDR_MISR_RSLT_REG_ADDR_TLMR_MAX      (0x001fffffU)

#define CSL_EMIF4FV_IODFT_ADDR_MISR_RSLT_RESETVAL               (0x00000000U)

/* IODFT_DATA_MISR_RSLT_1 */

#define CSL_EMIF4FV_IODFT_DATA_MISR_RSLT_1_REG_DATA_TLMR_31_0_MASK  (0xFFFFFFFFU)
#define CSL_EMIF4FV_IODFT_DATA_MISR_RSLT_1_REG_DATA_TLMR_31_0_SHIFT  (0U)
#define CSL_EMIF4FV_IODFT_DATA_MISR_RSLT_1_REG_DATA_TLMR_31_0_RESETVAL  (0x00000000U)
#define CSL_EMIF4FV_IODFT_DATA_MISR_RSLT_1_REG_DATA_TLMR_31_0_MAX  (0xffffffffU)

#define CSL_EMIF4FV_IODFT_DATA_MISR_RSLT_1_RESETVAL             (0x00000000U)

/* IODFT_DATA_MISR_RSLT_2 */

#define CSL_EMIF4FV_IODFT_DATA_MISR_RSLT_2_REG_DATA_TLMR_63_32__MASK  (0xFFFFFFFFU)
#define CSL_EMIF4FV_IODFT_DATA_MISR_RSLT_2_REG_DATA_TLMR_63_32__SHIFT  (0U)
#define CSL_EMIF4FV_IODFT_DATA_MISR_RSLT_2_REG_DATA_TLMR_63_32__RESETVAL  (0x00000000U)
#define CSL_EMIF4FV_IODFT_DATA_MISR_RSLT_2_REG_DATA_TLMR_63_32__MAX  (0xffffffffU)

#define CSL_EMIF4FV_IODFT_DATA_MISR_RSLT_2_RESETVAL             (0x00000000U)

/* IODFT_DATA_MISR_RSLT_3 */

#define CSL_EMIF4FV_IODFT_DATA_MISR_RSLT_3_REG_DATA_TLMR_95_64_MASK  (0xFFFFFFFFU)
#define CSL_EMIF4FV_IODFT_DATA_MISR_RSLT_3_REG_DATA_TLMR_95_64_SHIFT  (0U)
#define CSL_EMIF4FV_IODFT_DATA_MISR_RSLT_3_REG_DATA_TLMR_95_64_RESETVAL  (0x00000000U)
#define CSL_EMIF4FV_IODFT_DATA_MISR_RSLT_3_REG_DATA_TLMR_95_64_MAX  (0xffffffffU)

#define CSL_EMIF4FV_IODFT_DATA_MISR_RSLT_3_RESETVAL             (0x00000000U)

/* IODFT_DATA_MISR_RSLT_4 */

#define CSL_EMIF4FV_IODFT_DATA_MISR_RSLT_4_REG_DATA_TLMR_127_96_MASK  (0xFFFFFFFFU)
#define CSL_EMIF4FV_IODFT_DATA_MISR_RSLT_4_REG_DATA_TLMR_127_96_SHIFT  (0U)
#define CSL_EMIF4FV_IODFT_DATA_MISR_RSLT_4_REG_DATA_TLMR_127_96_RESETVAL  (0x00000000U)
#define CSL_EMIF4FV_IODFT_DATA_MISR_RSLT_4_REG_DATA_TLMR_127_96_MAX  (0xffffffffU)

#define CSL_EMIF4FV_IODFT_DATA_MISR_RSLT_4_RESETVAL             (0x00000000U)

/* IODFT_DATA_MISR_RSLT_5 */

#define CSL_EMIF4FV_IODFT_DATA_MISR_RSLT_5_REG_DATA_TLMR_146_128_MASK  (0x0007FFFFU)
#define CSL_EMIF4FV_IODFT_DATA_MISR_RSLT_5_REG_DATA_TLMR_146_128_SHIFT  (0U)
#define CSL_EMIF4FV_IODFT_DATA_MISR_RSLT_5_REG_DATA_TLMR_146_128_RESETVAL  (0x00000000U)
#define CSL_EMIF4FV_IODFT_DATA_MISR_RSLT_5_REG_DATA_TLMR_146_128_MAX  (0x0007ffffU)

#define CSL_EMIF4FV_IODFT_DATA_MISR_RSLT_5_RESETVAL             (0x00000000U)

/* PERF_CNT_1 */

#define CSL_EMIF4FV_PERF_CNT_1_REG_COUNTER1_MASK                (0xFFFFFFFFU)
#define CSL_EMIF4FV_PERF_CNT_1_REG_COUNTER1_SHIFT               (0U)
#define CSL_EMIF4FV_PERF_CNT_1_REG_COUNTER1_RESETVAL            (0x00000000U)
#define CSL_EMIF4FV_PERF_CNT_1_REG_COUNTER1_MAX                 (0xffffffffU)

#define CSL_EMIF4FV_PERF_CNT_1_RESETVAL                         (0x00000000U)

/* PERF_CNT_2 */

#define CSL_EMIF4FV_PERF_CNT_2_REG_COUNTER2_MASK                (0xFFFFFFFFU)
#define CSL_EMIF4FV_PERF_CNT_2_REG_COUNTER2_SHIFT               (0U)
#define CSL_EMIF4FV_PERF_CNT_2_REG_COUNTER2_RESETVAL            (0x00000000U)
#define CSL_EMIF4FV_PERF_CNT_2_REG_COUNTER2_MAX                 (0xffffffffU)

#define CSL_EMIF4FV_PERF_CNT_2_RESETVAL                         (0x00000000U)

/* PERF_CNT_CFG */

#define CSL_EMIF4FV_PERF_CNT_CFG_REG_CNTR1_CFG_MASK             (0x0000000FU)
#define CSL_EMIF4FV_PERF_CNT_CFG_REG_CNTR1_CFG_SHIFT            (0U)
#define CSL_EMIF4FV_PERF_CNT_CFG_REG_CNTR1_CFG_RESETVAL         (0x00000000U)
#define CSL_EMIF4FV_PERF_CNT_CFG_REG_CNTR1_CFG_MAX              (0x0000000fU)

#define CSL_EMIF4FV_PERF_CNT_CFG_REG_CNTR1_REGION_EN_MASK       (0x00004000U)
#define CSL_EMIF4FV_PERF_CNT_CFG_REG_CNTR1_REGION_EN_SHIFT      (14U)
#define CSL_EMIF4FV_PERF_CNT_CFG_REG_CNTR1_REGION_EN_RESETVAL   (0x00000000U)
#define CSL_EMIF4FV_PERF_CNT_CFG_REG_CNTR1_REGION_EN_MAX        (0x00000001U)

#define CSL_EMIF4FV_PERF_CNT_CFG_REG_CNTR1_MSTID_EN_MASK        (0x00008000U)
#define CSL_EMIF4FV_PERF_CNT_CFG_REG_CNTR1_MSTID_EN_SHIFT       (15U)
#define CSL_EMIF4FV_PERF_CNT_CFG_REG_CNTR1_MSTID_EN_RESETVAL    (0x00000000U)
#define CSL_EMIF4FV_PERF_CNT_CFG_REG_CNTR1_MSTID_EN_MAX         (0x00000001U)

#define CSL_EMIF4FV_PERF_CNT_CFG_REG_CNTR2_CFG_MASK             (0x000F0000U)
#define CSL_EMIF4FV_PERF_CNT_CFG_REG_CNTR2_CFG_SHIFT            (16U)
#define CSL_EMIF4FV_PERF_CNT_CFG_REG_CNTR2_CFG_RESETVAL         (0x00000001U)
#define CSL_EMIF4FV_PERF_CNT_CFG_REG_CNTR2_CFG_MAX              (0x0000000fU)

#define CSL_EMIF4FV_PERF_CNT_CFG_REG_CNTR2_REGION_EN_MASK       (0x40000000U)
#define CSL_EMIF4FV_PERF_CNT_CFG_REG_CNTR2_REGION_EN_SHIFT      (30U)
#define CSL_EMIF4FV_PERF_CNT_CFG_REG_CNTR2_REGION_EN_RESETVAL   (0x00000000U)
#define CSL_EMIF4FV_PERF_CNT_CFG_REG_CNTR2_REGION_EN_MAX        (0x00000001U)

#define CSL_EMIF4FV_PERF_CNT_CFG_REG_CNTR2_MSTID_EN_MASK        (0x80000000U)
#define CSL_EMIF4FV_PERF_CNT_CFG_REG_CNTR2_MSTID_EN_SHIFT       (31U)
#define CSL_EMIF4FV_PERF_CNT_CFG_REG_CNTR2_MSTID_EN_RESETVAL    (0x00000000U)
#define CSL_EMIF4FV_PERF_CNT_CFG_REG_CNTR2_MSTID_EN_MAX         (0x00000001U)

#define CSL_EMIF4FV_PERF_CNT_CFG_RESETVAL                       (0x00010000U)

/* PERF_CNT_SEL */

#define CSL_EMIF4FV_PERF_CNT_SEL_REG_REGION_SEL1_MASK           (0x0000000FU)
#define CSL_EMIF4FV_PERF_CNT_SEL_REG_REGION_SEL1_SHIFT          (0U)
#define CSL_EMIF4FV_PERF_CNT_SEL_REG_REGION_SEL1_RESETVAL       (0x00000000U)
#define CSL_EMIF4FV_PERF_CNT_SEL_REG_REGION_SEL1_MAX            (0x0000000fU)

#define CSL_EMIF4FV_PERF_CNT_SEL_REG_MSTID1_MASK                (0x0000FF00U)
#define CSL_EMIF4FV_PERF_CNT_SEL_REG_MSTID1_SHIFT               (8U)
#define CSL_EMIF4FV_PERF_CNT_SEL_REG_MSTID1_RESETVAL            (0x00000000U)
#define CSL_EMIF4FV_PERF_CNT_SEL_REG_MSTID1_MAX                 (0x000000ffU)

#define CSL_EMIF4FV_PERF_CNT_SEL_REG_REGION_SEL2_MASK           (0x000F0000U)
#define CSL_EMIF4FV_PERF_CNT_SEL_REG_REGION_SEL2_SHIFT          (16U)
#define CSL_EMIF4FV_PERF_CNT_SEL_REG_REGION_SEL2_RESETVAL       (0x00000000U)
#define CSL_EMIF4FV_PERF_CNT_SEL_REG_REGION_SEL2_MAX            (0x0000000fU)

#define CSL_EMIF4FV_PERF_CNT_SEL_REG_MSTID2_MASK                (0xFF000000U)
#define CSL_EMIF4FV_PERF_CNT_SEL_REG_MSTID2_SHIFT               (24U)
#define CSL_EMIF4FV_PERF_CNT_SEL_REG_MSTID2_RESETVAL            (0x00000000U)
#define CSL_EMIF4FV_PERF_CNT_SEL_REG_MSTID2_MAX                 (0x000000ffU)

#define CSL_EMIF4FV_PERF_CNT_SEL_RESETVAL                       (0x00000000U)

/* PERF_CNT_TIM */

#define CSL_EMIF4FV_PERF_CNT_TIM_REG_TOTAL_TIME_MASK            (0xFFFFFFFFU)
#define CSL_EMIF4FV_PERF_CNT_TIM_REG_TOTAL_TIME_SHIFT           (0U)
#define CSL_EMIF4FV_PERF_CNT_TIM_REG_TOTAL_TIME_RESETVAL        (0x00000000U)
#define CSL_EMIF4FV_PERF_CNT_TIM_REG_TOTAL_TIME_MAX             (0xffffffffU)

#define CSL_EMIF4FV_PERF_CNT_TIM_RESETVAL                       (0x00000000U)

/* IRQ_EOI */

#define CSL_EMIF4FV_IRQ_EOI_REG_EOI_MASK                        (0x00000001U)
#define CSL_EMIF4FV_IRQ_EOI_REG_EOI_SHIFT                       (0U)
#define CSL_EMIF4FV_IRQ_EOI_REG_EOI_RESETVAL                    (0x00000000U)
#define CSL_EMIF4FV_IRQ_EOI_REG_EOI_MAX                         (0x00000001U)

#define CSL_EMIF4FV_IRQ_EOI_RESETVAL                            (0x00000000U)

/* IRQSTATUS_RAW_SYS */

#define CSL_EMIF4FV_IRQSTATUS_RAW_SYS_REG_ERR_SYS_MASK          (0x00000001U)
#define CSL_EMIF4FV_IRQSTATUS_RAW_SYS_REG_ERR_SYS_SHIFT         (0U)
#define CSL_EMIF4FV_IRQSTATUS_RAW_SYS_REG_ERR_SYS_RESETVAL      (0x00000000U)
#define CSL_EMIF4FV_IRQSTATUS_RAW_SYS_REG_ERR_SYS_MAX           (0x00000001U)

#define CSL_EMIF4FV_IRQSTATUS_RAW_SYS_REG_WR_ECC_ERR_SYS_MASK   (0x00000008U)
#define CSL_EMIF4FV_IRQSTATUS_RAW_SYS_REG_WR_ECC_ERR_SYS_SHIFT  (3U)
#define CSL_EMIF4FV_IRQSTATUS_RAW_SYS_REG_WR_ECC_ERR_SYS_RESETVAL  (0x00000000U)
#define CSL_EMIF4FV_IRQSTATUS_RAW_SYS_REG_WR_ECC_ERR_SYS_MAX    (0x00000001U)

#define CSL_EMIF4FV_IRQSTATUS_RAW_SYS_REG_2B_ECC_ERR_SYS_MASK   (0x00000010U)
#define CSL_EMIF4FV_IRQSTATUS_RAW_SYS_REG_2B_ECC_ERR_SYS_SHIFT  (4U)
#define CSL_EMIF4FV_IRQSTATUS_RAW_SYS_REG_2B_ECC_ERR_SYS_RESETVAL  (0x00000000U)
#define CSL_EMIF4FV_IRQSTATUS_RAW_SYS_REG_2B_ECC_ERR_SYS_MAX    (0x00000001U)

#define CSL_EMIF4FV_IRQSTATUS_RAW_SYS_REG_1B_ECC_ERR_SYS_MASK   (0x00000020U)
#define CSL_EMIF4FV_IRQSTATUS_RAW_SYS_REG_1B_ECC_ERR_SYS_SHIFT  (5U)
#define CSL_EMIF4FV_IRQSTATUS_RAW_SYS_REG_1B_ECC_ERR_SYS_RESETVAL  (0x00000000U)
#define CSL_EMIF4FV_IRQSTATUS_RAW_SYS_REG_1B_ECC_ERR_SYS_MAX    (0x00000001U)

#define CSL_EMIF4FV_IRQSTATUS_RAW_SYS_RESETVAL                  (0x00000000U)

/* IRQSTATUS_SYS */

#define CSL_EMIF4FV_IRQSTATUS_SYS_REG_ERR_SYS_MASK              (0x00000001U)
#define CSL_EMIF4FV_IRQSTATUS_SYS_REG_ERR_SYS_SHIFT             (0U)
#define CSL_EMIF4FV_IRQSTATUS_SYS_REG_ERR_SYS_RESETVAL          (0x00000000U)
#define CSL_EMIF4FV_IRQSTATUS_SYS_REG_ERR_SYS_MAX               (0x00000001U)

#define CSL_EMIF4FV_IRQSTATUS_SYS_REG_WR_ECC_ERR_SYS_MASK       (0x00000008U)
#define CSL_EMIF4FV_IRQSTATUS_SYS_REG_WR_ECC_ERR_SYS_SHIFT      (3U)
#define CSL_EMIF4FV_IRQSTATUS_SYS_REG_WR_ECC_ERR_SYS_RESETVAL   (0x00000000U)
#define CSL_EMIF4FV_IRQSTATUS_SYS_REG_WR_ECC_ERR_SYS_MAX        (0x00000001U)

#define CSL_EMIF4FV_IRQSTATUS_SYS_REG_2B_ECC_ERR_SYS_MASK       (0x00000010U)
#define CSL_EMIF4FV_IRQSTATUS_SYS_REG_2B_ECC_ERR_SYS_SHIFT      (4U)
#define CSL_EMIF4FV_IRQSTATUS_SYS_REG_2B_ECC_ERR_SYS_RESETVAL   (0x00000000U)
#define CSL_EMIF4FV_IRQSTATUS_SYS_REG_2B_ECC_ERR_SYS_MAX        (0x00000001U)

#define CSL_EMIF4FV_IRQSTATUS_SYS_REG_1B_ECC_ERR_SYS_MASK       (0x00000020U)
#define CSL_EMIF4FV_IRQSTATUS_SYS_REG_1B_ECC_ERR_SYS_SHIFT      (5U)
#define CSL_EMIF4FV_IRQSTATUS_SYS_REG_1B_ECC_ERR_SYS_RESETVAL   (0x00000000U)
#define CSL_EMIF4FV_IRQSTATUS_SYS_REG_1B_ECC_ERR_SYS_MAX        (0x00000001U)

#define CSL_EMIF4FV_IRQSTATUS_SYS_RESETVAL                      (0x00000000U)

/* IRQENABLE_SET_SYS */

#define CSL_EMIF4FV_IRQENABLE_SET_SYS_REG_EN_ERR_SYS_MASK       (0x00000001U)
#define CSL_EMIF4FV_IRQENABLE_SET_SYS_REG_EN_ERR_SYS_SHIFT      (0U)
#define CSL_EMIF4FV_IRQENABLE_SET_SYS_REG_EN_ERR_SYS_RESETVAL   (0x00000000U)
#define CSL_EMIF4FV_IRQENABLE_SET_SYS_REG_EN_ERR_SYS_MAX        (0x00000001U)

#define CSL_EMIF4FV_IRQENABLE_SET_SYS_REG_EN_WR_ECC_ERR_SYS_MASK  (0x00000008U)
#define CSL_EMIF4FV_IRQENABLE_SET_SYS_REG_EN_WR_ECC_ERR_SYS_SHIFT  (3U)
#define CSL_EMIF4FV_IRQENABLE_SET_SYS_REG_EN_WR_ECC_ERR_SYS_RESETVAL  (0x00000000U)
#define CSL_EMIF4FV_IRQENABLE_SET_SYS_REG_EN_WR_ECC_ERR_SYS_MAX  (0x00000001U)

#define CSL_EMIF4FV_IRQENABLE_SET_SYS_REG_EN_2B_ECC_ERR_SYS_MASK  (0x00000010U)
#define CSL_EMIF4FV_IRQENABLE_SET_SYS_REG_EN_2B_ECC_ERR_SYS_SHIFT  (4U)
#define CSL_EMIF4FV_IRQENABLE_SET_SYS_REG_EN_2B_ECC_ERR_SYS_RESETVAL  (0x00000000U)
#define CSL_EMIF4FV_IRQENABLE_SET_SYS_REG_EN_2B_ECC_ERR_SYS_MAX  (0x00000001U)

#define CSL_EMIF4FV_IRQENABLE_SET_SYS_REG_EN_1B_ECC_ERR_SYS_MASK  (0x00000020U)
#define CSL_EMIF4FV_IRQENABLE_SET_SYS_REG_EN_1B_ECC_ERR_SYS_SHIFT  (5U)
#define CSL_EMIF4FV_IRQENABLE_SET_SYS_REG_EN_1B_ECC_ERR_SYS_RESETVAL  (0x00000000U)
#define CSL_EMIF4FV_IRQENABLE_SET_SYS_REG_EN_1B_ECC_ERR_SYS_MAX  (0x00000001U)

#define CSL_EMIF4FV_IRQENABLE_SET_SYS_RESETVAL                  (0x00000000U)

/* IRQENABLE_CLR_SYS */

#define CSL_EMIF4FV_IRQENABLE_CLR_SYS_REG_EN_ERR_SYS_MASK       (0x00000001U)
#define CSL_EMIF4FV_IRQENABLE_CLR_SYS_REG_EN_ERR_SYS_SHIFT      (0U)
#define CSL_EMIF4FV_IRQENABLE_CLR_SYS_REG_EN_ERR_SYS_RESETVAL   (0x00000000U)
#define CSL_EMIF4FV_IRQENABLE_CLR_SYS_REG_EN_ERR_SYS_MAX        (0x00000001U)

#define CSL_EMIF4FV_IRQENABLE_CLR_SYS_REG_EN_WR_ECC_ERR_SYS_MASK  (0x00000008U)
#define CSL_EMIF4FV_IRQENABLE_CLR_SYS_REG_EN_WR_ECC_ERR_SYS_SHIFT  (3U)
#define CSL_EMIF4FV_IRQENABLE_CLR_SYS_REG_EN_WR_ECC_ERR_SYS_RESETVAL  (0x00000000U)
#define CSL_EMIF4FV_IRQENABLE_CLR_SYS_REG_EN_WR_ECC_ERR_SYS_MAX  (0x00000001U)

#define CSL_EMIF4FV_IRQENABLE_CLR_SYS_REG_EN_2B_ECC_ERR_SYS_MASK  (0x00000010U)
#define CSL_EMIF4FV_IRQENABLE_CLR_SYS_REG_EN_2B_ECC_ERR_SYS_SHIFT  (4U)
#define CSL_EMIF4FV_IRQENABLE_CLR_SYS_REG_EN_2B_ECC_ERR_SYS_RESETVAL  (0x00000000U)
#define CSL_EMIF4FV_IRQENABLE_CLR_SYS_REG_EN_2B_ECC_ERR_SYS_MAX  (0x00000001U)

#define CSL_EMIF4FV_IRQENABLE_CLR_SYS_REG_EN_1B_ECC_ERR_SYS_MASK  (0x00000020U)
#define CSL_EMIF4FV_IRQENABLE_CLR_SYS_REG_EN_1B_ECC_ERR_SYS_SHIFT  (5U)
#define CSL_EMIF4FV_IRQENABLE_CLR_SYS_REG_EN_1B_ECC_ERR_SYS_RESETVAL  (0x00000000U)
#define CSL_EMIF4FV_IRQENABLE_CLR_SYS_REG_EN_1B_ECC_ERR_SYS_MAX  (0x00000001U)

#define CSL_EMIF4FV_IRQENABLE_CLR_SYS_RESETVAL                  (0x00000000U)

/* ZQ_CONFIG */

#define CSL_EMIF4FV_ZQ_CONFIG_REG_ZQ_REFINTERVAL_MASK           (0x0000FFFFU)
#define CSL_EMIF4FV_ZQ_CONFIG_REG_ZQ_REFINTERVAL_SHIFT          (0U)
#define CSL_EMIF4FV_ZQ_CONFIG_REG_ZQ_REFINTERVAL_RESETVAL       (0x00000000U)
#define CSL_EMIF4FV_ZQ_CONFIG_REG_ZQ_REFINTERVAL_MAX            (0x0000ffffU)

#define CSL_EMIF4FV_ZQ_CONFIG_REG_ZQ_ZQCL_MULT_MASK             (0x00070000U)
#define CSL_EMIF4FV_ZQ_CONFIG_REG_ZQ_ZQCL_MULT_SHIFT            (16U)
#define CSL_EMIF4FV_ZQ_CONFIG_REG_ZQ_ZQCL_MULT_RESETVAL         (0x00000000U)
#define CSL_EMIF4FV_ZQ_CONFIG_REG_ZQ_ZQCL_MULT_MAX              (0x00000007U)

#define CSL_EMIF4FV_ZQ_CONFIG_REG_ZQ_SFEXITEN_MASK              (0x10000000U)
#define CSL_EMIF4FV_ZQ_CONFIG_REG_ZQ_SFEXITEN_SHIFT             (28U)
#define CSL_EMIF4FV_ZQ_CONFIG_REG_ZQ_SFEXITEN_RESETVAL          (0x00000000U)
#define CSL_EMIF4FV_ZQ_CONFIG_REG_ZQ_SFEXITEN_MAX               (0x00000001U)

#define CSL_EMIF4FV_ZQ_CONFIG_REG_ZQ_DUALCALEN_MASK             (0x20000000U)
#define CSL_EMIF4FV_ZQ_CONFIG_REG_ZQ_DUALCALEN_SHIFT            (29U)
#define CSL_EMIF4FV_ZQ_CONFIG_REG_ZQ_DUALCALEN_RESETVAL         (0x00000000U)
#define CSL_EMIF4FV_ZQ_CONFIG_REG_ZQ_DUALCALEN_MAX              (0x00000001U)

#define CSL_EMIF4FV_ZQ_CONFIG_REG_ZQ_CS0EN_MASK                 (0x40000000U)
#define CSL_EMIF4FV_ZQ_CONFIG_REG_ZQ_CS0EN_SHIFT                (30U)
#define CSL_EMIF4FV_ZQ_CONFIG_REG_ZQ_CS0EN_RESETVAL             (0x00000000U)
#define CSL_EMIF4FV_ZQ_CONFIG_REG_ZQ_CS0EN_MAX                  (0x00000001U)

#define CSL_EMIF4FV_ZQ_CONFIG_REG_ZQ_CS1EN_MASK                 (0x80000000U)
#define CSL_EMIF4FV_ZQ_CONFIG_REG_ZQ_CS1EN_SHIFT                (31U)
#define CSL_EMIF4FV_ZQ_CONFIG_REG_ZQ_CS1EN_RESETVAL             (0x00000000U)
#define CSL_EMIF4FV_ZQ_CONFIG_REG_ZQ_CS1EN_MAX                  (0x00000001U)

#define CSL_EMIF4FV_ZQ_CONFIG_RESETVAL                          (0x00000000U)

/* VBUSM_ERR_LOG */

#define CSL_EMIF4FV_VBUSM_ERR_LOG_REG_CMSTID_MASK               (0x000000FFU)
#define CSL_EMIF4FV_VBUSM_ERR_LOG_REG_CMSTID_SHIFT              (0U)
#define CSL_EMIF4FV_VBUSM_ERR_LOG_REG_CMSTID_RESETVAL           (0x00000000U)
#define CSL_EMIF4FV_VBUSM_ERR_LOG_REG_CMSTID_MAX                (0x000000ffU)

#define CSL_EMIF4FV_VBUSM_ERR_LOG_REG_CDIR_MASK                 (0x00000100U)
#define CSL_EMIF4FV_VBUSM_ERR_LOG_REG_CDIR_SHIFT                (8U)
#define CSL_EMIF4FV_VBUSM_ERR_LOG_REG_CDIR_RESETVAL             (0x00000000U)
#define CSL_EMIF4FV_VBUSM_ERR_LOG_REG_CDIR_MAX                  (0x00000001U)

#define CSL_EMIF4FV_VBUSM_ERR_LOG_REG_CAMODE_MASK               (0x00000600U)
#define CSL_EMIF4FV_VBUSM_ERR_LOG_REG_CAMODE_SHIFT              (9U)
#define CSL_EMIF4FV_VBUSM_ERR_LOG_REG_CAMODE_RESETVAL           (0x00000000U)
#define CSL_EMIF4FV_VBUSM_ERR_LOG_REG_CAMODE_MAX                (0x00000003U)

#define CSL_EMIF4FV_VBUSM_ERR_LOG_REG_CRSEL_MASK                (0x00007800U)
#define CSL_EMIF4FV_VBUSM_ERR_LOG_REG_CRSEL_SHIFT               (11U)
#define CSL_EMIF4FV_VBUSM_ERR_LOG_REG_CRSEL_RESETVAL            (0x00000000U)
#define CSL_EMIF4FV_VBUSM_ERR_LOG_REG_CRSEL_MAX                 (0x0000000fU)

#define CSL_EMIF4FV_VBUSM_ERR_LOG_RESETVAL                      (0x00000000U)

/* PRI_COS_MAP */

#define CSL_EMIF4FV_PRI_COS_MAP_REG_PRI_0_COS_MASK              (0x00000003U)
#define CSL_EMIF4FV_PRI_COS_MAP_REG_PRI_0_COS_SHIFT             (0U)
#define CSL_EMIF4FV_PRI_COS_MAP_REG_PRI_0_COS_RESETVAL          (0x00000000U)
#define CSL_EMIF4FV_PRI_COS_MAP_REG_PRI_0_COS_MAX               (0x00000003U)

#define CSL_EMIF4FV_PRI_COS_MAP_REG_PRI_1_COS_MASK              (0x0000000CU)
#define CSL_EMIF4FV_PRI_COS_MAP_REG_PRI_1_COS_SHIFT             (2U)
#define CSL_EMIF4FV_PRI_COS_MAP_REG_PRI_1_COS_RESETVAL          (0x00000000U)
#define CSL_EMIF4FV_PRI_COS_MAP_REG_PRI_1_COS_MAX               (0x00000003U)

#define CSL_EMIF4FV_PRI_COS_MAP_REG_PRI_2_COS_MASK              (0x00000030U)
#define CSL_EMIF4FV_PRI_COS_MAP_REG_PRI_2_COS_SHIFT             (4U)
#define CSL_EMIF4FV_PRI_COS_MAP_REG_PRI_2_COS_RESETVAL          (0x00000000U)
#define CSL_EMIF4FV_PRI_COS_MAP_REG_PRI_2_COS_MAX               (0x00000003U)

#define CSL_EMIF4FV_PRI_COS_MAP_REG_PRI_3_COS_MASK              (0x000000C0U)
#define CSL_EMIF4FV_PRI_COS_MAP_REG_PRI_3_COS_SHIFT             (6U)
#define CSL_EMIF4FV_PRI_COS_MAP_REG_PRI_3_COS_RESETVAL          (0x00000000U)
#define CSL_EMIF4FV_PRI_COS_MAP_REG_PRI_3_COS_MAX               (0x00000003U)

#define CSL_EMIF4FV_PRI_COS_MAP_REG_PRI_4_COS_MASK              (0x00000300U)
#define CSL_EMIF4FV_PRI_COS_MAP_REG_PRI_4_COS_SHIFT             (8U)
#define CSL_EMIF4FV_PRI_COS_MAP_REG_PRI_4_COS_RESETVAL          (0x00000000U)
#define CSL_EMIF4FV_PRI_COS_MAP_REG_PRI_4_COS_MAX               (0x00000003U)

#define CSL_EMIF4FV_PRI_COS_MAP_REG_PRI_5_COS_MASK              (0x00000C00U)
#define CSL_EMIF4FV_PRI_COS_MAP_REG_PRI_5_COS_SHIFT             (10U)
#define CSL_EMIF4FV_PRI_COS_MAP_REG_PRI_5_COS_RESETVAL          (0x00000000U)
#define CSL_EMIF4FV_PRI_COS_MAP_REG_PRI_5_COS_MAX               (0x00000003U)

#define CSL_EMIF4FV_PRI_COS_MAP_REG_PRI_6_COS_MASK              (0x00003000U)
#define CSL_EMIF4FV_PRI_COS_MAP_REG_PRI_6_COS_SHIFT             (12U)
#define CSL_EMIF4FV_PRI_COS_MAP_REG_PRI_6_COS_RESETVAL          (0x00000000U)
#define CSL_EMIF4FV_PRI_COS_MAP_REG_PRI_6_COS_MAX               (0x00000003U)

#define CSL_EMIF4FV_PRI_COS_MAP_REG_PRI_7_COS_MASK              (0x0000C000U)
#define CSL_EMIF4FV_PRI_COS_MAP_REG_PRI_7_COS_SHIFT             (14U)
#define CSL_EMIF4FV_PRI_COS_MAP_REG_PRI_7_COS_RESETVAL          (0x00000000U)
#define CSL_EMIF4FV_PRI_COS_MAP_REG_PRI_7_COS_MAX               (0x00000003U)

#define CSL_EMIF4FV_PRI_COS_MAP_REG_PRI_COS_MAP_EN_MASK         (0x80000000U)
#define CSL_EMIF4FV_PRI_COS_MAP_REG_PRI_COS_MAP_EN_SHIFT        (31U)
#define CSL_EMIF4FV_PRI_COS_MAP_REG_PRI_COS_MAP_EN_RESETVAL     (0x00000000U)
#define CSL_EMIF4FV_PRI_COS_MAP_REG_PRI_COS_MAP_EN_MAX          (0x00000001U)

#define CSL_EMIF4FV_PRI_COS_MAP_RESETVAL                        (0x00000000U)

/* MSTID_COS_1_MAP */

#define CSL_EMIF4FV_MSTID_COS_1_MAP_REG_MSK_3_COS_1_MASK        (0x00000003U)
#define CSL_EMIF4FV_MSTID_COS_1_MAP_REG_MSK_3_COS_1_SHIFT       (0U)
#define CSL_EMIF4FV_MSTID_COS_1_MAP_REG_MSK_3_COS_1_RESETVAL    (0x00000000U)
#define CSL_EMIF4FV_MSTID_COS_1_MAP_REG_MSK_3_COS_1_MAX         (0x00000003U)

#define CSL_EMIF4FV_MSTID_COS_1_MAP_REG_MSTID_3_COS_1_MASK      (0x000003FCU)
#define CSL_EMIF4FV_MSTID_COS_1_MAP_REG_MSTID_3_COS_1_SHIFT     (2U)
#define CSL_EMIF4FV_MSTID_COS_1_MAP_REG_MSTID_3_COS_1_RESETVAL  (0x00000000U)
#define CSL_EMIF4FV_MSTID_COS_1_MAP_REG_MSTID_3_COS_1_MAX       (0x000000ffU)

#define CSL_EMIF4FV_MSTID_COS_1_MAP_REG_MSK_2_COS_1_MASK        (0x00000C00U)
#define CSL_EMIF4FV_MSTID_COS_1_MAP_REG_MSK_2_COS_1_SHIFT       (10U)
#define CSL_EMIF4FV_MSTID_COS_1_MAP_REG_MSK_2_COS_1_RESETVAL    (0x00000000U)
#define CSL_EMIF4FV_MSTID_COS_1_MAP_REG_MSK_2_COS_1_MAX         (0x00000003U)

#define CSL_EMIF4FV_MSTID_COS_1_MAP_REG_MSTID_2_COS_1_MASK      (0x000FF000U)
#define CSL_EMIF4FV_MSTID_COS_1_MAP_REG_MSTID_2_COS_1_SHIFT     (12U)
#define CSL_EMIF4FV_MSTID_COS_1_MAP_REG_MSTID_2_COS_1_RESETVAL  (0x00000000U)
#define CSL_EMIF4FV_MSTID_COS_1_MAP_REG_MSTID_2_COS_1_MAX       (0x000000ffU)

#define CSL_EMIF4FV_MSTID_COS_1_MAP_REG_MSK_1_COS_1_MASK        (0x00700000U)
#define CSL_EMIF4FV_MSTID_COS_1_MAP_REG_MSK_1_COS_1_SHIFT       (20U)
#define CSL_EMIF4FV_MSTID_COS_1_MAP_REG_MSK_1_COS_1_RESETVAL    (0x00000000U)
#define CSL_EMIF4FV_MSTID_COS_1_MAP_REG_MSK_1_COS_1_MAX         (0x00000007U)

#define CSL_EMIF4FV_MSTID_COS_1_MAP_REG_MSTID_1_COS_1_MASK      (0x7F800000U)
#define CSL_EMIF4FV_MSTID_COS_1_MAP_REG_MSTID_1_COS_1_SHIFT     (23U)
#define CSL_EMIF4FV_MSTID_COS_1_MAP_REG_MSTID_1_COS_1_RESETVAL  (0x00000000U)
#define CSL_EMIF4FV_MSTID_COS_1_MAP_REG_MSTID_1_COS_1_MAX       (0x000000ffU)

#define CSL_EMIF4FV_MSTID_COS_1_MAP_REG_MSTID_COS_1_MAP_EN_MASK  (0x80000000U)
#define CSL_EMIF4FV_MSTID_COS_1_MAP_REG_MSTID_COS_1_MAP_EN_SHIFT  (31U)
#define CSL_EMIF4FV_MSTID_COS_1_MAP_REG_MSTID_COS_1_MAP_EN_RESETVAL  (0x00000000U)
#define CSL_EMIF4FV_MSTID_COS_1_MAP_REG_MSTID_COS_1_MAP_EN_MAX  (0x00000001U)

#define CSL_EMIF4FV_MSTID_COS_1_MAP_RESETVAL                    (0x00000000U)

/* MSTID_COS_2_MAP */

#define CSL_EMIF4FV_MSTID_COS_2_MAP_REG_MSK_3_COS_2_MASK        (0x00000003U)
#define CSL_EMIF4FV_MSTID_COS_2_MAP_REG_MSK_3_COS_2_SHIFT       (0U)
#define CSL_EMIF4FV_MSTID_COS_2_MAP_REG_MSK_3_COS_2_RESETVAL    (0x00000000U)
#define CSL_EMIF4FV_MSTID_COS_2_MAP_REG_MSK_3_COS_2_MAX         (0x00000003U)

#define CSL_EMIF4FV_MSTID_COS_2_MAP_REG_MSTID_3_COS_2_MASK      (0x000003FCU)
#define CSL_EMIF4FV_MSTID_COS_2_MAP_REG_MSTID_3_COS_2_SHIFT     (2U)
#define CSL_EMIF4FV_MSTID_COS_2_MAP_REG_MSTID_3_COS_2_RESETVAL  (0x00000000U)
#define CSL_EMIF4FV_MSTID_COS_2_MAP_REG_MSTID_3_COS_2_MAX       (0x000000ffU)

#define CSL_EMIF4FV_MSTID_COS_2_MAP_REG_MSK_2_COS_2_MASK        (0x00000C00U)
#define CSL_EMIF4FV_MSTID_COS_2_MAP_REG_MSK_2_COS_2_SHIFT       (10U)
#define CSL_EMIF4FV_MSTID_COS_2_MAP_REG_MSK_2_COS_2_RESETVAL    (0x00000000U)
#define CSL_EMIF4FV_MSTID_COS_2_MAP_REG_MSK_2_COS_2_MAX         (0x00000003U)

#define CSL_EMIF4FV_MSTID_COS_2_MAP_REG_MSTID_2_COS_2_MASK      (0x000FF000U)
#define CSL_EMIF4FV_MSTID_COS_2_MAP_REG_MSTID_2_COS_2_SHIFT     (12U)
#define CSL_EMIF4FV_MSTID_COS_2_MAP_REG_MSTID_2_COS_2_RESETVAL  (0x00000000U)
#define CSL_EMIF4FV_MSTID_COS_2_MAP_REG_MSTID_2_COS_2_MAX       (0x000000ffU)

#define CSL_EMIF4FV_MSTID_COS_2_MAP_REG_MSK_1_COS_2_MASK        (0x00700000U)
#define CSL_EMIF4FV_MSTID_COS_2_MAP_REG_MSK_1_COS_2_SHIFT       (20U)
#define CSL_EMIF4FV_MSTID_COS_2_MAP_REG_MSK_1_COS_2_RESETVAL    (0x00000000U)
#define CSL_EMIF4FV_MSTID_COS_2_MAP_REG_MSK_1_COS_2_MAX         (0x00000007U)

#define CSL_EMIF4FV_MSTID_COS_2_MAP_REG_MSTID_1_COS_2_MASK      (0x7F800000U)
#define CSL_EMIF4FV_MSTID_COS_2_MAP_REG_MSTID_1_COS_2_SHIFT     (23U)
#define CSL_EMIF4FV_MSTID_COS_2_MAP_REG_MSTID_1_COS_2_RESETVAL  (0x00000000U)
#define CSL_EMIF4FV_MSTID_COS_2_MAP_REG_MSTID_1_COS_2_MAX       (0x000000ffU)

#define CSL_EMIF4FV_MSTID_COS_2_MAP_REG_MSTID_COS_2_MAP_EN_MASK  (0x80000000U)
#define CSL_EMIF4FV_MSTID_COS_2_MAP_REG_MSTID_COS_2_MAP_EN_SHIFT  (31U)
#define CSL_EMIF4FV_MSTID_COS_2_MAP_REG_MSTID_COS_2_MAP_EN_RESETVAL  (0x00000000U)
#define CSL_EMIF4FV_MSTID_COS_2_MAP_REG_MSTID_COS_2_MAP_EN_MAX  (0x00000001U)

#define CSL_EMIF4FV_MSTID_COS_2_MAP_RESETVAL                    (0x00000000U)

/* ECC_CTRL */

#define CSL_EMIF4FV_ECC_CTRL_REG_ECC_ADDR_RNG_1_EN_MASK         (0x00000001U)
#define CSL_EMIF4FV_ECC_CTRL_REG_ECC_ADDR_RNG_1_EN_SHIFT        (0U)
#define CSL_EMIF4FV_ECC_CTRL_REG_ECC_ADDR_RNG_1_EN_RESETVAL     (0x00000000U)
#define CSL_EMIF4FV_ECC_CTRL_REG_ECC_ADDR_RNG_1_EN_MAX          (0x00000001U)

#define CSL_EMIF4FV_ECC_CTRL_REG_ECC_ADDR_RNG_2_EN_MASK         (0x00000002U)
#define CSL_EMIF4FV_ECC_CTRL_REG_ECC_ADDR_RNG_2_EN_SHIFT        (1U)
#define CSL_EMIF4FV_ECC_CTRL_REG_ECC_ADDR_RNG_2_EN_RESETVAL     (0x00000000U)
#define CSL_EMIF4FV_ECC_CTRL_REG_ECC_ADDR_RNG_2_EN_MAX          (0x00000001U)

#define CSL_EMIF4FV_ECC_CTRL_REG_RMW_EN_MASK                    (0x10000000U)
#define CSL_EMIF4FV_ECC_CTRL_REG_RMW_EN_SHIFT                   (28U)
#define CSL_EMIF4FV_ECC_CTRL_REG_RMW_EN_RESETVAL                (0x00000000U)
#define CSL_EMIF4FV_ECC_CTRL_REG_RMW_EN_MAX                     (0x00000001U)

#define CSL_EMIF4FV_ECC_CTRL_REG_ECC_VERIFY_EN_MASK             (0x20000000U)
#define CSL_EMIF4FV_ECC_CTRL_REG_ECC_VERIFY_EN_SHIFT            (29U)
#define CSL_EMIF4FV_ECC_CTRL_REG_ECC_VERIFY_EN_RESETVAL         (0x00000000U)
#define CSL_EMIF4FV_ECC_CTRL_REG_ECC_VERIFY_EN_MAX              (0x00000001U)

#define CSL_EMIF4FV_ECC_CTRL_REG_ECC_ADDR_RNG_PROT_MASK         (0x40000000U)
#define CSL_EMIF4FV_ECC_CTRL_REG_ECC_ADDR_RNG_PROT_SHIFT        (30U)
#define CSL_EMIF4FV_ECC_CTRL_REG_ECC_ADDR_RNG_PROT_RESETVAL     (0x00000000U)
#define CSL_EMIF4FV_ECC_CTRL_REG_ECC_ADDR_RNG_PROT_MAX          (0x00000001U)

#define CSL_EMIF4FV_ECC_CTRL_REG_ECC_EN_MASK                    (0x80000000U)
#define CSL_EMIF4FV_ECC_CTRL_REG_ECC_EN_SHIFT                   (31U)
#define CSL_EMIF4FV_ECC_CTRL_REG_ECC_EN_RESETVAL                (0x00000000U)
#define CSL_EMIF4FV_ECC_CTRL_REG_ECC_EN_MAX                     (0x00000001U)

#define CSL_EMIF4FV_ECC_CTRL_RESETVAL                           (0x00000000U)

/* ECC_ADDR_RNG_1 */

#define CSL_EMIF4FV_ECC_ADDR_RNG_1_REG_ECC_STRT_ADDR_1_MASK     (0x0000FFFFU)
#define CSL_EMIF4FV_ECC_ADDR_RNG_1_REG_ECC_STRT_ADDR_1_SHIFT    (0U)
#define CSL_EMIF4FV_ECC_ADDR_RNG_1_REG_ECC_STRT_ADDR_1_RESETVAL  (0x00000000U)
#define CSL_EMIF4FV_ECC_ADDR_RNG_1_REG_ECC_STRT_ADDR_1_MAX      (0x0000ffffU)

#define CSL_EMIF4FV_ECC_ADDR_RNG_1_REG_ECC_END_ADDR_1_MASK      (0xFFFF0000U)
#define CSL_EMIF4FV_ECC_ADDR_RNG_1_REG_ECC_END_ADDR_1_SHIFT     (16U)
#define CSL_EMIF4FV_ECC_ADDR_RNG_1_REG_ECC_END_ADDR_1_RESETVAL  (0x00000000U)
#define CSL_EMIF4FV_ECC_ADDR_RNG_1_REG_ECC_END_ADDR_1_MAX       (0x0000ffffU)

#define CSL_EMIF4FV_ECC_ADDR_RNG_1_RESETVAL                     (0x00000000U)

/* ECC_ADDR_RNG_2 */

#define CSL_EMIF4FV_ECC_ADDR_RNG_2_REG_ECC_STRT_ADDR_2_MASK     (0x0000FFFFU)
#define CSL_EMIF4FV_ECC_ADDR_RNG_2_REG_ECC_STRT_ADDR_2_SHIFT    (0U)
#define CSL_EMIF4FV_ECC_ADDR_RNG_2_REG_ECC_STRT_ADDR_2_RESETVAL  (0x00000000U)
#define CSL_EMIF4FV_ECC_ADDR_RNG_2_REG_ECC_STRT_ADDR_2_MAX      (0x0000ffffU)

#define CSL_EMIF4FV_ECC_ADDR_RNG_2_REG_ECC_END_ADDR_2_MASK      (0xFFFF0000U)
#define CSL_EMIF4FV_ECC_ADDR_RNG_2_REG_ECC_END_ADDR_2_SHIFT     (16U)
#define CSL_EMIF4FV_ECC_ADDR_RNG_2_REG_ECC_END_ADDR_2_RESETVAL  (0x00000000U)
#define CSL_EMIF4FV_ECC_ADDR_RNG_2_REG_ECC_END_ADDR_2_MAX       (0x0000ffffU)

#define CSL_EMIF4FV_ECC_ADDR_RNG_2_RESETVAL                     (0x00000000U)

/* RD_WR_EXEC_THRSH */

#define CSL_EMIF4FV_RD_WR_EXEC_THRSH_REG_RD_THRSH_MASK          (0x0000001FU)
#define CSL_EMIF4FV_RD_WR_EXEC_THRSH_REG_RD_THRSH_SHIFT         (0U)
#define CSL_EMIF4FV_RD_WR_EXEC_THRSH_REG_RD_THRSH_RESETVAL      (0x00000005U)
#define CSL_EMIF4FV_RD_WR_EXEC_THRSH_REG_RD_THRSH_MAX           (0x0000001fU)

#define CSL_EMIF4FV_RD_WR_EXEC_THRSH_REG_WR_THRSH_MASK          (0x00001F00U)
#define CSL_EMIF4FV_RD_WR_EXEC_THRSH_REG_WR_THRSH_SHIFT         (8U)
#define CSL_EMIF4FV_RD_WR_EXEC_THRSH_REG_WR_THRSH_RESETVAL      (0x00000003U)
#define CSL_EMIF4FV_RD_WR_EXEC_THRSH_REG_WR_THRSH_MAX           (0x0000001fU)

#define CSL_EMIF4FV_RD_WR_EXEC_THRSH_RESETVAL                   (0x00000305U)

/* ONE_BIT_ECC_ERR_CNT */

#define CSL_EMIF4FV_ONE_BIT_ECC_ERR_CNT_REG_1B_ECC_ERR_CNT_MASK  (0xFFFFFFFFU)
#define CSL_EMIF4FV_ONE_BIT_ECC_ERR_CNT_REG_1B_ECC_ERR_CNT_SHIFT  (0U)
#define CSL_EMIF4FV_ONE_BIT_ECC_ERR_CNT_REG_1B_ECC_ERR_CNT_RESETVAL  (0x00000000U)
#define CSL_EMIF4FV_ONE_BIT_ECC_ERR_CNT_REG_1B_ECC_ERR_CNT_MAX  (0xffffffffU)

#define CSL_EMIF4FV_ONE_BIT_ECC_ERR_CNT_RESETVAL                (0x00000000U)

/* ONE_BIT_ECC_ERR_THRSH */

#define CSL_EMIF4FV_ONE_BIT_ECC_ERR_THRSH_REG_1B_ECC_ERR_WIN_MASK  (0x0000FFFFU)
#define CSL_EMIF4FV_ONE_BIT_ECC_ERR_THRSH_REG_1B_ECC_ERR_WIN_SHIFT  (0U)
#define CSL_EMIF4FV_ONE_BIT_ECC_ERR_THRSH_REG_1B_ECC_ERR_WIN_RESETVAL  (0x00000000U)
#define CSL_EMIF4FV_ONE_BIT_ECC_ERR_THRSH_REG_1B_ECC_ERR_WIN_MAX  (0x0000ffffU)

#define CSL_EMIF4FV_ONE_BIT_ECC_ERR_THRSH_REG_1B_ECC_ERR_THRSH_MASK  (0xFF000000U)
#define CSL_EMIF4FV_ONE_BIT_ECC_ERR_THRSH_REG_1B_ECC_ERR_THRSH_SHIFT  (24U)
#define CSL_EMIF4FV_ONE_BIT_ECC_ERR_THRSH_REG_1B_ECC_ERR_THRSH_RESETVAL  (0x00000000U)
#define CSL_EMIF4FV_ONE_BIT_ECC_ERR_THRSH_REG_1B_ECC_ERR_THRSH_MAX  (0x000000ffU)

#define CSL_EMIF4FV_ONE_BIT_ECC_ERR_THRSH_RESETVAL              (0x00000000U)

/* ONE_BIT_ECC_ERR_DIST_1 */

#define CSL_EMIF4FV_ONE_BIT_ECC_ERR_DIST_1_REG_1B_ECC_ERR_DIST_1_MASK  (0xFFFFFFFFU)
#define CSL_EMIF4FV_ONE_BIT_ECC_ERR_DIST_1_REG_1B_ECC_ERR_DIST_1_SHIFT  (0U)
#define CSL_EMIF4FV_ONE_BIT_ECC_ERR_DIST_1_REG_1B_ECC_ERR_DIST_1_RESETVAL  (0x00000000U)
#define CSL_EMIF4FV_ONE_BIT_ECC_ERR_DIST_1_REG_1B_ECC_ERR_DIST_1_MAX  (0xffffffffU)

#define CSL_EMIF4FV_ONE_BIT_ECC_ERR_DIST_1_RESETVAL             (0x00000000U)

/* ONE_BIT_ECC_ERR_ADDR_LOG */

#define CSL_EMIF4FV_ONE_BIT_ECC_ERR_ADDR_LOG_REG_1B_ECC_ERR_ADDR_MASK  (0xFFFFFFFFU)
#define CSL_EMIF4FV_ONE_BIT_ECC_ERR_ADDR_LOG_REG_1B_ECC_ERR_ADDR_SHIFT  (0U)
#define CSL_EMIF4FV_ONE_BIT_ECC_ERR_ADDR_LOG_REG_1B_ECC_ERR_ADDR_RESETVAL  (0x00000000U)
#define CSL_EMIF4FV_ONE_BIT_ECC_ERR_ADDR_LOG_REG_1B_ECC_ERR_ADDR_MAX  (0xffffffffU)

#define CSL_EMIF4FV_ONE_BIT_ECC_ERR_ADDR_LOG_RESETVAL           (0x00000000U)

/* TWO_BIT_ECC_ERR_ADDR_LOG */

#define CSL_EMIF4FV_TWO_BIT_ECC_ERR_ADDR_LOG_REG_2B_ECC_ERR_ADDR_MASK  (0xFFFFFFFFU)
#define CSL_EMIF4FV_TWO_BIT_ECC_ERR_ADDR_LOG_REG_2B_ECC_ERR_ADDR_SHIFT  (0U)
#define CSL_EMIF4FV_TWO_BIT_ECC_ERR_ADDR_LOG_REG_2B_ECC_ERR_ADDR_RESETVAL  (0x00000000U)
#define CSL_EMIF4FV_TWO_BIT_ECC_ERR_ADDR_LOG_REG_2B_ECC_ERR_ADDR_MAX  (0xffffffffU)

#define CSL_EMIF4FV_TWO_BIT_ECC_ERR_ADDR_LOG_RESETVAL           (0x00000000U)

/* ONE_BIT_ECC_ERR_DIST_2 */

#define CSL_EMIF4FV_ONE_BIT_ECC_ERR_DIST_2_REG_1B_ECC_ERR_DIST_2_MASK  (0xFFFFFFFFU)
#define CSL_EMIF4FV_ONE_BIT_ECC_ERR_DIST_2_REG_1B_ECC_ERR_DIST_2_SHIFT  (0U)
#define CSL_EMIF4FV_ONE_BIT_ECC_ERR_DIST_2_REG_1B_ECC_ERR_DIST_2_RESETVAL  (0x00000000U)
#define CSL_EMIF4FV_ONE_BIT_ECC_ERR_DIST_2_REG_1B_ECC_ERR_DIST_2_MAX  (0xffffffffU)

#define CSL_EMIF4FV_ONE_BIT_ECC_ERR_DIST_2_RESETVAL             (0x00000000U)

#ifdef __cplusplus
}
#endif
#endif
