diff --git a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
index 045ef170e17..e1879bdfe6d 100644
--- a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
@@ -103,27 +103,7 @@
 	bootph-all;
 };
 
-&main_i2c0 {
-	bootph-all;
-};
-
-&exp1 {
-	bootph-all;
-};
-
-&exp2 {
-	bootph-all;
-};
-
-&mcu_cpsw {
-	bootph-all;
-};
-
-&mcu_uart0 {
-	bootph-all;
-};
-
-&wkup_i2c0 {
+&mcu_i2c0 {
 	bootph-all;
 };
 
@@ -143,22 +123,10 @@
 	bootph-all;
 };
 
-&main_i2c0_pins_default {
-	bootph-all;
-};
-
 &wkup_i2c0_pins_default {
 	bootph-all;
 };
 
-&wkup_uart0_pins_default {
-	bootph-all;
-};
-
-&wkup_gpio_pins_default {
-	bootph-all;
-};
-
 &wkup_gpio0 {
 	bootph-all;
 };
diff --git a/arch/arm/dts/k3-j7200-ddr-evm-lp4-3200.dtsi b/arch/arm/dts/k3-j7200-ddr-evm-lp4-3200.dtsi
index 810415494ce..18ef9e734a9 100644
--- a/arch/arm/dts/k3-j7200-ddr-evm-lp4-3200.dtsi
+++ b/arch/arm/dts/k3-j7200-ddr-evm-lp4-3200.dtsi
@@ -2,20 +2,16 @@
 /*
  * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
  * This file was generated with the following tool revisions:
- *     - SysConfig: Revision 1.25.0+4268
- *     - Jacinto7_DDRSS_RegConfigTool: Revision 0.12.0
- * This file was generated on Thu Oct 30 2025 13:11:41 GMT+0530 (India Standard Time)
+ *     - SysConfig: Revision 1.20.0+3587
+ *     - Jacinto7_DDRSS_RegConfigTool: Revision 0.11.0
+ * This file was generated on Wed Jul 03 2024 10:38:37 GMT+0530 (India Standard Time)
 */
 
-#define DDRSS_PLL_FHS_CNT 5
+#define DDRSS_PLL_FHS_CNT 3
 #define DDRSS_PLL_FREQUENCY_0 27500000
-#define DDRSS_PLL_FREQUENCY_1 800000000
-#define DDRSS_PLL_FREQUENCY_2 800000000
+#define DDRSS_PLL_FREQUENCY_1 666500000
+#define DDRSS_PLL_FREQUENCY_2 666500000
 
-#define DDR_REG0_SIZE_MSB 0x00000000
-#define DDR_REG0_SIZE_LSB 0x80000000
-#define DDR_REG1_SIZE_MSB 0x00000000
-#define DDR_REG1_SIZE_LSB 0x80000000
 
 
 #define DDRSS_CTL_00_DATA 0x00000B00
@@ -29,16 +25,16 @@
 #define DDRSS_CTL_08_DATA 0x0001ADAF
 #define DDRSS_CTL_09_DATA 0x00000005
 #define DDRSS_CTL_10_DATA 0x0000006E
-#define DDRSS_CTL_11_DATA 0x0004E200
-#define DDRSS_CTL_12_DATA 0x0030D400
+#define DDRSS_CTL_11_DATA 0x000411AB
+#define DDRSS_CTL_12_DATA 0x0028B0AB
 #define DDRSS_CTL_13_DATA 0x00000005
-#define DDRSS_CTL_14_DATA 0x00000C80
-#define DDRSS_CTL_15_DATA 0x0004E200
-#define DDRSS_CTL_16_DATA 0x0030D400
+#define DDRSS_CTL_14_DATA 0x00000A6B
+#define DDRSS_CTL_15_DATA 0x000411AB
+#define DDRSS_CTL_16_DATA 0x0028B0AB
 #define DDRSS_CTL_17_DATA 0x00000005
-#define DDRSS_CTL_18_DATA 0x00000C80
+#define DDRSS_CTL_18_DATA 0x00000A6B
 #define DDRSS_CTL_19_DATA 0x01010000
-#define DDRSS_CTL_20_DATA 0x01011001
+#define DDRSS_CTL_20_DATA 0x02011001
 #define DDRSS_CTL_21_DATA 0x02010000
 #define DDRSS_CTL_22_DATA 0x00020100
 #define DDRSS_CTL_23_DATA 0x0000000B
@@ -46,66 +42,66 @@
 #define DDRSS_CTL_25_DATA 0x00000000
 #define DDRSS_CTL_26_DATA 0x00000000
 #define DDRSS_CTL_27_DATA 0x03020200
-#define DDRSS_CTL_28_DATA 0x00004040
+#define DDRSS_CTL_28_DATA 0x00003636
 #define DDRSS_CTL_29_DATA 0x00100000
 #define DDRSS_CTL_30_DATA 0x00000000
 #define DDRSS_CTL_31_DATA 0x00000000
 #define DDRSS_CTL_32_DATA 0x00000000
 #define DDRSS_CTL_33_DATA 0x00000000
 #define DDRSS_CTL_34_DATA 0x040C0000
-#define DDRSS_CTL_35_DATA 0x0E400E40
+#define DDRSS_CTL_35_DATA 0x0E380E38
 #define DDRSS_CTL_36_DATA 0x00050804
 #define DDRSS_CTL_37_DATA 0x09040008
-#define DDRSS_CTL_38_DATA 0x14000304
-#define DDRSS_CTL_39_DATA 0x15480068
-#define DDRSS_CTL_40_DATA 0x14004220
-#define DDRSS_CTL_41_DATA 0x15480068
-#define DDRSS_CTL_42_DATA 0x20004220
+#define DDRSS_CTL_38_DATA 0x0D000204
+#define DDRSS_CTL_39_DATA 0x113C0057
+#define DDRSS_CTL_40_DATA 0x0D00291B
+#define DDRSS_CTL_41_DATA 0x113C0057
+#define DDRSS_CTL_42_DATA 0x2000291B
 #define DDRSS_CTL_43_DATA 0x000A0A09
 #define DDRSS_CTL_44_DATA 0x040003C5
-#define DDRSS_CTL_45_DATA 0x17100D04
-#define DDRSS_CTL_46_DATA 0x0C006DB0
-#define DDRSS_CTL_47_DATA 0x17100D0C
-#define DDRSS_CTL_48_DATA 0x0C006DB0
-#define DDRSS_CTL_49_DATA 0x0203040C
-#define DDRSS_CTL_50_DATA 0x21060500
-#define DDRSS_CTL_51_DATA 0x08222122
+#define DDRSS_CTL_45_DATA 0x130E0B04
+#define DDRSS_CTL_46_DATA 0x0A005B68
+#define DDRSS_CTL_47_DATA 0x130E0B0A
+#define DDRSS_CTL_48_DATA 0x0A005B68
+#define DDRSS_CTL_49_DATA 0x0203040A
+#define DDRSS_CTL_50_DATA 0x1C040500
+#define DDRSS_CTL_51_DATA 0x081D1C1D
 #define DDRSS_CTL_52_DATA 0x14000E0A
-#define DDRSS_CTL_53_DATA 0x03010A0A
-#define DDRSS_CTL_54_DATA 0x01010003
-#define DDRSS_CTL_55_DATA 0x0442420A
-#define DDRSS_CTL_56_DATA 0x04252504
-#define DDRSS_CTL_57_DATA 0x00002525
+#define DDRSS_CTL_53_DATA 0x02010A0A
+#define DDRSS_CTL_54_DATA 0x01010002
+#define DDRSS_CTL_55_DATA 0x04383808
+#define DDRSS_CTL_56_DATA 0x041F1F04
+#define DDRSS_CTL_57_DATA 0x00001F1F
 #define DDRSS_CTL_58_DATA 0x00010100
 #define DDRSS_CTL_59_DATA 0x03010000
 #define DDRSS_CTL_60_DATA 0x00001008
-#define DDRSS_CTL_61_DATA 0x00000068
-#define DDRSS_CTL_62_DATA 0x000001C0
-#define DDRSS_CTL_63_DATA 0x00000C28
-#define DDRSS_CTL_64_DATA 0x000001C0
-#define DDRSS_CTL_65_DATA 0x00000C28
+#define DDRSS_CTL_61_DATA 0x00000063
+#define DDRSS_CTL_62_DATA 0x00000176
+#define DDRSS_CTL_63_DATA 0x00000A20
+#define DDRSS_CTL_64_DATA 0x00000176
+#define DDRSS_CTL_65_DATA 0x00000A20
 #define DDRSS_CTL_66_DATA 0x00000005
 #define DDRSS_CTL_67_DATA 0x00040000
-#define DDRSS_CTL_68_DATA 0x00700005
-#define DDRSS_CTL_69_DATA 0x0070017E
-#define DDRSS_CTL_70_DATA 0x0040017E
+#define DDRSS_CTL_68_DATA 0x005D0012
+#define DDRSS_CTL_69_DATA 0x005D0282
+#define DDRSS_CTL_70_DATA 0x00400282
 #define DDRSS_CTL_71_DATA 0x00120103
-#define DDRSS_CTL_72_DATA 0x000C0005
-#define DDRSS_CTL_73_DATA 0x2408000C
-#define DDRSS_CTL_74_DATA 0x05050124
+#define DDRSS_CTL_72_DATA 0x000A0005
+#define DDRSS_CTL_73_DATA 0x1F08000A
+#define DDRSS_CTL_74_DATA 0x0505011F
 #define DDRSS_CTL_75_DATA 0x0301030A
-#define DDRSS_CTL_76_DATA 0x03170C08
-#define DDRSS_CTL_77_DATA 0x0C080301
-#define DDRSS_CTL_78_DATA 0x00010317
+#define DDRSS_CTL_76_DATA 0x03130A07
+#define DDRSS_CTL_77_DATA 0x0A070301
+#define DDRSS_CTL_78_DATA 0x00010313
 #define DDRSS_CTL_79_DATA 0x00100010
-#define DDRSS_CTL_80_DATA 0x01CC01CC
-#define DDRSS_CTL_81_DATA 0x01CC01CC
+#define DDRSS_CTL_80_DATA 0x01800180
+#define DDRSS_CTL_81_DATA 0x01800180
 #define DDRSS_CTL_82_DATA 0x03050505
 #define DDRSS_CTL_83_DATA 0x03010303
-#define DDRSS_CTL_84_DATA 0x18080C08
-#define DDRSS_CTL_85_DATA 0x03030C03
-#define DDRSS_CTL_86_DATA 0x18080C08
-#define DDRSS_CTL_87_DATA 0x03030C03
+#define DDRSS_CTL_84_DATA 0x14070A07
+#define DDRSS_CTL_85_DATA 0x03030A03
+#define DDRSS_CTL_86_DATA 0x14070A07
+#define DDRSS_CTL_87_DATA 0x03030A03
 #define DDRSS_CTL_88_DATA 0x03010000
 #define DDRSS_CTL_89_DATA 0x00010000
 #define DDRSS_CTL_90_DATA 0x00000000
@@ -127,20 +123,20 @@
 #define DDRSS_CTL_106_DATA 0x000018C0
 #define DDRSS_CTL_107_DATA 0x00000000
 #define DDRSS_CTL_108_DATA 0x000002B5
-#define DDRSS_CTL_109_DATA 0x00030A00
-#define DDRSS_CTL_110_DATA 0x00030A00
-#define DDRSS_CTL_111_DATA 0x00030A00
-#define DDRSS_CTL_112_DATA 0x00030A00
-#define DDRSS_CTL_113_DATA 0x00030A00
+#define DDRSS_CTL_109_DATA 0x00028800
+#define DDRSS_CTL_110_DATA 0x00028800
+#define DDRSS_CTL_111_DATA 0x00028800
+#define DDRSS_CTL_112_DATA 0x00028800
+#define DDRSS_CTL_113_DATA 0x00028800
 #define DDRSS_CTL_114_DATA 0x00000000
-#define DDRSS_CTL_115_DATA 0x00005518
-#define DDRSS_CTL_116_DATA 0x00030A00
-#define DDRSS_CTL_117_DATA 0x00030A00
-#define DDRSS_CTL_118_DATA 0x00030A00
-#define DDRSS_CTL_119_DATA 0x00030A00
-#define DDRSS_CTL_120_DATA 0x00030A00
+#define DDRSS_CTL_115_DATA 0x000046E0
+#define DDRSS_CTL_116_DATA 0x00028800
+#define DDRSS_CTL_117_DATA 0x00028800
+#define DDRSS_CTL_118_DATA 0x00028800
+#define DDRSS_CTL_119_DATA 0x00028800
+#define DDRSS_CTL_120_DATA 0x00028800
 #define DDRSS_CTL_121_DATA 0x00000000
-#define DDRSS_CTL_122_DATA 0x00005518
+#define DDRSS_CTL_122_DATA 0x000046E0
 #define DDRSS_CTL_123_DATA 0x00000000
 #define DDRSS_CTL_124_DATA 0x00000000
 #define DDRSS_CTL_125_DATA 0x00000000
@@ -149,8 +145,8 @@
 #define DDRSS_CTL_128_DATA 0x00000000
 #define DDRSS_CTL_129_DATA 0x00000000
 #define DDRSS_CTL_130_DATA 0x00000000
-#define DDRSS_CTL_131_DATA 0x08030500
-#define DDRSS_CTL_132_DATA 0x00030803
+#define DDRSS_CTL_131_DATA 0x07030500
+#define DDRSS_CTL_132_DATA 0x00030703
 #define DDRSS_CTL_133_DATA 0x0A090000
 #define DDRSS_CTL_134_DATA 0x0A090701
 #define DDRSS_CTL_135_DATA 0x0900000E
@@ -185,31 +181,31 @@
 #define DDRSS_CTL_164_DATA 0x000B0000
 #define DDRSS_CTL_165_DATA 0x000E0006
 #define DDRSS_CTL_166_DATA 0x000E0404
-#define DDRSS_CTL_167_DATA 0x00A00140
-#define DDRSS_CTL_168_DATA 0x0C0C0190
-#define DDRSS_CTL_169_DATA 0x01400190
-#define DDRSS_CTL_170_DATA 0x019000A0
-#define DDRSS_CTL_171_DATA 0x01900C0C
+#define DDRSS_CTL_167_DATA 0x0086010B
+#define DDRSS_CTL_168_DATA 0x0A0A014E
+#define DDRSS_CTL_169_DATA 0x010B014E
+#define DDRSS_CTL_170_DATA 0x014E0086
+#define DDRSS_CTL_171_DATA 0x014E0A0A
 #define DDRSS_CTL_172_DATA 0x00000000
 #define DDRSS_CTL_173_DATA 0x00000000
 #define DDRSS_CTL_174_DATA 0x00000000
 #define DDRSS_CTL_175_DATA 0x2DD40084
-#define DDRSS_CTL_176_DATA 0xEB002DD4
-#define DDRSS_CTL_177_DATA 0x0000EBEB
+#define DDRSS_CTL_176_DATA 0xAB002DD4
+#define DDRSS_CTL_177_DATA 0x0000ABAB
 #define DDRSS_CTL_178_DATA 0x36000000
 #define DDRSS_CTL_179_DATA 0x27270036
 #define DDRSS_CTL_180_DATA 0x0F0F0000
 #define DDRSS_CTL_181_DATA 0x15000000
 #define DDRSS_CTL_182_DATA 0x00841515
 #define DDRSS_CTL_183_DATA 0x2DD42DD4
-#define DDRSS_CTL_184_DATA 0xEBEBEB00
+#define DDRSS_CTL_184_DATA 0xABABAB00
 #define DDRSS_CTL_185_DATA 0x00000000
 #define DDRSS_CTL_186_DATA 0x00363600
 #define DDRSS_CTL_187_DATA 0x00002727
 #define DDRSS_CTL_188_DATA 0x00000F0F
 #define DDRSS_CTL_189_DATA 0x15151500
 #define DDRSS_CTL_190_DATA 0x00000020
-#define DDRSS_CTL_191_DATA 0x01000000
+#define DDRSS_CTL_191_DATA 0x00000000
 #define DDRSS_CTL_192_DATA 0x00000001
 #define DDRSS_CTL_193_DATA 0x00000000
 #define DDRSS_CTL_194_DATA 0x01000000
@@ -279,24 +275,24 @@
 #define DDRSS_CTL_258_DATA 0x00370040
 #define DDRSS_CTL_259_DATA 0x00020008
 #define DDRSS_CTL_260_DATA 0x00400100
-#define DDRSS_CTL_261_DATA 0x00300640
+#define DDRSS_CTL_261_DATA 0x00280536
 #define DDRSS_CTL_262_DATA 0x01000200
-#define DDRSS_CTL_263_DATA 0x06400040
-#define DDRSS_CTL_264_DATA 0x00000030
-#define DDRSS_CTL_265_DATA 0x00500003
-#define DDRSS_CTL_266_DATA 0x01000050
-#define DDRSS_CTL_267_DATA 0x03030303
+#define DDRSS_CTL_263_DATA 0x05360040
+#define DDRSS_CTL_264_DATA 0x00000028
+#define DDRSS_CTL_265_DATA 0x00430003
+#define DDRSS_CTL_266_DATA 0x01000043
+#define DDRSS_CTL_267_DATA 0x01010101
 #define DDRSS_CTL_268_DATA 0x01010000
 #define DDRSS_CTL_269_DATA 0x00000202
 #define DDRSS_CTL_270_DATA 0x00000FFF
-#define DDRSS_CTL_271_DATA 0x1FFF1000
+#define DDRSS_CTL_271_DATA 0xFFFFFFFF
 #define DDRSS_CTL_272_DATA 0x01FF0000
-#define DDRSS_CTL_273_DATA 0x000101FF
+#define DDRSS_CTL_273_DATA 0x000001FF
 #define DDRSS_CTL_274_DATA 0x0FFF0B00
 #define DDRSS_CTL_275_DATA 0x01010001
 #define DDRSS_CTL_276_DATA 0x01010101
 #define DDRSS_CTL_277_DATA 0x01180101
-#define DDRSS_CTL_278_DATA 0x00030000
+#define DDRSS_CTL_278_DATA 0x00010000
 #define DDRSS_CTL_279_DATA 0x00000000
 #define DDRSS_CTL_280_DATA 0x00000000
 #define DDRSS_CTL_281_DATA 0x00000000
@@ -305,18 +301,18 @@
 #define DDRSS_CTL_284_DATA 0x00000000
 #define DDRSS_CTL_285_DATA 0x00000000
 #define DDRSS_CTL_286_DATA 0x00040101
-#define DDRSS_CTL_287_DATA 0x04010100
+#define DDRSS_CTL_287_DATA 0x00000100
 #define DDRSS_CTL_288_DATA 0x00000000
 #define DDRSS_CTL_289_DATA 0x00000000
 #define DDRSS_CTL_290_DATA 0x03030300
-#define DDRSS_CTL_291_DATA 0x00010101
+#define DDRSS_CTL_291_DATA 0x00000101
 #define DDRSS_CTL_292_DATA 0x00000000
 #define DDRSS_CTL_293_DATA 0x00000000
 #define DDRSS_CTL_294_DATA 0x00000000
 #define DDRSS_CTL_295_DATA 0x00000000
 #define DDRSS_CTL_296_DATA 0x00000000
-#define DDRSS_CTL_297_DATA 0xFFFFFFFF
-#define DDRSS_CTL_298_DATA 0x00000FFF
+#define DDRSS_CTL_297_DATA 0x00000000
+#define DDRSS_CTL_298_DATA 0x00000000
 #define DDRSS_CTL_299_DATA 0x00000000
 #define DDRSS_CTL_300_DATA 0x00000000
 #define DDRSS_CTL_301_DATA 0x00000000
@@ -336,15 +332,15 @@
 #define DDRSS_CTL_315_DATA 0x01000101
 #define DDRSS_CTL_316_DATA 0x01010001
 #define DDRSS_CTL_317_DATA 0x00010101
-#define DDRSS_CTL_318_DATA 0x05080803
-#define DDRSS_CTL_319_DATA 0x0C081C1C
-#define DDRSS_CTL_320_DATA 0x0009030C
-#define DDRSS_CTL_321_DATA 0x090B030F
-#define DDRSS_CTL_322_DATA 0x090B0306
-#define DDRSS_CTL_323_DATA 0x0B090006
-#define DDRSS_CTL_324_DATA 0x0100000B
-#define DDRSS_CTL_325_DATA 0x06030601
-#define DDRSS_CTL_326_DATA 0x00000003
+#define DDRSS_CTL_318_DATA 0x05090903
+#define DDRSS_CTL_319_DATA 0x0A081818
+#define DDRSS_CTL_320_DATA 0x0009030A
+#define DDRSS_CTL_321_DATA 0x080C030F
+#define DDRSS_CTL_322_DATA 0x080C0306
+#define DDRSS_CTL_323_DATA 0x0C090006
+#define DDRSS_CTL_324_DATA 0x0100000C
+#define DDRSS_CTL_325_DATA 0x05020501
+#define DDRSS_CTL_326_DATA 0x00000002
 #define DDRSS_CTL_327_DATA 0x00000000
 #define DDRSS_CTL_328_DATA 0x00010000
 #define DDRSS_CTL_329_DATA 0x00280D00
@@ -405,32 +401,32 @@
 #define DDRSS_CTL_384_DATA 0x00000000
 #define DDRSS_CTL_385_DATA 0x00000000
 #define DDRSS_CTL_386_DATA 0x00000000
-#define DDRSS_CTL_387_DATA 0x33331B00
+#define DDRSS_CTL_387_DATA 0x2E2E1B00
 #define DDRSS_CTL_388_DATA 0x000A0000
 #define DDRSS_CTL_389_DATA 0x000000C6
 #define DDRSS_CTL_390_DATA 0x00000200
 #define DDRSS_CTL_391_DATA 0x00000200
 #define DDRSS_CTL_392_DATA 0x00000200
 #define DDRSS_CTL_393_DATA 0x00000200
-#define DDRSS_CTL_394_DATA 0x00000270
+#define DDRSS_CTL_394_DATA 0x00000252
 #define DDRSS_CTL_395_DATA 0x000007BC
 #define DDRSS_CTL_396_DATA 0x00000204
-#define DDRSS_CTL_397_DATA 0x00001850
+#define DDRSS_CTL_397_DATA 0x00001440
 #define DDRSS_CTL_398_DATA 0x00000200
 #define DDRSS_CTL_399_DATA 0x00000200
 #define DDRSS_CTL_400_DATA 0x00000200
 #define DDRSS_CTL_401_DATA 0x00000200
-#define DDRSS_CTL_402_DATA 0x000048F0
-#define DDRSS_CTL_403_DATA 0x0000F320
-#define DDRSS_CTL_404_DATA 0x00000A14
-#define DDRSS_CTL_405_DATA 0x00001850
+#define DDRSS_CTL_402_DATA 0x00003CC0
+#define DDRSS_CTL_403_DATA 0x0000CA80
+#define DDRSS_CTL_404_DATA 0x00000A12
+#define DDRSS_CTL_405_DATA 0x00001440
 #define DDRSS_CTL_406_DATA 0x00000200
 #define DDRSS_CTL_407_DATA 0x00000200
 #define DDRSS_CTL_408_DATA 0x00000200
 #define DDRSS_CTL_409_DATA 0x00000200
-#define DDRSS_CTL_410_DATA 0x000048F0
-#define DDRSS_CTL_411_DATA 0x0000F320
-#define DDRSS_CTL_412_DATA 0x02020A14
+#define DDRSS_CTL_410_DATA 0x00003CC0
+#define DDRSS_CTL_411_DATA 0x0000CA80
+#define DDRSS_CTL_412_DATA 0x02020A12
 #define DDRSS_CTL_413_DATA 0x03030202
 #define DDRSS_CTL_414_DATA 0x00000022
 #define DDRSS_CTL_415_DATA 0x00000000
@@ -441,13 +437,13 @@
 #define DDRSS_CTL_420_DATA 0x00000000
 #define DDRSS_CTL_421_DATA 0x00030000
 #define DDRSS_CTL_422_DATA 0x0007001F
-#define DDRSS_CTL_423_DATA 0x0016002E
-#define DDRSS_CTL_424_DATA 0x0016002E
+#define DDRSS_CTL_423_DATA 0x0013002B
+#define DDRSS_CTL_424_DATA 0x0013002B
 #define DDRSS_CTL_425_DATA 0x00000000
 #define DDRSS_CTL_426_DATA 0x00000000
 #define DDRSS_CTL_427_DATA 0x02000000
 #define DDRSS_CTL_428_DATA 0x01000404
-#define DDRSS_CTL_429_DATA 0x071A071A
+#define DDRSS_CTL_429_DATA 0x07160716
 #define DDRSS_CTL_430_DATA 0x00000105
 #define DDRSS_CTL_431_DATA 0x00010101
 #define DDRSS_CTL_432_DATA 0x00010101
@@ -492,7 +488,7 @@
 #define DDRSS_PI_11_DATA 0x00000000
 #define DDRSS_PI_12_DATA 0x00000003
 #define DDRSS_PI_13_DATA 0x00010001
-#define DDRSS_PI_14_DATA 0x0800000F
+#define DDRSS_PI_14_DATA 0x08000005
 #define DDRSS_PI_15_DATA 0x00000103
 #define DDRSS_PI_16_DATA 0x00000005
 #define DDRSS_PI_17_DATA 0x00000000
@@ -507,7 +503,7 @@
 #define DDRSS_PI_26_DATA 0x00010100
 #define DDRSS_PI_27_DATA 0x00280A00
 #define DDRSS_PI_28_DATA 0x00000000
-#define DDRSS_PI_29_DATA 0x0F000000
+#define DDRSS_PI_29_DATA 0x05000000
 #define DDRSS_PI_30_DATA 0x00003200
 #define DDRSS_PI_31_DATA 0x00000000
 #define DDRSS_PI_32_DATA 0x00000000
@@ -523,8 +519,8 @@
 #define DDRSS_PI_42_DATA 0x000000B5
 #define DDRSS_PI_43_DATA 0x00000000
 #define DDRSS_PI_44_DATA 0x00000000
-#define DDRSS_PI_45_DATA 0x000F0F00
-#define DDRSS_PI_46_DATA 0x00000019
+#define DDRSS_PI_45_DATA 0x00050500
+#define DDRSS_PI_46_DATA 0x00000017
 #define DDRSS_PI_47_DATA 0x000007D0
 #define DDRSS_PI_48_DATA 0x00000300
 #define DDRSS_PI_49_DATA 0x00000000
@@ -533,7 +529,7 @@
 #define DDRSS_PI_52_DATA 0x00010101
 #define DDRSS_PI_53_DATA 0x00000000
 #define DDRSS_PI_54_DATA 0x00030000
-#define DDRSS_PI_55_DATA 0x0F000000
+#define DDRSS_PI_55_DATA 0x05000000
 #define DDRSS_PI_56_DATA 0x00000017
 #define DDRSS_PI_57_DATA 0x00000000
 #define DDRSS_PI_58_DATA 0x00000000
@@ -545,7 +541,7 @@
 #define DDRSS_PI_64_DATA 0x00000000
 #define DDRSS_PI_65_DATA 0x00000000
 #define DDRSS_PI_66_DATA 0x01000100
-#define DDRSS_PI_67_DATA 0x0102020F
+#define DDRSS_PI_67_DATA 0x01020205
 #define DDRSS_PI_68_DATA 0x00340000
 #define DDRSS_PI_69_DATA 0x00000000
 #define DDRSS_PI_70_DATA 0x00000000
@@ -639,20 +635,20 @@
 #define DDRSS_PI_158_DATA 0x00000000
 #define DDRSS_PI_159_DATA 0x00000401
 #define DDRSS_PI_160_DATA 0x00000000
-#define DDRSS_PI_161_DATA 0x05010000
-#define DDRSS_PI_162_DATA 0x00000001
-#define DDRSS_PI_163_DATA 0x20200201
+#define DDRSS_PI_161_DATA 0x00010000
+#define DDRSS_PI_162_DATA 0x00000000
+#define DDRSS_PI_163_DATA 0x1B1B0200
 #define DDRSS_PI_164_DATA 0x00000034
-#define DDRSS_PI_165_DATA 0x0000005C
-#define DDRSS_PI_166_DATA 0x0002005C
+#define DDRSS_PI_165_DATA 0x00000055
+#define DDRSS_PI_166_DATA 0x00020055
 #define DDRSS_PI_167_DATA 0x02000200
-#define DDRSS_PI_168_DATA 0x400E0C04
-#define DDRSS_PI_169_DATA 0x0010400E
-#define DDRSS_PI_170_DATA 0x00000068
-#define DDRSS_PI_171_DATA 0x000001C0
-#define DDRSS_PI_172_DATA 0x00000C28
-#define DDRSS_PI_173_DATA 0x000001C0
-#define DDRSS_PI_174_DATA 0x04000C28
+#define DDRSS_PI_168_DATA 0x380E0C04
+#define DDRSS_PI_169_DATA 0x0010380E
+#define DDRSS_PI_170_DATA 0x00000063
+#define DDRSS_PI_171_DATA 0x00000176
+#define DDRSS_PI_172_DATA 0x00000A20
+#define DDRSS_PI_173_DATA 0x00000176
+#define DDRSS_PI_174_DATA 0x04000A20
 #define DDRSS_PI_175_DATA 0x01010404
 #define DDRSS_PI_176_DATA 0x00001500
 #define DDRSS_PI_177_DATA 0x00150015
@@ -663,80 +659,80 @@
 #define DDRSS_PI_182_DATA 0x00010000
 #define DDRSS_PI_183_DATA 0x00010100
 #define DDRSS_PI_184_DATA 0x00010100
-#define DDRSS_PI_185_DATA 0x14040100
-#define DDRSS_PI_186_DATA 0x0A0A0214
+#define DDRSS_PI_185_DATA 0x12040100
+#define DDRSS_PI_186_DATA 0x0A0A0212
 #define DDRSS_PI_187_DATA 0x00040402
 #define DDRSS_PI_188_DATA 0x000D0035
-#define DDRSS_PI_189_DATA 0x001C0044
-#define DDRSS_PI_190_DATA 0x001C0044
+#define DDRSS_PI_189_DATA 0x00198041
+#define DDRSS_PI_190_DATA 0x00198041
 #define DDRSS_PI_191_DATA 0x01000101
-#define DDRSS_PI_192_DATA 0x0003000E
-#define DDRSS_PI_193_DATA 0x00030190
-#define DDRSS_PI_194_DATA 0x01000190
+#define DDRSS_PI_192_DATA 0x0002000E
+#define DDRSS_PI_193_DATA 0x0002014E
+#define DDRSS_PI_194_DATA 0x0100014E
 #define DDRSS_PI_195_DATA 0x000F000F
-#define DDRSS_PI_196_DATA 0x01910100
-#define DDRSS_PI_197_DATA 0x01000191
-#define DDRSS_PI_198_DATA 0x01910191
-#define DDRSS_PI_199_DATA 0x2F1B3200
-#define DDRSS_PI_200_DATA 0x01012F1B
+#define DDRSS_PI_196_DATA 0x014F0100
+#define DDRSS_PI_197_DATA 0x0100014F
+#define DDRSS_PI_198_DATA 0x014F014F
+#define DDRSS_PI_199_DATA 0x32103200
+#define DDRSS_PI_200_DATA 0x01013210
 #define DDRSS_PI_201_DATA 0x0A070601
-#define DDRSS_PI_202_DATA 0x180F090D
-#define DDRSS_PI_203_DATA 0x180F0911
-#define DDRSS_PI_204_DATA 0x0000C011
+#define DDRSS_PI_202_DATA 0x140D080D
+#define DDRSS_PI_203_DATA 0x140D0810
+#define DDRSS_PI_204_DATA 0x0000C010
 #define DDRSS_PI_205_DATA 0x00C01000
 #define DDRSS_PI_206_DATA 0x00C01000
 #define DDRSS_PI_207_DATA 0x00021000
-#define DDRSS_PI_208_DATA 0x001E000E
-#define DDRSS_PI_209_DATA 0x001E0190
-#define DDRSS_PI_210_DATA 0x00110190
+#define DDRSS_PI_208_DATA 0x001C000E
+#define DDRSS_PI_209_DATA 0x001C014E
+#define DDRSS_PI_210_DATA 0x0011014E
 #define DDRSS_PI_211_DATA 0x32000056
-#define DDRSS_PI_212_DATA 0x00000101
-#define DDRSS_PI_213_DATA 0x005E0030
+#define DDRSS_PI_212_DATA 0x00000301
+#define DDRSS_PI_213_DATA 0x005C002C
 #define DDRSS_PI_214_DATA 0x03013212
-#define DDRSS_PI_215_DATA 0x00003000
-#define DDRSS_PI_216_DATA 0x3212005E
+#define DDRSS_PI_215_DATA 0x00002C00
+#define DDRSS_PI_216_DATA 0x3212005C
 #define DDRSS_PI_217_DATA 0x09000001
-#define DDRSS_PI_218_DATA 0x06010504
+#define DDRSS_PI_218_DATA 0x04010504
 #define DDRSS_PI_219_DATA 0x04000364
 #define DDRSS_PI_220_DATA 0x0A032001
-#define DDRSS_PI_221_DATA 0x21250D0A
-#define DDRSS_PI_222_DATA 0x00002216
-#define DDRSS_PI_223_DATA 0x480062B8
-#define DDRSS_PI_224_DATA 0x17182006
-#define DDRSS_PI_225_DATA 0x21250D10
-#define DDRSS_PI_226_DATA 0x00002216
-#define DDRSS_PI_227_DATA 0x480062B8
-#define DDRSS_PI_228_DATA 0x17182006
-#define DDRSS_PI_229_DATA 0x0000C610
+#define DDRSS_PI_221_DATA 0x1C1F0B0A
+#define DDRSS_PI_222_DATA 0x00001D12
+#define DDRSS_PI_223_DATA 0x3C005244
+#define DDRSS_PI_224_DATA 0x13142005
+#define DDRSS_PI_225_DATA 0x1C1F0B0E
+#define DDRSS_PI_226_DATA 0x00001D12
+#define DDRSS_PI_227_DATA 0x3C005244
+#define DDRSS_PI_228_DATA 0x13142005
+#define DDRSS_PI_229_DATA 0x0000C60E
 #define DDRSS_PI_230_DATA 0x000007BC
-#define DDRSS_PI_231_DATA 0x00001850
-#define DDRSS_PI_232_DATA 0x0000F320
-#define DDRSS_PI_233_DATA 0x00001850
-#define DDRSS_PI_234_DATA 0x0000F320
-#define DDRSS_PI_235_DATA 0x01CC0010
-#define DDRSS_PI_236_DATA 0x030301CC
+#define DDRSS_PI_231_DATA 0x00001440
+#define DDRSS_PI_232_DATA 0x0000CA80
+#define DDRSS_PI_233_DATA 0x00001440
+#define DDRSS_PI_234_DATA 0x0000CA80
+#define DDRSS_PI_235_DATA 0x01800010
+#define DDRSS_PI_236_DATA 0x03030180
 #define DDRSS_PI_237_DATA 0x002AF803
 #define DDRSS_PI_238_DATA 0x0001ADAF
 #define DDRSS_PI_239_DATA 0x00000005
 #define DDRSS_PI_240_DATA 0x0000006E
 #define DDRSS_PI_241_DATA 0x00000010
-#define DDRSS_PI_242_DATA 0x0004E200
+#define DDRSS_PI_242_DATA 0x000411AB
 #define DDRSS_PI_243_DATA 0x0001ADAF
 #define DDRSS_PI_244_DATA 0x00000005
-#define DDRSS_PI_245_DATA 0x00000C80
-#define DDRSS_PI_246_DATA 0x000001CC
-#define DDRSS_PI_247_DATA 0x0004E200
+#define DDRSS_PI_245_DATA 0x00000A6B
+#define DDRSS_PI_246_DATA 0x00000180
+#define DDRSS_PI_247_DATA 0x000411AB
 #define DDRSS_PI_248_DATA 0x0001ADAF
 #define DDRSS_PI_249_DATA 0x00000005
-#define DDRSS_PI_250_DATA 0x00000C80
-#define DDRSS_PI_251_DATA 0x010001CC
+#define DDRSS_PI_250_DATA 0x00000A6B
+#define DDRSS_PI_251_DATA 0x01000180
 #define DDRSS_PI_252_DATA 0x00370040
 #define DDRSS_PI_253_DATA 0x00010008
-#define DDRSS_PI_254_DATA 0x06400040
-#define DDRSS_PI_255_DATA 0x00010030
-#define DDRSS_PI_256_DATA 0x06400040
-#define DDRSS_PI_257_DATA 0x00000330
-#define DDRSS_PI_258_DATA 0x00500050
+#define DDRSS_PI_254_DATA 0x05360040
+#define DDRSS_PI_255_DATA 0x00010028
+#define DDRSS_PI_256_DATA 0x05360040
+#define DDRSS_PI_257_DATA 0x00000328
+#define DDRSS_PI_258_DATA 0x00430043
 #define DDRSS_PI_259_DATA 0x08040404
 #define DDRSS_PI_260_DATA 0x00000055
 #define DDRSS_PI_261_DATA 0x55083C5A
@@ -753,29 +749,29 @@
 #define DDRSS_PI_272_DATA 0x00080804
 #define DDRSS_PI_273_DATA 0x00000000
 #define DDRSS_PI_274_DATA 0x00000000
-#define DDRSS_PI_275_DATA 0x00EB0084
+#define DDRSS_PI_275_DATA 0x00AB0084
 #define DDRSS_PI_276_DATA 0x00150000
-#define DDRSS_PI_277_DATA 0x36EB2DD4
+#define DDRSS_PI_277_DATA 0x36AB2DD4
 #define DDRSS_PI_278_DATA 0x00150F27
-#define DDRSS_PI_279_DATA 0x36EB2DD4
+#define DDRSS_PI_279_DATA 0x36AB2DD4
 #define DDRSS_PI_280_DATA 0x00150F27
-#define DDRSS_PI_281_DATA 0x00EB0084
+#define DDRSS_PI_281_DATA 0x00AB0084
 #define DDRSS_PI_282_DATA 0x00150000
-#define DDRSS_PI_283_DATA 0x36EB2DD4
+#define DDRSS_PI_283_DATA 0x36AB2DD4
 #define DDRSS_PI_284_DATA 0x00150F27
-#define DDRSS_PI_285_DATA 0x36EB2DD4
+#define DDRSS_PI_285_DATA 0x36AB2DD4
 #define DDRSS_PI_286_DATA 0x00150F27
-#define DDRSS_PI_287_DATA 0x00EB0084
+#define DDRSS_PI_287_DATA 0x00AB0084
 #define DDRSS_PI_288_DATA 0x00150000
-#define DDRSS_PI_289_DATA 0x36EB2DD4
+#define DDRSS_PI_289_DATA 0x36AB2DD4
 #define DDRSS_PI_290_DATA 0x00150F27
-#define DDRSS_PI_291_DATA 0x36EB2DD4
+#define DDRSS_PI_291_DATA 0x36AB2DD4
 #define DDRSS_PI_292_DATA 0x00150F27
-#define DDRSS_PI_293_DATA 0x00EB0084
+#define DDRSS_PI_293_DATA 0x00AB0084
 #define DDRSS_PI_294_DATA 0x00150000
-#define DDRSS_PI_295_DATA 0x36EB2DD4
+#define DDRSS_PI_295_DATA 0x36AB2DD4
 #define DDRSS_PI_296_DATA 0x00150F27
-#define DDRSS_PI_297_DATA 0x36EB2DD4
+#define DDRSS_PI_297_DATA 0x36AB2DD4
 #define DDRSS_PI_298_DATA 0x00150F27
 #define DDRSS_PI_299_DATA 0x00000000
 
@@ -881,10 +877,10 @@
 #define DDRSS_PHY_99_DATA 0x31C06000
 #define DDRSS_PHY_100_DATA 0x07AB01AB
 #define DDRSS_PHY_101_DATA 0x00C0C001
-#define DDRSS_PHY_102_DATA 0x0B0A0101
+#define DDRSS_PHY_102_DATA 0x09080001
 #define DDRSS_PHY_103_DATA 0x10001000
-#define DDRSS_PHY_104_DATA 0x0C073E42
-#define DDRSS_PHY_105_DATA 0x0F0C2D01
+#define DDRSS_PHY_104_DATA 0x0C063E42
+#define DDRSS_PHY_105_DATA 0x0F0C2701
 #define DDRSS_PHY_106_DATA 0x01000140
 #define DDRSS_PHY_107_DATA 0x0C000420
 #define DDRSS_PHY_108_DATA 0x00000198
@@ -892,7 +888,7 @@
 #define DDRSS_PHY_110_DATA 0x00030200
 #define DDRSS_PHY_111_DATA 0x02800000
 #define DDRSS_PHY_112_DATA 0x80800000
-#define DDRSS_PHY_113_DATA 0x000B2010
+#define DDRSS_PHY_113_DATA 0x00092010
 #define DDRSS_PHY_114_DATA 0x76543210
 #define DDRSS_PHY_115_DATA 0x00000008
 #define DDRSS_PHY_116_DATA 0x02800280
@@ -909,8 +905,8 @@
 #define DDRSS_PHY_127_DATA 0x00A000A0
 #define DDRSS_PHY_128_DATA 0x00A000A0
 #define DDRSS_PHY_129_DATA 0x00A000A0
-#define DDRSS_PHY_130_DATA 0x011900A0
-#define DDRSS_PHY_131_DATA 0x01A00004
+#define DDRSS_PHY_130_DATA 0x01C400A0
+#define DDRSS_PHY_131_DATA 0x01A00003
 #define DDRSS_PHY_132_DATA 0x00000000
 #define DDRSS_PHY_133_DATA 0x00000000
 #define DDRSS_PHY_134_DATA 0x00080200
@@ -1137,10 +1133,10 @@
 #define DDRSS_PHY_355_DATA 0x31C06000
 #define DDRSS_PHY_356_DATA 0x07AB01AB
 #define DDRSS_PHY_357_DATA 0x00C0C001
-#define DDRSS_PHY_358_DATA 0x0B0A0101
+#define DDRSS_PHY_358_DATA 0x09080001
 #define DDRSS_PHY_359_DATA 0x10001000
-#define DDRSS_PHY_360_DATA 0x0C073E42
-#define DDRSS_PHY_361_DATA 0x0F0C2D01
+#define DDRSS_PHY_360_DATA 0x0C063E42
+#define DDRSS_PHY_361_DATA 0x0F0C2701
 #define DDRSS_PHY_362_DATA 0x01000140
 #define DDRSS_PHY_363_DATA 0x0C000420
 #define DDRSS_PHY_364_DATA 0x00000198
@@ -1148,7 +1144,7 @@
 #define DDRSS_PHY_366_DATA 0x00030200
 #define DDRSS_PHY_367_DATA 0x02800000
 #define DDRSS_PHY_368_DATA 0x80800000
-#define DDRSS_PHY_369_DATA 0x000B2010
+#define DDRSS_PHY_369_DATA 0x00092010
 #define DDRSS_PHY_370_DATA 0x76543210
 #define DDRSS_PHY_371_DATA 0x00000008
 #define DDRSS_PHY_372_DATA 0x02800280
@@ -1165,8 +1161,8 @@
 #define DDRSS_PHY_383_DATA 0x00A000A0
 #define DDRSS_PHY_384_DATA 0x00A000A0
 #define DDRSS_PHY_385_DATA 0x00A000A0
-#define DDRSS_PHY_386_DATA 0x011900A0
-#define DDRSS_PHY_387_DATA 0x01A00004
+#define DDRSS_PHY_386_DATA 0x01C400A0
+#define DDRSS_PHY_387_DATA 0x01A00003
 #define DDRSS_PHY_388_DATA 0x00000000
 #define DDRSS_PHY_389_DATA 0x00000000
 #define DDRSS_PHY_390_DATA 0x00080200
@@ -1393,10 +1389,10 @@
 #define DDRSS_PHY_611_DATA 0x31C06000
 #define DDRSS_PHY_612_DATA 0x07AB01AB
 #define DDRSS_PHY_613_DATA 0x00C0C001
-#define DDRSS_PHY_614_DATA 0x0B0A0101
+#define DDRSS_PHY_614_DATA 0x09080001
 #define DDRSS_PHY_615_DATA 0x10001000
-#define DDRSS_PHY_616_DATA 0x0C073E42
-#define DDRSS_PHY_617_DATA 0x0F0C2D01
+#define DDRSS_PHY_616_DATA 0x0C063E42
+#define DDRSS_PHY_617_DATA 0x0F0C2701
 #define DDRSS_PHY_618_DATA 0x01000140
 #define DDRSS_PHY_619_DATA 0x0C000420
 #define DDRSS_PHY_620_DATA 0x00000198
@@ -1404,7 +1400,7 @@
 #define DDRSS_PHY_622_DATA 0x00030200
 #define DDRSS_PHY_623_DATA 0x02800000
 #define DDRSS_PHY_624_DATA 0x80800000
-#define DDRSS_PHY_625_DATA 0x000B2010
+#define DDRSS_PHY_625_DATA 0x00092010
 #define DDRSS_PHY_626_DATA 0x76543210
 #define DDRSS_PHY_627_DATA 0x00000008
 #define DDRSS_PHY_628_DATA 0x02800280
@@ -1421,8 +1417,8 @@
 #define DDRSS_PHY_639_DATA 0x00A000A0
 #define DDRSS_PHY_640_DATA 0x00A000A0
 #define DDRSS_PHY_641_DATA 0x00A000A0
-#define DDRSS_PHY_642_DATA 0x011900A0
-#define DDRSS_PHY_643_DATA 0x01A00004
+#define DDRSS_PHY_642_DATA 0x01C400A0
+#define DDRSS_PHY_643_DATA 0x01A00003
 #define DDRSS_PHY_644_DATA 0x00000000
 #define DDRSS_PHY_645_DATA 0x00000000
 #define DDRSS_PHY_646_DATA 0x00080200
@@ -1649,10 +1645,10 @@
 #define DDRSS_PHY_867_DATA 0x31C06000
 #define DDRSS_PHY_868_DATA 0x07AB01AB
 #define DDRSS_PHY_869_DATA 0x00C0C001
-#define DDRSS_PHY_870_DATA 0x0B0A0101
+#define DDRSS_PHY_870_DATA 0x09080001
 #define DDRSS_PHY_871_DATA 0x10001000
-#define DDRSS_PHY_872_DATA 0x0C073E42
-#define DDRSS_PHY_873_DATA 0x0F0C2D01
+#define DDRSS_PHY_872_DATA 0x0C063E42
+#define DDRSS_PHY_873_DATA 0x0F0C2701
 #define DDRSS_PHY_874_DATA 0x01000140
 #define DDRSS_PHY_875_DATA 0x0C000420
 #define DDRSS_PHY_876_DATA 0x00000198
@@ -1660,7 +1656,7 @@
 #define DDRSS_PHY_878_DATA 0x00030200
 #define DDRSS_PHY_879_DATA 0x02800000
 #define DDRSS_PHY_880_DATA 0x80800000
-#define DDRSS_PHY_881_DATA 0x000B2010
+#define DDRSS_PHY_881_DATA 0x00092010
 #define DDRSS_PHY_882_DATA 0x76543210
 #define DDRSS_PHY_883_DATA 0x00000008
 #define DDRSS_PHY_884_DATA 0x02800280
@@ -1677,8 +1673,8 @@
 #define DDRSS_PHY_895_DATA 0x00A000A0
 #define DDRSS_PHY_896_DATA 0x00A000A0
 #define DDRSS_PHY_897_DATA 0x00A000A0
-#define DDRSS_PHY_898_DATA 0x011900A0
-#define DDRSS_PHY_899_DATA 0x01A00004
+#define DDRSS_PHY_898_DATA 0x01C400A0
+#define DDRSS_PHY_899_DATA 0x01A00003
 #define DDRSS_PHY_900_DATA 0x00000000
 #define DDRSS_PHY_901_DATA 0x00000000
 #define DDRSS_PHY_902_DATA 0x00080200
@@ -1834,7 +1830,7 @@
 #define DDRSS_PHY_1052_DATA 0x00000033
 #define DDRSS_PHY_1053_DATA 0x00543210
 #define DDRSS_PHY_1054_DATA 0x003F0000
-#define DDRSS_PHY_1055_DATA 0x000F3F3F
+#define DDRSS_PHY_1055_DATA 0x000F013F
 #define DDRSS_PHY_1056_DATA 0x20202003
 #define DDRSS_PHY_1057_DATA 0x00202020
 #define DDRSS_PHY_1058_DATA 0x20008008
@@ -1843,7 +1839,7 @@
 #define DDRSS_PHY_1061_DATA 0x00000000
 #define DDRSS_PHY_1062_DATA 0x00000000
 #define DDRSS_PHY_1063_DATA 0x00000000
-#define DDRSS_PHY_1064_DATA 0x000305CC
+#define DDRSS_PHY_1064_DATA 0x000205CC
 #define DDRSS_PHY_1065_DATA 0x00030000
 #define DDRSS_PHY_1066_DATA 0x00000300
 #define DDRSS_PHY_1067_DATA 0x00000300
@@ -2173,7 +2169,7 @@
 #define DDRSS_PHY_1391_DATA 0x00000000
 #define DDRSS_PHY_1392_DATA 0x00000000
 #define DDRSS_PHY_1393_DATA 0x0001F7C0
-#define DDRSS_PHY_1394_DATA 0x00000003
+#define DDRSS_PHY_1394_DATA 0x00000002
 #define DDRSS_PHY_1395_DATA 0x00000000
 #define DDRSS_PHY_1396_DATA 0x00001142
 #define DDRSS_PHY_1397_DATA 0x040207AB
diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
index 8ed78da612e..6c2f840021f 100644
--- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
@@ -117,7 +117,7 @@
 };
 
 &wkup_vtm0 {
-	vdd-supply-2 = <&buckb1>;
+	vdd-supply-2 = <&bucka1>;
 	bootph-pre-ram;
 };
 
diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c
index 9104d88b0fe..9831c7841a5 100644
--- a/board/ti/j721e/evm.c
+++ b/board/ti/j721e/evm.c
@@ -95,56 +95,17 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
 #ifdef CONFIG_SPL_LOAD_FIT
 int board_fit_config_name_match(const char *name)
 {
-	bool eeprom_read = board_ti_was_eeprom_read();
 
 #if IS_ENABLED(CONFIG_TARGET_J7200_R5_EVM)
 	if (board_is_resuming())
 		if (!strcmp(name, "k3-lpm"))
 			return 0;
 #endif
-	if (!eeprom_read || board_is_j721e_som()) {
-		if (!strcmp(name, "k3-j721e-common-proc-board") ||
-		    !strcmp(name, "k3-j721e-r5-common-proc-board"))
-			return 0;
-	} else if (board_is_j721e_sk()) {
-		if (!strcmp(name, "k3-j721e-sk") ||
-		    !strcmp(name, "k3-j721e-r5-sk"))
-			return 0;
-	}
 
 	return -1;
 }
 #endif
 
-#if CONFIG_IS_ENABLED(DM_GPIO) && CONFIG_IS_ENABLED(OF_LIBFDT)
-/* Returns 1, if onboard mux is set to hyperflash */
-static void __maybe_unused detect_enable_hyperflash(void *blob)
-{
-	struct gpio_desc desc = {0};
-	char *hypermux_sel_gpio = (board_is_j721e_som()) ? "8" : "6";
-
-	if (dm_gpio_lookup_name(hypermux_sel_gpio, &desc))
-		return;
-
-	if (dm_gpio_request(&desc, hypermux_sel_gpio))
-		return;
-
-	if (dm_gpio_set_dir_flags(&desc, GPIOD_IS_IN))
-		return;
-
-	if (dm_gpio_get_value(&desc)) {
-		int offset;
-
-		do_fixup_by_compat(blob, "ti,am654-hbmc", "status",
-				   "okay", sizeof("okay"), 0);
-		offset = fdt_node_offset_by_compatible(blob, -1,
-						       "ti,am654-ospi");
-		fdt_setprop(blob, offset, "status", "disabled",
-			    sizeof("disabled"));
-	}
-}
-#endif
-
 #if defined(CONFIG_XPL_BUILD) && (defined(CONFIG_TARGET_J7200_A72_EVM) || defined(CONFIG_TARGET_J7200_R5_EVM) || \
 					defined(CONFIG_TARGET_J721E_A72_EVM) || defined(CONFIG_TARGET_J721E_R5_EVM))
 void spl_perform_fixups(struct spl_image_info *spl_image)
@@ -153,54 +114,17 @@ void spl_perform_fixups(struct spl_image_info *spl_image)
 	if (board_is_resuming())
 		return;
 #endif
-	detect_enable_hyperflash(spl_image->fdt_addr);
 }
 #endif
 
 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 int ft_board_setup(void *blob, struct bd_info *bd)
 {
-	detect_enable_hyperflash(blob);
-
 	return 0;
 }
 #endif
 
 #ifdef CONFIG_TI_I2C_BOARD_DETECT
-int do_board_detect(void)
-{
-	int ret;
-
-	if (board_ti_was_eeprom_read())
-		return 0;
-
-	ret = ti_i2c_eeprom_am6_get_base(CONFIG_EEPROM_BUS_ADDRESS,
-					 CONFIG_EEPROM_CHIP_ADDRESS);
-	if (ret) {
-		printf("EEPROM not available at 0x%02x, trying to read at 0x%02x\n",
-		       CONFIG_EEPROM_CHIP_ADDRESS, CONFIG_EEPROM_CHIP_ADDRESS + 1);
-		ret = ti_i2c_eeprom_am6_get_base(CONFIG_EEPROM_BUS_ADDRESS,
-						 CONFIG_EEPROM_CHIP_ADDRESS + 1);
-		if (ret)
-			pr_err("Reading on-board EEPROM at 0x%02x failed %d\n",
-			       CONFIG_EEPROM_CHIP_ADDRESS + 1, ret);
-	}
-
-	return ret;
-}
-
-int checkboard(void)
-{
-	struct ti_am6_eeprom *ep = TI_AM6_EEPROM_DATA;
-
-	if (do_board_detect())
-		/* EEPROM not populated */
-		printf("Board: %s rev %s\n", "J721EX-PM1-SOM", "E2");
-	else
-		printf("Board: %s rev %s\n", ep->name, ep->version);
-
-	return 0;
-}
 
 /*
  * Declaration of daughtercards to probe. Note that when adding more
@@ -427,9 +351,6 @@ static void setup_board_eeprom_env(void)
 {
 	char *name = NULL;
 
-	if (do_board_detect())
-		goto invalid_eeprom;
-
 	if (board_is_j721e_som())
 		name = "j721e";
 	else if (board_is_j721e_sk())
@@ -439,10 +360,6 @@ static void setup_board_eeprom_env(void)
 	else
 		printf("Unidentified board claims %s in eeprom header\n",
 		       board_ti_get_name());
-
-invalid_eeprom:
-	set_board_info_env_am6(name);
-	ti_set_fdt_env(name, ti_j721e_evm_fdt_map);
 }
 
 static void setup_serial(void)
@@ -468,7 +385,6 @@ static void setup_serial(void)
 int board_late_init(void)
 {
 	if (IS_ENABLED(CONFIG_TI_I2C_BOARD_DETECT)) {
-		setup_board_eeprom_env();
 		setup_serial();
 
 		/* Check for and probe any plugged-in daughtercards */
@@ -572,14 +488,6 @@ int board_is_resuming(void)
 	}
 	debug("%s: PMICA is detected (%s)\n", __func__, pmica->name);
 
-	ret = uclass_get_device_by_name(UCLASS_PMIC,
-					"pmic@4c", &pmicb);
-	if (ret) {
-		printf("Getting PMICB init failed: %d\n", ret);
-		goto end;
-	}
-	debug("%s: PMICB is detected (%s)\n", __func__, pmicb->name);
-
 	if (pmic_reg_read(pmica, SCRATCH_PAD_REG_3) == MAGIC_SUSPEND) {
 		debug("%s: board is resuming\n", __func__);
 		lpm_scratch->wake_src = LPM_WAKE_SOURCE_PMIC_GPIO;
diff --git a/board/ti/j721e/j721e.env b/board/ti/j721e/j721e.env
index 54cffa52ffc..15362c4e00e 100644
--- a/board/ti/j721e/j721e.env
+++ b/board/ti/j721e/j721e.env
@@ -12,10 +12,137 @@ defined(CONFIG_TARGET_J721E_R5_EVM)
 #include <env/ti/k3_rproc.env>
 #endif
 
+dfu_alt_info_emmc=
+	rootfs raw 0 0x2000000 mmcpart 0;
+	tiboot3.bin.raw raw 0x0 0x600 mmcpart 1;
+	tispl.bin.raw raw 0x600 0xC00 mmcpart 1;
+	u-boot.img.raw raw 0x1200 0xC00 mmcpart 1;
+	u-env.raw raw 0x1E00 0x100 mmcpart 1
+
+bootcmd_ti_mmc=
+	mmc dev ${mmcdev}; mmc rescan;
+	run init_${boot};
+	run update_do_main_cpsw0_qsgmii_phyinit;
+#if CONFIG_CMD_REMOTEPROC
+	if test ${do_main_cpsw0_qsgmii_phyinit} -eq 1;
+		then run main_cpsw0_qsgmii_phyinit;
+	fi;
+	run boot_rprocs;
+#endif
+	if test ${boot_fit} -eq 1;
+		then run get_fit_${boot}; run get_fit_overlaystring; run run_fit;
+	else;
+		run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern;
+	fi;
+
+args_net=
+	setenv bootargs console=${console} ${optargs}
+	root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp
+	rootfstype=nfs
+init_net=
+	echo Booting from net ...;
+	run args_all args_net;
+	if test ${ip_dyn} = yes; then
+		setenv get_cmd dhcp;
+	else
+	setenv get_cmd tftp;
+	fi;
+
+get_fdt_net=${get_cmd} ${fdtaddr} ${default_device_tree}
+get_overlay_net=
+	fdt address ${fdtaddr}; fdt resize 0x100000;
+	for overlay in $name_overlays;
+	do;
+	${get_cmd} ${dtboaddr} ${overlay} &&
+	fdt apply ${dtboaddr};
+	done;
+get_kern_net=${get_cmd} ${loadaddr} ${name_kern}
+get_fit_net=${get_cmd} ${addr_fit} ${name_fit}
+bootcmd_ti_dhcp=
+	run findfdt; run init_net;
+	if test ${do_main_cpsw0_qsgmii_phyinit} -eq 1;
+		then run main_cpsw0_qsgmii_phyinit;
+	fi;
+	run boot_rprocs_dhcp; 
+	if test ${boot_fit} -eq 1; 
+		then run get_fit_net; run get_overlaystring; run run_fit; 
+	else; 
+		if ${get_cmd} ${loadaddr} ${name_kern} && ${get_cmd} ${fdtaddr} ${default_device_tree};
+			then run get_overlay_net; run run_kern;
+		fi;
+	fi
+
+boot_rprocs_dhcp=
+		setenv name_mcur5f0_0fw j7200-mcu-r5f0_0-fw;
+		if test ${dorprocboot} -eq 1 && test ${boot} = dhcp; 
+			then rproc init; run boot_rprocs_tftp; 
+		fi;
+boot_rprocs_tftp=
+		env set rproc_id; env set rproc_fw; env set secure_suffix; 
+		if test ${secure_rprocs} -eq 1; 
+		        then env set secure_suffix -sec; 
+		fi; 
+		for i in ${rproc_fw_binaries_tftp} ; 
+		do 
+		        if test -z "${rproc_id}" ; 
+		                then env set rproc_id $i; 
+		        else 
+				env set rproc_fw $i${secure_suffix}; 
+				run rproc_load_and_boot_tftp; 
+				env set rproc_id; env set rproc_fw; 
+			fi; 
+		done
+
+rproc_load_and_boot_tftp=
+                         if ${get_cmd} $loadaddr ${rproc_fw}; 
+			 then if rproc load ${rproc_id} ${loadaddr} ${filesize}; 
+			              then rproc start ${rproc_id}; 
+	                       fi;
+			  fi
+
+args_mmc=setenv bootpart ${mmcdev}:${mmcpart};
+        run finduuid;setenv bootargs console=${console}
+        ${optargs}
+        root=/dev/mmcblk${mmcdev}p${mmcpart} rw
+        rootfstype=${mmcrootfstype}
+
+get_env=mmc dev ${mmcdev};
+        mmc rescan;
+        load mmc ${mmcdev} ${loadaddr} ${bootenvfile};
+        env import -t ${loadaddr} ${filesize}
+
+save_env=env export -t ${loadaddr};
+        mmc dev ${mmcdev};
+        mmc rescan;
+        fatwrite mmc ${mmcdev}:1 ${loadaddr} ${bootenvfile} $filesize;
+
+loadbootenv=
+	mmc dev ${mmcdev};mmc rescan;
+	load mmc ${mmcdev}:1 ${loadaddr} ${bootenvfile};
+ 
+envboot=if mmc dev ${mmcdev}; then
+        if mmc rescan; then
+                echo SD/MMC found on device ${mmcdev};
+                if test -n "${loadbootscript}" && run loadbootscript; then
+                        run bootscript;
+                else
+                        if run get_env; then
+                                echo Loaded env from ${bootenvfile};
+                        fi;
+                        if test -n $uenvcmd; then
+                                echo Running uenvcmd ...;
+                                run uenvcmd;
+                        fi;
+                fi;
+        fi;
+  fi;
+ethaddr=0a:0b:0c:0d:0e:0f
+eth1addr=1a:2b:3c:4d:5e:6f
+ethact=eth0
 name_kern=Image
+fdtfile=ti/k3-j7200-iwg59s-prgjj-01.dtb
 console=ttyS2,115200n8
 args_all=setenv optargs ${optargs} earlycon=ns16550a,mmio32,0x02800000
-	${mtdparts}
 run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}
 
 #if CONFIG_TARGET_J721E_R5_EVM
@@ -28,14 +155,15 @@ name_mcur5f0_0fw=/lib/firmware/j7200-mcu-r5f0_0-fw
 
 boot_targets=mmc1 mmc0 usb pxe dhcp
 boot=mmc
-mmcdev=1
-bootpart=1:2
+#mmcdev=0
+mmcpart=2
 bootdir=/boot
 rd_spec=-
 dorprocboot=1
+usb_typec=okay
 
 #if CONFIG_TARGET_J7200_A72_EVM
-update_do_main_cpsw0_qsgmii_phyinit=setenv do_main_cpsw0_qsgmii_phyinit 1;
+update_do_main_cpsw0_qsgmii_phyinit=setenv do_main_cpsw0_qsgmii_phyinit 0;
 init_main_cpsw0_qsgmii_phy=gpio set gpio@22_17;
 	gpio clear gpio@22_16
 main_cpsw0_qsgmii_phyinit=
diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
index ea2ec69dcda..16bde968024 100644
--- a/common/spl/spl_mmc.c
+++ b/common/spl/spl_mmc.c
@@ -470,6 +470,6 @@ int spl_mmc_load_image(struct spl_image_info *spl_image,
 #endif
 }
 
-SPL_LOAD_IMAGE_METHOD("MMC1", 0, BOOT_DEVICE_MMC1, spl_mmc_load_image);
-SPL_LOAD_IMAGE_METHOD("MMC2", 0, BOOT_DEVICE_MMC2, spl_mmc_load_image);
+SPL_LOAD_IMAGE_METHOD("MMC0", 0, BOOT_DEVICE_MMC1, spl_mmc_load_image);
+SPL_LOAD_IMAGE_METHOD("MMC1", 0, BOOT_DEVICE_MMC2, spl_mmc_load_image);
 SPL_LOAD_IMAGE_METHOD("MMC2_2", 0, BOOT_DEVICE_MMC2_2, spl_mmc_load_image);
diff --git a/configs/j7200_evm_a72_defconfig b/configs/j7200_evm_a72_defconfig
index 8d9d839a267..fb0d3ed5538 100644
--- a/configs/j7200_evm_a72_defconfig
+++ b/configs/j7200_evm_a72_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_K3=y
+CONFIG_SYS_PROMPT="iWave-G59M > "
 CONFIG_SYS_MALLOC_F_LEN=0x8000
 CONFIG_SPL_GPIO=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
@@ -44,7 +45,7 @@ CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
 CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1800
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1200
 CONFIG_SPL_DMA=y
 CONFIG_SPL_ENV_SUPPORT=y
 CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
@@ -114,7 +115,6 @@ CONFIG_DA8XX_GPIO=y
 CONFIG_DM_PCA953X=y
 CONFIG_DM_I2C=y
 CONFIG_DM_I2C_GPIO=y
-CONFIG_SYS_I2C_OMAP24XX=y
 CONFIG_DM_MAILBOX=y
 CONFIG_K3_SEC_PROXY=y
 CONFIG_SUPPORT_EMMC_BOOT=y
diff --git a/configs/j7200_evm_r5_defconfig b/configs/j7200_evm_r5_defconfig
index b2829d817cd..963db06ef16 100644
--- a/configs/j7200_evm_r5_defconfig
+++ b/configs/j7200_evm_r5_defconfig
@@ -43,7 +43,7 @@ CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xa3000000
 CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000
 CONFIG_SPL_EARLY_BSS=y
 CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x600
 CONFIG_SPL_DMA=y
 CONFIG_SPL_ENV_SUPPORT=y
 CONFIG_SPL_FS_EXT4=y
diff --git a/dts/upstream/src/arm64/ti/k3-j7200-common-proc-board.dts b/dts/upstream/src/arm64/ti/k3-j7200-common-proc-board.dts
index 735ffd3f35a..9cf0c27662d 100644
--- a/dts/upstream/src/arm64/ti/k3-j7200-common-proc-board.dts
+++ b/dts/upstream/src/arm64/ti/k3-j7200-common-proc-board.dts
@@ -31,23 +31,12 @@
 		stdout-path = "serial2:115200n8";
 	};
 
-	evm_12v0: fixedregulator-evm12v0 {
-		/* main supply */
-		compatible = "regulator-fixed";
-		regulator-name = "evm_12v0";
-		regulator-min-microvolt = <12000000>;
-		regulator-max-microvolt = <12000000>;
-		regulator-always-on;
-		regulator-boot-on;
-	};
-
 	vsys_3v3: fixedregulator-vsys3v3 {
 		/* Output of LM5140 */
 		compatible = "regulator-fixed";
 		regulator-name = "vsys_3v3";
 		regulator-min-microvolt = <3300000>;
 		regulator-max-microvolt = <3300000>;
-		vin-supply = <&evm_12v0>;
 		regulator-always-on;
 		regulator-boot-on;
 	};
@@ -58,7 +47,6 @@
 		regulator-name = "vsys_5v0";
 		regulator-min-microvolt = <5000000>;
 		regulator-max-microvolt = <5000000>;
-		vin-supply = <&evm_12v0>;
 		regulator-always-on;
 		regulator-boot-on;
 	};
@@ -72,7 +60,9 @@
 		regulator-boot-on;
 		enable-active-high;
 		vin-supply = <&vsys_3v3>;
-		gpio = <&exp2 2 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&wkup_vdd_mmc1_pins_default>;
+		gpio = <&wkup_gpio0 84 GPIO_ACTIVE_HIGH>;
 	};
 
 	vdd_sd_dv: gpio-regulator-TLV71033 {
@@ -80,42 +70,10 @@
 		compatible = "regulator-gpio";
 		regulator-name = "tlv71033";
 		pinctrl-names = "default";
-		pinctrl-0 = <&vdd_sd_dv_pins_default>;
-		regulator-min-microvolt = <1800000>;
+		pinctrl-0 = <&main_vdd_sd_pins_default>;
+		regulator-min-microvolt = <3300000>;
 		regulator-max-microvolt = <3300000>;
 		regulator-boot-on;
-		vin-supply = <&vsys_5v0>;
-		gpios = <&main_gpio0 55 GPIO_ACTIVE_HIGH>;
-		states = <1800000 0x0>,
-			 <3300000 0x1>;
-	};
-
-	transceiver1: can-phy1 {
-		compatible = "ti,tcan1043";
-		#phy-cells = <0>;
-		max-bitrate = <5000000>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&mcu_mcan0_gpio_pins_default>;
-		standby-gpios = <&wkup_gpio0 58 GPIO_ACTIVE_LOW>;
-		enable-gpios = <&wkup_gpio0 0 GPIO_ACTIVE_HIGH>;
-	};
-
-	transceiver2: can-phy2 {
-		compatible = "ti,tcan1042";
-		#phy-cells = <0>;
-		max-bitrate = <5000000>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&mcu_mcan1_gpio_pins_default>;
-		standby-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>;
-	};
-
-	transceiver3: can-phy3 {
-		compatible = "ti,tcan1043";
-		#phy-cells = <0>;
-		max-bitrate = <5000000>;
-		standby-gpios = <&exp2 7 GPIO_ACTIVE_LOW>;
-		enable-gpios = <&exp2 6 GPIO_ACTIVE_HIGH>;
-		mux-states = <&mux0 1>;
 	};
 };
 
@@ -123,78 +81,13 @@
 };
 
 &wkup_pmx2 {
-	mcu_uart0_pins_default: mcu-uart0-default-pins {
-		pinctrl-single,pins = <
-			J721E_WKUP_IOPAD(0x90, PIN_INPUT, 0) /* (E20) MCU_UART0_CTSn */
-			J721E_WKUP_IOPAD(0x94, PIN_OUTPUT, 0) /* (E21) MCU_UART0_RTSn */
-			J721E_WKUP_IOPAD(0x8c, PIN_INPUT, 0) /* (D20) MCU_UART0_RXD */
-			J721E_WKUP_IOPAD(0x88, PIN_OUTPUT, 0) /* (D19) MCU_UART0_TXD */
-		>;
-		bootph-all;
-	};
 
-	wkup_uart0_pins_default: wkup-uart0-default-pins {
-		pinctrl-single,pins = <
-			J721E_WKUP_IOPAD(0x48, PIN_INPUT, 0) /* (B14) WKUP_UART0_RXD */
-			J721E_WKUP_IOPAD(0x4c, PIN_OUTPUT, 0) /* (A14) WKUP_UART0_TXD */
-		>;
-		bootph-all;
-	};
-
-	mcu_cpsw_pins_default: mcu-cpsw-default-pins {
-		pinctrl-single,pins = <
-			J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */
-			J721E_WKUP_IOPAD(0x0004, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */
-			J721E_WKUP_IOPAD(0x0008, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */
-			J721E_WKUP_IOPAD(0x000c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */
-			J721E_WKUP_IOPAD(0x0010, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */
-			J721E_WKUP_IOPAD(0x0014, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */
-			J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */
-			J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */
-			J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */
-			J721E_WKUP_IOPAD(0x002c, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */
-			J721E_WKUP_IOPAD(0x0018, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */
-			J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_RGMII1_RXC */
-		>;
-	};
-
-	wkup_gpio_pins_default: wkup-gpio-default-pins {
-		pinctrl-single,pins = <
-			J721E_WKUP_IOPAD(0x70, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_6 */
-		>;
-	};
-
-	mcu_mdio_pins_default: mcu-mdio1-default-pins {
-		pinctrl-single,pins = <
-			J721E_WKUP_IOPAD(0x0034, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
-			J721E_WKUP_IOPAD(0x0030, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
-		>;
-	};
-
-	mcu_mcan0_pins_default: mcu-mcan0-default-pins {
-		pinctrl-single,pins = <
-			J721E_WKUP_IOPAD(0x54, PIN_INPUT, 0) /* (A17) MCU_MCAN0_RX */
-			J721E_WKUP_IOPAD(0x50, PIN_OUTPUT, 0) /* (A16) MCU_MCAN0_TX */
-		>;
-	};
-
-	mcu_mcan1_pins_default: mcu-mcan1-default-pins {
-		pinctrl-single,pins = <
-			J721E_WKUP_IOPAD(0x6c, PIN_INPUT, 0) /* (B16) WKUP_GPIO0_5.MCU_MCAN1_RX */
-			J721E_WKUP_IOPAD(0x68, PIN_OUTPUT, 0) /* (D13) WKUP_GPIO0_4.MCU_MCAN1_TX */
-		>;
-	};
-
-	mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins {
-		pinctrl-single,pins = <
-			J721E_WKUP_IOPAD(0x58, PIN_INPUT, 7) /* (B18) WKUP_GPIO0_0 */
-			J721E_WKUP_IOPAD(0x40, PIN_INPUT, 7) /* (B17) MCU_SPI0_D1 */
-		>;
-	};
+};
 
-	mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-default-pins {
+&wkup_pmx3 {
+	wkup_vdd_mmc1_pins_default: wkup-vdd-mmc1-pins-default {
 		pinctrl-single,pins = <
-			J721E_WKUP_IOPAD(0x60, PIN_INPUT, 7) /* (D14) WKUP_GPIO0_2 */
+			J721E_WKUP_IOPAD(0x1C, PIN_OUTPUT, 7) /* (E18) WKUP_GPIO0_84 */
 		>;
 	};
 };
@@ -204,33 +97,10 @@
 		pinctrl-single,pins = <
 			J721E_IOPAD(0xb0, PIN_INPUT, 0) /* (T16) UART0_RXD */
 			J721E_IOPAD(0xb4, PIN_OUTPUT, 0) /* (T17) UART0_TXD */
-			J721E_IOPAD(0xc0, PIN_INPUT, 2) /* (W3) SPI0_CS0.UART0_CTSn */
-			J721E_IOPAD(0xc4, PIN_OUTPUT, 2) /* (U5) SPI0_CS1.UART0_RTSn */
 		>;
 		bootph-all;
 	};
 
-	main_uart1_pins_default: main-uart1-default-pins {
-		pinctrl-single,pins = <
-			J721E_IOPAD(0xb8, PIN_INPUT, 0) /* (T18) UART1_RXD */
-			J721E_IOPAD(0xbc, PIN_INPUT, 0) /* (T20) UART1_TXD */
-		>;
-	};
-
-	main_uart3_pins_default: main-uart3-default-pins {
-		pinctrl-single,pins = <
-			J721E_IOPAD(0x60, PIN_INPUT, 11) /* (T15) MCAN8_TX.UART3_CTSn */
-			J721E_IOPAD(0x30, PIN_INPUT, 11) /* (Y18) MCAN2_TX.UART3_RXD */
-		>;
-	};
-
-	main_i2c1_pins_default: main-i2c1-default-pins {
-		pinctrl-single,pins = <
-			J721E_IOPAD(0xdc, PIN_INPUT_PULLUP, 3) /* (U3) ECAP0_IN_APWM_OUT.I2C1_SCL */
-			J721E_IOPAD(0xe0, PIN_INPUT_PULLUP, 3) /* (T3) EXT_REFCLK1.I2C1_SDA */
-		>;
-	};
-
 	main_mmc1_pins_default: main-mmc1-default-pins {
 		pinctrl-single,pins = <
 			J721E_IOPAD(0x104, PIN_INPUT, 0) /* (M20) MMC1_CMD */
@@ -245,41 +115,24 @@
 		bootph-all;
 	};
 
-	vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
-		pinctrl-single,pins = <
-			J721E_IOPAD(0xd0, PIN_OUTPUT, 7) /* (T5) SPI0_D1.GPIO0_55 */
-		>;
-	};
-
-	main_mcan3_pins_default: main-mcan3-default-pins {
+	main_vdd_sd_pins_default: main-vdd-sd-pins-default {
 		pinctrl-single,pins = <
-			J721E_IOPAD(0x3c, PIN_INPUT, 0) /* (W16) MCAN3_RX */
-			J721E_IOPAD(0x38, PIN_OUTPUT, 0) /* (Y21) MCAN3_TX */
+			J721E_IOPAD(0x18, PIN_OUTPUT, 7) /* (V17) RMII1_TX_EN.GPIO0_7 */
 		>;
 	};
 };
 
 &main_pmx2 {
-	main_usbss0_pins_default: main-usbss0-default-pins {
-		pinctrl-single,pins = <
-			J721E_IOPAD(0x04, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */
-		>;
-		bootph-all;
-	};
 };
 
 &wkup_uart0 {
 	/* Wakeup UART is used by System firmware */
 	status = "reserved";
-	pinctrl-names = "default";
-	pinctrl-0 = <&wkup_uart0_pins_default>;
 	bootph-all;
 };
 
 &mcu_uart0 {
 	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&mcu_uart0_pins_default>;
 	bootph-all;
 };
 
@@ -295,8 +148,6 @@
 &main_uart1 {
 	status = "okay";
 	/* Default pinmux */
-	pinctrl-names = "default";
-	pinctrl-0 = <&main_uart1_pins_default>;
 };
 
 &main_uart2 {
@@ -306,9 +157,7 @@
 
 &main_uart3 {
 	/* Shared with MCAN Interface */
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&main_uart3_pins_default>;
+	status = "disabled";
 };
 
 &main_gpio0 {
@@ -317,76 +166,6 @@
 
 &wkup_gpio0 {
 	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&wkup_gpio_pins_default>;
-};
-
-&mcu_cpsw {
-	pinctrl-names = "default";
-	pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>;
-
-	cpts@3d000 {
-		/* Map HW4_TS_PUSH to GENF1 */
-		ti,pps = <3 1>;
-	};
-};
-
-&davinci_mdio {
-	phy0: ethernet-phy@0 {
-		reg = <0>;
-		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
-		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
-	};
-};
-
-&cpsw_port1 {
-	phy-mode = "rgmii-rxid";
-	phy-handle = <&phy0>;
-};
-
-&main_i2c0 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&main_i2c0_pins_default>;
-	clock-frequency = <400000>;
-
-	exp1: gpio@20 {
-		compatible = "ti,tca6416";
-		reg = <0x20>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
-
-	exp2: gpio@22 {
-		compatible = "ti,tca6424";
-		reg = <0x22>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
-};
-
-/*
- * The j7200 CPB board is identical to the CPB used for J721E, the SOMs can be
- * swapped on the CPB.
- *
- * main_i2c1 of J7200 is connected to the CPB i2c bus labeled as i2c3.
- * The i2c1 of the CPB (as it is labeled) is not connected to j7200.
- */
-&main_i2c1 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&main_i2c1_pins_default>;
-	clock-frequency = <400000>;
-
-	exp3: gpio@20 {
-		compatible = "ti,tca6408";
-		reg = <0x20>;
-		gpio-controller;
-		#gpio-cells = <2>;
-		gpio-line-names = "CODEC_RSTz", "CODEC_SPARE1", "UB926_RESETn",
-				  "UB926_LOCK", "UB926_PWR_SW_CNTRL",
-				  "UB926_TUNER_RESET", "UB926_GPIO_SPARE", "";
-	};
 };
 
 &main_sdhci0 {
@@ -408,93 +187,19 @@
 	bootph-all;
 	ti,driver-strength-ohm = <50>;
 	disable-wp;
-};
-
-&serdes_ln_ctrl {
-	idle-states = <J7200_SERDES0_LANE0_PCIE1_LANE0>, <J7200_SERDES0_LANE1_PCIE1_LANE1>,
-		      <J7200_SERDES0_LANE2_QSGMII_LANE1>, <J7200_SERDES0_LANE3_IP4_UNUSED>;
+	sdhci-caps-mask = <0x00000007 0x00000000>; /* Limiting to SD HS speed mode */
 };
 
 &mcu_spi1 {
 	mux-controls = <&spi1_linkdis 0>;
 };
 
-&usb_serdes_mux {
-	idle-states = <1>; /* USB0 to SERDES lane 3 */
-	bootph-all;
-};
-
-&usbss0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&main_usbss0_pins_default>;
-	bootph-all;
-	ti,vbus-divider;
-	ti,usb2-only;
-};
-
-&usb0 {
-	dr_mode = "otg";
-	maximum-speed = "high-speed";
-	bootph-all;
-};
-
 &tscadc0 {
 	adc {
 		ti,adc-channels = <0 1 2 3 4 5 6 7>;
 	};
 };
 
-&serdes_refclk {
-	clock-frequency = <100000000>;
-};
-
-&serdes0 {
-	serdes0_pcie_link: phy@0 {
-		reg = <0>;
-		cdns,num-lanes = <2>;
-		#phy-cells = <0>;
-		cdns,phy-type = <PHY_TYPE_PCIE>;
-		resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>;
-	};
-
-	serdes0_qsgmii_link: phy@1 {
-		reg = <2>;
-		cdns,num-lanes = <1>;
-		#phy-cells = <0>;
-		cdns,phy-type = <PHY_TYPE_QSGMII>;
-		resets = <&serdes_wiz0 3>;
-	};
-};
-
-&pcie1_rc {
-	status = "okay";
-	reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
-	phys = <&serdes0_pcie_link>;
-	phy-names = "pcie-phy";
-	num-lanes = <2>;
-};
-
-&mcu_mcan0 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&mcu_mcan0_pins_default>;
-	phys = <&transceiver1>;
-};
-
-&mcu_mcan1 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&mcu_mcan1_pins_default>;
-	phys = <&transceiver2>;
-};
-
-&main_mcan3 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&main_mcan3_pins_default>;
-	phys = <&transceiver3>;
-};
-
 &timesync_router {
 	/* Use Time Sync Router to map GENF1 input to HW4_TS_PUSH output */
 	mux-reg-masks-state = <
diff --git a/dts/upstream/src/arm64/ti/k3-j7200-som-p0.dtsi b/dts/upstream/src/arm64/ti/k3-j7200-som-p0.dtsi
index fb264693506..8ff4708661e 100644
--- a/dts/upstream/src/arm64/ti/k3-j7200-som-p0.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-j7200-som-p0.dtsi
@@ -13,9 +13,8 @@
 	memory@80000000 {
 		device_type = "memory";
 		bootph-all;
-		/* 4G RAM */
-		reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
-		      <0x00000008 0x80000000 0x00000000 0x80000000>;
+		/* 2G RAM */
+		reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
 	};
 
 	reserved_memory: reserved-memory {
@@ -87,59 +86,15 @@
 	mux0: mux-controller-0 {
 		compatible = "gpio-mux";
 		#mux-state-cells = <1>;
-		mux-gpios = <&exp_som 1 GPIO_ACTIVE_HIGH>;
 	};
 
 	mux1: mux-controller-1 {
 		compatible = "gpio-mux";
 		#mux-state-cells = <1>;
-		mux-gpios = <&exp_som 2 GPIO_ACTIVE_HIGH>;
-	};
-
-	transceiver0: can-phy0 {
-		/* standby pin has been grounded by default */
-		compatible = "ti,tcan1042";
-		#phy-cells = <0>;
-		max-bitrate = <5000000>;
 	};
 };
 
 &wkup_pmx0 {
-	mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-default-pins {
-		pinctrl-single,pins = <
-			J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (B6) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */
-			J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C8) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */
-			J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (D6) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */
-			J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (D7) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */
-			J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (B7) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */
-			J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D8) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */
-			J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* (C7) MCU_OSPI0_D1.MCU_HYPERBUS0_DQ1 */
-			J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (C5) MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */
-			J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (A5) MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */
-			J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (A6) MCU_OSPI0_D4.MCU_HYPERBUS0_DQ4 */
-			J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (B8) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */
-			J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (A8) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */
-			J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (A7) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */
-		>;
-		bootph-all;
-	};
-
-	mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
-		pinctrl-single,pins = <
-			J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */
-			J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */
-			J721E_WKUP_IOPAD(0x000c, PIN_INPUT, 0)  /* MCU_OSPI0_D0 */
-			J721E_WKUP_IOPAD(0x0010, PIN_INPUT, 0)  /* MCU_OSPI0_D1 */
-			J721E_WKUP_IOPAD(0x0014, PIN_INPUT, 0)  /* MCU_OSPI0_D2 */
-			J721E_WKUP_IOPAD(0x0018, PIN_INPUT, 0)  /* MCU_OSPI0_D3 */
-			J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0)  /* MCU_OSPI0_D4 */
-			J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0)  /* MCU_OSPI0_D5 */
-			J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0)  /* MCU_OSPI0_D6 */
-			J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0)  /* MCU_OSPI0_D7 */
-			J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0)  /* MCU_OSPI0_DQS */
-		>;
-		bootph-all;
-	};
 };
 
 &wkup_pmx2 {
@@ -153,25 +108,12 @@
 };
 
 &wkup_pmx3 {
-	pmic_irq_pins_default: pmic-irq-default-pins {
-		pinctrl-single,pins = <
-			J721E_WKUP_IOPAD(0x01c, PIN_INPUT, 7) /* (E18) WKUP_GPIO0_84 */
-		>;
-	};
 };
 
 &main_pmx0 {
-	main_i2c0_pins_default: main-i2c0-default-pins {
-		pinctrl-single,pins = <
-			J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */
-			J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */
-		>;
-	};
-
-	main_mcan0_pins_default: main-mcan0-default-pins {
+	pmic_irq_pins_default: pmic-irq-pins-default {
 		pinctrl-single,pins = <
-			J721E_IOPAD(0x24, PIN_INPUT, 0) /* (V20) MCAN0_RX */
-			J721E_IOPAD(0x20, PIN_OUTPUT, 0) /* (V18) MCAN0_TX */
+			J721E_IOPAD(0x0, PIN_INPUT, 7) /* (U6) EXTINTn.GPIO0_0*/
 		>;
 	};
 };
@@ -181,47 +123,6 @@
 	 * appropriate node based on board detection
 	 */
 	status = "disabled";
-	pinctrl-names = "default";
-	pinctrl-0 = <&mcu_fss0_hpb0_pins_default>;
-	ranges = <0x00 0x00 0x05 0x00000000 0x4000000>, /* 64MB Flash on CS0 */
-		 <0x01 0x00 0x05 0x04000000 0x800000>; /* 8MB RAM on CS1 */
-
-	flash@0,0 {
-		compatible = "cypress,hyperflash", "cfi-flash";
-		reg = <0x00 0x00 0x4000000>;
-		bootph-all;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "hbmc.tiboot3";
-				reg = <0x0 0x100000>;
-			};
-
-			partition@100000 {
-				label = "hbmc.tispl";
-				reg = <0x100000 0x200000>;
-			};
-
-			partition@300000 {
-				label = "hbmc.u-boot";
-				reg = <0x300000 0x400000>;
-			};
-
-			partition@700000 {
-				label = "hbmc.env";
-				reg = <0x700000 0x40000>;
-			};
-
-			partition@800000 {
-				label = "hbmc.rootfs";
-				reg = <0x800000 0x3800000>;
-			};
-		};
-	};
 };
 
 &mailbox0_cluster0 {
@@ -295,32 +196,17 @@
 			<&main_r5fss0_core1_memory_region>;
 };
 
-&main_i2c0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&main_i2c0_pins_default>;
-	clock-frequency = <400000>;
-
-	exp_som: gpio@21 {
-		compatible = "ti,tca6408";
-		reg = <0x21>;
-		gpio-controller;
-		#gpio-cells = <2>;
-		gpio-line-names = "USB2.0_MUX_SEL", "CANUART_MUX1_SEL0",
-				  "CANUART_MUX2_SEL0", "CANUART_MUX_SEL1",
-				  "UART/LIN_MUX_SEL", "TRC_D17/AUDIO_REFCLK_SEL",
-				  "GPIO_LIN_EN", "CAN_STB";
-	};
-};
-
 &wkup_i2c0 {
 	status = "okay";
 	pinctrl-names = "default";
 	pinctrl-0 = <&wkup_i2c0_pins_default>;
 	clock-frequency = <400000>;
 
-	eeprom@50 {
-		compatible = "atmel,24c256";
-		reg = <0x50>;
+	eeprom_gp:eeprom@54 {
+		compatible = "atmel,24c04";
+		reg = <0x54>;
+		pagesize = <16>;
+		status = "okay";
 	};
 
 	tps659414: pmic@48 {
@@ -329,65 +215,66 @@
 		system-power-controller;
 		pinctrl-names = "default";
 		pinctrl-0 = <&pmic_irq_pins_default>;
-		interrupt-parent = <&wkup_gpio0>;
-		interrupts = <84 IRQ_TYPE_EDGE_FALLING>;
+		interrupt-parent = <&main_gpio0>;
+		interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
 		gpio-controller;
 		#gpio-cells = <2>;
 		ti,primary-pmic;
-		buck1-supply = <&vsys_3v3>;
-		buck2-supply = <&vsys_3v3>;
-		buck3-supply = <&vsys_3v3>;
-		buck4-supply = <&vsys_3v3>;
-		buck5-supply = <&vsys_3v3>;
+		buck1-supply = <&vsys_5v0>;
+		buck2-supply = <&vsys_5v0>;
+		buck3-supply = <&vsys_5v0>;
+		buck4-supply = <&vsys_5v0>;
+		buck5-supply = <&vsys_5v0>;
 		ldo1-supply = <&vsys_3v3>;
 		ldo2-supply = <&vsys_3v3>;
 		ldo3-supply = <&vsys_3v3>;
 		ldo4-supply = <&vsys_3v3>;
+		status = "okay";
 
 		regulators {
 			bucka1: buck1 {
-				regulator-name = "vda_mcu_1v8";
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
+				regulator-name = "vdd1_cpu_avs_0v8";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <800000>;
 				regulator-boot-on;
 				regulator-always-on;
 				bootph-all;
 			};
 
 			bucka2: buck2 {
-				regulator-name = "vdd_mcuio_1v8";
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
+				regulator-name = "vdd2_cpu_avs_0v8";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <800000>;
 				regulator-boot-on;
 				regulator-always-on;
 			};
 
 			bucka3: buck3 {
-				regulator-name = "vdd_mcu_0v85";
-				regulator-min-microvolt = <850000>;
-				regulator-max-microvolt = <850000>;
+				regulator-name = "vdd1_core_0v8";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <800000>;
 				regulator-boot-on;
 				regulator-always-on;
 			};
 
 			bucka4: buck4 {
-				regulator-name = "vdd_ddr_1v1";
-				regulator-min-microvolt = <1100000>;
-				regulator-max-microvolt = <1100000>;
+				regulator-name = "vdd2_core_0v8";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <800000>;
 				regulator-boot-on;
 				regulator-always-on;
 			};
 
 			bucka5: buck5 {
-				regulator-name = "vdd_phyio_1v8";
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
+				regulator-name = "vdd_ddr_1v1";
+				regulator-min-microvolt = <1100000>;
+				regulator-max-microvolt = <1100000>;
 				regulator-boot-on;
 				regulator-always-on;
 			};
 
 			ldoa1: ldo1 {
-				regulator-name = "vdd1_lpddr4_1v8";
+				regulator-name = "vdd_1v8";
 				regulator-min-microvolt = <1800000>;
 				regulator-max-microvolt = <1800000>;
 				regulator-boot-on;
@@ -395,15 +282,15 @@
 			};
 
 			ldoa2: ldo2 {
-				regulator-name = "vda_dll_0v8";
-				regulator-min-microvolt = <800000>;
-				regulator-max-microvolt = <800000>;
+				regulator-name = "vdd_ram_0v85";
+				regulator-min-microvolt = <850000>;
+				regulator-max-microvolt = <850000>;
 				regulator-boot-on;
 				regulator-always-on;
 			};
 
 			ldoa3: ldo3 {
-				regulator-name = "vdd_wk_0v8";
+				regulator-name = "vdda_pll_0v8";
 				regulator-min-microvolt = <800000>;
 				regulator-max-microvolt = <800000>;
 				regulator-boot-on;
@@ -411,56 +298,7 @@
 			};
 
 			ldoa4: ldo4 {
-				regulator-name = "vda_pll_1v8";
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-		};
-	};
-
-	lp876441: pmic@4c {
-		compatible = "ti,lp8764-q1";
-		reg = <0x4c>;
-		system-power-controller;
-		interrupt-parent = <&wkup_gpio0>;
-		interrupts = <84 IRQ_TYPE_EDGE_FALLING>;
-		gpio-controller;
-		#gpio-cells = <2>;
-		buck1-supply = <&vsys_3v3>;
-		buck2-supply = <&vsys_3v3>;
-		buck3-supply = <&vsys_3v3>;
-		buck4-supply = <&vsys_3v3>;
-
-		regulators: regulators {
-			buckb1: buck1 {
-				regulator-name = "vdd_cpu_avs";
-				regulator-min-microvolt = <600000>;
-				regulator-max-microvolt = <900000>;
-				regulator-always-on;
-				regulator-boot-on;
-				bootph-pre-ram;
-			};
-
-			buckb2: buck2 {
-				regulator-name = "vdd_ram_0v85";
-				regulator-min-microvolt = <850000>;
-				regulator-max-microvolt = <850000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			buckb3: buck3 {
-				regulator-name = "vdd_core_0v85";
-				regulator-min-microvolt = <850000>;
-				regulator-max-microvolt = <850000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			buckb4: buck4 {
-				regulator-name = "vdd_io_1v8";
+				regulator-name = "vdd_ana_1v8";
 				regulator-min-microvolt = <1800000>;
 				regulator-max-microvolt = <1800000>;
 				regulator-boot-on;
@@ -470,71 +308,3 @@
 	};
 };
 
-&ospi0 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
-
-	flash@0 {
-		compatible = "jedec,spi-nor";
-		reg = <0x0>;
-		spi-tx-bus-width = <8>;
-		spi-rx-bus-width = <8>;
-		spi-max-frequency = <25000000>;
-		cdns,tshsl-ns = <60>;
-		cdns,tsd2d-ns = <60>;
-		cdns,tchsh-ns = <60>;
-		cdns,tslch-ns = <60>;
-		cdns,read-delay = <4>;
-		cdns,phy-mode;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			partition@0 {
-				label = "ospi.tiboot3";
-				reg = <0x0 0x100000>;
-			};
-
-			partition@100000 {
-				label = "ospi.tispl";
-				reg = <0x100000 0x200000>;
-			};
-
-			partition@300000 {
-				label = "ospi.u-boot";
-				reg = <0x300000 0x400000>;
-			};
-
-			partition@700000 {
-				label = "ospi.env";
-				reg = <0x700000 0x40000>;
-			};
-
-			partition@740000 {
-				label = "ospi.env.backup";
-				reg = <0x740000 0x40000>;
-			};
-
-			partition@800000 {
-				label = "ospi.rootfs";
-				reg = <0x800000 0x37c0000>;
-			};
-
-			partition@3fc0000 {
-				label = "ospi.phypattern";
-				reg = <0x3fc0000 0x40000>;
-				bootph-all;
-			};
-		};
-	};
-};
-
-&main_mcan0 {
-	status = "okay";
-	pinctrl-0 = <&main_mcan0_pins_default>;
-	pinctrl-names = "default";
-	phys = <&transceiver0>;
-};