Changing Crystal source clock to 19.2 MHz In WinCE ARM-A8 BSP
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Introduction[edit]
In WinCE ARM-A8 BSP, the default crystal source clock is 26MHz for Both AM/DM37x and OMAP35x processors. This page summarizes the changes to switch to a 19.2 MHz Crystal for AM/DM37x.
BSP Modification details[edit]
- 1. Source clock selection - The selection of source clock frequency is done through BSP_PRM_CLKSEL(bsp_def.h). This definition is used in ClockSetup() (platform.c) to setup Source-Clock Selection Register (PRM_CLKSEL).
// // Define: BSP_PRM_CLKSEL // // Determines the system clock frequency. Used to update PRM_CLKSEL // // Allowed values: // // 0x0: Input clock is 12 MHz // 0x1: Input clock is 13 MHz // 0x2: Input clock is 19.2 MHz // 0x3: Input clock is 26 MHz // 0x4: Input clock is 38.4 MHz // #define BSP_PRM_CLKSEL (2)
- 2. DPLLs default (MPU running @ 1GHz) setting modification - DPLL settings need to be adjusted to use 19.2MHz clock source
- 2.1 DPLL1(MPU)
OPP |
Multiplier |
divider |
Fint |
CLKOUT (MHz) |
clkoutx2(MHz) |
100 |
125 |
3 |
4.8 |
600 |
1200 |
130 |
375 |
8 |
2.1 |
800 |
1600 |
1G |
1875 |
35 |
0.5 |
1000 |
2000 |
EVM_OMAP3530\SRC\BOOTLOADER\XLDR\platform.c typedef struct CPU_OPP_SETTINGS { UINT16 MPUSpeed; UINT16 IVASpeed; UINT16 VDD1Init; UINT16 VDD2Init; UINT16 dpll1_m; UINT16 dpll1_n; UINT16 dpll2_m; UINT16 dpll2_n; }CPU_OPP_Settings, *pCPU_OPP_Settings; CPU_OPP_Settings OMAP35x_OPP_Table[OMAP35x_OPP_NUM]= { // MPU[125Mhz @ 0.975V], IVA2[ 90Mhz @ 0.975V] {125, 90, 0x1e, 0x2c,125,25,45,12}, // MPU[250Mhz @ 1.000V], IVA2[180Mhz @ 1.00V] {250, 180, 0x20, 0x2c,125,12,90,12}, // MPU[500Mhz @ 1.2000V], IVA2[360Mhz @ 1.20V] {500, 360, 0x30, 0x2c,250,12,180,12}, // MPU[550Mhz @ 1.2750V], IVA2[400Mhz @ 1.27V] {550, 400, 0x36, 0x2c,225,12,200,12}, // MPU[600Mhz @ 1.3500V], IVA2[430Mhz @ 1.35V] {600, 430, 0x3c, 0x2c,300,12,215,12}, // MPU[720hz @ 1.3500V], IVA2[520Mhz @ 1.35V] {720, 520, 0x3c, 0x2c,360,12,260,12} }; CPU_OPP_Settings OMAP37x_OPP_Table[OMAP37x_OPP_NUM]= { // MPU[300Mhz @ 0.9375V], IVA2[260Mhz @ 0.9375V] {300, 260, 0x1b, 0x2b,125,7,325,23}, // MPU[600Mhz @ 1.1000V], IVA2[520Mhz @ 1.1000V] {600, 520, 0x28, 0x2b,125,3,325,11}, // MPU[800Mhz @ 1.2625V], IVA2[660Mhz @ 1.2625V] {800, 660, 0x35, 0x2b,375,8,275,7}, // MPU[1000Mhz @ 1.3125V], IVA2[875Mhz @ 1.3125V] {1000, 800, 0x3E, 0x2b,1875,35,375,8} }; //------------------------------------------------------------------------------ // // Function: Mpu_dpll_init // // Helper function to initialize OMAP 35xx/37xx/36xx MPU DPLL. // void Mpu_dpll_init(pCPU_OPP_Settings opp_setting) { OMAP_PRCM_MPU_CM_REGS* pPrcmMpuCM = OALPAtoUA(OMAP_PRCM_MPU_CM_REGS_PA); unsigned int val, mpu_mult; // put mpu dpll in bypass val = INREG32(&pPrcmMpuCM->CM_CLKEN_PLL_MPU); val &= ~DPLL_MODE_MASK; val |= DPLL_MODE_LOWPOWER_BYPASS; OUTREG32(&pPrcmMpuCM->CM_CLKEN_PLL_MPU, val); while ((INREG32(&pPrcmMpuCM->CM_IDLEST_PLL_MPU) & DPLL_STATUS_MASK) != DPLL_STATUS_BYPASSED); // setup DPLL1 divider OUTREG32(&pPrcmMpuCM->CM_CLKSEL2_PLL_MPU, BSP_CM_CLKSEL2_PLL_MPU); // configure m:n clock ratios as well as frequency selection for mpu dpll mpu_mult = opp_setting->dpll1_m << 8; val = BSP_MPU_CLK_SRC | mpu_mult | opp_setting->dpll1_n <<0; OUTREG32(&pPrcmMpuCM->CM_CLKSEL1_PLL_MPU, val); // lock dpll with correct frequency selection OUTREG32(&pPrcmMpuCM->CM_CLKEN_PLL_MPU, BSP_CM_CLKEN_PLL_MPU); while ((INREG32(&pPrcmMpuCM->CM_IDLEST_PLL_MPU) & DPLL_STATUS_MASK) != DPLL_STATUS_LOCKED); }
- 2.2 DPLL2(IVA)
OPP |
Multiplier |
divider |
Fint |
CLKOUT (MHz) |
clkoutx2(MHz) |
100 |
325 |
11 |
1.6 |
520 |
1040 |
130 |
275 |
7 |
2.4 | 660 |
1320 |
1G |
375 |
8 |
2.1 |
800 |
1600 |
EVM_OMAP3530\SRC\BOOTLOADER\XLDR\platform.c //------------------------------------------------------------------------------ // // Function: Iva_dpll_init // // Helper function to initialize OMAP 35xx IVA DPLL. // void Iva_dpll_init(pCPU_OPP_Settings opp_setting) { OMAP_PRCM_IVA2_CM_REGS* pPrcmIvaCM = OALPAtoUA(OMAP_PRCM_IVA2_CM_REGS_PA); unsigned int val, iva_mult; //--------------------------------- // setup dpll timings for iva2 dpll // // put iva2 dpll in bypass val = INREG32(&pPrcmIvaCM->CM_CLKEN_PLL_IVA2); val &= ~DPLL_MODE_MASK; val |= DPLL_MODE_LOWPOWER_BYPASS; OUTREG32(&pPrcmIvaCM->CM_CLKEN_PLL_IVA2, val); while ((INREG32(&pPrcmIvaCM->CM_IDLEST_PLL_IVA2) & DPLL_STATUS_MASK) != DPLL_STATUS_BYPASSED); // setup DPLL1 divider OUTREG32(&pPrcmIvaCM->CM_CLKSEL2_PLL_IVA2, BSP_CM_CLKSEL2_PLL_IVA2); // configure m:n clock ratios as well as frequency selection for iva dpll iva_mult = ((opp_setting->dpll2_m) << 8); val = BSP_3530_IVA2_CLK_SRC | iva_mult | (opp_setting->dpll2_n << 0); OUTREG32(&pPrcmIvaCM->CM_CLKSEL1_PLL_IVA2, val); // lock dpll with correct frequency selection if(gCPU_family == CPU_FAMILY_DM37XX) { //val = (BSP_EN_IVA2_DPLL_LPMODE | BSP_EN_IVA2_DPLL_DRIFTGUARD | BSP_EN_IVA2_DPLL); val = (BSP_EN_IVA2_DPLL_LPMODE | BSP_EN_IVA2_DPLL); } else { val = BSP_CM_CLKEN_PLL_IVA2; } OUTREG32(&pPrcmIvaCM->CM_CLKEN_PLL_IVA2, val); while ((INREG32(&pPrcmIvaCM->CM_IDLEST_PLL_IVA2) & DPLL_STATUS_MASK) != DPLL_STATUS_LOCKED); }
2.3 DPLL3(CORE)
OPP |
Multiplier |
divider |
Fint |
M2 |
M3 |
L3_DIV |
L4_DIV |
CLKOUT (MHz) |
clkoutx2(MHz) |
L3(MHz) |
L4(MHz) |
100 |
375 |
17 |
1.1 |
1 |
4 |
2 |
2 |
400 |
800 |
200 |
100 |
50 |
375 |
17 |
1.1 |
2 |
4 |
2 |
2 |
400 |
800 |
100 |
50 |
bsp_def.h #define CORE_DPLL_MULT_400 (375 << 16) #define CORE_DPLL_DIV_400 (17 << 8)
- 2.4 DPLL4(PER1)
OPP |
Multiplier |
divider |
Fint |
CLKOUT (MHz) |
clkoutx2(MHz) |
M2 output |
360 |
7 |
2.4 |
864 |
1728 |
54 |
bsp_def.h #define BSP_PERIPH_DPLL_MULT_37xx (360 << 8) // freq = 864MHz #define BSP_PERIPH_DPLL_DIV (7 << 0) //
- 2.5 DPLL5(PER2)
OPP |
Multiplier |
divider |
Fint |
M2 |
CLKOUT (MHz) |
clkoutx2(MHz) |
50 |
0 |
8 |
120 |
240 |
bsp_def.h //------------------------------------------------------------------------------ // // Define: BSP_TWL_HFCLK_FREQ // // defines the high frequency clock used // HFCLK_FREQ_19_2 (1) // HFCLK_FREQ_26 (2) // HFCLK_FREQ_38_4 (3) // #define BSP_TWL_HFCLK_FREQ (1) //------------------------------------------------------------------------------ // // Define: BSP_CM_CLKSEL4_PLL // // Determines master clock frequency. Used to update CM_CLKSEL4_PLL // // Allowed values: // #define BSP_PERIPH2_DPLL_MULT (25 << 8) // Multiplier #define BSP_PERIPH2_DPLL_DIV (3 << 0) // Divider
3. multipler and divider in bsp_opp_map.h
// 37xx family CPU Settings // (just a placeholder) static VddOppSetting_t vdd1Opp0Info_37x = { { kSmartReflex_Channel1, BSP_SRCLKLEN_INIT // smartreflex info }, { kVoltageProcessor1, 0, 0 // voltage processor info }, 2, { // vdd1 has 2 dpll's { kDPLL1, 0, (UINT)-1, 0, 0, 1 // dpll1 (MPU) }, { kDPLL2, 0, (UINT)-1, 0, 0, 1 // dpll2 (DSP) } } }; // MPU[300Mhz @ 0.xxxV], IVA2[ 260Mhz @ 0.975V] static VddOppSetting_t vdd1Opp1Info_37x = { { kSmartReflex_Channel1, BSP_SRCLKLEN_INIT // smartreflex info }, { kVoltageProcessor1, 0x1B, 0x1B // voltage processor info }, 2, { // vdd1 has 2 dpll's { kDPLL1, 300, 125, 7, 0, 1 // dpll1 (MPU) }, { kDPLL2, 260, 325, 23, 0, 1 // dpll2 (DSP) } } }; // MPU[600Mhz @ 1.00V], IVA2[520Mhz @ 1.05V] static VddOppSetting_t vdd1Opp2Info_37x = { { kSmartReflex_Channel1, BSP_SRCLKLEN_INIT // smartreflex info }, { kVoltageProcessor1, 0x28, 0x28 // voltage processor info }, 2, { // vdd1 has 2 dpll's { kDPLL1, 600, 125, 3, 0, 1 // dpll1 (MPU) }, { kDPLL2, 520, 325, 11, 0, 1 // dpll2 (DSP) } } }; // MPU[800Mhz @ 1.20V], IVA2[660Mhz @ 1.20V] static VddOppSetting_t vdd1Opp3Info_37x = { { kSmartReflex_Channel1, BSP_SRCLKLEN_INIT // smartreflex info }, { kVoltageProcessor1, 0x35, 0x35 // voltage processor info }, 2, { // vdd1 has 2 dpll's { kDPLL1, 800, 375, 8, 0, 1 // dpll1 (MPU) }, { kDPLL2, 660, 275, 7, 0, 1 // dpll2 (DSP) } } }; // MPU[1000Mhz @ 1.27V], IVA2[875Mhz @ 1.27V] static VddOppSetting_t vdd1Opp4Info_37x = { { kSmartReflex_Channel1, BSP_SRCLKLEN_INIT // smartreflex info }, { kVoltageProcessor1, 0x3E, 0x3E // voltage processor info }, 2, { // vdd1 has 2 dpll's { kDPLL1, 1000, 1875, 35, 0, 1 // dpll1 (MPU) }, { kDPLL2, 800, 375, 8, 0, 1 // dpll2 (DSP) } } };
Notes[edit]
In ARM-A8 BSP, OMAP35x and AM/DM37x share the same BSP image. Since the above modification only applies to AM/DM37x, the same image can not be used for OMAP35x.
- I used the following for DPLL4 with success. -- D. Baughman Jan. 2012
#define BSP_PERIPH_DPLL_MULT (216 << 8) // freq = 864MHz
// in 37xx, DPLL4_M2 is 192MHz"
//#define BSP_PERIPH_DPLL_MULT_37xx (432 << 8) // for 26 MHz freq = 864MHz
//#define BSP_PERIPH_DPLL_DIV (12 << 0) //
define BSP_PERIPH_DPLL_MULT_37xx (360 << 8) // for 19.2 MHz freq = 864MHz
define BSP_PERIPH_DPLL_DIV (7 << 0) //
// #define BSP_PERIPH_DPLL_MULT (360 << 8) // for 19.2 MHz freq = 864MHz
// #define BSP_PERIPH_DPLL_DIV (7 << 0) //
define BSP_CM_CLKSEL2_PLL (BSP_PERIPH_DPLL_MULT_37xx | \BSP_PERIPH_DPLL_DIV)