C:\VMWare\mount\k3-j722s-evm.dts_org		C:\VMWare\mount\k3-j722s-evm.dts
1	/dts-v1/;	1	/dts-v1/;
2		2
3	/ {	3	/ {
4	model = "Texas Instruments J722S EVM";	4	model = "Texas Instruments J722S EVM";
5	compatible = "ti,j722s-evm\0ti,j722s";	5	compatible = "ti,j722s-evm\0ti,j722s";
6	interrupt-parent = <0x01>;	6	interrupt-parent = <0x01>;
7	#address-cells = <0x02>;	7	#address-cells = <0x02>;
8	#size-cells = <0x02>;	8	#size-cells = <0x02>;
9		9
10	cpus {	10	cpus {
11	#address-cells = <0x01>;	11	#address-cells = <0x01>;
12	#size-cells = <0x00>;	12	#size-cells = <0x00>;
13		13
14	cpu-map {	14	cpu-map {
15		15
16	cluster0 {	16	cluster0 {
17	phandle = <0x77>;	17	phandle = <0x77>;
18		18
19	core0 {	19	core0 {
20	cpu = <0x02>;	20	cpu = <0x02>;
21	};	21	};
22		22
23	core1 {	23	core1 {
24	cpu = <0x03>;	24	cpu = <0x03>;
25	};	25	};
26		26
27	core2 {	27	core2 {
28	cpu = <0x04>;	28	cpu = <0x04>;
29	};	29	};
30		30
31	core3 {	31	core3 {
32	cpu = <0x05>;	32	cpu = <0x05>;
33	};	33	};
34	};	34	};
35	};	35	};
36		36
37	cpu@0 {	37	cpu@0 {
38	compatible = "arm,cortex-a53";	38	compatible = "arm,cortex-a53";
39	reg = <0x00>;	39	reg = <0x00>;
40	device_type = "cpu";	40	device_type = "cpu";
41	enable-method = "psci";	41	enable-method = "psci";
42	i-cache-size = <0x8000>;	42	i-cache-size = <0x8000>;
43	i-cache-line-size = <0x40>;	43	i-cache-line-size = <0x40>;
44	i-cache-sets = <0x100>;	44	i-cache-sets = <0x100>;
45	d-cache-size = <0x8000>;	45	d-cache-size = <0x8000>;
46	d-cache-line-size = <0x40>;	46	d-cache-line-size = <0x40>;
47	d-cache-sets = <0x80>;	47	d-cache-sets = <0x80>;
48	next-level-cache = <0x06>;	48	next-level-cache = <0x06>;
49	clocks = <0x07 0x87 0x00>;	49	clocks = <0x07 0x87 0x00>;
50	phandle = <0x02>;	50	phandle = <0x02>;
51	};	51	};
52		52
53	cpu@1 {	53	cpu@1 {
54	compatible = "arm,cortex-a53";	54	compatible = "arm,cortex-a53";
55	reg = <0x01>;	55	reg = <0x01>;
56	device_type = "cpu";	56	device_type = "cpu";
57	enable-method = "psci";	57	enable-method = "psci";
58	i-cache-size = <0x8000>;	58	i-cache-size = <0x8000>;
59	i-cache-line-size = <0x40>;	59	i-cache-line-size = <0x40>;
60	i-cache-sets = <0x100>;	60	i-cache-sets = <0x100>;
61	d-cache-size = <0x8000>;	61	d-cache-size = <0x8000>;
62	d-cache-line-size = <0x40>;	62	d-cache-line-size = <0x40>;
63	d-cache-sets = <0x80>;	63	d-cache-sets = <0x80>;
64	next-level-cache = <0x06>;	64	next-level-cache = <0x06>;
65	clocks = <0x07 0x88 0x00>;	65	clocks = <0x07 0x88 0x00>;
66	phandle = <0x03>;	66	phandle = <0x03>;
67	};	67	};
68		68
69	cpu@2 {	69	cpu@2 {
70	compatible = "arm,cortex-a53";	70	compatible = "arm,cortex-a53";
71	reg = <0x02>;	71	reg = <0x02>;
72	device_type = "cpu";	72	device_type = "cpu";
73	enable-method = "psci";	73	enable-method = "psci";
74	i-cache-size = <0x8000>;	74	i-cache-size = <0x8000>;
75	i-cache-line-size = <0x40>;	75	i-cache-line-size = <0x40>;
76	i-cache-sets = <0x100>;	76	i-cache-sets = <0x100>;
77	d-cache-size = <0x8000>;	77	d-cache-size = <0x8000>;
78	d-cache-line-size = <0x40>;	78	d-cache-line-size = <0x40>;
79	d-cache-sets = <0x80>;	79	d-cache-sets = <0x80>;
80	next-level-cache = <0x06>;	80	next-level-cache = <0x06>;
81	clocks = <0x07 0x89 0x00>;	81	clocks = <0x07 0x89 0x00>;
82	phandle = <0x04>;	82	phandle = <0x04>;
83	};	83	};
84		84
85	cpu@3 {	85	cpu@3 {
86	compatible = "arm,cortex-a53";	86	compatible = "arm,cortex-a53";
87	reg = <0x03>;	87	reg = <0x03>;
88	device_type = "cpu";	88	device_type = "cpu";
89	enable-method = "psci";	89	enable-method = "psci";
90	i-cache-size = <0x8000>;	90	i-cache-size = <0x8000>;
91	i-cache-line-size = <0x40>;	91	i-cache-line-size = <0x40>;
92	i-cache-sets = <0x100>;	92	i-cache-sets = <0x100>;
93	d-cache-size = <0x8000>;	93	d-cache-size = <0x8000>;
94	d-cache-line-size = <0x40>;	94	d-cache-line-size = <0x40>;
95	d-cache-sets = <0x80>;	95	d-cache-sets = <0x80>;
96	next-level-cache = <0x06>;	96	next-level-cache = <0x06>;
97	clocks = <0x07 0x8a 0x00>;	97	clocks = <0x07 0x8a 0x00>;
98	phandle = <0x05>;	98	phandle = <0x05>;
99	};	99	};
100	};	100	};
101		101
102	l2-cache0 {	102	l2-cache0 {
103	compatible = "cache";	103	compatible = "cache";
104	cache-unified;	104	cache-unified;
105	cache-level = <0x02>;	105	cache-level = <0x02>;
106	cache-size = <0x80000>;	106	cache-size = <0x80000>;
107	cache-line-size = <0x40>;	107	cache-line-size = <0x40>;
108	cache-sets = <0x200>;	108	cache-sets = <0x200>;
109	phandle = <0x06>;	109	phandle = <0x06>;
110	};	110	};
111		111
112	firmware {	112	firmware {
113		113
114	optee {	114	optee {
115	compatible = "linaro,optee-tz";	115	compatible = "linaro,optee-tz";
116	method = "smc";	116	method = "smc";
117	};	117	};
118		118
119	psci {	119	psci {
120	compatible = "arm,psci-1.0";	120	compatible = "arm,psci-1.0";
121	method = "smc";	121	method = "smc";
122	phandle = <0x78>;	122	phandle = <0x78>;
123	};	123	};
124	};	124	};
125		125
126	timer-cl0-cpu0 {	126	timer-cl0-cpu0 {
127	compatible = "arm,armv8-timer";	127	compatible = "arm,armv8-timer";
128	interrupts = <0x01 0x0d 0x08 0x01 0x0e 0x08 0x01 0x0b 0x08 0x01 0x0a 0x08>;	128	interrupts = <0x01 0x0d 0x08 0x01 0x0e 0x08 0x01 0x0b 0x08 0x01 0x0a 0x08>;
129	phandle = <0x79>;	129	phandle = <0x79>;
130	};	130	};
131		131
132	pmu {	132	pmu {
133	compatible = "arm,cortex-a53-pmu";	133	compatible = "arm,cortex-a53-pmu";
134	interrupts = <0x01 0x07 0x04>;	134	interrupts = <0x01 0x07 0x04>;
135	phandle = <0x7a>;	135	phandle = <0x7a>;
136	};	136	};
137		137
138	bus@f0000 {	138	bus@f0000 {
139	compatible = "simple-bus";	139	compatible = "simple-bus";
140	#address-cells = <0x02>;	140	#address-cells = <0x02>;
141	#size-cells = <0x02>;	141	#size-cells = <0x02>;
142	ranges = <0x00 0xf0000 0x00 0xf0000 0x00 0x30000 0x00 0x420000 0x00 0x420000 0x00 0x1000 0x00 0x600000 0x00 0x600000 0x00 0x1100 0x00 0x703000 0x00 0x703000 0x00 0x200 0x00 0x70c000 0x00 0x70c000 0x00 0x200 0x00 0xa40000 0x00 0xa40000 0x00 0x800 0x00 0x1000000 0x00 0x1000000 0x00 0x1b28400 0x00 0x8000000 0x00 0x8000000 0x00 0x200000 0x00 0xd000000 0x00 0xd000000 0x00 0x800000 0x00 0xe000000 0x00 0xe000000 0x00 0x1d20000 0x00 0xfd80000 0x00 0xfd80000 0x00 0x80000 0x00 0xfd20000 0x00 0xfd20000 0x00 0x100 0x00 0xfd20200 0x00 0xfd20200 0x00 0x200 0x00 0x20000000 0x00 0x20000000 0x00 0xa008000 0x00 0x30040000 0x00 0x30040000 0x00 0x80000 0x00 0x301c0000 0x00 0x301c0000 0x00 0x1000 0x00 0x30101000 0x00 0x30101000 0x00 0x80100 0x00 0x30200000 0x00 0x30200000 0x00 0x10000 0x00 0x30210000 0x00 0x30210000 0x00 0x10000 0x00 0x30220000 0x00 0x30220000 0x00 0x10000 0x00 0x30270000 0x00 0x30270000 0x00 0x10000 0x00 0x30300000 0x00 0x30300000 0x00 0x1000 0x00 0x30500000 0x00 0x30500000 0x00 0x100000 0x00 0x31000000 0x00 0x31000000 0x00 0x50000 0x00 0x31200000 0x00 0x31200000 0x00 0x40000 0x00 0x40900000 0x00 0x40900000 0x00 0x30000 0x00 0x43600000 0x00 0x43600000 0x00 0x10000 0x00 0x44043000 0x00 0x44043000 0x00 0xfe0 0x00 0x44860000 0x00 0x44860000 0x00 0x40000 0x00 0x48000000 0x00 0x48000000 0x00 0x6408000 0x00 0x60000000 0x00 0x60000000 0x00 0x8000000 0x00 0x68000000 0x00 0x68000000 0x00 0x8000000 0x00 0x70000000 0x00 0x70000000 0x00 0x40000 0x00 0x78400000 0x00 0x78400000 0x00 0x8000 0x00 0x78500000 0x00 0x78500000 0x00 0x8000 0x00 0x7e000000 0x00 0x7e000000 0x00 0x200000 0x00 0x7e200000 0x00 0x7e200000 0x00 0x200000 0x01 0x00 0x01 0x00 0x00 0x310000 0x05 0x00 0x05 0x00 0x01 0x00 0x06 0x00 0x06 0x00 0x01 0x00 0x00 0x4000000 0x00 0x4000000 0x00 0x1ff1400 0x00 0x79000000 0x00 0x79000000 0x00 0x8000 0x00 0x79020000 0x00 0x79020000 0x00 0x8000 0x00 0x79100000 0x00 0x79100000 0x00 0x40000 0x00 0x79140000 0x00 0x79140000 0x00 0x40000 0x00 0xb00000 0x00 0xb00000 0x00 0x2400 0x00 0x2b000000 0x00 0x2b000000 0x00 0x300400 0x00 0x43000000 0x00 0x43000000 0x00 0x20000 0x00 0x78000000 0x00 0x78000000 0x00 0x8000 0x00 0x78100000 0x00 0x78100000 0x00 0x8000>;	142	ranges = <0x00 0xf0000 0x00 0xf0000 0x00 0x30000 0x00 0x420000 0x00 0x420000 0x00 0x1000 0x00 0x600000 0x00 0x600000 0x00 0x1100 0x00 0x703000 0x00 0x703000 0x00 0x200 0x00 0x70c000 0x00 0x70c000 0x00 0x200 0x00 0xa40000 0x00 0xa40000 0x00 0x800 0x00 0x1000000 0x00 0x1000000 0x00 0x1b28400 0x00 0x8000000 0x00 0x8000000 0x00 0x200000 0x00 0xd000000 0x00 0xd000000 0x00 0x800000 0x00 0xe000000 0x00 0xe000000 0x00 0x1d20000 0x00 0xfd80000 0x00 0xfd80000 0x00 0x80000 0x00 0xfd20000 0x00 0xfd20000 0x00 0x100 0x00 0xfd20200 0x00 0xfd20200 0x00 0x200 0x00 0x20000000 0x00 0x20000000 0x00 0xa008000 0x00 0x30040000 0x00 0x30040000 0x00 0x80000 0x00 0x301c0000 0x00 0x301c0000 0x00 0x1000 0x00 0x30101000 0x00 0x30101000 0x00 0x80100 0x00 0x30200000 0x00 0x30200000 0x00 0x10000 0x00 0x30210000 0x00 0x30210000 0x00 0x10000 0x00 0x30220000 0x00 0x30220000 0x00 0x10000 0x00 0x30270000 0x00 0x30270000 0x00 0x10000 0x00 0x30300000 0x00 0x30300000 0x00 0x1000 0x00 0x30500000 0x00 0x30500000 0x00 0x100000 0x00 0x31000000 0x00 0x31000000 0x00 0x50000 0x00 0x31200000 0x00 0x31200000 0x00 0x40000 0x00 0x40900000 0x00 0x40900000 0x00 0x30000 0x00 0x43600000 0x00 0x43600000 0x00 0x10000 0x00 0x44043000 0x00 0x44043000 0x00 0xfe0 0x00 0x44860000 0x00 0x44860000 0x00 0x40000 0x00 0x48000000 0x00 0x48000000 0x00 0x6408000 0x00 0x60000000 0x00 0x60000000 0x00 0x8000000 0x00 0x68000000 0x00 0x68000000 0x00 0x8000000 0x00 0x70000000 0x00 0x70000000 0x00 0x40000 0x00 0x78400000 0x00 0x78400000 0x00 0x8000 0x00 0x78500000 0x00 0x78500000 0x00 0x8000 0x00 0x7e000000 0x00 0x7e000000 0x00 0x200000 0x00 0x7e200000 0x00 0x7e200000 0x00 0x200000 0x01 0x00 0x01 0x00 0x00 0x310000 0x05 0x00 0x05 0x00 0x01 0x00 0x06 0x00 0x06 0x00 0x01 0x00 0x00 0x4000000 0x00 0x4000000 0x00 0x1ff1400 0x00 0x79000000 0x00 0x79000000 0x00 0x8000 0x00 0x79020000 0x00 0x79020000 0x00 0x8000 0x00 0x79100000 0x00 0x79100000 0x00 0x40000 0x00 0x79140000 0x00 0x79140000 0x00 0x40000 0x00 0xb00000 0x00 0xb00000 0x00 0x2400 0x00 0x2b000000 0x00 0x2b000000 0x00 0x300400 0x00 0x43000000 0x00 0x43000000 0x00 0x20000 0x00 0x78000000 0x00 0x78000000 0x00 0x8000 0x00 0x78100000 0x00 0x78100000 0x00 0x8000>;
143	phandle = <0x7b>;	143	phandle = <0x7b>;
144		144
145	bus@4000000 {	145	bus@4000000 {
146	compatible = "simple-bus";	146	compatible = "simple-bus";
147	#address-cells = <0x02>;	147	#address-cells = <0x02>;
148	#size-cells = <0x02>;	148	#size-cells = <0x02>;
149	ranges = <0x00 0x4000000 0x00 0x4000000 0x00 0x1ff1400 0x00 0x79000000 0x00 0x79000000 0x00 0x8000 0x00 0x79020000 0x00 0x79020000 0x00 0x8000 0x00 0x79100000 0x00 0x79100000 0x00 0x40000 0x00 0x79140000 0x00 0x79140000 0x00 0x40000>;	149	ranges = <0x00 0x4000000 0x00 0x4000000 0x00 0x1ff1400 0x00 0x79000000 0x00 0x79000000 0x00 0x8000 0x00 0x79020000 0x00 0x79020000 0x00 0x8000 0x00 0x79100000 0x00 0x79100000 0x00 0x40000 0x00 0x79140000 0x00 0x79140000 0x00 0x40000>;
150	bootph-all;	150	bootph-all;
151	phandle = <0x7c>;	151	phandle = <0x7c>;
152		152
153	sram@79100000 {	153	sram@79100000 {
154	compatible = "mmio-sram";	154	compatible = "mmio-sram";
155	reg = <0x00 0x79100000 0x00 0x80000>;	155	reg = <0x00 0x79100000 0x00 0x80000>;
156	ranges = <0x00 0x00 0x79100000 0x80000>;	156	ranges = <0x00 0x00 0x79100000 0x80000>;
157	#address-cells = <0x01>;	157	#address-cells = <0x01>;
158	#size-cells = <0x01>;	158	#size-cells = <0x01>;
159	phandle = <0x13>;	159	phandle = <0x13>;
160		160
161	mcu_sram1@0 {	161	mcu_sram1@0 {
162	reg = <0x00 0x80000>;	162	reg = <0x00 0x80000>;
163	};	163	};
164	};	164	};
165		165
166	pinctrl@4084000 {	166	pinctrl@4084000 {
167	compatible = "pinctrl-single";	167	compatible = "pinctrl-single";
168	reg = <0x00 0x4084000 0x00 0x88>;	168	reg = <0x00 0x4084000 0x00 0x88>;
169	#pinctrl-cells = <0x01>;	169	#pinctrl-cells = <0x01>;
170	pinctrl-single,register-width = <0x20>;	170	pinctrl-single,register-width = <0x20>;
171	pinctrl-single,function-mask = <0xffffffff>;	171	pinctrl-single,function-mask = <0xffffffff>;
172	pinctrl-single,gpio-range = <0x08 0x00 0x15 0x54007 0x08 0x17 0x01 0x54007 0x08 0x20 0x02 0x54007>;	172	pinctrl-single,gpio-range = <0x08 0x00 0x15 0x54007 0x08 0x17 0x01 0x54007 0x08 0x20 0x02 0x54007>;
173	bootph-all;	173	bootph-all;
174	phandle = <0x0d>;	174	phandle = <0x0d>;
175		175
176	gpio-range {	176	gpio-range {
177	#pinctrl-single,gpio-range-cells = <0x03>;	177	#pinctrl-single,gpio-range-cells = <0x03>;
178	phandle = <0x08>;	178	phandle = <0x08>;
179	};	179	};
180		180
181	mcu-i2c0-default-pins {	181	mcu-i2c0-default-pins {
182	pinctrl-single,pins = <0x48 0x54000 0x44 0x54000>;	182	pinctrl-single,pins = <0x48 0x54000 0x44 0x54000>;
183	phandle = <0x0a>;	183	phandle = <0x0a>;
184	};	184	};
185		185
186	mcu-mcan0-default-pins {	186	mcu-mcan0-default-pins {
187	pinctrl-single,pins = <0x38 0x54000 0x34 0x10000>;	187	pinctrl-single,pins = <0x38 0x54000 0x34 0x10000>;
188	phandle = <0x0e>;	188	phandle = <0x0e>;
189	};	189	};
190		190
191	mcu-mcan1-default-pins {	191	mcu-mcan1-default-pins {
192	pinctrl-single,pins = <0x40 0x54000 0x3c 0x10000>;	192	pinctrl-single,pins = <0x40 0x54000 0x3c 0x10000>;
193	phandle = <0x10>;	193	phandle = <0x10>;
194	};	194	};
195		195
196	mcu-mcan0-gpio-default-pins {	196	mcu-mcan0-gpio-default-pins {
197	pinctrl-single,pins = <0x30 0x10007>;	197	pinctrl-single,pins = <0x30 0x10007>;
198	phandle = <0x72>;	198	phandle = <0x72>;
199	};	199	};
200		200
201	wkup-uart0-default-pins {	201	wkup-uart0-default-pins {
202	pinctrl-single,pins = <0x2c 0x54000 0x30 0x10000 0x24 0x54000 0x28 0x10000>;	202	pinctrl-single,pins = <0x2c 0x54000 0x30 0x10000 0x24 0x54000 0x28 0x10000>;
203	bootph-all;	203	bootph-all;
204	phandle = <0x18>;	204	phandle = <0x18>;
205	};	205	};
206		206
207	wkup-i2c0-default-pins {	207	wkup-i2c0-default-pins {
208	pinctrl-single,pins = <0x4c 0x64000 0x50 0x64000>;	208	pinctrl-single,pins = <0x4c 0x64000 0x50 0x64000>;
209	bootph-all;	209	bootph-all;
210	phandle = <0x19>;	210	phandle = <0x19>;
211	};	211	};
212	};	212	};
213		213
214	esm@4100000 {	214	esm@4100000 {
215	compatible = "ti,j721e-esm";	215	compatible = "ti,j721e-esm";
216	reg = <0x00 0x4100000 0x00 0x1000>;	216	reg = <0x00 0x4100000 0x00 0x1000>;
217	bootph-pre-ram;	217	bootph-pre-ram;
218	ti,esm-pins = <0x00 0x01 0x02 0x55 0x56>;	218	ti,esm-pins = <0x00 0x01 0x02 0x55 0x56>;
219	phandle = <0x7d>;	219	phandle = <0x7d>;
220	};	220	};
221		221
222	timer@4800000 {	222	timer@4800000 {
223	compatible = "ti,am654-timer";	223	compatible = "ti,am654-timer";
224	reg = <0x00 0x4800000 0x00 0x400>;	224	reg = <0x00 0x4800000 0x00 0x400>;
225	clocks = <0x07 0x23 0x02>;	225	clocks = <0x07 0x23 0x02>;
226	clock-names = "fck";	226	clock-names = "fck";
227	power-domains = <0x09 0x23 0x01>;	227	power-domains = <0x09 0x23 0x01>;
228	ti,timer-pwm;	228	ti,timer-pwm;
229	status = "reserved";	229	status = "reserved";
230	phandle = <0x7e>;	230	phandle = <0x7e>;
231	};	231	};
232		232
233	timer@4810000 {	233	timer@4810000 {
234	compatible = "ti,am654-timer";	234	compatible = "ti,am654-timer";
235	reg = <0x00 0x4810000 0x00 0x400>;	235	reg = <0x00 0x4810000 0x00 0x400>;
236	clocks = <0x07 0x30 0x02>;	236	clocks = <0x07 0x30 0x02>;
237	clock-names = "fck";	237	clock-names = "fck";
238	power-domains = <0x09 0x30 0x01>;	238	power-domains = <0x09 0x30 0x01>;
239	ti,timer-pwm;	239	ti,timer-pwm;
240	status = "reserved";	240	status = "reserved";
241	phandle = <0x7f>;	241	phandle = <0x7f>;
242	};	242	};
243		243
244	timer@4820000 {	244	timer@4820000 {
245	compatible = "ti,am654-timer";	245	compatible = "ti,am654-timer";
246	reg = <0x00 0x4820000 0x00 0x400>;	246	reg = <0x00 0x4820000 0x00 0x400>;
247	clocks = <0x07 0x31 0x02>;	247	clocks = <0x07 0x31 0x02>;
248	clock-names = "fck";	248	clock-names = "fck";
249	power-domains = <0x09 0x31 0x01>;	249	power-domains = <0x09 0x31 0x01>;
250	ti,timer-pwm;	250	ti,timer-pwm;
251	status = "reserved";	251	status = "reserved";
252	phandle = <0x80>;	252	phandle = <0x80>;
253	};	253	};
254		254
255	timer@4830000 {	255	timer@4830000 {
256	compatible = "ti,am654-timer";	256	compatible = "ti,am654-timer";
257	reg = <0x00 0x4830000 0x00 0x400>;	257	reg = <0x00 0x4830000 0x00 0x400>;
258	clocks = <0x07 0x32 0x02>;	258	clocks = <0x07 0x32 0x02>;
259	clock-names = "fck";	259	clock-names = "fck";
260	power-domains = <0x09 0x32 0x01>;	260	power-domains = <0x09 0x32 0x01>;
261	ti,timer-pwm;	261	ti,timer-pwm;
262	status = "reserved";	262	status = "reserved";
263	phandle = <0x81>;	263	phandle = <0x81>;
264	};	264	};
265		265
266	serial@4a00000 {	266	serial@4a00000 {
267	compatible = "ti,am64-uart\0ti,am654-uart";	267	compatible = "ti,am64-uart\0ti,am654-uart";
268	reg = <0x00 0x4a00000 0x00 0x100>;	268	reg = <0x00 0x4a00000 0x00 0x100>;
269	interrupts = <0x00 0xb9 0x04>;	269	interrupts = <0x00 0xb9 0x04>;
270	power-domains = <0x09 0x95 0x01>;	270	power-domains = <0x09 0x95 0x01>;
271	clocks = <0x07 0x95 0x00>;	271	clocks = <0x07 0x95 0x00>;
272	clock-names = "fclk";	272	clock-names = "fclk";
273	status = "disabled";	273	status = "disabled";
274	phandle = <0x82>;	274	phandle = <0x82>;
275	};	275	};
276		276
277	i2c@4900000 {	277	i2c@4900000 {
278	compatible = "ti,am64-i2c\0ti,omap4-i2c";	278	compatible = "ti,am64-i2c\0ti,omap4-i2c";
279	reg = <0x00 0x4900000 0x00 0x100>;	279	reg = <0x00 0x4900000 0x00 0x100>;
280	interrupts = <0x00 0x6b 0x04>;	280	interrupts = <0x00 0x6b 0x04>;
281	#address-cells = <0x01>;	281	#address-cells = <0x01>;
282	#size-cells = <0x00>;	282	#size-cells = <0x00>;
283	power-domains = <0x09 0x6a 0x01>;	283	power-domains = <0x09 0x6a 0x01>;
284	clocks = <0x07 0x6a 0x02>;	284	clocks = <0x07 0x6a 0x02>;
285	clock-names = "fck";	285	clock-names = "fck";
286	status = "okay";	286	status = "okay";
287	pinctrl-names = "default";	287	pinctrl-names = "default";
288	pinctrl-0 = <0x0a>;	288	pinctrl-0 = <0x0a>;
289	clock-frequency = <0x61a80>;	289	clock-frequency = <0x61a80>;
290	phandle = <0x83>;	290	phandle = <0x83>;
291	};	291	};
292		292
293	spi@4b00000 {	293	spi@4b00000 {
294	compatible = "ti,am654-mcspi\0ti,omap4-mcspi";	294	compatible = "ti,am654-mcspi\0ti,omap4-mcspi";
295	reg = <0x00 0x4b00000 0x00 0x400>;	295	reg = <0x00 0x4b00000 0x00 0x400>;
296	interrupts = <0x00 0xb0 0x04>;	296	interrupts = <0x00 0xb0 0x04>;
297	#address-cells = <0x01>;	297	#address-cells = <0x01>;
298	#size-cells = <0x00>;	298	#size-cells = <0x00>;
299	power-domains = <0x09 0x93 0x01>;	299	power-domains = <0x09 0x93 0x01>;
300	clocks = <0x07 0x93 0x00>;	300	clocks = <0x07 0x93 0x00>;
301	status = "disabled";	301	status = "disabled";
302	phandle = <0x84>;	302	phandle = <0x84>;
303	};	303	};
304		304
305	spi@4b10000 {	305	spi@4b10000 {
306	compatible = "ti,am654-mcspi\0ti,omap4-mcspi";	306	compatible = "ti,am654-mcspi\0ti,omap4-mcspi";
307	reg = <0x00 0x4b10000 0x00 0x400>;	307	reg = <0x00 0x4b10000 0x00 0x400>;
308	interrupts = <0x00 0xb1 0x04>;	308	interrupts = <0x00 0xb1 0x04>;
309	#address-cells = <0x01>;	309	#address-cells = <0x01>;
310	#size-cells = <0x00>;	310	#size-cells = <0x00>;
311	power-domains = <0x09 0x94 0x01>;	311	power-domains = <0x09 0x94 0x01>;
312	clocks = <0x07 0x94 0x00>;	312	clocks = <0x07 0x94 0x00>;
313	status = "disabled";	313	status = "disabled";
314	phandle = <0x85>;	314	phandle = <0x85>;
315	};	315	};
316		316
317	interrupt-controller@4210000 {	317	interrupt-controller@4210000 {
318	compatible = "ti,sci-intr";	318	compatible = "ti,sci-intr";
319	reg = <0x00 0x4210000 0x00 0x200>;	319	reg = <0x00 0x4210000 0x00 0x200>;
320	ti,intr-trigger-type = <0x01>;	320	ti,intr-trigger-type = <0x01>;
321	interrupt-controller;	321	interrupt-controller;
322	interrupt-parent = <0x01>;	322	interrupt-parent = <0x01>;
323	#interrupt-cells = <0x01>;	323	#interrupt-cells = <0x01>;
324	ti,sci = <0x0b>;	324	ti,sci = <0x0b>;
325	ti,sci-dev-id = <0x05>;	325	ti,sci-dev-id = <0x05>;
326	ti,interrupt-ranges = <0x00 0x68 0x04>;	326	ti,interrupt-ranges = <0x00 0x68 0x04>;
327	phandle = <0x0c>;	327	phandle = <0x0c>;
328	};	328	};
329		329
330	gpio@4201000 {	330	gpio@4201000 {
331	compatible = "ti,am64-gpio\0ti,keystone-gpio";	331	compatible = "ti,am64-gpio\0ti,keystone-gpio";
332	reg = <0x00 0x4201000 0x00 0x100>;	332	reg = <0x00 0x4201000 0x00 0x100>;
333	gpio-controller;	333	gpio-controller;
334	#gpio-cells = <0x02>;	334	#gpio-cells = <0x02>;
335	interrupt-parent = <0x0c>;	335	interrupt-parent = <0x0c>;
336	interrupts = <0x1e 0x1f>;	336	interrupts = <0x1e 0x1f>;
337	interrupt-controller;	337	interrupt-controller;
338	#interrupt-cells = <0x02>;	338	#interrupt-cells = <0x02>;
339	ti,ngpio = <0x18>;	339	ti,ngpio = <0x18>;
340	ti,davinci-gpio-unbanked = <0x00>;	340	ti,davinci-gpio-unbanked = <0x00>;
341	power-domains = <0x09 0x4f 0x01>;	341	power-domains = <0x09 0x4f 0x01>;
342	clocks = <0x07 0x4f 0x00>;	342	clocks = <0x07 0x4f 0x00>;
343	clock-names = "gpio";	343	clock-names = "gpio";
344	gpio-ranges = <0x0d 0x00 0x00 0x15 0x0d 0x15 0x17 0x01 0x0d 0x16 0x20 0x02>;	344	gpio-ranges = <0x0d 0x00 0x00 0x15 0x0d 0x15 0x17 0x01 0x0d 0x16 0x20 0x02>;
345	status = "okay";	345	status = "okay";
346	phandle = <0x73>;	346	phandle = <0x73>;
347	};	347	};
348		348
349	watchdog@4880000 {	349	watchdog@4880000 {
350	compatible = "ti,j7-rti-wdt";	350	compatible = "ti,j7-rti-wdt";
351	reg = <0x00 0x4880000 0x00 0x100>;	351	reg = <0x00 0x4880000 0x00 0x100>;
352	clocks = <0x07 0x83 0x00>;	352	clocks = <0x07 0x83 0x00>;
353	power-domains = <0x09 0x83 0x01>;	353	power-domains = <0x09 0x83 0x01>;
354	assigned-clocks = <0x07 0x83 0x00>;	354	assigned-clocks = <0x07 0x83 0x00>;
355	assigned-clock-parents = <0x07 0x83 0x04>;	355	assigned-clock-parents = <0x07 0x83 0x04>;
356	status = "reserved";	356	status = "reserved";
357	phandle = <0x86>;	357	phandle = <0x86>;
358	};	358	};
359		359
360	can@4e08000 {	360	can@4e08000 {
361	compatible = "bosch,m_can";	361	compatible = "bosch,m_can";
362	reg = <0x00 0x4e08000 0x00 0x200 0x00 0x4e00000 0x00 0x8000>;	362	reg = <0x00 0x4e08000 0x00 0x200 0x00 0x4e00000 0x00 0x8000>;
363	reg-names = "m_can\0message_ram";	363	reg-names = "m_can\0message_ram";
364	power-domains = <0x09 0xbc 0x01>;	364	power-domains = <0x09 0xbc 0x01>;
365	clocks = <0x07 0xbc 0x06 0x07 0xbc 0x01>;	365	clocks = <0x07 0xbc 0x06 0x07 0xbc 0x01>;
366	clock-names = "hclk\0cclk";	366	clock-names = "hclk\0cclk";
367	bosch,mram-cfg = <0x00 0x80 0x40 0x40 0x40 0x40 0x20 0x20>;	367	bosch,mram-cfg = <0x00 0x80 0x40 0x40 0x40 0x40 0x20 0x20>;
368	interrupts = <0x00 0x1a 0x04 0x00 0x1b 0x04>;	368	interrupts = <0x00 0x1a 0x04 0x00 0x1b 0x04>;
369	interrupt-names = "int0\0int1";	369	interrupt-names = "int0\0int1";
370	wakeup-source = "suspend\0poweroff";	370	wakeup-source = "suspend\0poweroff";
371	status = "okay";	371	status = "disabled";
372	pinctrl-names = "default";	372	pinctrl-names = "default";
373	pinctrl-0 = <0x0e>;	373	pinctrl-0 = <0x0e>;
374	phys = <0x0f>;	374	phys = <0x0f>;
375	phandle = <0x87>;	375	phandle = <0x87>;
376	};	376	};
377		377
378	can@4e18000 {	378	can@4e18000 {
379	compatible = "bosch,m_can";	379	compatible = "bosch,m_can";
380	reg = <0x00 0x4e18000 0x00 0x200 0x00 0x4e10000 0x00 0x8000>;	380	reg = <0x00 0x4e18000 0x00 0x200 0x00 0x4e10000 0x00 0x8000>;
381	reg-names = "m_can\0message_ram";	381	reg-names = "m_can\0message_ram";
382	power-domains = <0x09 0xbd 0x01>;	382	power-domains = <0x09 0xbd 0x01>;
383	clocks = <0x07 0xbd 0x06 0x07 0xbd 0x01>;	383	clocks = <0x07 0xbd 0x06 0x07 0xbd 0x01>;
384	clock-names = "hclk\0cclk";	384	clock-names = "hclk\0cclk";
385	bosch,mram-cfg = <0x00 0x80 0x40 0x40 0x40 0x40 0x20 0x20>;	385	bosch,mram-cfg = <0x00 0x80 0x40 0x40 0x40 0x40 0x20 0x20>;
386	interrupts = <0x00 0x1c 0x04 0x00 0x1d 0x04>;	386	interrupts = <0x00 0x1c 0x04 0x00 0x1d 0x04>;
387	interrupt-names = "int0\0int1";	387	interrupt-names = "int0\0int1";
388	wakeup-source = "suspend\0poweroff";	388	wakeup-source = "suspend\0poweroff";
389	status = "okay";	389	status = "okay";
390	pinctrl-names = "default";	390	pinctrl-names = "default";
391	pinctrl-0 = <0x10>;	391	pinctrl-0 = <0x10>;
392	phys = <0x11>;	392	phys = <0x11>;
393	phandle = <0x88>;	393	phandle = <0x88>;
394	};	394	};
395		395
396	r5fss@79000000 {	396	r5fss@79000000 {
397	compatible = "ti,am62-r5fss";	397	compatible = "ti,am62-r5fss";
398	#address-cells = <0x01>;	398	#address-cells = <0x01>;
399	#size-cells = <0x01>;	399	#size-cells = <0x01>;
400	ranges = <0x79000000 0x00 0x79000000 0x8000 0x79020000 0x00 0x79020000 0x8000>;	400	ranges = <0x79000000 0x00 0x79000000 0x8000 0x79020000 0x00 0x79020000 0x8000>;
401	power-domains = <0x09 0x07 0x01>;	401	power-domains = <0x09 0x07 0x01>;
402	status = "okay";	402	status = "okay";
403	phandle = <0x89>;	403	phandle = <0x89>;
404		404
405	r5f@79000000 {	405	r5f@79000000 {
406	compatible = "ti,am62-r5f";	406	compatible = "ti,am62-r5f";
407	reg = <0x79000000 0x8000 0x79020000 0x8000>;	407	reg = <0x79000000 0x8000 0x79020000 0x8000>;
408	reg-names = "atcm\0btcm";	408	reg-names = "atcm\0btcm";
409	ti,sci = <0x0b>;	409	ti,sci = <0x0b>;
410	ti,sci-dev-id = <0x09>;	410	ti,sci-dev-id = <0x09>;
411	ti,sci-proc-ids = <0x03 0xff>;	411	ti,sci-proc-ids = <0x03 0xff>;
412	resets = <0x12 0x09 0x01>;	412	resets = <0x12 0x09 0x01>;
413	firmware-name = "j722s-mcu-r5f0_0-fw";	413	firmware-name = "j722s-mcu-r5f0_0-fw";
414	ti,atcm-enable = <0x00>;	414	ti,atcm-enable = <0x00>;
415	ti,btcm-enable = <0x01>;	415	ti,btcm-enable = <0x01>;
416	ti,loczrama = <0x00>;	416	ti,loczrama = <0x00>;
417	sram = <0x13>;	417	sram = <0x13>;
418	mboxes = <0x14 0x15>;	418	mboxes = <0x14 0x15>;
419	memory-region = <0x16 0x17>;	419	memory-region = <0x16 0x17>;
420	phandle = <0x8a>;	420	phandle = <0x8a>;
421	};	421	};
422	};	422	};
423	};	423	};
424		424
425	bus@b00000 {	425	bus@b00000 {
426	compatible = "simple-bus";	426	compatible = "simple-bus";
427	#address-cells = <0x02>;	427	#address-cells = <0x02>;
428	#size-cells = <0x02>;	428	#size-cells = <0x02>;
429	ranges = <0x00 0xb00000 0x00 0xb00000 0x00 0x2400 0x00 0x2b000000 0x00 0x2b000000 0x00 0x300400 0x00 0x43000000 0x00 0x43000000 0x00 0x20000 0x00 0x78000000 0x00 0x78000000 0x00 0x8000 0x00 0x78100000 0x00 0x78100000 0x00 0x8000>;	429	ranges = <0x00 0xb00000 0x00 0xb00000 0x00 0x2400 0x00 0x2b000000 0x00 0x2b000000 0x00 0x300400 0x00 0x43000000 0x00 0x43000000 0x00 0x20000 0x00 0x78000000 0x00 0x78000000 0x00 0x8000 0x00 0x78100000 0x00 0x78100000 0x00 0x8000>;
430	bootph-all;	430	bootph-all;
431	phandle = <0x8b>;	431	phandle = <0x8b>;
432		432
433	bus@43000000 {	433	bus@43000000 {
434	compatible = "simple-bus";	434	compatible = "simple-bus";
435	reg = <0x00 0x43000000 0x00 0x20000>;	435	reg = <0x00 0x43000000 0x00 0x20000>;
436	#address-cells = <0x01>;	436	#address-cells = <0x01>;
437	#size-cells = <0x01>;	437	#size-cells = <0x01>;
438	ranges = <0x00 0x00 0x43000000 0x20000>;	438	ranges = <0x00 0x00 0x43000000 0x20000>;
439	bootph-all;	439	bootph-all;
440	phandle = <0x8c>;	440	phandle = <0x8c>;
441		441
442	chipid@14 {	442	chipid@14 {
443	compatible = "ti,am654-chipid";	443	compatible = "ti,am654-chipid";
444	reg = <0x14 0x04>;	444	reg = <0x14 0x04>;
445	bootph-all;	445	bootph-all;
446	phandle = <0x8d>;	446	phandle = <0x8d>;
447	};	447	};
448		448
449	syscon@18 {	449	syscon@18 {
450	compatible = "ti,am62-opp-efuse-table\0syscon";	450	compatible = "ti,am62-opp-efuse-table\0syscon";
451	reg = <0x18 0x04>;	451	reg = <0x18 0x04>;
452	phandle = <0x8e>;	452	phandle = <0x8e>;
453	};	453	};
454		454
455	ethernet-mac-syscon@200 {	455	ethernet-mac-syscon@200 {
456	compatible = "ti,am62p-cpsw-mac-efuse\0syscon";	456	compatible = "ti,am62p-cpsw-mac-efuse\0syscon";
457	reg = <0x200 0x08>;	457	reg = <0x200 0x08>;
458	phandle = <0x40>;	458	phandle = <0x40>;
459	};	459	};
460		460
461	syscon@4008 {	461	syscon@4008 {
462	compatible = "ti,am62-usb-phy-ctrl\0syscon";	462	compatible = "ti,am62-usb-phy-ctrl\0syscon";
463	reg = <0x4008 0x04>;	463	reg = <0x4008 0x04>;
464	phandle = <0x3c>;	464	phandle = <0x3c>;
465	};	465	};
466		466
467	syscon@4018 {	467	syscon@4018 {
468	compatible = "ti,am62-usb-phy-ctrl\0syscon";	468	compatible = "ti,am62-usb-phy-ctrl\0syscon";
469	reg = <0x4018 0x04>;	469	reg = <0x4018 0x04>;
470	phandle = <0x8f>;	470	phandle = <0x8f>;
471	};	471	};
472		472
473	syscon@80d0 {	473	syscon@80d0 {
474	compatible = "ti,am62-ddr-pmctrl\0syscon";	474	compatible = "ti,am62-ddr-pmctrl\0syscon";
475	reg = <0x80d0 0x04>;	475	reg = <0x80d0 0x04>;
476	phandle = <0x90>;	476	phandle = <0x90>;
477	};	477	};
478		478
479	syscon@18300 {	479	syscon@18300 {
480	compatible = "ti,am62-canuart-wake\0syscon";	480	compatible = "ti,am62-canuart-wake\0syscon";
481	reg = <0x18300 0x44>;	481	reg = <0x18300 0x44>;
482	phandle = <0x91>;	482	phandle = <0x91>;
483	};	483	};
484		484
485	pcie0-ctrl@4070 {	485	pcie0-ctrl@4070 {
486	compatible = "ti,j784s4-pcie-ctrl\0syscon";	486	compatible = "ti,j784s4-pcie-ctrl\0syscon";
487	reg = <0x4070 0x04>;	487	reg = <0x4070 0x04>;
488	phandle = <0x56>;	488	phandle = <0x56>;
489	};	489	};
490	};	490	};
491		491
492	target-module@2b300050 {	492	target-module@2b300050 {
493	compatible = "ti,sysc-omap2\0ti,sysc";	493	compatible = "ti,sysc-omap2\0ti,sysc";
494	reg = <0x00 0x2b300050 0x00 0x04 0x00 0x2b300054 0x00 0x04 0x00 0x2b300058 0x00 0x04>;	494	reg = <0x00 0x2b300050 0x00 0x04 0x00 0x2b300054 0x00 0x04 0x00 0x2b300058 0x00 0x04>;
495	reg-names = "rev\0sysc\0syss";	495	reg-names = "rev\0sysc\0syss";
496	ti,sysc-mask = <0x07>;	496	ti,sysc-mask = <0x07>;
497	ti,sysc-sidle = <0x00 0x01 0x02 0x03>;	497	ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
498	ti,syss-mask = <0x01>;	498	ti,syss-mask = <0x01>;
499	ti,no-reset-on-init;	499	ti,no-reset-on-init;
500	power-domains = <0x09 0x72 0x01>;	500	power-domains = <0x09 0x72 0x01>;
501	clocks = <0x07 0x72 0x00>;	501	clocks = <0x07 0x72 0x00>;
502	clock-names = "fck";	502	clock-names = "fck";
503	#address-cells = <0x01>;	503	#address-cells = <0x01>;
504	#size-cells = <0x01>;	504	#size-cells = <0x01>;
505	ranges = <0x00 0x00 0x2b300000 0x100000>;	505	ranges = <0x00 0x00 0x2b300000 0x100000>;
506		506
507	serial@0 {	507	serial@0 {
508	compatible = "ti,am64-uart\0ti,am654-uart";	508	compatible = "ti,am64-uart\0ti,am654-uart";
509	reg = <0x00 0x100>;	509	reg = <0x00 0x100>;
510	interrupts = <0x00 0xba 0x04>;	510	interrupts = <0x00 0xba 0x04>;
511	status = "reserved";	511	status = "reserved";
512	pinctrl-names = "default";	512	pinctrl-names = "default";
513	pinctrl-0 = <0x18>;	513	pinctrl-0 = <0x18>;
514	bootph-all;	514	bootph-all;
515	phandle = <0x92>;	515	phandle = <0x92>;
516	};	516	};
517	};	517	};
518		518
519	i2c@2b200000 {	519	i2c@2b200000 {
520	compatible = "ti,am64-i2c\0ti,omap4-i2c";	520	compatible = "ti,am64-i2c\0ti,omap4-i2c";
521	reg = <0x00 0x2b200000 0x00 0x100>;	521	reg = <0x00 0x2b200000 0x00 0x100>;
522	interrupts = <0x00 0xa5 0x04>;	522	interrupts = <0x00 0xa5 0x04>;
523	#address-cells = <0x01>;	523	#address-cells = <0x01>;
524	#size-cells = <0x00>;	524	#size-cells = <0x00>;
525	power-domains = <0x09 0x6b 0x01>;	525	power-domains = <0x09 0x6b 0x01>;
526	clocks = <0x07 0x6b 0x04>;	526	clocks = <0x07 0x6b 0x04>;
527	clock-names = "fck";	527	clock-names = "fck";
528	status = "okay";	528	status = "okay";
529	pinctrl-names = "default";	529	pinctrl-names = "default";
530	pinctrl-0 = <0x19>;	530	pinctrl-0 = <0x19>;
531	clock-frequency = <0x61a80>;	531	clock-frequency = <0x61a80>;
532	bootph-all;	532	bootph-all;
533	phandle = <0x93>;	533	phandle = <0x93>;
534		534
535	pmic@48 {	535	pmic@48 {
536	compatible = "ti,tps65224-q1";	536	compatible = "ti,tps65224-q1";
537	reg = <0x48>;	537	reg = <0x48>;
538	pinctrl-names = "default";	538	pinctrl-names = "default";
539	pinctrl-0 = <0x1a>;	539	pinctrl-0 = <0x1a>;
540	interrupt-parent = <0x1b>;	540	interrupt-parent = <0x1b>;
541	interrupts = <0x00 0x02>;	541	interrupts = <0x00 0x02>;
542	ti,primary-pmic;	542	ti,primary-pmic;
543	gpio-controller;	543	gpio-controller;
544	#gpio-cells = <0x02>;	544	#gpio-cells = <0x02>;
545	buck12-supply = <0x1c>;	545	buck12-supply = <0x1c>;
546	buck3-supply = <0x1c>;	546	buck3-supply = <0x1c>;
547	buck4-supply = <0x1c>;	547	buck4-supply = <0x1c>;
548	ldo1-supply = <0x1c>;	548	ldo1-supply = <0x1c>;
549	ldo2-supply = <0x1c>;	549	ldo2-supply = <0x1c>;
550	ldo3-supply = <0x1c>;	550	ldo3-supply = <0x1c>;
551	phandle = <0x94>;	551	phandle = <0x94>;
552		552
553	regulators {	553	regulators {
554		554
555	buck1 {	555	buck1 {
556	regulator-name = "vcc1v8_io_buck1";	556	regulator-name = "vcc1v8_io_buck1";
557	regulator-min-microvolt = <0x1b7740>;	557	regulator-min-microvolt = <0x1b7740>;
558	regulator-max-microvolt = <0x1b7740>;	558	regulator-max-microvolt = <0x1b7740>;
559	regulator-boot-on;	559	regulator-boot-on;
560	regulator-always-on;	560	regulator-always-on;
561	bootph-all;	561	bootph-all;
562	phandle = <0x95>;	562	phandle = <0x95>;
563	};	563	};
564		564
565	buck2 {	565	buck2 {
566	regulator-name = "vcc1v1_ddr_buck2";	566	regulator-name = "vcc1v1_ddr_buck2";
567	regulator-min-microvolt = <0x10c8e0>;	567	regulator-min-microvolt = <0x10c8e0>;
568	regulator-max-microvolt = <0x10c8e0>;	568	regulator-max-microvolt = <0x10c8e0>;
569	regulator-boot-on;	569	regulator-boot-on;
570	regulator-always-on;	570	regulator-always-on;
571	phandle = <0x96>;	571	phandle = <0x96>;
572	};	572	};
573		573
574	buck3 {	574	buck3 {
575	regulator-name = "vcc0v85_ram_buck3";	575	regulator-name = "vcc0v85_ram_buck3";
576	regulator-min-microvolt = <0xcf850>;	576	regulator-min-microvolt = <0xcf850>;
577	regulator-max-microvolt = <0xcf850>;	577	regulator-max-microvolt = <0xcf850>;
578	regulator-boot-on;	578	regulator-boot-on;
579	regulator-always-on;	579	regulator-always-on;
580	phandle = <0x97>;	580	phandle = <0x97>;
581	};	581	};
582		582
583	buck4 {	583	buck4 {
584	regulator-name = "vcc0v75_ioret_buck4";	584	regulator-name = "vcc0v75_ioret_buck4";
585	regulator-min-microvolt = <0xb71b0>;	585	regulator-min-microvolt = <0xb71b0>;
586	regulator-max-microvolt = <0xb71b0>;	586	regulator-max-microvolt = <0xb71b0>;
587	regulator-boot-on;	587	regulator-boot-on;
588	regulator-always-on;	588	regulator-always-on;
589	phandle = <0x98>;	589	phandle = <0x98>;
590	};	590	};
591		591
592	ldo1 {	592	ldo1 {
593	regulator-name = "vdda1v8_pll_ldo1";	593	regulator-name = "vdda1v8_pll_ldo1";
594	regulator-min-microvolt = <0x1b7740>;	594	regulator-min-microvolt = <0x1b7740>;
595	regulator-max-microvolt = <0x1b7740>;	595	regulator-max-microvolt = <0x1b7740>;
596	regulator-boot-on;	596	regulator-boot-on;
597	regulator-always-on;	597	regulator-always-on;
598	phandle = <0x99>;	598	phandle = <0x99>;
599	};	599	};
600		600
601	ldo2 {	601	ldo2 {
602	regulator-name = "dvdd3v3_ldo2";	602	regulator-name = "dvdd3v3_ldo2";
603	regulator-min-microvolt = <0x325aa0>;	603	regulator-min-microvolt = <0x325aa0>;
604	regulator-max-microvolt = <0x325aa0>;	604	regulator-max-microvolt = <0x325aa0>;
605	regulator-boot-on;	605	regulator-boot-on;
606	regulator-always-on;	606	regulator-always-on;
607	phandle = <0x9a>;	607	phandle = <0x9a>;
608	};	608	};
609		609
610	ldo3 {	610	ldo3 {
611	regulator-name = "vdd1v85_phy_ldo3";	611	regulator-name = "vdd1v85_phy_ldo3";
612	regulator-min-microvolt = <0x1b7740>;	612	regulator-min-microvolt = <0x1b7740>;
613	regulator-max-microvolt = <0x1b7740>;	613	regulator-max-microvolt = <0x1b7740>;
614	regulator-boot-on;	614	regulator-boot-on;
615	regulator-always-on;	615	regulator-always-on;
616	phandle = <0x9b>;	616	phandle = <0x9b>;
617	};	617	};
618	};	618	};
619	};	619	};
620	};	620	};
621		621
622	rtc@2b1f0000 {	622	rtc@2b1f0000 {
623	compatible = "ti,am62-rtc";	623	compatible = "ti,am62-rtc";
624	reg = <0x00 0x2b1f0000 0x00 0x100>;	624	reg = <0x00 0x2b1f0000 0x00 0x100>;
625	interrupts = <0x00 0x64 0x04>;	625	interrupts = <0x00 0x64 0x04>;
626	clocks = <0x07 0x75 0x06 0x07 0x75 0x00>;	626	clocks = <0x07 0x75 0x06 0x07 0x75 0x00>;
627	clock-names = "vbus\0osc32k";	627	clock-names = "vbus\0osc32k";
628	power-domains = <0x09 0x75 0x01>;	628	power-domains = <0x09 0x75 0x01>;
629	wakeup-source;	629	wakeup-source;
630	phandle = <0x9c>;	630	phandle = <0x9c>;
631	};	631	};
632		632
633	watchdog@2b000000 {	633	watchdog@2b000000 {
634	compatible = "ti,j7-rti-wdt";	634	compatible = "ti,j7-rti-wdt";
635	reg = <0x00 0x2b000000 0x00 0x100>;	635	reg = <0x00 0x2b000000 0x00 0x100>;
636	clocks = <0x07 0x84 0x00>;	636	clocks = <0x07 0x84 0x00>;
637	power-domains = <0x09 0x84 0x01>;	637	power-domains = <0x09 0x84 0x01>;
638	assigned-clocks = <0x07 0x84 0x00>;	638	assigned-clocks = <0x07 0x84 0x00>;
639	assigned-clock-parents = <0x07 0x84 0x02>;	639	assigned-clock-parents = <0x07 0x84 0x02>;
640	status = "reserved";	640	status = "reserved";
641	phandle = <0x9d>;	641	phandle = <0x9d>;
642	};	642	};
643		643
644	temperature-sensor@b00000 {	644	temperature-sensor@b00000 {
645	compatible = "ti,j7200-vtm";	645	compatible = "ti,j7200-vtm";
646	reg = <0x00 0xb00000 0x00 0x400 0x00 0xb01000 0x00 0x400>;	646	reg = <0x00 0xb00000 0x00 0x400 0x00 0xb01000 0x00 0x400>;
647	power-domains = <0x09 0x5f 0x01>;	647	power-domains = <0x09 0x5f 0x01>;
648	#thermal-sensor-cells = <0x01>;	648	#thermal-sensor-cells = <0x01>;
649	phandle = <0x6a>;	649	phandle = <0x6a>;
650	};	650	};
651		651
652	r5fss@78000000 {	652	r5fss@78000000 {
653	compatible = "ti,am62-r5fss";	653	compatible = "ti,am62-r5fss";
654	#address-cells = <0x01>;	654	#address-cells = <0x01>;
655	#size-cells = <0x01>;	655	#size-cells = <0x01>;
656	ranges = <0x78000000 0x00 0x78000000 0x8000 0x78100000 0x00 0x78100000 0x8000>;	656	ranges = <0x78000000 0x00 0x78000000 0x8000 0x78100000 0x00 0x78100000 0x8000>;
657	power-domains = <0x09 0x77 0x01>;	657	power-domains = <0x09 0x77 0x01>;
658	status = "okay";	658	status = "okay";
659	phandle = <0x9e>;	659	phandle = <0x9e>;
660		660
661	r5f@78000000 {	661	r5f@78000000 {
662	compatible = "ti,am62-r5f";	662	compatible = "ti,am62-r5f";
663	reg = <0x78000000 0x8000 0x78100000 0x8000>;	663	reg = <0x78000000 0x8000 0x78100000 0x8000>;
664	reg-names = "atcm\0btcm";	664	reg-names = "atcm\0btcm";
665	ti,sci = <0x0b>;	665	ti,sci = <0x0b>;
666	ti,sci-dev-id = <0x79>;	666	ti,sci-dev-id = <0x79>;
667	ti,sci-proc-ids = <0x01 0xff>;	667	ti,sci-proc-ids = <0x01 0xff>;
668	resets = <0x12 0x79 0x01>;	668	resets = <0x12 0x79 0x01>;
669	firmware-name = "j722s-wkup-r5f0_0-fw";	669	firmware-name = "j722s-wkup-r5f0_0-fw";
670	ti,atcm-enable = <0x01>;	670	ti,atcm-enable = <0x01>;
671	ti,btcm-enable = <0x01>;	671	ti,btcm-enable = <0x01>;
672	ti,loczrama = <0x01>;	672	ti,loczrama = <0x01>;
673	mboxes = <0x1d 0x1e>;	673	mboxes = <0x1d 0x1e>;
674	memory-region = <0x1f 0x20>;	674	memory-region = <0x1f 0x20>;
675	phandle = <0x9f>;	675	phandle = <0x9f>;
676	};	676	};
677	};	677	};
678	};	678	};
679		679
680	sram@70000000 {	680	sram@70000000 {
681	compatible = "mmio-sram";	681	compatible = "mmio-sram";
682	#address-cells = <0x01>;	682	#address-cells = <0x01>;
683	#size-cells = <0x01>;	683	#size-cells = <0x01>;
684	reg = <0x00 0x70000000 0x00 0x40000>;	684	reg = <0x00 0x70000000 0x00 0x40000>;
685	ranges = <0x00 0x00 0x70000000 0x40000>;	685	ranges = <0x00 0x00 0x70000000 0x40000>;
686	phandle = <0x50>;	686	phandle = <0x50>;
687	};	687	};
688		688
689	interrupt-controller@1800000 {	689	interrupt-controller@1800000 {
690	compatible = "arm,gic-v3";	690	compatible = "arm,gic-v3";
691	#address-cells = <0x02>;	691	#address-cells = <0x02>;
692	#size-cells = <0x02>;	692	#size-cells = <0x02>;
693	ranges;	693	ranges;
694	#interrupt-cells = <0x03>;	694	#interrupt-cells = <0x03>;
695	interrupt-controller;	695	interrupt-controller;
696	reg = <0x00 0x1800000 0x00 0x10000 0x00 0x1880000 0x00 0xc0000 0x01 0x00 0x00 0x2000 0x01 0x10000 0x00 0x1000 0x01 0x20000 0x00 0x2000>;	696	reg = <0x00 0x1800000 0x00 0x10000 0x00 0x1880000 0x00 0xc0000 0x01 0x00 0x00 0x2000 0x01 0x10000 0x00 0x1000 0x01 0x20000 0x00 0x2000>;
697	interrupts = <0x01 0x09 0x04>;	697	interrupts = <0x01 0x09 0x04>;
698	phandle = <0x01>;	698	phandle = <0x01>;
699		699
700	msi-controller@1820000 {	700	msi-controller@1820000 {
701	compatible = "arm,gic-v3-its";	701	compatible = "arm,gic-v3-its";
702	reg = <0x00 0x1820000 0x00 0x10000>;	702	reg = <0x00 0x1820000 0x00 0x10000>;
703	socionext,synquacer-pre-its = <0x1000000 0x400000>;	703	socionext,synquacer-pre-its = <0x1000000 0x400000>;
704	msi-controller;	704	msi-controller;
705	#msi-cells = <0x01>;	705	#msi-cells = <0x01>;
706	phandle = <0x57>;	706	phandle = <0x57>;
707	};	707	};
708	};	708	};
709		709
710	bus@100000 {	710	bus@100000 {
711	compatible = "simple-bus";	711	compatible = "simple-bus";
712	reg = <0x00 0x100000 0x00 0x20000>;	712	reg = <0x00 0x100000 0x00 0x20000>;
713	#address-cells = <0x01>;	713	#address-cells = <0x01>;
714	#size-cells = <0x01>;	714	#size-cells = <0x01>;
715	ranges = <0x00 0x00 0x100000 0x20000>;	715	ranges = <0x00 0x00 0x100000 0x20000>;
716	phandle = <0xa0>;	716	phandle = <0xa0>;
717		717
718	phy@4044 {	718	phy@4044 {
719	compatible = "ti,am654-phy-gmii-sel";	719	compatible = "ti,am654-phy-gmii-sel";
720	reg = <0x4044 0x08>;	720	reg = <0x4044 0x08>;
721	#phy-cells = <0x01>;	721	#phy-cells = <0x01>;
722	bootph-all;	722	bootph-all;
723	phandle = <0x3f>;	723	phandle = <0x3f>;
724	};	724	};
725		725
726	clock-controller@4130 {	726	clock-controller@4130 {
727	compatible = "ti,am62-epwm-tbclk";	727	compatible = "ti,am62-epwm-tbclk";
728	reg = <0x4130 0x04>;	728	reg = <0x4130 0x04>;
729	#clock-cells = <0x01>;	729	#clock-cells = <0x01>;
730	phandle = <0x45>;	730	phandle = <0x45>;
731	};	731	};
732		732
733	dss-oldi-io-ctrl@8600 {	733	dss-oldi-io-ctrl@8600 {
734	compatible = "syscon";	734	compatible = "syscon";
735	reg = <0x8600 0x200>;	735	reg = <0x8600 0x200>;
736	phandle = <0x49>;	736	phandle = <0x49>;
737	};	737	};
738		738
739	mux-controller@4080 {	739	mux-controller@4080 {
740	compatible = "reg-mux";	740	compatible = "reg-mux";
741	reg = <0x4080 0x14>;	741	reg = <0x4080 0x14>;
742	#mux-control-cells = <0x01>;	742	#mux-control-cells = <0x01>;
743	mux-reg-masks = <0x00 0x03 0x10 0x03>;	743	mux-reg-masks = <0x00 0x03 0x10 0x03>;
744	idle-states = <0x00 0x00>;	744	idle-states = <0x00 0x00>;
745	phandle = <0xa1>;	745	phandle = <0xa1>;
746	};	746	};
747		747
748	clock@82e4 {	748	clock@82e4 {
749	compatible = "ti,am62-audio-refclk";	749	compatible = "ti,am62-audio-refclk";
750	reg = <0x82e4 0x04>;	750	reg = <0x82e4 0x04>;
751	clocks = <0x07 0x9d 0x12>;	751	clocks = <0x07 0x9d 0x12>;
752	assigned-clocks = <0x07 0x9d 0x12>;	752	assigned-clocks = <0x07 0x9d 0x12>;
753	assigned-clock-parents = <0x07 0x9d 0x21>;	753	assigned-clock-parents = <0x07 0x9d 0x21>;
754	#clock-cells = <0x00>;	754	#clock-cells = <0x00>;
755	phandle = <0x71>;	755	phandle = <0x71>;
756	};	756	};
757	};	757	};
758		758
759	bus@48000000 {	759	bus@48000000 {
760	compatible = "simple-bus";	760	compatible = "simple-bus";
761	#address-cells = <0x02>;	761	#address-cells = <0x02>;
762	#size-cells = <0x02>;	762	#size-cells = <0x02>;
763	dma-ranges;	763	dma-ranges;
764	ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x6400000>;	764	ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x6400000>;
765	bootph-all;	765	bootph-all;
766	ti,sci-dev-id = <0x19>;	766	ti,sci-dev-id = <0x19>;
767	phandle = <0xa2>;	767	phandle = <0xa2>;
768		768
769	mailbox@4d000000 {	769	mailbox@4d000000 {
770	compatible = "ti,am654-secure-proxy";	770	compatible = "ti,am654-secure-proxy";
771	#mbox-cells = <0x01>;	771	#mbox-cells = <0x01>;
772	reg-names = "target_data\0rt\0scfg";	772	reg-names = "target_data\0rt\0scfg";
773	reg = <0x00 0x4d000000 0x00 0x80000 0x00 0x4a600000 0x00 0x80000 0x00 0x4a400000 0x00 0x80000>;	773	reg = <0x00 0x4d000000 0x00 0x80000 0x00 0x4a600000 0x00 0x80000 0x00 0x4a400000 0x00 0x80000>;
774	interrupt-names = "rx_012";	774	interrupt-names = "rx_012";
775	interrupts = <0x00 0x22 0x04>;	775	interrupts = <0x00 0x22 0x04>;
776	bootph-all;	776	bootph-all;
777	phandle = <0x26>;	777	phandle = <0x26>;
778	};	778	};
779		779
780	interrupt-controller@48000000 {	780	interrupt-controller@48000000 {
781	compatible = "ti,sci-inta";	781	compatible = "ti,sci-inta";
782	reg = <0x00 0x48000000 0x00 0x100000>;	782	reg = <0x00 0x48000000 0x00 0x100000>;
783	#interrupt-cells = <0x00>;	783	#interrupt-cells = <0x00>;
784	interrupt-controller;	784	interrupt-controller;
785	interrupt-parent = <0x01>;	785	interrupt-parent = <0x01>;
786	msi-controller;	786	msi-controller;
787	ti,sci = <0x0b>;	787	ti,sci = <0x0b>;
788	ti,sci-dev-id = <0x1c>;	788	ti,sci-dev-id = <0x1c>;
789	ti,unmapped-event-sources = <0x21 0x22>;	789	ti,unmapped-event-sources = <0x21 0x22>;
790	ti,interrupt-ranges = <0x07 0x47 0x15>;	790	ti,interrupt-ranges = <0x07 0x47 0x15>;
791	phandle = <0x23>;	791	phandle = <0x23>;
792	};	792	};
793		793
794	dma-controller@485c0100 {	794	dma-controller@485c0100 {
795	compatible = "ti,am64-dmss-bcdma";	795	compatible = "ti,am64-dmss-bcdma";
796	reg = <0x00 0x485c0100 0x00 0x100 0x00 0x4c000000 0x00 0x20000 0x00 0x4a820000 0x00 0x20000 0x00 0x4aa40000 0x00 0x20000 0x00 0x4bc00000 0x00 0x100000 0x00 0x48600000 0x00 0x8000 0x00 0x484a4000 0x00 0x2000 0x00 0x484c2000 0x00 0x2000 0x00 0x48420000 0x00 0x2000>;	796	reg = <0x00 0x485c0100 0x00 0x100 0x00 0x4c000000 0x00 0x20000 0x00 0x4a820000 0x00 0x20000 0x00 0x4aa40000 0x00 0x20000 0x00 0x4bc00000 0x00 0x100000 0x00 0x48600000 0x00 0x8000 0x00 0x484a4000 0x00 0x2000 0x00 0x484c2000 0x00 0x2000 0x00 0x48420000 0x00 0x2000>;
797	reg-names = "gcfg\0bchanrt\0rchanrt\0tchanrt\0ringrt\0ring\0tchan\0rchan\0bchan";	797	reg-names = "gcfg\0bchanrt\0rchanrt\0tchanrt\0ringrt\0ring\0tchan\0rchan\0bchan";
798	msi-parent = <0x23>;	798	msi-parent = <0x23>;
799	#dma-cells = <0x03>;	799	#dma-cells = <0x03>;
800	ti,sci = <0x0b>;	800	ti,sci = <0x0b>;
801	ti,sci-dev-id = <0x1a>;	801	ti,sci-dev-id = <0x1a>;
802	ti,sci-rm-range-bchan = <0x20>;	802	ti,sci-rm-range-bchan = <0x20>;
803	ti,sci-rm-range-rchan = <0x21>;	803	ti,sci-rm-range-rchan = <0x21>;
804	ti,sci-rm-range-tchan = <0x22>;	804	ti,sci-rm-range-tchan = <0x22>;
805	bootph-all;	805	bootph-all;
806	phandle = <0x21>;	806	phandle = <0x21>;
807	};	807	};
808		808
809	dma-controller@485c0000 {	809	dma-controller@485c0000 {
810	compatible = "ti,am64-dmss-pktdma";	810	compatible = "ti,am64-dmss-pktdma";
811	reg = <0x00 0x485c0000 0x00 0x100 0x00 0x4a800000 0x00 0x20000 0x00 0x4aa00000 0x00 0x20000 0x00 0x4b800000 0x00 0x200000 0x00 0x485e0000 0x00 0x10000 0x00 0x484a0000 0x00 0x2000 0x00 0x484c0000 0x00 0x2000 0x00 0x48430000 0x00 0x1000>;	811	reg = <0x00 0x485c0000 0x00 0x100 0x00 0x4a800000 0x00 0x20000 0x00 0x4aa00000 0x00 0x20000 0x00 0x4b800000 0x00 0x200000 0x00 0x485e0000 0x00 0x10000 0x00 0x484a0000 0x00 0x2000 0x00 0x484c0000 0x00 0x2000 0x00 0x48430000 0x00 0x1000>;
812	reg-names = "gcfg\0rchanrt\0tchanrt\0ringrt\0ring\0tchan\0rchan\0rflow";	812	reg-names = "gcfg\0rchanrt\0tchanrt\0ringrt\0ring\0tchan\0rchan\0rflow";
813	msi-parent = <0x23>;	813	msi-parent = <0x23>;
814	#dma-cells = <0x02>;	814	#dma-cells = <0x02>;
815	bootph-all;	815	bootph-all;
816	ti,sci = <0x0b>;	816	ti,sci = <0x0b>;
817	ti,sci-dev-id = <0x1e>;	817	ti,sci-dev-id = <0x1e>;
818	ti,sci-rm-range-tchan = <0x23 0x24 0x25 0x26>;	818	ti,sci-rm-range-tchan = <0x23 0x24 0x25 0x26>;
819	ti,sci-rm-range-tflow = <0x10 0x11 0x12 0x13>;	819	ti,sci-rm-range-tflow = <0x10 0x11 0x12 0x13>;
820	ti,sci-rm-range-rchan = <0x29 0x2b 0x2d 0x2f 0x31 0x33>;	820	ti,sci-rm-range-rchan = <0x29 0x2b 0x2d 0x2f 0x31 0x33>;
821	ti,sci-rm-range-rflow = <0x2a 0x2c 0x2e 0x32>;	821	ti,sci-rm-range-rflow = <0x2a 0x2c 0x2e 0x32>;
822	phandle = <0x22>;	822	phandle = <0x22>;
823	};	823	};
824	};	824	};
825		825
826	bus@4e000000 {	826	bus@4e000000 {
827	compatible = "simple-bus";	827	compatible = "simple-bus";
828	ranges = <0x00 0x4e000000 0x00 0x4e000000 0x00 0x408000>;	828	ranges = <0x00 0x4e000000 0x00 0x4e000000 0x00 0x408000>;
829	#address-cells = <0x02>;	829	#address-cells = <0x02>;
830	#size-cells = <0x02>;	830	#size-cells = <0x02>;
831	dma-ranges;	831	dma-ranges;
832	ti,sci-dev-id = <0xc6>;	832	ti,sci-dev-id = <0xc6>;
833	phandle = <0xa3>;	833	phandle = <0xa3>;
834		834
835	interrupt-controller@4e400000 {	835	interrupt-controller@4e400000 {
836	compatible = "ti,sci-inta";	836	compatible = "ti,sci-inta";
837	reg = <0x00 0x4e400000 0x00 0x8000>;	837	reg = <0x00 0x4e400000 0x00 0x8000>;
838	#interrupt-cells = <0x00>;	838	#interrupt-cells = <0x00>;
839	interrupt-controller;	839	interrupt-controller;
840	interrupt-parent = <0x01>;	840	interrupt-parent = <0x01>;
841	msi-controller;	841	msi-controller;
842	power-domains = <0x09 0xb6 0x01>;	842	power-domains = <0x09 0xb6 0x01>;
843	ti,sci = <0x0b>;	843	ti,sci = <0x0b>;
844	ti,sci-dev-id = <0xc8>;	844	ti,sci-dev-id = <0xc8>;
845	ti,interrupt-ranges = <0x00 0xed 0x08>;	845	ti,interrupt-ranges = <0x00 0xed 0x08>;
846	ti,unmapped-event-sources = <0x24>;	846	ti,unmapped-event-sources = <0x24>;
847	phandle = <0x25>;	847	phandle = <0x25>;
848	};	848	};
849		849
850	dma-controller@4e230000 {	850	dma-controller@4e230000 {
851	compatible = "ti,j722s-dmss-bcdma-csi";	851	compatible = "ti,j722s-dmss-bcdma-csi";
852	reg = <0x00 0x4e230000 0x00 0x100 0x00 0x4e180000 0x00 0x20000 0x00 0x4e300000 0x00 0x10000 0x00 0x4e100000 0x00 0x80000>;	852	reg = <0x00 0x4e230000 0x00 0x100 0x00 0x4e180000 0x00 0x20000 0x00 0x4e300000 0x00 0x10000 0x00 0x4e100000 0x00 0x80000>;
853	reg-names = "gcfg\0rchanrt\0tchanrt\0ringrt";	853	reg-names = "gcfg\0rchanrt\0tchanrt\0ringrt";
854	#dma-cells = <0x03>;	854	#dma-cells = <0x03>;
855	msi-parent = <0x25>;	855	msi-parent = <0x25>;
856	power-domains = <0x09 0xb6 0x01>;	856	power-domains = <0x09 0xb6 0x01>;
857	ti,sci = <0x0b>;	857	ti,sci = <0x0b>;
858	ti,sci-dev-id = <0xc7>;	858	ti,sci-dev-id = <0xc7>;
859	ti,sci-rm-range-rchan = <0x21>;	859	ti,sci-rm-range-rchan = <0x21>;
860	ti,sci-rm-range-tchan = <0x22>;	860	ti,sci-rm-range-tchan = <0x22>;
861	phandle = <0x24>;	861	phandle = <0x24>;
862	};	862	};
863	};	863	};
864		864
865	system-controller@44043000 {	865	system-controller@44043000 {
866	compatible = "ti,k2g-sci";	866	compatible = "ti,k2g-sci";
867	ti,host-id = <0x0c>;	867	ti,host-id = <0x0c>;
868	mbox-names = "rx\0tx";	868	mbox-names = "rx\0tx";
869	mboxes = <0x26 0x0c 0x26 0x0d>;	869	mboxes = <0x26 0x0c 0x26 0x0d>;
870	reg-names = "debug_messages";	870	reg-names = "debug_messages";
871	reg = <0x00 0x44043000 0x00 0xfe0>;	871	reg = <0x00 0x44043000 0x00 0xfe0>;
872	bootph-all;	872	bootph-all;
873	phandle = <0x0b>;	873	phandle = <0x0b>;
874		874
875	power-controller {	875	power-controller {
876	compatible = "ti,sci-pm-domain";	876	compatible = "ti,sci-pm-domain";
877	#power-domain-cells = <0x02>;	877	#power-domain-cells = <0x02>;
878	bootph-all;	878	bootph-all;
879	phandle = <0x09>;	879	phandle = <0x09>;
880	};	880	};
881		881
882	clock-controller {	882	clock-controller {
883	compatible = "ti,k2g-sci-clk";	883	compatible = "ti,k2g-sci-clk";
884	#clock-cells = <0x02>;	884	#clock-cells = <0x02>;
885	bootph-all;	885	bootph-all;
886	pinctrl-names = "default";	886	pinctrl-names = "default";
887	pinctrl-0 = <0x27>;	887	pinctrl-0 = <0x27>;
888	phandle = <0x07>;	888	phandle = <0x07>;
889	};	889	};
890		890
891	reset-controller {	891	reset-controller {
892	compatible = "ti,sci-reset";	892	compatible = "ti,sci-reset";
893	#reset-cells = <0x02>;	893	#reset-cells = <0x02>;
894	bootph-all;	894	bootph-all;
895	phandle = <0x12>;	895	phandle = <0x12>;
896	};	896	};
897	};	897	};
898		898
899	crypto@40900000 {	899	crypto@40900000 {
900	compatible = "ti,am62-sa3ul";	900	compatible = "ti,am62-sa3ul";
901	reg = <0x00 0x40900000 0x00 0x1200>;	901	reg = <0x00 0x40900000 0x00 0x1200>;
902	#address-cells = <0x02>;	902	#address-cells = <0x02>;
903	#size-cells = <0x02>;	903	#size-cells = <0x02>;
904	dmas = <0x22 0xf501 0x00 0x22 0x7506 0x00 0x22 0x7507 0x00>;	904	dmas = <0x22 0xf501 0x00 0x22 0x7506 0x00 0x22 0x7507 0x00>;
905	dma-names = "tx\0rx1\0rx2";	905	dma-names = "tx\0rx1\0rx2";
906	phandle = <0xa4>;	906	phandle = <0xa4>;
907	};	907	};
908		908
909	crc@30300000 {	909	crc@30300000 {
910	compatible = "ti,am62-mcrc64";	910	compatible = "ti,am62-mcrc64";
911	reg = <0x00 0x30300000 0x00 0x1000>;	911	reg = <0x00 0x30300000 0x00 0x1000>;
912	clocks = <0x07 0x74 0x00>;	912	clocks = <0x07 0x74 0x00>;
913	power-domains = <0x09 0x74 0x01>;	913	power-domains = <0x09 0x74 0x01>;
914	phandle = <0xa5>;	914	phandle = <0xa5>;
915	};	915	};
916		916
917	mailbox@43600000 {	917	mailbox@43600000 {
918	compatible = "ti,am654-secure-proxy";	918	compatible = "ti,am654-secure-proxy";
919	#mbox-cells = <0x01>;	919	#mbox-cells = <0x01>;
920	reg-names = "target_data\0rt\0scfg";	920	reg-names = "target_data\0rt\0scfg";
921	reg = <0x00 0x43600000 0x00 0x10000 0x00 0x44880000 0x00 0x20000 0x00 0x44860000 0x00 0x20000>;	921	reg = <0x00 0x43600000 0x00 0x10000 0x00 0x44880000 0x00 0x20000 0x00 0x44860000 0x00 0x20000>;
922	status = "disabled";	922	status = "disabled";
923	bootph-all;	923	bootph-all;
924	phandle = <0xa6>;	924	phandle = <0xa6>;
925	};	925	};
926		926
927	pinctrl@f4000 {	927	pinctrl@f4000 {
928	compatible = "ti,am654-padconf\0pinctrl-single";	928	compatible = "ti,am654-padconf\0pinctrl-single";
929	reg = <0x00 0xf4000 0x00 0x2ac>;	929	reg = <0x00 0xf4000 0x00 0x2ac>;
930	#pinctrl-cells = <0x01>;	930	#pinctrl-cells = <0x01>;
931	pinctrl-single,register-width = <0x20>;	931	pinctrl-single,register-width = <0x20>;
932	pinctrl-single,function-mask = <0xffffffff>;	932	pinctrl-single,function-mask = <0xffffffff>;
933	interrupt-controller;	933	interrupt-controller;
934	#interrupt-cells = <0x01>;	934	#interrupt-cells = <0x01>;
935	bootph-all;	935	bootph-all;
936	pinctrl-single,gpio-range = <0x28 0x00 0x20 0x54007 0x28 0x21 0x26 0x54007 0x28 0x48 0x11 0x54007 0x28 0x65 0x19 0x54007 0x28 0x89 0x05 0x54007 0x28 0x8f 0x03 0x54007 0x28 0x95 0x02 0x54007>;	936	pinctrl-single,gpio-range = <0x28 0x00 0x20 0x54007 0x28 0x21 0x26 0x54007 0x28 0x48 0x11 0x54007 0x28 0x65 0x19 0x54007 0x28 0x89 0x05 0x54007 0x28 0x8f 0x03 0x54007 0x28 0x95 0x02 0x54007>;
937	phandle = <0x38>;	937	phandle = <0x38>;
938		938
939	gpio-range {	939	gpio-range {
940	#pinctrl-single,gpio-range-cells = <0x03>;	940	#pinctrl-single,gpio-range-cells = <0x03>;
941	phandle = <0x28>;	941	phandle = <0x28>;
942	};	942	};
943		943
944	main-mcan0-default-pins {	944	main-mcan0-default-pins {
945	pinctrl-single,pins = <0x1dc 0x54000 0x1d8 0x10000>;	945	pinctrl-single,pins = <0x1dc 0x54000 0x1d8 0x10000>;
946	phandle = <0x43>;	946	phandle = <0x43>;
947	};	947	};
948		948
949	main-i2c0-default-pins {	949	main-i2c0-default-pins {
950	pinctrl-single,pins = <0x1e0 0x64000 0x1e4 0x64000>;	950	pinctrl-single,pins = <0x1e0 0x64000 0x1e4 0x64000>;
951	bootph-all;	951	bootph-all;
952	phandle = <0x2b>;	952	phandle = <0x2b>;
953	};	953	};
954		954
955	main-i2c1-default-pins {	955	main-i2c1-default-pins {
956	pinctrl-single,pins = <0x1e8 0x64000 0x1ec 0x64000>;	956	pinctrl-single,pins = <0x1e8 0x64000 0x1ec 0x64000>;
957	bootph-all;	957	bootph-all;
958	phandle = <0x2d>;	958	phandle = <0x2d>;
959	};	959	};
960		960
961	main-i2c2-default-pins {	961	main-i2c2-default-pins {
962	pinctrl-single,pins = <0xb0 0x64001 0xb4 0x64001>;	962	pinctrl-single,pins = <0xb0 0x64001 0xb4 0x64001>;
963	phandle = <0x36>;	963	phandle = <0x36>;
964	};	964	};
965		965
966	main-uart0-default-pins {	966	main-uart0-default-pins {
967	pinctrl-single,pins = <0x1c8 0x54000 0x1cc 0x10000>;	967	pinctrl-single,pins = <0x1c8 0x54000 0x1cc 0x10000>;
968	bootph-all;	968	bootph-all;
969	phandle = <0x29>;	969	phandle = <0x29>;
970	};	970	};
971		971
972	main-uart5-default-pins {	972	main-uart5-default-pins {
973	pinctrl-single,pins = <0x108 0x54003 0x10c 0x10003>;	973	pinctrl-single,pins = <0x108 0x54003 0x10c 0x10003>;
974	phandle = <0x2a>;	974	phandle = <0x2a>;
975	};	975	};
976		976
977	vdd-sd-dv-default-pins {	977	vdd-sd-dv-default-pins {
978	pinctrl-single,pins = <0x120 0x54007>;	978	pinctrl-single,pins = <0x120 0x54007>;
979	bootph-all;	979	bootph-all;
980	phandle = <0x6c>;	980	phandle = <0x6c>;
981	};	981	};
982		982
983	main-mmc1-default-pins {	983	main-mmc1-default-pins {
984	pinctrl-single,pins = <0x23c 0x54000 0x234 0x10000 0x230 0x54000 0x22c 0x64000 0x228 0x64000 0x224 0x64000 0x240 0x54000>;	984	pinctrl-single,pins = <0x23c 0x54000 0x234 0x10000 0x230 0x54000 0x22c 0x64000 0x228 0x64000 0x224 0x64000 0x240 0x54000>;
985	bootph-all;	985	bootph-all;
986	phandle = <0x3b>;	986	phandle = <0x3b>;
987	};	987	};
988		988
989	mdio-default-pins {	989	mdio-default-pins {
990	pinctrl-single,pins = <0x160 0x10000 0x15c 0x54000>;	990	pinctrl-single,pins = <0x160 0x10000 0x15c 0x54000>;
991	bootph-all;	991	bootph-all;
992	phandle = <0x42>;	992	phandle = <0x42>;
993	};	993	};
994		994
995	ospi0-default-pins {	995	ospi0-default-pins {
996	pinctrl-single,pins = <0x00 0x10000 0x2c 0x10000 0x0c 0x54000 0x10 0x54000 0x14 0x54000 0x18 0x54000 0x1c 0x54000 0x20 0x54000 0x24 0x54000 0x28 0x54000 0x08 0x54000>;	996	pinctrl-single,pins = <0x00 0x10000 0x2c 0x10000 0x0c 0x54000 0x10 0x54000 0x14 0x54000 0x18 0x54000 0x1c 0x54000 0x20 0x54000 0x24 0x54000 0x28 0x54000 0x08 0x54000>;
997	bootph-all;	997	bootph-all;
998	phandle = <0x3d>;	998	phandle = <0x3d>;
999	};	999	};
1000		1000
1001	rgmii1-default-pins {	1001	rgmii1-default-pins {
1002	pinctrl-single,pins = <0x14c 0x54000 0x150 0x54000 0x154 0x54000 0x158 0x54000 0x148 0x54000 0x144 0x54000 0x134 0x10000 0x138 0x10000 0x13c 0x10000 0x140 0x10000 0x130 0x10000 0x12c 0x10000>;	1002	pinctrl-single,pins = <0x14c 0x54000 0x150 0x54000 0x154 0x54000 0x158 0x54000 0x148 0x54000 0x144 0x54000 0x134 0x10000 0x138 0x10000 0x13c 0x10000 0x140 0x10000 0x130 0x10000 0x12c 0x10000>;
1003	bootph-all;	1003	bootph-all;
1004	phandle = <0x3e>;	1004	phandle = <0x3e>;
1005	};	1005	};
1006		1006
1007	main-usb1-default-pins {	1007	main-usb1-default-pins {
1008	pinctrl-single,pins = <0x258 0x54000>;	1008	pinctrl-single,pins = <0x258 0x54000>;
1009	phandle = <0x5a>;	1009	phandle = <0x5a>;
1010	};	1010	};
1011		1011
1012	main-mcasp1-default-pins {	1012	main-mcasp1-default-pins {
1013	pinctrl-single,pins = <0x90 0x54002 0x98 0x54002 0x8c 0x10002 0x84 0x54002>;	1013	pinctrl-single,pins = <0x90 0x54002 0x98 0x54002 0x8c 0x10002 0x84 0x54002>;
1014	phandle = <0x46>;	1014	phandle = <0x46>;
1015	};	1015	};
1016		1016
1017	audio-ext-refclk1-default-pins {	1017	audio-ext-refclk1-default-pins {
1018	pinctrl-single,pins = <0xa0 0x10001>;	1018	pinctrl-single,pins = <0xa0 0x10001>;
1019	phandle = <0x27>;	1019	phandle = <0x27>;
1020	};	1020	};
1021		1021
1022	pmic-irq-default-pins {	1022	pmic-irq-default-pins {
1023	pinctrl-single,pins = <0x30 0x54007>;	1023	pinctrl-single,pins = <0x30 0x54007>;
1024	phandle = <0x1a>;	1024	phandle = <0x1a>;
1025	};	1025	};
1026		1026
1027	main-gpio0-ioexp-intr-default-pins {	1027	main-gpio0-ioexp-intr-default-pins {
1028	pinctrl-single,pins = <0x110 0x54007>;	1028	pinctrl-single,pins = <0x110 0x54007>;
1029	phandle = <0x2e>;	1029	phandle = <0x2e>;
1030	};	1030	};
1031		1031
1032	main-dpi-default-pins {	1032	main-dpi-default-pins {
1033	pinctrl-single,pins = <0x100 0x10000 0xf8 0x10000 0x104 0x10000 0xfc 0x10000 0xb8 0x10000 0xbc 0x10000 0xc0 0x10000 0xc4 0x10000 0xc8 0x10000 0xcc 0x10000 0xd0 0x10000 0xd4 0x10000 0xd8 0x10000 0xdc 0x10000 0xe0 0x10000 0xe4 0x10000 0xe8 0x10000 0xec 0x10000 0xf0 0x10000 0xf4 0x10000 0x5c 0x10001 0x60 0x10001 0x64 0x10001 0x68 0x10001 0x6c 0x10001 0x70 0x10001 0x74 0x10001 0x78 0x10001 0x9c 0x10001>;	1033	pinctrl-single,pins = <0x100 0x10000 0xf8 0x10000 0x104 0x10000 0xfc 0x10000 0xb8 0x10000 0xbc 0x10000 0xc0 0x10000 0xc4 0x10000 0xc8 0x10000 0xcc 0x10000 0xd0 0x10000 0xd4 0x10000 0xd8 0x10000 0xdc 0x10000 0xe0 0x10000 0xe4 0x10000 0xe8 0x10000 0xec 0x10000 0xf0 0x10000 0xf4 0x10000 0x5c 0x10001 0x60 0x10001 0x64 0x10001 0x68 0x10001 0x6c 0x10001 0x70 0x10001 0x74 0x10001 0x78 0x10001 0x9c 0x10001>;
1034	phandle = <0x4a>;	1034	phandle = <0x4a>;
1035	};	1035	};
1036	};	1036	};
1037		1037
1038	esm@420000 {	1038	esm@420000 {
1039	compatible = "ti,j721e-esm";	1039	compatible = "ti,j721e-esm";
1040	reg = <0x00 0x420000 0x00 0x1000>;	1040	reg = <0x00 0x420000 0x00 0x1000>;
1041	bootph-pre-ram;	1041	bootph-pre-ram;
1042	ti,esm-pins = <0xe0 0xe1 0xe3 0xf1 0xf2 0xf8>;	1042	ti,esm-pins = <0xe0 0xe1 0xe3 0xf1 0xf2 0xf8>;
1043	phandle = <0xa7>;	1043	phandle = <0xa7>;
1044	};	1044	};
1045		1045
1046	timer@2400000 {	1046	timer@2400000 {
1047	compatible = "ti,am654-timer";	1047	compatible = "ti,am654-timer";
1048	reg = <0x00 0x2400000 0x00 0x400>;	1048	reg = <0x00 0x2400000 0x00 0x400>;
1049	interrupts = <0x00 0x78 0x04>;	1049	interrupts = <0x00 0x78 0x04>;
1050	clocks = <0x07 0x24 0x02>;	1050	clocks = <0x07 0x24 0x02>;
1051	clock-names = "fck";	1051	clock-names = "fck";
1052	assigned-clocks = <0x07 0x24 0x02>;	1052	assigned-clocks = <0x07 0x24 0x02>;
1053	assigned-clock-parents = <0x07 0x24 0x03>;	1053	assigned-clock-parents = <0x07 0x24 0x03>;
1054	power-domains = <0x09 0x24 0x01>;	1054	power-domains = <0x09 0x24 0x01>;
1055	ti,timer-pwm;	1055	ti,timer-pwm;
1056	bootph-all;	1056	bootph-all;
1057	status = "reserved";	1057	status = "reserved";
1058	phandle = <0xa8>;	1058	phandle = <0xa8>;
1059	};	1059	};
1060		1060
1061	timer@2410000 {	1061	timer@2410000 {
1062	compatible = "ti,am654-timer";	1062	compatible = "ti,am654-timer";
1063	reg = <0x00 0x2410000 0x00 0x400>;	1063	reg = <0x00 0x2410000 0x00 0x400>;
1064	interrupts = <0x00 0x79 0x04>;	1064	interrupts = <0x00 0x79 0x04>;
1065	clocks = <0x07 0x25 0x02>;	1065	clocks = <0x07 0x25 0x02>;
1066	clock-names = "fck";	1066	clock-names = "fck";
1067	assigned-clocks = <0x07 0x25 0x02>;	1067	assigned-clocks = <0x07 0x25 0x02>;
1068	assigned-clock-parents = <0x07 0x25 0x03>;	1068	assigned-clock-parents = <0x07 0x25 0x03>;
1069	power-domains = <0x09 0x25 0x01>;	1069	power-domains = <0x09 0x25 0x01>;
1070	ti,timer-pwm;	1070	ti,timer-pwm;
1071	status = "reserved";	1071	status = "reserved";
1072	phandle = <0xa9>;	1072	phandle = <0xa9>;
1073	};	1073	};
1074		1074
1075	timer@2420000 {	1075	timer@2420000 {
1076	compatible = "ti,am654-timer";	1076	compatible = "ti,am654-timer";
1077	reg = <0x00 0x2420000 0x00 0x400>;	1077	reg = <0x00 0x2420000 0x00 0x400>;
1078	interrupts = <0x00 0x7a 0x04>;	1078	interrupts = <0x00 0x7a 0x04>;
1079	clocks = <0x07 0x26 0x02>;	1079	clocks = <0x07 0x26 0x02>;
1080	clock-names = "fck";	1080	clock-names = "fck";
1081	assigned-clocks = <0x07 0x26 0x02>;	1081	assigned-clocks = <0x07 0x26 0x02>;
1082	assigned-clock-parents = <0x07 0x26 0x03>;	1082	assigned-clock-parents = <0x07 0x26 0x03>;
1083	power-domains = <0x09 0x26 0x01>;	1083	power-domains = <0x09 0x26 0x01>;
1084	ti,timer-pwm;	1084	ti,timer-pwm;
1085	status = "reserved";	1085	status = "reserved";
1086	phandle = <0xaa>;	1086	phandle = <0xaa>;
1087	};	1087	};
1088		1088
1089	timer@2430000 {	1089	timer@2430000 {
1090	compatible = "ti,am654-timer";	1090	compatible = "ti,am654-timer";
1091	reg = <0x00 0x2430000 0x00 0x400>;	1091	reg = <0x00 0x2430000 0x00 0x400>;
1092	interrupts = <0x00 0x7b 0x04>;	1092	interrupts = <0x00 0x7b 0x04>;
1093	clocks = <0x07 0x27 0x02>;	1093	clocks = <0x07 0x27 0x02>;
1094	clock-names = "fck";	1094	clock-names = "fck";
1095	assigned-clocks = <0x07 0x27 0x02>;	1095	assigned-clocks = <0x07 0x27 0x02>;
1096	assigned-clock-parents = <0x07 0x27 0x03>;	1096	assigned-clock-parents = <0x07 0x27 0x03>;
1097	power-domains = <0x09 0x27 0x01>;	1097	power-domains = <0x09 0x27 0x01>;
1098	ti,timer-pwm;	1098	ti,timer-pwm;
1099	phandle = <0xab>;	1099	phandle = <0xab>;
1100	};	1100	};
1101		1101
1102	timer@2440000 {	1102	timer@2440000 {
1103	compatible = "ti,am654-timer";	1103	compatible = "ti,am654-timer";
1104	reg = <0x00 0x2440000 0x00 0x400>;	1104	reg = <0x00 0x2440000 0x00 0x400>;
1105	interrupts = <0x00 0x7c 0x04>;	1105	interrupts = <0x00 0x7c 0x04>;
1106	clocks = <0x07 0x28 0x02>;	1106	clocks = <0x07 0x28 0x02>;
1107	clock-names = "fck";	1107	clock-names = "fck";
1108	assigned-clocks = <0x07 0x28 0x02>;	1108	assigned-clocks = <0x07 0x28 0x02>;
1109	assigned-clock-parents = <0x07 0x28 0x03>;	1109	assigned-clock-parents = <0x07 0x28 0x03>;
1110	power-domains = <0x09 0x28 0x01>;	1110	power-domains = <0x09 0x28 0x01>;
1111	ti,timer-pwm;	1111	ti,timer-pwm;
1112	phandle = <0xac>;	1112	phandle = <0xac>;
1113	};	1113	};
1114		1114
1115	timer@2450000 {	1115	timer@2450000 {
1116	compatible = "ti,am654-timer";	1116	compatible = "ti,am654-timer";
1117	reg = <0x00 0x2450000 0x00 0x400>;	1117	reg = <0x00 0x2450000 0x00 0x400>;
1118	interrupts = <0x00 0x7d 0x04>;	1118	interrupts = <0x00 0x7d 0x04>;
1119	clocks = <0x07 0x29 0x02>;	1119	clocks = <0x07 0x29 0x02>;
1120	clock-names = "fck";	1120	clock-names = "fck";
1121	assigned-clocks = <0x07 0x29 0x02>;	1121	assigned-clocks = <0x07 0x29 0x02>;
1122	assigned-clock-parents = <0x07 0x29 0x03>;	1122	assigned-clock-parents = <0x07 0x29 0x03>;
1123	power-domains = <0x09 0x29 0x01>;	1123	power-domains = <0x09 0x29 0x01>;
1124	ti,timer-pwm;	1124	ti,timer-pwm;
1125	phandle = <0xad>;	1125	phandle = <0xad>;
1126	};	1126	};
1127		1127
1128	timer@2460000 {	1128	timer@2460000 {
1129	compatible = "ti,am654-timer";	1129	compatible = "ti,am654-timer";
1130	reg = <0x00 0x2460000 0x00 0x400>;	1130	reg = <0x00 0x2460000 0x00 0x400>;
1131	interrupts = <0x00 0x7e 0x04>;	1131	interrupts = <0x00 0x7e 0x04>;
1132	clocks = <0x07 0x2a 0x02>;	1132	clocks = <0x07 0x2a 0x02>;
1133	clock-names = "fck";	1133	clock-names = "fck";
1134	assigned-clocks = <0x07 0x2a 0x02>;	1134	assigned-clocks = <0x07 0x2a 0x02>;
1135	assigned-clock-parents = <0x07 0x2a 0x03>;	1135	assigned-clock-parents = <0x07 0x2a 0x03>;
1136	power-domains = <0x09 0x2a 0x01>;	1136	power-domains = <0x09 0x2a 0x01>;
1137	ti,timer-pwm;	1137	ti,timer-pwm;
1138	phandle = <0xae>;	1138	phandle = <0xae>;
1139	};	1139	};
1140		1140
1141	timer@2470000 {	1141	timer@2470000 {
1142	compatible = "ti,am654-timer";	1142	compatible = "ti,am654-timer";
1143	reg = <0x00 0x2470000 0x00 0x400>;	1143	reg = <0x00 0x2470000 0x00 0x400>;
1144	interrupts = <0x00 0x7f 0x04>;	1144	interrupts = <0x00 0x7f 0x04>;
1145	clocks = <0x07 0x2b 0x02>;	1145	clocks = <0x07 0x2b 0x02>;
1146	clock-names = "fck";	1146	clock-names = "fck";
1147	assigned-clocks = <0x07 0x2b 0x02>;	1147	assigned-clocks = <0x07 0x2b 0x02>;
1148	assigned-clock-parents = <0x07 0x2b 0x03>;	1148	assigned-clock-parents = <0x07 0x2b 0x03>;
1149	power-domains = <0x09 0x2b 0x01>;	1149	power-domains = <0x09 0x2b 0x01>;
1150	ti,timer-pwm;	1150	ti,timer-pwm;
1151	phandle = <0xaf>;	1151	phandle = <0xaf>;
1152	};	1152	};
1153		1153
1154	serial@2800000 {	1154	serial@2800000 {
1155	compatible = "ti,am64-uart\0ti,am654-uart";	1155	compatible = "ti,am64-uart\0ti,am654-uart";
1156	reg = <0x00 0x2800000 0x00 0x100>;	1156	reg = <0x00 0x2800000 0x00 0x100>;
1157	interrupts = <0x00 0xb2 0x04>;	1157	interrupts = <0x00 0xb2 0x04>;
1158	power-domains = <0x09 0x92 0x01>;	1158	power-domains = <0x09 0x92 0x01>;
1159	clocks = <0x07 0x92 0x00>;	1159	clocks = <0x07 0x92 0x00>;
1160	clock-names = "fclk";	1160	clock-names = "fclk";
1161	status = "okay";	1161	status = "okay";
1162	pinctrl-names = "default";	1162	pinctrl-names = "default";
1163	pinctrl-0 = <0x29>;	1163	pinctrl-0 = <0x29>;
1164	bootph-all;	1164	bootph-all;
1165	phandle = <0xb0>;	1165	phandle = <0xb0>;
1166	};	1166	};
1167		1167
1168	serial@2810000 {	1168	serial@2810000 {
1169	compatible = "ti,am64-uart\0ti,am654-uart";	1169	compatible = "ti,am64-uart\0ti,am654-uart";
1170	reg = <0x00 0x2810000 0x00 0x100>;	1170	reg = <0x00 0x2810000 0x00 0x100>;
1171	interrupts = <0x00 0xb3 0x04>;	1171	interrupts = <0x00 0xb3 0x04>;
1172	power-domains = <0x09 0x98 0x01>;	1172	power-domains = <0x09 0x98 0x01>;
1173	clocks = <0x07 0x98 0x00>;	1173	clocks = <0x07 0x98 0x00>;
1174	clock-names = "fclk";	1174	clock-names = "fclk";
1175	status = "disabled";	1175	status = "disabled";
1176	phandle = <0xb1>;	1176	phandle = <0xb1>;
1177	};	1177	};
1178		1178
1179	serial@2820000 {	1179	serial@2820000 {
1180	compatible = "ti,am64-uart\0ti,am654-uart";	1180	compatible = "ti,am64-uart\0ti,am654-uart";
1181	reg = <0x00 0x2820000 0x00 0x100>;	1181	reg = <0x00 0x2820000 0x00 0x100>;
1182	interrupts = <0x00 0xb4 0x04>;	1182	interrupts = <0x00 0xb4 0x04>;
1183	power-domains = <0x09 0x99 0x01>;	1183	power-domains = <0x09 0x99 0x01>;
1184	clocks = <0x07 0x99 0x00>;	1184	clocks = <0x07 0x99 0x00>;
1185	clock-names = "fclk";	1185	clock-names = "fclk";
1186	status = "disabled";	1186	status = "disabled";
1187	phandle = <0xb2>;	1187	phandle = <0xb2>;
1188	};	1188	};
1189		1189
1190	serial@2830000 {	1190	serial@2830000 {
1191	compatible = "ti,am64-uart\0ti,am654-uart";	1191	compatible = "ti,am64-uart\0ti,am654-uart";
1192	reg = <0x00 0x2830000 0x00 0x100>;	1192	reg = <0x00 0x2830000 0x00 0x100>;
1193	interrupts = <0x00 0xb5 0x04>;	1193	interrupts = <0x00 0xb5 0x04>;
1194	power-domains = <0x09 0x9a 0x01>;	1194	power-domains = <0x09 0x9a 0x01>;
1195	clocks = <0x07 0x9a 0x00>;	1195	clocks = <0x07 0x9a 0x00>;
1196	clock-names = "fclk";	1196	clock-names = "fclk";
1197	status = "disabled";	1197	status = "disabled";
1198	phandle = <0xb3>;	1198	phandle = <0xb3>;
1199	};	1199	};
1200		1200
1201	serial@2840000 {	1201	serial@2840000 {
1202	compatible = "ti,am64-uart\0ti,am654-uart";	1202	compatible = "ti,am64-uart\0ti,am654-uart";
1203	reg = <0x00 0x2840000 0x00 0x100>;	1203	reg = <0x00 0x2840000 0x00 0x100>;
1204	interrupts = <0x00 0xb6 0x04>;	1204	interrupts = <0x00 0xb6 0x04>;
1205	power-domains = <0x09 0x9b 0x01>;	1205	power-domains = <0x09 0x9b 0x01>;
1206	clocks = <0x07 0x9b 0x00>;	1206	clocks = <0x07 0x9b 0x00>;
1207	clock-names = "fclk";	1207	clock-names = "fclk";
1208	status = "disabled";	1208	status = "disabled";
1209	phandle = <0xb4>;	1209	phandle = <0xb4>;
1210	};	1210	};
1211		1211
1212	serial@2850000 {	1212	serial@2850000 {
1213	compatible = "ti,am64-uart\0ti,am654-uart";	1213	compatible = "ti,am64-uart\0ti,am654-uart";
1214	reg = <0x00 0x2850000 0x00 0x100>;	1214	reg = <0x00 0x2850000 0x00 0x100>;
1215	interrupts = <0x00 0xb7 0x04>;	1215	interrupts = <0x00 0xb7 0x04>;
1216	power-domains = <0x09 0x9c 0x01>;	1216	power-domains = <0x09 0x9c 0x01>;
1217	clocks = <0x07 0x9c 0x00>;	1217	clocks = <0x07 0x9c 0x00>;
1218	clock-names = "fclk";	1218	clock-names = "fclk";
1219	status = "reserved";	1219	status = "reserved";
1220	pinctrl-names = "default";	1220	pinctrl-names = "default";
1221	pinctrl-0 = <0x2a>;	1221	pinctrl-0 = <0x2a>;
1222	phandle = <0xb5>;	1222	phandle = <0xb5>;
1223	};	1223	};
1224		1224
1225	serial@2860000 {	1225	serial@2860000 {
1226	compatible = "ti,am64-uart\0ti,am654-uart";	1226	compatible = "ti,am64-uart\0ti,am654-uart";
1227	reg = <0x00 0x2860000 0x00 0x100>;	1227	reg = <0x00 0x2860000 0x00 0x100>;
1228	interrupts = <0x00 0xb8 0x04>;	1228	interrupts = <0x00 0xb8 0x04>;
1229	power-domains = <0x09 0x9e 0x01>;	1229	power-domains = <0x09 0x9e 0x01>;
1230	clocks = <0x07 0x9e 0x00>;	1230	clocks = <0x07 0x9e 0x00>;
1231	clock-names = "fclk";	1231	clock-names = "fclk";
1232	status = "disabled";	1232	status = "disabled";
1233	phandle = <0xb6>;	1233	phandle = <0xb6>;
1234	};	1234	};
1235		1235
1236	i2c@20000000 {	1236	i2c@20000000 {
1237	compatible = "ti,am64-i2c\0ti,omap4-i2c";	1237	compatible = "ti,am64-i2c\0ti,omap4-i2c";
1238	reg = <0x00 0x20000000 0x00 0x100>;	1238	reg = <0x00 0x20000000 0x00 0x100>;
1239	interrupts = <0x00 0xa1 0x04>;	1239	interrupts = <0x00 0xa1 0x04>;
1240	#address-cells = <0x01>;	1240	#address-cells = <0x01>;
1241	#size-cells = <0x00>;	1241	#size-cells = <0x00>;
1242	power-domains = <0x09 0x66 0x01>;	1242	power-domains = <0x09 0x66 0x01>;
1243	clocks = <0x07 0x66 0x02>;	1243	clocks = <0x07 0x66 0x02>;
1244	clock-names = "fck";	1244	clock-names = "fck";
1245	status = "okay";	1245	status = "okay";
1246	pinctrl-names = "default";	1246	pinctrl-names = "default";
1247	pinctrl-0 = <0x2b>;	1247	pinctrl-0 = <0x2b>;
1248	clock-frequency = <0x61a80>;	1248	clock-frequency = <0x61a80>;
1249	bootph-all;	1249	bootph-all;
1250	phandle = <0xb7>;	1250	phandle = <0xb7>;
1251		1251
1252	gpio@23 {	1252	gpio@23 {
1253	compatible = "ti,tca6424";	1253	compatible = "ti,tca6424";
1254	reg = <0x23>;	1254	reg = <0x23>;
1255	gpio-controller;	1255	gpio-controller;
1256	#gpio-cells = <0x02>;	1256	#gpio-cells = <0x02>;
1257	gpio-line-names = "TRC_MUX_SEL\0OSPI/ONAND_MUX_SEL\0MCASP1_FET_SEL\0CTRL_PM_I2C_OE#\0CSI_VIO_SEL\0USB2.0_MUX_SEL\0CSI01_MUX_SEL_2\0CSI23_MUX_SEL_2\0LMK1_OE1\0LMK1_OE0\0LMK2_OE0\0LMK2_OE1\0GPIO_RGMII1_RST#\0GPIO_AUD_RSTn\0GPIO_eMMC_RSTn\0GPIO_uSD_PWR_EN\0USER_LED2\0MCAN0_STB\0PCIe0_1L_RC_RSTz\0PCIe0_1L_PRSNT#\0ENET1_EXP_SPARE2\0ENET1_EXP_PWRDN\0PD_I2ENET1_I2CMUX_SELC_IRQ\0ENET1_EXP_RESETZ";	1257	gpio-line-names = "TRC_MUX_SEL\0OSPI/ONAND_MUX_SEL\0MCASP1_FET_SEL\0CTRL_PM_I2C_OE#\0CSI_VIO_SEL\0USB2.0_MUX_SEL\0CSI01_MUX_SEL_2\0CSI23_MUX_SEL_2\0LMK1_OE1\0LMK1_OE0\0LMK2_OE0\0LMK2_OE1\0GPIO_RGMII1_RST#\0GPIO_AUD_RSTn\0GPIO_eMMC_RSTn\0GPIO_uSD_PWR_EN\0USER_LED2\0MCAN0_STB\0PCIe0_1L_RC_RSTz\0PCIe0_1L_PRSNT#\0ENET1_EXP_SPARE2\0ENET1_EXP_PWRDN\0PD_I2ENET1_I2CMUX_SELC_IRQ\0ENET1_EXP_RESETZ";
1258	bootph-all;	1258	bootph-all;
1259	phandle = <0x58>;	1259	phandle = <0x58>;
1260		1260
1261	p05-hog {	1261	p05-hog {
1262	gpio-hog;	1262	gpio-hog;
1263	gpios = <0x05 0x01>;	1263	gpios = <0x05 0x01>;
1264	output-high;	1264	output-high;
1265	};	1265	};
1266		1266
1267	p01-hog {	1267	p01-hog {
1268	gpio-hog;	1268	gpio-hog;
1269	gpios = <0x00 0x00>;	1269	gpios = <0x00 0x00>;
1270	output-low;	1270	output-low;
1271	line-name = "TRC_MUX_SEL";	1271	line-name = "TRC_MUX_SEL";
1272	phandle = <0xb8>;	1272	phandle = <0xb8>;
1273	};	1273	};
1274		1274
1275	p02-hog {	1275	p02-hog {
1276	gpio-hog;	1276	gpio-hog;
1277	gpios = <0x02 0x00>;	1277	gpios = <0x02 0x00>;
1278	output-high;	1278	output-high;
1279	line-name = "MCASP1_FET_SEL";	1279	line-name = "MCASP1_FET_SEL";
1280	phandle = <0xb9>;	1280	phandle = <0xb9>;
1281	};	1281	};
1282		1282
1283	p13-hog {	1283	p13-hog {
1284	gpio-hog;	1284	gpio-hog;
1285	gpios = <0x0d 0x00>;	1285	gpios = <0x0d 0x00>;
1286	output-high;	1286	output-high;
1287	line-name = "GPIO_AUD_RSTn";	1287	line-name = "GPIO_AUD_RSTn";
1288	phandle = <0xba>;	1288	phandle = <0xba>;
1289	};	1289	};
1290	};	1290	};
1291		1291
1292	audio-codec@1b {	1292	audio-codec@1b {
1293	#sound-dai-cells = <0x00>;	1293	#sound-dai-cells = <0x00>;
1294	compatible = "ti,tlv320aic3106";	1294	compatible = "ti,tlv320aic3106";
1295	reg = <0x1b>;	1295	reg = <0x1b>;
1296	ai3x-micbias-vg = <0x01>;	1296	ai3x-micbias-vg = <0x01>;
1297	AVDD-supply = <0x1c>;	1297	AVDD-supply = <0x1c>;
1298	IOVDD-supply = <0x1c>;	1298	IOVDD-supply = <0x1c>;
1299	DRVDD-supply = <0x1c>;	1299	DRVDD-supply = <0x1c>;
1300	DVDD-supply = <0x2c>;	1300	DVDD-supply = <0x2c>;
1301	phandle = <0x70>;	1301	phandle = <0x70>;
1302	};	1302	};
1303	};	1303	};
1304		1304
1305	i2c@20010000 {	1305	i2c@20010000 {
1306	compatible = "ti,am64-i2c\0ti,omap4-i2c";	1306	compatible = "ti,am64-i2c\0ti,omap4-i2c";
1307	reg = <0x00 0x20010000 0x00 0x100>;	1307	reg = <0x00 0x20010000 0x00 0x100>;
1308	interrupts = <0x00 0xa2 0x04>;	1308	interrupts = <0x00 0xa2 0x04>;
1309	#address-cells = <0x01>;	1309	#address-cells = <0x01>;
1310	#size-cells = <0x00>;	1310	#size-cells = <0x00>;
1311	power-domains = <0x09 0x67 0x01>;	1311	power-domains = <0x09 0x67 0x01>;
1312	clocks = <0x07 0x67 0x02>;	1312	clocks = <0x07 0x67 0x02>;
1313	clock-names = "fck";	1313	clock-names = "fck";
1314	status = "okay";	1314	status = "okay";
1315	pinctrl-names = "default";	1315	pinctrl-names = "default";
1316	pinctrl-0 = <0x2d>;	1316	pinctrl-0 = <0x2d>;
1317	clock-frequency = <0x186a0>;	1317	clock-frequency = <0x186a0>;
1318	phandle = <0xbb>;	1318	phandle = <0xbb>;
1319		1319
1320	gpio@20 {	1320	gpio@20 {
1321	compatible = "ti,tca6416";	1321	compatible = "ti,tca6416";
1322	reg = <0x20>;	1322	reg = <0x20>;
1323	gpio-controller;	1323	gpio-controller;
1324	#gpio-cells = <0x02>;	1324	#gpio-cells = <0x02>;
1325	gpio-line-names = "DSI_Mux_SEL_2\0GPIO_eDP_ENABLE\0DP0_PWR_SW_EN\0GPIO_OLDI_RSTn\0GPIO_HDMI_RSTn\0HDMI_LS_OE\0\0\0DSI_GPIO0\0DSI_GPIO1\0DSI_EDID\0IO_eDP_IRQ\0OLDI_INT#\0HDMI_INTn\0\0";	1325	gpio-line-names = "DSI_Mux_SEL_2\0GPIO_eDP_ENABLE\0DP0_PWR_SW_EN\0GPIO_OLDI_RSTn\0GPIO_HDMI_RSTn\0HDMI_LS_OE\0\0\0DSI_GPIO0\0DSI_GPIO1\0DSI_EDID\0IO_eDP_IRQ\0OLDI_INT#\0HDMI_INTn\0\0";
1326	interrupt-parent = <0x1b>;	1326	interrupt-parent = <0x1b>;
1327	interrupts = <0x43 0x02>;	1327	interrupts = <0x43 0x02>;
1328	interrupt-controller;	1328	interrupt-controller;
1329	#interrupt-cells = <0x02>;	1329	#interrupt-cells = <0x02>;
1330	pinctrl-names = "default";	1330	pinctrl-names = "default";
1331	pinctrl-0 = <0x2e>;	1331	pinctrl-0 = <0x2e>;
1332	bootph-all;	1332	bootph-all;
1333	phandle = <0x2f>;	1333	phandle = <0x2f>;
1334		1334
1335	p04-hog {	1335	p04-hog {
1336	gpio-hog;	1336	gpio-hog;
1337	gpios = <0x04 0x01>;	1337	gpios = <0x04 0x01>;
1338	output-low;	1338	output-low;
1339	line-name = "GPIO_HDMI_RSTn";	1339	line-name = "GPIO_HDMI_RSTn";
1340	};	1340	};
1341		1341
1342	p03-hog {	1342	p03-hog {
1343	gpio-hog;	1343	gpio-hog;
1344	gpios = <0x03 0x01>;	1344	gpios = <0x03 0x01>;
1345	output-low;	1345	output-low;
1346	line-name = "GPIO_OLDI_RSTn";	1346	line-name = "GPIO_OLDI_RSTn";
1347	};	1347	};
1348		1348
1349	p05-hog {	1349	p05-hog {
1350	gpio-hog;	1350	gpio-hog;
1351	gpios = <0x05 0x00>;	1351	gpios = <0x05 0x00>;
1352	output-high;	1352	output-high;
1353	line-name = "HDMI_LS_OE";	1353	line-name = "HDMI_LS_OE";
1354	};	1354	};
1355	};	1355	};
1356		1356
1357	bridge-hdmi@3b {	1357	bridge-hdmi@3b {
1358	compatible = "sil,sii9022";	1358	compatible = "sil,sii9022";
1359	reg = <0x3b>;	1359	reg = <0x3b>;
1360	interrupt-parent = <0x2f>;	1360	interrupt-parent = <0x2f>;
1361	interrupts = <0x0d 0x02>;	1361	interrupts = <0x0d 0x02>;
1362	#sound-dai-cells = <0x00>;	1362	#sound-dai-cells = <0x00>;
1363	sil,i2s-data-lanes = <0x00>;	1363	sil,i2s-data-lanes = <0x00>;
1364	phandle = <0xbc>;	1364	phandle = <0xbc>;
1365		1365
1366	ports {	1366	ports {
1367	#address-cells = <0x01>;	1367	#address-cells = <0x01>;
1368	#size-cells = <0x00>;	1368	#size-cells = <0x00>;
1369	phandle = <0xbd>;	1369	phandle = <0xbd>;
1370		1370
1371	port@0 {	1371	port@0 {
1372	reg = <0x00>;	1372	reg = <0x00>;
1373		1373
1374	endpoint {	1374	endpoint {
1375	remote-endpoint = <0x30>;	1375	remote-endpoint = <0x30>;
1376	phandle = <0x4b>;	1376	phandle = <0x4b>;
1377	};	1377	};
1378	};	1378	};
1379		1379
1380	port@1 {	1380	port@1 {
1381	reg = <0x01>;	1381	reg = <0x01>;
1382		1382
1383	endpoint {	1383	endpoint {
1384	remote-endpoint = <0x31>;	1384	remote-endpoint = <0x31>;
1385	phandle = <0x74>;	1385	phandle = <0x74>;
1386	};	1386	};
1387	};	1387	};
1388	};	1388	};
1389	};	1389	};
1390		1390
1391	dsi-edp-bridge@2c {	1391	dsi-edp-bridge@2c {
1392	compatible = "ti,sn65dsi86";	1392	compatible = "ti,sn65dsi86";
1393	reg = <0x2c>;	1393	reg = <0x2c>;
1394	clock-names = "refclk";	1394	clock-names = "refclk";
1395	clocks = <0x32>;	1395	clocks = <0x32>;
1396	enable-gpios = <0x2f 0x01 0x00>;	1396	enable-gpios = <0x2f 0x01 0x00>;
1397	vpll-supply = <0x2c>;	1397	vpll-supply = <0x2c>;
1398	vccio-supply = <0x2c>;	1398	vccio-supply = <0x2c>;
1399	vcca-supply = <0x33>;	1399	vcca-supply = <0x33>;
1400	vcc-supply = <0x33>;	1400	vcc-supply = <0x33>;
1401	phandle = <0xbe>;	1401	phandle = <0xbe>;
1402		1402
1403	ports {	1403	ports {
1404	#address-cells = <0x01>;	1404	#address-cells = <0x01>;
1405	#size-cells = <0x00>;	1405	#size-cells = <0x00>;
1406	phandle = <0xbf>;	1406	phandle = <0xbf>;
1407		1407
1408	port@0 {	1408	port@0 {
1409	reg = <0x00>;	1409	reg = <0x00>;
1410		1410
1411	endpoint {	1411	endpoint {
1412	remote-endpoint = <0x34>;	1412	remote-endpoint = <0x34>;
1413	phandle = <0x4e>;	1413	phandle = <0x4e>;
1414	};	1414	};
1415	};	1415	};
1416		1416
1417	port@1 {	1417	port@1 {
1418	reg = <0x01>;	1418	reg = <0x01>;
1419		1419
1420	endpoint {	1420	endpoint {
1421	remote-endpoint = <0x35>;	1421	remote-endpoint = <0x35>;
1422	phandle = <0x76>;	1422	phandle = <0x76>;
1423	};	1423	};
1424	};	1424	};
1425	};	1425	};
1426	};	1426	};
1427	};	1427	};
1428		1428
1429	i2c@20020000 {	1429	i2c@20020000 {
1430	compatible = "ti,am64-i2c\0ti,omap4-i2c";	1430	compatible = "ti,am64-i2c\0ti,omap4-i2c";
1431	reg = <0x00 0x20020000 0x00 0x100>;	1431	reg = <0x00 0x20020000 0x00 0x100>;
1432	interrupts = <0x00 0xa3 0x04>;	1432	interrupts = <0x00 0xa3 0x04>;
1433	#address-cells = <0x01>;	1433	#address-cells = <0x01>;
1434	#size-cells = <0x00>;	1434	#size-cells = <0x00>;
1435	power-domains = <0x09 0x68 0x01>;	1435	power-domains = <0x09 0x68 0x01>;
1436	clocks = <0x07 0x68 0x02>;	1436	clocks = <0x07 0x68 0x02>;
1437	clock-names = "fck";	1437	clock-names = "fck";
1438	status = "okay";	1438	status = "okay";
1439	pinctrl-names = "default";	1439	pinctrl-names = "default";
1440	pinctrl-0 = <0x36>;	1440	pinctrl-0 = <0x36>;
1441	clock-frequency = <0x61a80>;	1441	clock-frequency = <0x61a80>;
1442	phandle = <0xc0>;	1442	phandle = <0xc0>;
1443		1443
1444	i2c-mux@70 {	1444	i2c-mux@70 {
1445	compatible = "nxp,pca9543";	1445	compatible = "nxp,pca9543";
1446	#address-cells = <0x01>;	1446	#address-cells = <0x01>;
1447	#size-cells = <0x00>;	1447	#size-cells = <0x00>;
1448	reg = <0x70>;	1448	reg = <0x70>;
1449	phandle = <0xc1>;	1449	phandle = <0xc1>;
1450	};	1450	};
1451		1451
1452	i2c-mux@71 {	1452	i2c-mux@71 {
1453	compatible = "nxp,pca9543";	1453	compatible = "nxp,pca9543";
1454	#address-cells = <0x01>;	1454	#address-cells = <0x01>;
1455	#size-cells = <0x00>;	1455	#size-cells = <0x00>;
1456	reg = <0x71>;	1456	reg = <0x71>;
1457	phandle = <0xc2>;	1457	phandle = <0xc2>;
1458	};	1458	};
1459	};	1459	};
1460		1460
1461	i2c@20030000 {	1461	i2c@20030000 {
1462	compatible = "ti,am64-i2c\0ti,omap4-i2c";	1462	compatible = "ti,am64-i2c\0ti,omap4-i2c";
1463	reg = <0x00 0x20030000 0x00 0x100>;	1463	reg = <0x00 0x20030000 0x00 0x100>;
1464	interrupts = <0x00 0xa4 0x04>;	1464	interrupts = <0x00 0xa4 0x04>;
1465	#address-cells = <0x01>;	1465	#address-cells = <0x01>;
1466	#size-cells = <0x00>;	1466	#size-cells = <0x00>;
1467	power-domains = <0x09 0x69 0x01>;	1467	power-domains = <0x09 0x69 0x01>;
1468	clocks = <0x07 0x69 0x02>;	1468	clocks = <0x07 0x69 0x02>;
1469	clock-names = "fck";	1469	clock-names = "fck";
1470	status = "disabled";	1470	status = "disabled";
1471	phandle = <0xc3>;	1471	phandle = <0xc3>;
1472	};	1472	};
1473		1473
1474	spi@20100000 {	1474	spi@20100000 {
1475	compatible = "ti,am654-mcspi\0ti,omap4-mcspi";	1475	compatible = "ti,am654-mcspi\0ti,omap4-mcspi";
1476	reg = <0x00 0x20100000 0x00 0x400>;	1476	reg = <0x00 0x20100000 0x00 0x400>;
1477	interrupts = <0x00 0xac 0x04>;	1477	interrupts = <0x00 0xac 0x04>;
1478	#address-cells = <0x01>;	1478	#address-cells = <0x01>;
1479	#size-cells = <0x00>;	1479	#size-cells = <0x00>;
1480	power-domains = <0x09 0x8d 0x01>;	1480	power-domains = <0x09 0x8d 0x01>;
1481	clocks = <0x07 0x8d 0x00>;	1481	clocks = <0x07 0x8d 0x00>;
1482	status = "disabled";	1482	status = "disabled";
1483	phandle = <0xc4>;	1483	phandle = <0xc4>;
1484	};	1484	};
1485		1485
1486	spi@20110000 {	1486	spi@20110000 {
1487	compatible = "ti,am654-mcspi\0ti,omap4-mcspi";	1487	compatible = "ti,am654-mcspi\0ti,omap4-mcspi";
1488	reg = <0x00 0x20110000 0x00 0x400>;	1488	reg = <0x00 0x20110000 0x00 0x400>;
1489	interrupts = <0x00 0xad 0x04>;	1489	interrupts = <0x00 0xad 0x04>;
1490	#address-cells = <0x01>;	1490	#address-cells = <0x01>;
1491	#size-cells = <0x00>;	1491	#size-cells = <0x00>;
1492	power-domains = <0x09 0x8e 0x01>;	1492	power-domains = <0x09 0x8e 0x01>;
1493	clocks = <0x07 0x8e 0x00>;	1493	clocks = <0x07 0x8e 0x00>;
1494	status = "disabled";	1494	status = "disabled";
1495	phandle = <0xc5>;	1495	phandle = <0xc5>;
1496	};	1496	};
1497		1497
1498	spi@20120000 {	1498	spi@20120000 {
1499	compatible = "ti,am654-mcspi\0ti,omap4-mcspi";	1499	compatible = "ti,am654-mcspi\0ti,omap4-mcspi";
1500	reg = <0x00 0x20120000 0x00 0x400>;	1500	reg = <0x00 0x20120000 0x00 0x400>;
1501	interrupts = <0x00 0xae 0x04>;	1501	interrupts = <0x00 0xae 0x04>;
1502	#address-cells = <0x01>;	1502	#address-cells = <0x01>;
1503	#size-cells = <0x00>;	1503	#size-cells = <0x00>;
1504	power-domains = <0x09 0x8f 0x01>;	1504	power-domains = <0x09 0x8f 0x01>;
1505	clocks = <0x07 0x8f 0x00>;	1505	clocks = <0x07 0x8f 0x00>;
1506	status = "disabled";	1506	status = "disabled";
1507	phandle = <0xc6>;	1507	phandle = <0xc6>;
1508	};	1508	};
1509		1509
1510	interrupt-controller@a00000 {	1510	interrupt-controller@a00000 {
1511	compatible = "ti,sci-intr";	1511	compatible = "ti,sci-intr";
1512	reg = <0x00 0xa00000 0x00 0x800>;	1512	reg = <0x00 0xa00000 0x00 0x800>;
1513	ti,intr-trigger-type = <0x01>;	1513	ti,intr-trigger-type = <0x01>;
1514	interrupt-controller;	1514	interrupt-controller;
1515	interrupt-parent = <0x01>;	1515	interrupt-parent = <0x01>;
1516	#interrupt-cells = <0x01>;	1516	#interrupt-cells = <0x01>;
1517	ti,sci = <0x0b>;	1517	ti,sci = <0x0b>;
1518	ti,sci-dev-id = <0x03>;	1518	ti,sci-dev-id = <0x03>;
1519	ti,interrupt-ranges = <0x00 0x20 0x10>;	1519	ti,interrupt-ranges = <0x00 0x20 0x10>;
1520	phandle = <0x37>;	1520	phandle = <0x37>;
1521	};	1521	};
1522		1522
1523	gpio@600000 {	1523	gpio@600000 {
1524	compatible = "ti,am64-gpio\0ti,keystone-gpio";	1524	compatible = "ti,am64-gpio\0ti,keystone-gpio";
1525	reg = <0x00 0x600000 0x00 0x100>;	1525	reg = <0x00 0x600000 0x00 0x100>;
1526	gpio-controller;	1526	gpio-controller;
1527	#gpio-cells = <0x02>;	1527	#gpio-cells = <0x02>;
1528	interrupt-parent = <0x37>;	1528	interrupt-parent = <0x37>;
1529	interrupts = <0xbe 0xbf 0xc0 0xc1 0xc2 0xc3>;	1529	interrupts = <0xbe 0xbf 0xc0 0xc1 0xc2 0xc3>;
1530	interrupt-controller;	1530	interrupt-controller;
1531	#interrupt-cells = <0x02>;	1531	#interrupt-cells = <0x02>;
1532	ti,davinci-gpio-unbanked = <0x00>;	1532	ti,davinci-gpio-unbanked = <0x00>;
1533	power-domains = <0x09 0x4d 0x01>;	1533	power-domains = <0x09 0x4d 0x01>;
1534	clocks = <0x07 0x4d 0x00>;	1534	clocks = <0x07 0x4d 0x00>;
1535	clock-names = "gpio";	1535	clock-names = "gpio";
1536	gpio-ranges = <0x38 0x00 0x00 0x20 0x38 0x20 0x21 0x26 0x38 0x46 0x48 0x11>;	1536	gpio-ranges = <0x38 0x00 0x00 0x20 0x38 0x20 0x21 0x26 0x38 0x46 0x48 0x11>;
1537	ti,ngpio = <0x57>;	1537	ti,ngpio = <0x57>;
1538	phandle = <0x1b>;	1538	phandle = <0x1b>;
1539	};	1539	};
1540		1540
1541	gpio@601000 {	1541	gpio@601000 {
1542	compatible = "ti,am64-gpio\0ti,keystone-gpio";	1542	compatible = "ti,am64-gpio\0ti,keystone-gpio";
1543	reg = <0x00 0x601000 0x00 0x100>;	1543	reg = <0x00 0x601000 0x00 0x100>;
1544	gpio-controller;	1544	gpio-controller;
1545	#gpio-cells = <0x02>;	1545	#gpio-cells = <0x02>;
1546	interrupt-parent = <0x37>;	1546	interrupt-parent = <0x37>;
1547	interrupts = <0xb4 0xb5 0xb6 0xb7 0xb8 0xb9>;	1547	interrupts = <0xb4 0xb5 0xb6 0xb7 0xb8 0xb9>;
1548	interrupt-controller;	1548	interrupt-controller;
1549	#interrupt-cells = <0x02>;	1549	#interrupt-cells = <0x02>;
1550	ti,davinci-gpio-unbanked = <0x00>;	1550	ti,davinci-gpio-unbanked = <0x00>;
1551	power-domains = <0x09 0x4e 0x01>;	1551	power-domains = <0x09 0x4e 0x01>;
1552	clocks = <0x07 0x4e 0x00>;	1552	clocks = <0x07 0x4e 0x00>;
1553	clock-names = "gpio";	1553	clock-names = "gpio";
1554	gpio-ranges = <0x38 0x07 0x65 0x19 0x38 0x2a 0x89 0x05 0x38 0x2f 0x8f 0x03 0x38 0x32 0x95 0x02>;	1554	gpio-ranges = <0x38 0x07 0x65 0x19 0x38 0x2a 0x89 0x05 0x38 0x2f 0x8f 0x03 0x38 0x32 0x95 0x02>;
1555	gpio-reserved-ranges = <0x00 0x07 0x20 0x0a>;	1555	gpio-reserved-ranges = <0x00 0x07 0x20 0x0a>;
1556	ti,ngpio = <0x49>;	1556	ti,ngpio = <0x49>;
1557	status = "okay";	1557	status = "okay";
1558	phandle = <0xc7>;	1558	phandle = <0xc7>;
1559	};	1559	};
1560		1560
1561	mmc@fa10000 {	1561	mmc@fa10000 {
1562	compatible = "ti,am64-sdhci-8bit";	1562	compatible = "ti,am64-sdhci-8bit";
1563	reg = <0x00 0xfa10000 0x00 0x1000 0x00 0xfa18000 0x00 0x400>;	1563	reg = <0x00 0xfa10000 0x00 0x1000 0x00 0xfa18000 0x00 0x400>;
1564	interrupts = <0x00 0x85 0x04>;	1564	interrupts = <0x00 0x85 0x04>;
1565	power-domains = <0x09 0x39 0x01>;	1565	power-domains = <0x09 0x39 0x01>;
1566	clocks = <0x07 0x39 0x01 0x07 0x39 0x02>;	1566	clocks = <0x07 0x39 0x01 0x07 0x39 0x02>;
1567	clock-names = "clk_ahb\0clk_xin";	1567	clock-names = "clk_ahb\0clk_xin";
1568	bus-width = <0x08>;	1568	bus-width = <0x08>;
1569	mmc-ddr-1_8v;	1569	mmc-ddr-1_8v;
1570	mmc-hs200-1_8v;	1570	mmc-hs200-1_8v;
1571	ti,clkbuf-sel = <0x07>;	1571	ti,clkbuf-sel = <0x07>;
1572	ti,trm-icp = <0x08>;	1572	ti,trm-icp = <0x08>;
1573	ti,otap-del-sel-legacy = <0x01>;	1573	ti,otap-del-sel-legacy = <0x01>;
1574	ti,otap-del-sel-mmc-hs = <0x01>;	1574	ti,otap-del-sel-mmc-hs = <0x01>;
1575	ti,otap-del-sel-ddr52 = <0x06>;	1575	ti,otap-del-sel-ddr52 = <0x06>;
1576	ti,otap-del-sel-hs200 = <0x08>;	1576	ti,otap-del-sel-hs200 = <0x08>;
1577	ti,itap-del-sel-legacy = <0x10>;	1577	ti,itap-del-sel-legacy = <0x10>;
1578	ti,itap-del-sel-mmc-hs = <0x0a>;	1578	ti,itap-del-sel-mmc-hs = <0x0a>;
1579	ti,itap-del-sel-ddr52 = <0x03>;	1579	ti,itap-del-sel-ddr52 = <0x03>;
1580	status = "okay";	1580	status = "okay";
1581	disable-wp;	1581	disable-wp;
1582	bootph-all;	1582	bootph-all;
1583	ti,driver-strength-ohm = <0x32>;	1583	ti,driver-strength-ohm = <0x32>;
1584	phandle = <0xc8>;	1584	phandle = <0xc8>;
1585	};	1585	};
1586		1586
1587	mmc@fa00000 {	1587	mmc@fa00000 {
1588	compatible = "ti,am62-sdhci";	1588	compatible = "ti,am62-sdhci";
1589	reg = <0x00 0xfa00000 0x00 0x1000 0x00 0xfa08000 0x00 0x400>;	1589	reg = <0x00 0xfa00000 0x00 0x1000 0x00 0xfa08000 0x00 0x400>;
1590	interrupts = <0x00 0x53 0x04>;	1590	interrupts = <0x00 0x53 0x04>;
1591	power-domains = <0x09 0x3a 0x01>;	1591	power-domains = <0x09 0x3a 0x01>;
1592	clocks = <0x07 0x3a 0x05 0x07 0x3a 0x06>;	1592	clocks = <0x07 0x3a 0x05 0x07 0x3a 0x06>;
1593	clock-names = "clk_ahb\0clk_xin";	1593	clock-names = "clk_ahb\0clk_xin";
1594	bus-width = <0x04>;	1594	bus-width = <0x04>;
1595	ti,clkbuf-sel = <0x07>;	1595	ti,clkbuf-sel = <0x07>;
1596	ti,otap-del-sel-legacy = <0x00>;	1596	ti,otap-del-sel-legacy = <0x00>;
1597	ti,otap-del-sel-sd-hs = <0x00>;	1597	ti,otap-del-sel-sd-hs = <0x00>;
1598	ti,otap-del-sel-sdr12 = <0x0f>;	1598	ti,otap-del-sel-sdr12 = <0x0f>;
1599	ti,otap-del-sel-sdr25 = <0x0f>;	1599	ti,otap-del-sel-sdr25 = <0x0f>;
1600	ti,otap-del-sel-sdr50 = <0x0c>;	1600	ti,otap-del-sel-sdr50 = <0x0c>;
1601	ti,otap-del-sel-ddr50 = <0x09>;	1601	ti,otap-del-sel-ddr50 = <0x09>;
1602	ti,otap-del-sel-sdr104 = <0x06>;	1602	ti,otap-del-sel-sdr104 = <0x06>;
1603	ti,itap-del-sel-legacy = <0x00>;	1603	ti,itap-del-sel-legacy = <0x00>;
1604	ti,itap-del-sel-sd-hs = <0x00>;	1604	ti,itap-del-sel-sd-hs = <0x00>;
1605	ti,itap-del-sel-sdr12 = <0x00>;	1605	ti,itap-del-sel-sdr12 = <0x00>;
1606	ti,itap-del-sel-sdr25 = <0x00>;	1606	ti,itap-del-sel-sdr25 = <0x00>;
1607	status = "okay";	1607	status = "okay";
1608	vmmc-supply = <0x39>;	1608	vmmc-supply = <0x39>;
1609	vqmmc-supply = <0x3a>;	1609	vqmmc-supply = <0x3a>;
1610	pinctrl-names = "default";	1610	pinctrl-names = "default";
1611	pinctrl-0 = <0x3b>;	1611	pinctrl-0 = <0x3b>;
1612	ti,driver-strength-ohm = <0x32>;	1612	ti,driver-strength-ohm = <0x32>;
1613	disable-wp;	1613	disable-wp;
1614	bootph-all;	1614	bootph-all;
1615	phandle = <0xc9>;	1615	phandle = <0xc9>;
1616	};	1616	};
1617		1617
1618	mmc@fa20000 {	1618	mmc@fa20000 {
1619	compatible = "ti,am62-sdhci";	1619	compatible = "ti,am62-sdhci";
1620	reg = <0x00 0xfa20000 0x00 0x1000 0x00 0xfa28000 0x00 0x400>;	1620	reg = <0x00 0xfa20000 0x00 0x1000 0x00 0xfa28000 0x00 0x400>;
1621	interrupts = <0x00 0x52 0x04>;	1621	interrupts = <0x00 0x52 0x04>;
1622	power-domains = <0x09 0xb8 0x01>;	1622	power-domains = <0x09 0xb8 0x01>;
1623	clocks = <0x07 0xb8 0x05 0x07 0xb8 0x06>;	1623	clocks = <0x07 0xb8 0x05 0x07 0xb8 0x06>;
1624	clock-names = "clk_ahb\0clk_xin";	1624	clock-names = "clk_ahb\0clk_xin";
1625	bus-width = <0x04>;	1625	bus-width = <0x04>;
1626	ti,clkbuf-sel = <0x07>;	1626	ti,clkbuf-sel = <0x07>;
1627	ti,otap-del-sel-legacy = <0x00>;	1627	ti,otap-del-sel-legacy = <0x00>;
1628	ti,otap-del-sel-sd-hs = <0x00>;	1628	ti,otap-del-sel-sd-hs = <0x00>;
1629	ti,otap-del-sel-sdr12 = <0x0f>;	1629	ti,otap-del-sel-sdr12 = <0x0f>;
1630	ti,otap-del-sel-sdr25 = <0x0f>;	1630	ti,otap-del-sel-sdr25 = <0x0f>;
1631	ti,otap-del-sel-sdr50 = <0x0c>;	1631	ti,otap-del-sel-sdr50 = <0x0c>;
1632	ti,otap-del-sel-ddr50 = <0x09>;	1632	ti,otap-del-sel-ddr50 = <0x09>;
1633	ti,otap-del-sel-sdr104 = <0x06>;	1633	ti,otap-del-sel-sdr104 = <0x06>;
1634	ti,itap-del-sel-legacy = <0x00>;	1634	ti,itap-del-sel-legacy = <0x00>;
1635	ti,itap-del-sel-sd-hs = <0x00>;	1635	ti,itap-del-sel-sd-hs = <0x00>;
1636	ti,itap-del-sel-sdr12 = <0x00>;	1636	ti,itap-del-sel-sdr12 = <0x00>;
1637	ti,itap-del-sel-sdr25 = <0x00>;	1637	ti,itap-del-sel-sdr25 = <0x00>;
1638	status = "disabled";	1638	status = "disabled";
1639	phandle = <0xca>;	1639	phandle = <0xca>;
1640	};	1640	};
1641		1641
1642	usb@f900000 {	1642	usb@f900000 {
1643	compatible = "ti,am62-usb";	1643	compatible = "ti,am62-usb";
1644	reg = <0x00 0xf900000 0x00 0x800 0x00 0xf908000 0x00 0x400>;	1644	reg = <0x00 0xf900000 0x00 0x800 0x00 0xf908000 0x00 0x400>;
1645	clocks = <0x07 0xa1 0x03>;	1645	clocks = <0x07 0xa1 0x03>;
1646	clock-names = "ref";	1646	clock-names = "ref";
1647	ti,syscon-phy-pll-refclk = <0x3c 0x00>;	1647	ti,syscon-phy-pll-refclk = <0x3c 0x00>;
1648	#address-cells = <0x02>;	1648	#address-cells = <0x02>;
1649	#size-cells = <0x02>;	1649	#size-cells = <0x02>;
1650	power-domains = <0x09 0xb2 0x01>;	1650	power-domains = <0x09 0xb2 0x01>;
1651	ranges;	1651	ranges;
1652	status = "okay";	1652	status = "okay";
1653	ti,vbus-divider;	1653	ti,vbus-divider;
1654	phandle = <0xcb>;	1654	phandle = <0xcb>;
1655		1655
1656	usb@31000000 {	1656	usb@31000000 {
1657	compatible = "snps,dwc3";	1657	compatible = "snps,dwc3";
1658	reg = <0x00 0x31000000 0x00 0x50000>;	1658	reg = <0x00 0x31000000 0x00 0x50000>;
1659	interrupts = <0x00 0xbc 0x04 0x00 0xbc 0x04>;	1659	interrupts = <0x00 0xbc 0x04 0x00 0xbc 0x04>;
1660	interrupt-names = "host\0peripheral";	1660	interrupt-names = "host\0peripheral";
1661	maximum-speed = "high-speed";	1661	maximum-speed = "high-speed";
1662	dr_mode = "otg";	1662	dr_mode = "otg";
1663	bootph-all;	1663	bootph-all;
1664	snps,usb2-gadget-lpm-disable;	1664	snps,usb2-gadget-lpm-disable;
1665	snps,usb2-lpm-disable;	1665	snps,usb2-lpm-disable;
1666	usb-role-switch;	1666	usb-role-switch;
1667	phandle = <0xcc>;	1667	phandle = <0xcc>;
1668	};	1668	};
1669	};	1669	};
1670		1670
1671	bus@fc00000 {	1671	bus@fc00000 {
1672	compatible = "simple-bus";	1672	compatible = "simple-bus";
1673	reg = <0x00 0xfc00000 0x00 0x70000>;	1673	reg = <0x00 0xfc00000 0x00 0x70000>;
1674	#address-cells = <0x02>;	1674	#address-cells = <0x02>;
1675	#size-cells = <0x02>;	1675	#size-cells = <0x02>;
1676	ranges;	1676	ranges;
1677	phandle = <0xcd>;	1677	phandle = <0xcd>;
1678		1678
1679	spi@fc40000 {	1679	spi@fc40000 {
1680	compatible = "ti,am654-ospi\0cdns,qspi-nor";	1680	compatible = "ti,am654-ospi\0cdns,qspi-nor";
1681	reg = <0x00 0xfc40000 0x00 0x100 0x05 0x00 0x01 0x00>;	1681	reg = <0x00 0xfc40000 0x00 0x100 0x05 0x00 0x01 0x00>;
1682	interrupts = <0x00 0x8b 0x04>;	1682	interrupts = <0x00 0x8b 0x04>;
1683	cdns,fifo-depth = <0x100>;	1683	cdns,fifo-depth = <0x100>;
1684	cdns,fifo-width = <0x04>;	1684	cdns,fifo-width = <0x04>;
1685	cdns,trigger-address = <0x00>;	1685	cdns,trigger-address = <0x00>;
1686	cdns,phase-detect-selector = <0x00>;	1686	cdns,phase-detect-selector = <0x00>;
1687	clocks = <0x07 0x4b 0x07>;	1687	clocks = <0x07 0x4b 0x07>;
1688	assigned-clocks = <0x07 0x4b 0x07>;	1688	assigned-clocks = <0x07 0x4b 0x07>;
1689	assigned-clock-parents = <0x07 0x4b 0x08>;	1689	assigned-clock-parents = <0x07 0x4b 0x08>;
1690	assigned-clock-rates = <0x9ef21aa>;	1690	assigned-clock-rates = <0x9ef21aa>;
1691	power-domains = <0x09 0x4b 0x01>;	1691	power-domains = <0x09 0x4b 0x01>;
1692	#address-cells = <0x01>;	1692	#address-cells = <0x01>;
1693	#size-cells = <0x00>;	1693	#size-cells = <0x00>;
1694	status = "okay";	1694	status = "okay";
1695	pinctrl-names = "default";	1695	pinctrl-names = "default";
1696	pinctrl-0 = <0x3d>;	1696	pinctrl-0 = <0x3d>;
1697	phandle = <0xce>;	1697	phandle = <0xce>;
1698		1698
1699	flash@0 {	1699	flash@0 {
1700	compatible = "jedec,spi-nor";	1700	compatible = "jedec,spi-nor";
1701	reg = <0x00>;	1701	reg = <0x00>;
1702	spi-tx-bus-width = <0x08>;	1702	spi-tx-bus-width = <0x08>;
1703	spi-rx-bus-width = <0x08>;	1703	spi-rx-bus-width = <0x08>;
1704	spi-max-frequency = <0x17d7840>;	1704	spi-max-frequency = <0x17d7840>;
1705	cdns,tshsl-ns = <0x3c>;	1705	cdns,tshsl-ns = <0x3c>;
1706	cdns,tsd2d-ns = <0x3c>;	1706	cdns,tsd2d-ns = <0x3c>;
1707	cdns,tchsh-ns = <0x3c>;	1707	cdns,tchsh-ns = <0x3c>;
1708	cdns,tslch-ns = <0x3c>;	1708	cdns,tslch-ns = <0x3c>;
1709	cdns,read-delay = <0x04>;	1709	cdns,read-delay = <0x04>;
1710	cdns,phy-mode;	1710	cdns,phy-mode;
1711	bootph-all;	1711	bootph-all;
1712		1712
1713	partitions {	1713	partitions {
1714	compatible = "fixed-partitions";	1714	compatible = "fixed-partitions";
1715	#address-cells = <0x01>;	1715	#address-cells = <0x01>;
1716	#size-cells = <0x01>;	1716	#size-cells = <0x01>;
1717		1717
1718	partition@0 {	1718	partition@0 {
1719	label = "ospi.tiboot3";	1719	label = "ospi.tiboot3";
1720	reg = <0x00 0x80000>;	1720	reg = <0x00 0x80000>;
1721	};	1721	};
1722		1722
1723	partition@80000 {	1723	partition@80000 {
1724	label = "ospi.tispl";	1724	label = "ospi.tispl";
1725	reg = <0x80000 0x200000>;	1725	reg = <0x80000 0x200000>;
1726	};	1726	};
1727		1727
1728	partition@280000 {	1728	partition@280000 {
1729	label = "ospi.u-boot";	1729	label = "ospi.u-boot";
1730	reg = <0x280000 0x400000>;	1730	reg = <0x280000 0x400000>;
1731	};	1731	};
1732		1732
1733	partition@680000 {	1733	partition@680000 {
1734	label = "ospi.env";	1734	label = "ospi.env";
1735	reg = <0x680000 0x40000>;	1735	reg = <0x680000 0x40000>;
1736	};	1736	};
1737		1737
1738	partition@6c0000 {	1738	partition@6c0000 {
1739	label = "ospi.env.backup";	1739	label = "ospi.env.backup";
1740	reg = <0x6c0000 0x40000>;	1740	reg = <0x6c0000 0x40000>;
1741	};	1741	};
1742		1742
1743	partition@800000 {	1743	partition@800000 {
1744	label = "ospi.rootfs";	1744	label = "ospi.rootfs";
1745	reg = <0x800000 0x37c0000>;	1745	reg = <0x800000 0x37c0000>;
1746	};	1746	};
1747		1747
1748	partition@3fc0000 {	1748	partition@3fc0000 {
1749	bootph-all;	1749	bootph-all;
1750	label = "ospi.phypattern";	1750	label = "ospi.phypattern";
1751	reg = <0x3fc0000 0x40000>;	1751	reg = <0x3fc0000 0x40000>;
1752	};	1752	};
1753	};	1753	};
1754	};	1754	};
1755		1755
1756	nand@0 {	1756	nand@0 {
1757	compatible = "spi-nand";	1757	compatible = "spi-nand";
1758	reg = <0x00>;	1758	reg = <0x00>;
1759	spi-tx-bus-width = <0x08>;	1759	spi-tx-bus-width = <0x08>;
1760	spi-rx-bus-width = <0x08>;	1760	spi-rx-bus-width = <0x08>;
1761	spi-max-frequency = <0x17d7840>;	1761	spi-max-frequency = <0x17d7840>;
1762	cdns,tshsl-ns = <0x3c>;	1762	cdns,tshsl-ns = <0x3c>;
1763	cdns,tsd2d-ns = <0x3c>;	1763	cdns,tsd2d-ns = <0x3c>;
1764	cdns,tchsh-ns = <0x3c>;	1764	cdns,tchsh-ns = <0x3c>;
1765	cdns,tslch-ns = <0x3c>;	1765	cdns,tslch-ns = <0x3c>;
1766	cdns,read-delay = <0x02>;	1766	cdns,read-delay = <0x02>;
1767	#address-cells = <0x01>;	1767	#address-cells = <0x01>;
1768	#size-cells = <0x01>;	1768	#size-cells = <0x01>;
1769	bootph-all;	1769	bootph-all;
1770	cdns,phy-mode;	1770	cdns,phy-mode;
1771	phandle = <0xcf>;	1771	phandle = <0xcf>;
1772		1772
1773	partitions {	1773	partitions {
1774	compatible = "fixed-partitions";	1774	compatible = "fixed-partitions";
1775	#address-cells = <0x01>;	1775	#address-cells = <0x01>;
1776	#size-cells = <0x01>;	1776	#size-cells = <0x01>;
1777		1777
1778	partition@0 {	1778	partition@0 {
1779	label = "ospi_nand.tiboot3";	1779	label = "ospi_nand.tiboot3";
1780	reg = <0x00 0x80000>;	1780	reg = <0x00 0x80000>;
1781	};	1781	};
1782		1782
1783	partition@80000 {	1783	partition@80000 {
1784	label = "ospi_nand.tispl";	1784	label = "ospi_nand.tispl";
1785	reg = <0x80000 0x200000>;	1785	reg = <0x80000 0x200000>;
1786	};	1786	};
1787		1787
1788	partition@280000 {	1788	partition@280000 {
1789	label = "ospi_nand.u-boot";	1789	label = "ospi_nand.u-boot";
1790	reg = <0x280000 0x400000>;	1790	reg = <0x280000 0x400000>;
1791	};	1791	};
1792		1792
1793	partition@680000 {	1793	partition@680000 {
1794	label = "ospi_nand.env";	1794	label = "ospi_nand.env";
1795	reg = <0x680000 0x40000>;	1795	reg = <0x680000 0x40000>;
1796	};	1796	};
1797		1797
1798	partition@6c0000 {	1798	partition@6c0000 {
1799	label = "ospi_nand.env.backup";	1799	label = "ospi_nand.env.backup";
1800	reg = <0x6c0000 0x40000>;	1800	reg = <0x6c0000 0x40000>;
1801	};	1801	};
1802		1802
1803	partition@2000000 {	1803	partition@2000000 {
1804	label = "ospi_nand.rootfs";	1804	label = "ospi_nand.rootfs";
1805	reg = <0x2000000 0x5fc0000>;	1805	reg = <0x2000000 0x5fc0000>;
1806	};	1806	};
1807		1807
1808	partition@7fc0000 {	1808	partition@7fc0000 {
1809	bootph-all;	1809	bootph-all;
1810	label = "ospi_nand.phypattern";	1810	label = "ospi_nand.phypattern";
1811	reg = <0x7fc0000 0x40000>;	1811	reg = <0x7fc0000 0x40000>;
1812	};	1812	};
1813	};	1813	};
1814	};	1814	};
1815	};	1815	};
1816	};	1816	};
1817		1817
1818	ethernet@8000000 {	1818	ethernet@8000000 {
1819	compatible = "ti,am642-cpsw-nuss";	1819	compatible = "ti,am642-cpsw-nuss";
1820	#address-cells = <0x02>;	1820	#address-cells = <0x02>;
1821	#size-cells = <0x02>;	1821	#size-cells = <0x02>;
1822	reg = <0x00 0x8000000 0x00 0x200000>;	1822	reg = <0x00 0x8000000 0x00 0x200000>;
1823	reg-names = "cpsw_nuss";	1823	reg-names = "cpsw_nuss";
1824	ranges = <0x00 0x00 0x00 0x8000000 0x00 0x200000>;	1824	ranges = <0x00 0x00 0x00 0x8000000 0x00 0x200000>;
1825	clocks = <0x07 0x0d 0x00>;	1825	clocks = <0x07 0x0d 0x00>;
1826	assigned-clocks = <0x07 0x0d 0x03>;	1826	assigned-clocks = <0x07 0x0d 0x03>;
1827	assigned-clock-parents = <0x07 0x0d 0x0b>;	1827	assigned-clock-parents = <0x07 0x0d 0x0b>;
1828	clock-names = "fck";	1828	clock-names = "fck";
1829	power-domains = <0x09 0x0d 0x01>;	1829	power-domains = <0x09 0x0d 0x01>;
1830	status = "okay";	1830	status = "okay";
1831	dmas = <0x22 0xc600 0x0f 0x22 0xc601 0x0f 0x22 0xc602 0x0f 0x22 0xc603 0x0f 0x22 0xc604 0x0f 0x22 0xc605 0x0f 0x22 0xc606 0x0f 0x22 0xc607 0x0f 0x22 0x4600 0x0f>;	1831	dmas = <0x22 0xc600 0x0f 0x22 0xc601 0x0f 0x22 0xc602 0x0f 0x22 0xc603 0x0f 0x22 0xc604 0x0f 0x22 0xc605 0x0f 0x22 0xc606 0x0f 0x22 0xc607 0x0f 0x22 0x4600 0x0f>;
1832	dma-names = "tx0\0tx1\0tx2\0tx3\0tx4\0tx5\0tx6\0tx7\0rx";	1832	dma-names = "tx0\0tx1\0tx2\0tx3\0tx4\0tx5\0tx6\0tx7\0rx";
1833	pinctrl-names = "default";	1833	pinctrl-names = "default";
1834	pinctrl-0 = <0x3e>;	1834	pinctrl-0 = <0x3e>;
1835	phandle = <0xd0>;	1835	phandle = <0xd0>;
1836		1836
1837	ethernet-ports {	1837	ethernet-ports {
1838	#address-cells = <0x01>;	1838	#address-cells = <0x01>;
1839	#size-cells = <0x00>;	1839	#size-cells = <0x00>;
1840		1840
1841	port@1 {	1841	port@1 {
1842	reg = <0x01>;	1842	reg = <0x01>;
1843	ti,mac-only;	1843	ti,mac-only;
1844	label = "port1";	1844	label = "port1";
1845	phys = <0x3f 0x01>;	1845	phys = <0x3f 0x01>;
1846	mac-address = [00 00 00 00 00 00];	1846	mac-address = [00 00 00 00 00 00];
1847	ti,syscon-efuse = <0x40 0x00>;	1847	ti,syscon-efuse = <0x40 0x00>;
1848	status = "okay";	1848	status = "okay";
1849	bootph-all;	1849	bootph-all;
1850	phy-mode = "rgmii-rxid";	1850	phy-mode = "rgmii-rxid";
1851	phy-handle = <0x41>;	1851	phy-handle = <0x41>;
1852	phandle = <0xd1>;	1852	phandle = <0xd1>;
1853	};	1853	};
1854		1854
1855	port@2 {	1855	port@2 {
1856	reg = <0x02>;	1856	reg = <0x02>;
1857	ti,mac-only;	1857	ti,mac-only;
1858	label = "port2";	1858	label = "port2";
1859	phys = <0x3f 0x02>;	1859	phys = <0x3f 0x02>;
1860	mac-address = [00 00 00 00 00 00];	1860	mac-address = [00 00 00 00 00 00];
1861	status = "disabled";	1861	status = "disabled";
1862	phandle = <0xd2>;	1862	phandle = <0xd2>;
1863	};	1863	};
1864	};	1864	};
1865		1865
1866	mdio@f00 {	1866	mdio@f00 {
1867	compatible = "ti,cpsw-mdio\0ti,davinci_mdio";	1867	compatible = "ti,cpsw-mdio\0ti,davinci_mdio";
1868	reg = <0x00 0xf00 0x00 0x100>;	1868	reg = <0x00 0xf00 0x00 0x100>;
1869	#address-cells = <0x01>;	1869	#address-cells = <0x01>;
1870	#size-cells = <0x00>;	1870	#size-cells = <0x00>;
1871	clocks = <0x07 0x0d 0x00>;	1871	clocks = <0x07 0x0d 0x00>;
1872	clock-names = "fck";	1872	clock-names = "fck";
1873	bus_freq = <0xf4240>;	1873	bus_freq = <0xf4240>;
1874	status = "okay";	1874	status = "okay";
1875	bootph-all;	1875	bootph-all;
1876	pinctrl-names = "default";	1876	pinctrl-names = "default";
1877	pinctrl-0 = <0x42>;	1877	pinctrl-0 = <0x42>;
1878	phandle = <0xd3>;	1878	phandle = <0xd3>;
1879		1879
1880	ethernet-phy@0 {	1880	ethernet-phy@0 {
1881	reg = <0x00>;	1881	reg = <0x00>;
1882	bootph-all;	1882	bootph-all;
1883	ti,rx-internal-delay = <0x07>;	1883	ti,rx-internal-delay = <0x07>;
1884	ti,fifo-depth = <0x01>;	1884	ti,fifo-depth = <0x01>;
1885	ti,min-output-impedance;	1885	ti,min-output-impedance;
1886	phandle = <0x41>;	1886	phandle = <0x41>;
1887	};	1887	};
1888	};	1888	};
1889		1889
1890	cpts@3d000 {	1890	cpts@3d000 {
1891	compatible = "ti,j721e-cpts";	1891	compatible = "ti,j721e-cpts";
1892	reg = <0x00 0x3d000 0x00 0x400>;	1892	reg = <0x00 0x3d000 0x00 0x400>;
1893	clocks = <0x07 0x0d 0x03>;	1893	clocks = <0x07 0x0d 0x03>;
1894	clock-names = "cpts";	1894	clock-names = "cpts";
1895	interrupts-extended = <0x01 0x00 0x66 0x04>;	1895	interrupts-extended = <0x01 0x00 0x66 0x04>;
1896	interrupt-names = "cpts";	1896	interrupt-names = "cpts";
1897	ti,cpts-ext-ts-inputs = <0x04>;	1897	ti,cpts-ext-ts-inputs = <0x04>;
1898	ti,cpts-periodic-outputs = <0x02>;	1898	ti,cpts-periodic-outputs = <0x02>;
1899	ti,pps = <0x02 0x01>;	1899	ti,pps = <0x02 0x01>;
1900	};	1900	};
1901	};	1901	};
1902		1902
1903	gpu@fd80000 {	1903	gpu@fd80000 {
1904	compatible = "ti,am62p-pvr\0img,pvr-bxs64";	1904	compatible = "ti,am62p-pvr\0img,pvr-bxs64";
1905	reg = <0x00 0xfd80000 0x00 0x80000>;	1905	reg = <0x00 0xfd80000 0x00 0x80000>;
1906	interrupts = <0x00 0xf1 0x04>;	1906	interrupts = <0x00 0xf1 0x04>;
1907	power-domains = <0x09 0xed 0x01 0x09 0xf2 0x01>;	1907	power-domains = <0x09 0xed 0x01 0x09 0xf2 0x01>;
1908	assigned-clocks = <0x07 0xed 0x03>;	1908	assigned-clocks = <0x07 0xed 0x03>;
1909	assigned-clock-rates = <0x2faf0800>;	1909	assigned-clock-rates = <0x2faf0800>;
1910	power-domain-names = "firmware\0dust";	1910	power-domain-names = "firmware\0dust";
1911	clocks = <0x07 0xed 0x03>;	1911	clocks = <0x07 0xed 0x03>;
1912	clock-names = "core";	1912	clock-names = "core";
1913	phandle = <0xd4>;	1913	phandle = <0xd4>;
1914	};	1914	};
1915		1915
1916	spinlock@2a000000 {	1916	spinlock@2a000000 {
1917	compatible = "ti,am64-hwspinlock";	1917	compatible = "ti,am64-hwspinlock";
1918	reg = <0x00 0x2a000000 0x00 0x1000>;	1918	reg = <0x00 0x2a000000 0x00 0x1000>;
1919	#hwlock-cells = <0x01>;	1919	#hwlock-cells = <0x01>;
1920	phandle = <0xd5>;	1920	phandle = <0xd5>;
1921	};	1921	};
1922		1922
1923	mux-controller@a40000 {	1923	mux-controller@a40000 {
1924	compatible = "reg-mux";	1924	compatible = "reg-mux";
1925	reg = <0x00 0xa40000 0x00 0x800>;	1925	reg = <0x00 0xa40000 0x00 0x800>;
1926	#mux-control-cells = <0x01>;	1926	#mux-control-cells = <0x01>;
1927	status = "okay";	1927	status = "okay";
1928	mux-reg-masks-state = <0x34 0x1ffff 0x10011>;	1928	mux-reg-masks-state = <0x34 0x1ffff 0x10011>;
1929	phandle = <0xd6>;	1929	phandle = <0xd6>;
1930	};	1930	};
1931		1931
1932	mailbox@29000000 {	1932	mailbox@29000000 {
1933	compatible = "ti,am64-mailbox";	1933	compatible = "ti,am64-mailbox";
1934	reg = <0x00 0x29000000 0x00 0x200>;	1934	reg = <0x00 0x29000000 0x00 0x200>;
1935	interrupts = <0x00 0x4c 0x04>;	1935	interrupts = <0x00 0x4c 0x04>;
1936	#mbox-cells = <0x01>;	1936	#mbox-cells = <0x01>;
1937	ti,mbox-num-users = <0x04>;	1937	ti,mbox-num-users = <0x04>;
1938	ti,mbox-num-fifos = <0x10>;	1938	ti,mbox-num-fifos = <0x10>;
1939	status = "okay";	1939	status = "okay";
1940	phandle = <0x1d>;	1940	phandle = <0x1d>;
1941		1941
1942	mbox-wkup-r5-0 {	1942	mbox-wkup-r5-0 {
1943	ti,mbox-rx = <0x00 0x00 0x00>;	1943	ti,mbox-rx = <0x00 0x00 0x00>;
1944	ti,mbox-tx = <0x01 0x00 0x00>;	1944	ti,mbox-tx = <0x01 0x00 0x00>;
1945	phandle = <0x1e>;	1945	phandle = <0x1e>;
1946	};	1946	};
1947	};	1947	};
1948		1948
1949	mailbox@29010000 {	1949	mailbox@29010000 {
1950	compatible = "ti,am64-mailbox";	1950	compatible = "ti,am64-mailbox";
1951	reg = <0x00 0x29010000 0x00 0x200>;	1951	reg = <0x00 0x29010000 0x00 0x200>;
1952	interrupts = <0x00 0x4d 0x04>;	1952	interrupts = <0x00 0x4d 0x04>;
1953	#mbox-cells = <0x01>;	1953	#mbox-cells = <0x01>;
1954	ti,mbox-num-users = <0x04>;	1954	ti,mbox-num-users = <0x04>;
1955	ti,mbox-num-fifos = <0x10>;	1955	ti,mbox-num-fifos = <0x10>;
1956	status = "okay";	1956	status = "okay";
1957	phandle = <0x14>;	1957	phandle = <0x14>;
1958		1958
1959	mbox-mcu-r5-0 {	1959	mbox-mcu-r5-0 {
1960	ti,mbox-rx = <0x00 0x00 0x00>;	1960	ti,mbox-rx = <0x00 0x00 0x00>;
1961	ti,mbox-tx = <0x01 0x00 0x00>;	1961	ti,mbox-tx = <0x01 0x00 0x00>;
1962	phandle = <0x15>;	1962	phandle = <0x15>;
1963	};	1963	};
1964	};	1964	};
1965		1965
1966	mailbox@29020000 {	1966	mailbox@29020000 {
1967	compatible = "ti,am64-mailbox";	1967	compatible = "ti,am64-mailbox";
1968	reg = <0x00 0x29020000 0x00 0x200>;	1968	reg = <0x00 0x29020000 0x00 0x200>;
1969	interrupts = <0x00 0x6c 0x04>;	1969	interrupts = <0x00 0x6c 0x04>;
1970	#mbox-cells = <0x01>;	1970	#mbox-cells = <0x01>;
1971	ti,mbox-num-users = <0x04>;	1971	ti,mbox-num-users = <0x04>;
1972	ti,mbox-num-fifos = <0x10>;	1972	ti,mbox-num-fifos = <0x10>;
1973	status = "okay";	1973	status = "okay";
1974	phandle = <0x63>;	1974	phandle = <0x63>;
1975		1975
1976	mbox-c7x-0 {	1976	mbox-c7x-0 {
1977	ti,mbox-rx = <0x00 0x00 0x00>;	1977	ti,mbox-rx = <0x00 0x00 0x00>;
1978	ti,mbox-tx = <0x01 0x00 0x00>;	1978	ti,mbox-tx = <0x01 0x00 0x00>;
1979	phandle = <0x64>;	1979	phandle = <0x64>;
1980	};	1980	};
1981	};	1981	};
1982		1982
1983	mailbox@29030000 {	1983	mailbox@29030000 {
1984	compatible = "ti,am64-mailbox";	1984	compatible = "ti,am64-mailbox";
1985	reg = <0x00 0x29030000 0x00 0x200>;	1985	reg = <0x00 0x29030000 0x00 0x200>;
1986	interrupts = <0x00 0x6d 0x04>;	1986	interrupts = <0x00 0x6d 0x04>;
1987	#mbox-cells = <0x01>;	1987	#mbox-cells = <0x01>;
1988	ti,mbox-num-users = <0x04>;	1988	ti,mbox-num-users = <0x04>;
1989	ti,mbox-num-fifos = <0x10>;	1989	ti,mbox-num-fifos = <0x10>;
1990	status = "okay";	1990	status = "okay";
1991	phandle = <0x5f>;	1991	phandle = <0x5f>;
1992		1992
1993	mbox-main-r5-0 {	1993	mbox-main-r5-0 {
1994	ti,mbox-rx = <0x00 0x00 0x00>;	1994	ti,mbox-rx = <0x00 0x00 0x00>;
1995	ti,mbox-tx = <0x01 0x00 0x00>;	1995	ti,mbox-tx = <0x01 0x00 0x00>;
1996	phandle = <0x60>;	1996	phandle = <0x60>;
1997	};	1997	};
1998		1998
1999	mbox-c7x-1 {	1999	mbox-c7x-1 {
2000	ti,mbox-rx = <0x02 0x00 0x00>;	2000	ti,mbox-rx = <0x02 0x00 0x00>;
2001	ti,mbox-tx = <0x03 0x00 0x00>;	2001	ti,mbox-tx = <0x03 0x00 0x00>;
2002	phandle = <0x67>;	2002	phandle = <0x67>;
2003	};	2003	};
2004	};	2004	};
2005		2005
2006	pwm@23100000 {	2006	pwm@23100000 {
2007	compatible = "ti,am3352-ecap";	2007	compatible = "ti,am3352-ecap";
2008	#pwm-cells = <0x03>;	2008	#pwm-cells = <0x03>;
2009	reg = <0x00 0x23100000 0x00 0x100>;	2009	reg = <0x00 0x23100000 0x00 0x100>;
2010	power-domains = <0x09 0x33 0x01>;	2010	power-domains = <0x09 0x33 0x01>;
2011	clocks = <0x07 0x33 0x00>;	2011	clocks = <0x07 0x33 0x00>;
2012	clock-names = "fck";	2012	clock-names = "fck";
2013	status = "disabled";	2013	status = "disabled";
2014	phandle = <0xd7>;	2014	phandle = <0xd7>;
2015	};	2015	};
2016		2016
2017	pwm@23110000 {	2017	pwm@23110000 {
2018	compatible = "ti,am3352-ecap";	2018	compatible = "ti,am3352-ecap";
2019	#pwm-cells = <0x03>;	2019	#pwm-cells = <0x03>;
2020	reg = <0x00 0x23110000 0x00 0x100>;	2020	reg = <0x00 0x23110000 0x00 0x100>;
2021	power-domains = <0x09 0x34 0x01>;	2021	power-domains = <0x09 0x34 0x01>;
2022	clocks = <0x07 0x34 0x00>;	2022	clocks = <0x07 0x34 0x00>;
2023	clock-names = "fck";	2023	clock-names = "fck";
2024	status = "disabled";	2024	status = "disabled";
2025	phandle = <0xd8>;	2025	phandle = <0xd8>;
2026	};	2026	};
2027		2027
2028	pwm@23120000 {	2028	pwm@23120000 {
2029	compatible = "ti,am3352-ecap";	2029	compatible = "ti,am3352-ecap";
2030	#pwm-cells = <0x03>;	2030	#pwm-cells = <0x03>;
2031	reg = <0x00 0x23120000 0x00 0x100>;	2031	reg = <0x00 0x23120000 0x00 0x100>;
2032	power-domains = <0x09 0x35 0x01>;	2032	power-domains = <0x09 0x35 0x01>;
2033	clocks = <0x07 0x35 0x00>;	2033	clocks = <0x07 0x35 0x00>;
2034	clock-names = "fck";	2034	clock-names = "fck";
2035	status = "disabled";	2035	status = "disabled";
2036	phandle = <0xd9>;	2036	phandle = <0xd9>;
2037	};	2037	};
2038		2038
2039	counter@23200000 {	2039	counter@23200000 {
2040	compatible = "ti,am62-eqep";	2040	compatible = "ti,am62-eqep";
2041	reg = <0x00 0x23200000 0x00 0x100>;	2041	reg = <0x00 0x23200000 0x00 0x100>;
2042	power-domains = <0x09 0x3b 0x01>;	2042	power-domains = <0x09 0x3b 0x01>;
2043	clocks = <0x07 0x3b 0x00>;	2043	clocks = <0x07 0x3b 0x00>;
2044	interrupts = <0x00 0x74 0x01>;	2044	interrupts = <0x00 0x74 0x01>;
2045	status = "disabled";	2045	status = "disabled";
2046	phandle = <0xda>;	2046	phandle = <0xda>;
2047	};	2047	};
2048		2048
2049	counter@23210000 {	2049	counter@23210000 {
2050	compatible = "ti,am62-eqep";	2050	compatible = "ti,am62-eqep";
2051	reg = <0x00 0x23210000 0x00 0x100>;	2051	reg = <0x00 0x23210000 0x00 0x100>;
2052	power-domains = <0x09 0x3c 0x01>;	2052	power-domains = <0x09 0x3c 0x01>;
2053	clocks = <0x07 0x3c 0x00>;	2053	clocks = <0x07 0x3c 0x00>;
2054	interrupts = <0x00 0x75 0x01>;	2054	interrupts = <0x00 0x75 0x01>;
2055	status = "disabled";	2055	status = "disabled";
2056	phandle = <0xdb>;	2056	phandle = <0xdb>;
2057	};	2057	};
2058		2058
2059	counter@23220000 {	2059	counter@23220000 {
2060	compatible = "ti,am62-eqep";	2060	compatible = "ti,am62-eqep";
2061	reg = <0x00 0x23220000 0x00 0x100>;	2061	reg = <0x00 0x23220000 0x00 0x100>;
2062	power-domains = <0x09 0x3e 0x01>;	2062	power-domains = <0x09 0x3e 0x01>;
2063	clocks = <0x07 0x3e 0x00>;	2063	clocks = <0x07 0x3e 0x00>;
2064	interrupts = <0x00 0x76 0x01>;	2064	interrupts = <0x00 0x76 0x01>;
2065	status = "disabled";	2065	status = "disabled";
2066	phandle = <0xdc>;	2066	phandle = <0xdc>;
2067	};	2067	};
2068		2068
2069	can@20701000 {	2069	can@20701000 {
2070	compatible = "bosch,m_can";	2070	compatible = "bosch,m_can";
2071	reg = <0x00 0x20701000 0x00 0x200 0x00 0x20708000 0x00 0x8000>;	2071	reg = <0x00 0x20701000 0x00 0x200 0x00 0x20708000 0x00 0x8000>;
2072	reg-names = "m_can\0message_ram";	2072	reg-names = "m_can\0message_ram";
2073	power-domains = <0x09 0x62 0x01>;	2073	power-domains = <0x09 0x62 0x01>;
2074	clocks = <0x07 0x62 0x06 0x07 0x62 0x01>;	2074	clocks = <0x07 0x62 0x06 0x07 0x62 0x01>;
2075	clock-names = "hclk\0cclk";	2075	clock-names = "hclk\0cclk";
2076	interrupts = <0x00 0x9b 0x04 0x00 0x9c 0x04>;	2076	interrupts = <0x00 0x9b 0x04 0x00 0x9c 0x04>;
2077	interrupt-names = "int0\0int1";	2077	interrupt-names = "int0\0int1";
2078	bosch,mram-cfg = <0x00 0x80 0x40 0x40 0x40 0x40 0x20 0x20>;	2078	bosch,mram-cfg = <0x00 0x80 0x40 0x40 0x40 0x40 0x20 0x20>;
2079	status = "okay";	2079	status = "disabled";
2080	pinctrl-names = "default";	2080	pinctrl-names = "default";
2081	pinctrl-0 = <0x43>;	2081	pinctrl-0 = <0x43>;
2082	phys = <0x44>;	2082	phys = <0x44>;
2083	phandle = <0xdd>;	2083	phandle = <0xdd>;
2084	};	2084	};
2085		2085
2086	can@20711000 {	2086	can@20711000 {
2087	compatible = "bosch,m_can";	2087	compatible = "bosch,m_can";
2088	reg = <0x00 0x20711000 0x00 0x200 0x00 0x20718000 0x00 0x8000>;	2088	reg = <0x00 0x20711000 0x00 0x200 0x00 0x20718000 0x00 0x8000>;
2089	reg-names = "m_can\0message_ram";	2089	reg-names = "m_can\0message_ram";
2090	power-domains = <0x09 0x63 0x01>;	2090	power-domains = <0x09 0x63 0x01>;
2091	clocks = <0x07 0x63 0x06 0x07 0x63 0x01>;	2091	clocks = <0x07 0x63 0x06 0x07 0x63 0x01>;
2092	clock-names = "hclk\0cclk";	2092	clock-names = "hclk\0cclk";
2093	interrupts = <0x00 0xd5 0x04 0x00 0xd6 0x04>;	2093	interrupts = <0x00 0xd5 0x04 0x00 0xd6 0x04>;
2094	interrupt-names = "int0\0int1";	2094	interrupt-names = "int0\0int1";
2095	bosch,mram-cfg = <0x00 0x80 0x40 0x40 0x40 0x40 0x20 0x20>;	2095	bosch,mram-cfg = <0x00 0x80 0x40 0x40 0x40 0x40 0x20 0x20>;
2096	status = "disabled";	2096	status = "disabled";
2097	phandle = <0xde>;	2097	phandle = <0xde>;
2098	};	2098	};
2099		2099
2100	watchdog@e000000 {	2100	watchdog@e000000 {
2101	compatible = "ti,j7-rti-wdt";	2101	compatible = "ti,j7-rti-wdt";
2102	reg = <0x00 0xe000000 0x00 0x100>;	2102	reg = <0x00 0xe000000 0x00 0x100>;
2103	clocks = <0x07 0x7d 0x00>;	2103	clocks = <0x07 0x7d 0x00>;
2104	power-domains = <0x09 0x7d 0x01>;	2104	power-domains = <0x09 0x7d 0x01>;
2105	assigned-clocks = <0x07 0x7d 0x00>;	2105	assigned-clocks = <0x07 0x7d 0x00>;
2106	assigned-clock-parents = <0x07 0x7d 0x04>;	2106	assigned-clock-parents = <0x07 0x7d 0x04>;
2107	phandle = <0xdf>;	2107	phandle = <0xdf>;
2108	};	2108	};
2109		2109
2110	watchdog@e010000 {	2110	watchdog@e010000 {
2111	compatible = "ti,j7-rti-wdt";	2111	compatible = "ti,j7-rti-wdt";
2112	reg = <0x00 0xe010000 0x00 0x100>;	2112	reg = <0x00 0xe010000 0x00 0x100>;
2113	clocks = <0x07 0x7e 0x00>;	2113	clocks = <0x07 0x7e 0x00>;
2114	power-domains = <0x09 0x7e 0x01>;	2114	power-domains = <0x09 0x7e 0x01>;
2115	assigned-clocks = <0x07 0x7e 0x00>;	2115	assigned-clocks = <0x07 0x7e 0x00>;
2116	assigned-clock-parents = <0x07 0x7e 0x04>;	2116	assigned-clock-parents = <0x07 0x7e 0x04>;
2117	phandle = <0xe0>;	2117	phandle = <0xe0>;
2118	};	2118	};
2119		2119
2120	watchdog@e020000 {	2120	watchdog@e020000 {
2121	compatible = "ti,j7-rti-wdt";	2121	compatible = "ti,j7-rti-wdt";
2122	reg = <0x00 0xe020000 0x00 0x100>;	2122	reg = <0x00 0xe020000 0x00 0x100>;
2123	clocks = <0x07 0x7f 0x00>;	2123	clocks = <0x07 0x7f 0x00>;
2124	power-domains = <0x09 0x7f 0x01>;	2124	power-domains = <0x09 0x7f 0x01>;
2125	assigned-clocks = <0x07 0x7f 0x00>;	2125	assigned-clocks = <0x07 0x7f 0x00>;
2126	assigned-clock-parents = <0x07 0x7f 0x04>;	2126	assigned-clock-parents = <0x07 0x7f 0x04>;
2127	phandle = <0xe1>;	2127	phandle = <0xe1>;
2128	};	2128	};
2129		2129
2130	watchdog@e030000 {	2130	watchdog@e030000 {
2131	compatible = "ti,j7-rti-wdt";	2131	compatible = "ti,j7-rti-wdt";
2132	reg = <0x00 0xe030000 0x00 0x100>;	2132	reg = <0x00 0xe030000 0x00 0x100>;
2133	clocks = <0x07 0x80 0x00>;	2133	clocks = <0x07 0x80 0x00>;
2134	power-domains = <0x09 0x80 0x01>;	2134	power-domains = <0x09 0x80 0x01>;
2135	assigned-clocks = <0x07 0x80 0x00>;	2135	assigned-clocks = <0x07 0x80 0x00>;
2136	assigned-clock-parents = <0x07 0x80 0x04>;	2136	assigned-clock-parents = <0x07 0x80 0x04>;
2137	phandle = <0xe2>;	2137	phandle = <0xe2>;
2138	};	2138	};
2139		2139
2140	watchdog@e0f0000 {	2140	watchdog@e0f0000 {
2141	compatible = "ti,j7-rti-wdt";	2141	compatible = "ti,j7-rti-wdt";
2142	reg = <0x00 0xe0f0000 0x00 0x100>;	2142	reg = <0x00 0xe0f0000 0x00 0x100>;
2143	clocks = <0x07 0x82 0x00>;	2143	clocks = <0x07 0x82 0x00>;
2144	power-domains = <0x09 0x82 0x01>;	2144	power-domains = <0x09 0x82 0x01>;
2145	assigned-clocks = <0x07 0x82 0x00>;	2145	assigned-clocks = <0x07 0x82 0x00>;
2146	assigned-clock-parents = <0x07 0x82 0x02>;	2146	assigned-clock-parents = <0x07 0x82 0x02>;
2147	phandle = <0xe3>;	2147	phandle = <0xe3>;
2148	};	2148	};
2149		2149
2150	pwm@23000000 {	2150	pwm@23000000 {
2151	compatible = "ti,am64-epwm\0ti,am3352-ehrpwm";	2151	compatible = "ti,am64-epwm\0ti,am3352-ehrpwm";
2152	#pwm-cells = <0x03>;	2152	#pwm-cells = <0x03>;
2153	reg = <0x00 0x23000000 0x00 0x100>;	2153	reg = <0x00 0x23000000 0x00 0x100>;
2154	power-domains = <0x09 0x56 0x01>;	2154	power-domains = <0x09 0x56 0x01>;
2155	clocks = <0x45 0x00 0x07 0x56 0x00>;	2155	clocks = <0x45 0x00 0x07 0x56 0x00>;
2156	clock-names = "tbclk\0fck";	2156	clock-names = "tbclk\0fck";
2157	status = "disabled";	2157	status = "disabled";
2158	phandle = <0xe4>;	2158	phandle = <0xe4>;
2159	};	2159	};
2160		2160
2161	pwm@23010000 {	2161	pwm@23010000 {
2162	compatible = "ti,am64-epwm\0ti,am3352-ehrpwm";	2162	compatible = "ti,am64-epwm\0ti,am3352-ehrpwm";
2163	#pwm-cells = <0x03>;	2163	#pwm-cells = <0x03>;
2164	reg = <0x00 0x23010000 0x00 0x100>;	2164	reg = <0x00 0x23010000 0x00 0x100>;
2165	power-domains = <0x09 0x57 0x01>;	2165	power-domains = <0x09 0x57 0x01>;
2166	clocks = <0x45 0x01 0x07 0x57 0x00>;	2166	clocks = <0x45 0x01 0x07 0x57 0x00>;
2167	clock-names = "tbclk\0fck";	2167	clock-names = "tbclk\0fck";
2168	status = "disabled";	2168	status = "disabled";
2169	phandle = <0xe5>;	2169	phandle = <0xe5>;
2170	};	2170	};
2171		2171
2172	pwm@23020000 {	2172	pwm@23020000 {
2173	compatible = "ti,am64-epwm\0ti,am3352-ehrpwm";	2173	compatible = "ti,am64-epwm\0ti,am3352-ehrpwm";
2174	#pwm-cells = <0x03>;	2174	#pwm-cells = <0x03>;
2175	reg = <0x00 0x23020000 0x00 0x100>;	2175	reg = <0x00 0x23020000 0x00 0x100>;
2176	power-domains = <0x09 0x58 0x01>;	2176	power-domains = <0x09 0x58 0x01>;
2177	clocks = <0x45 0x02 0x07 0x58 0x00>;	2177	clocks = <0x45 0x02 0x07 0x58 0x00>;
2178	clock-names = "tbclk\0fck";	2178	clock-names = "tbclk\0fck";
2179	status = "disabled";	2179	status = "disabled";
2180	phandle = <0xe6>;	2180	phandle = <0xe6>;
2181	};	2181	};
2182		2182
2183	audio-controller@2b00000 {	2183	audio-controller@2b00000 {
2184	compatible = "ti,am33xx-mcasp-audio";	2184	compatible = "ti,am33xx-mcasp-audio";
2185	reg = <0x00 0x2b00000 0x00 0x2000 0x00 0x2b08000 0x00 0x400>;	2185	reg = <0x00 0x2b00000 0x00 0x2000 0x00 0x2b08000 0x00 0x400>;
2186	reg-names = "mpu\0dat";	2186	reg-names = "mpu\0dat";
2187	interrupts = <0x00 0xec 0x04 0x00 0xeb 0x04>;	2187	interrupts = <0x00 0xec 0x04 0x00 0xeb 0x04>;
2188	interrupt-names = "tx\0rx";	2188	interrupt-names = "tx\0rx";
2189	dmas = <0x21 0x00 0xc500 0x00 0x21 0x00 0x4500 0x00>;	2189	dmas = <0x21 0x00 0xc500 0x00 0x21 0x00 0x4500 0x00>;
2190	dma-names = "tx\0rx";	2190	dma-names = "tx\0rx";
2191	clocks = <0x07 0xbe 0x00>;	2191	clocks = <0x07 0xbe 0x00>;
2192	clock-names = "fck";	2192	clock-names = "fck";
2193	assigned-clocks = <0x07 0xbe 0x00>;	2193	assigned-clocks = <0x07 0xbe 0x00>;
2194	assigned-clock-parents = <0x07 0xbe 0x02>;	2194	assigned-clock-parents = <0x07 0xbe 0x02>;
2195	power-domains = <0x09 0xbe 0x01>;	2195	power-domains = <0x09 0xbe 0x01>;
2196	status = "disabled";	2196	status = "disabled";
2197	phandle = <0xe7>;	2197	phandle = <0xe7>;
2198	};	2198	};
2199		2199
2200	audio-controller@2b10000 {	2200	audio-controller@2b10000 {
2201	compatible = "ti,am33xx-mcasp-audio";	2201	compatible = "ti,am33xx-mcasp-audio";
2202	reg = <0x00 0x2b10000 0x00 0x2000 0x00 0x2b18000 0x00 0x400>;	2202	reg = <0x00 0x2b10000 0x00 0x2000 0x00 0x2b18000 0x00 0x400>;
2203	reg-names = "mpu\0dat";	2203	reg-names = "mpu\0dat";
2204	interrupts = <0x00 0xee 0x04 0x00 0xed 0x04>;	2204	interrupts = <0x00 0xee 0x04 0x00 0xed 0x04>;
2205	interrupt-names = "tx\0rx";	2205	interrupt-names = "tx\0rx";
2206	dmas = <0x21 0x00 0xc501 0x00 0x21 0x00 0x4501 0x00>;	2206	dmas = <0x21 0x00 0xc501 0x00 0x21 0x00 0x4501 0x00>;
2207	dma-names = "tx\0rx";	2207	dma-names = "tx\0rx";
2208	clocks = <0x07 0xbf 0x00>;	2208	clocks = <0x07 0xbf 0x00>;
2209	clock-names = "fck";	2209	clock-names = "fck";
2210	assigned-clocks = <0x07 0xbf 0x00>;	2210	assigned-clocks = <0x07 0xbf 0x00>;
2211	assigned-clock-parents = <0x07 0xbf 0x02>;	2211	assigned-clock-parents = <0x07 0xbf 0x02>;
2212	power-domains = <0x09 0xbf 0x01>;	2212	power-domains = <0x09 0xbf 0x01>;
2213	status = "okay";	2213	status = "okay";
2214	#sound-dai-cells = <0x00>;	2214	#sound-dai-cells = <0x00>;
2215	pinctrl-names = "default";	2215	pinctrl-names = "default";
2216	pinctrl-0 = <0x46>;	2216	pinctrl-0 = <0x46>;
2217	op-mode = <0x00>;	2217	op-mode = <0x00>;
2218	tdm-slots = <0x02>;	2218	tdm-slots = <0x02>;
2219	serial-dir = <0x01 0x00 0x02 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>;	2219	serial-dir = <0x01 0x00 0x02 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>;
2220	phandle = <0x6f>;	2220	phandle = <0x6f>;
2221	};	2221	};
2222		2222
2223	audio-controller@2b20000 {	2223	audio-controller@2b20000 {
2224	compatible = "ti,am33xx-mcasp-audio";	2224	compatible = "ti,am33xx-mcasp-audio";
2225	reg = <0x00 0x2b20000 0x00 0x2000 0x00 0x2b28000 0x00 0x400>;	2225	reg = <0x00 0x2b20000 0x00 0x2000 0x00 0x2b28000 0x00 0x400>;
2226	reg-names = "mpu\0dat";	2226	reg-names = "mpu\0dat";
2227	interrupts = <0x00 0xf0 0x04 0x00 0xef 0x04>;	2227	interrupts = <0x00 0xf0 0x04 0x00 0xef 0x04>;
2228	interrupt-names = "tx\0rx";	2228	interrupt-names = "tx\0rx";
2229	dmas = <0x21 0x00 0xc502 0x00 0x21 0x00 0x4502 0x00>;	2229	dmas = <0x21 0x00 0xc502 0x00 0x21 0x00 0x4502 0x00>;
2230	dma-names = "tx\0rx";	2230	dma-names = "tx\0rx";
2231	clocks = <0x07 0xc0 0x00>;	2231	clocks = <0x07 0xc0 0x00>;
2232	clock-names = "fck";	2232	clock-names = "fck";
2233	assigned-clocks = <0x07 0xc0 0x00>;	2233	assigned-clocks = <0x07 0xc0 0x00>;
2234	assigned-clock-parents = <0x07 0xc0 0x02>;	2234	assigned-clock-parents = <0x07 0xc0 0x02>;
2235	power-domains = <0x09 0xc0 0x01>;	2235	power-domains = <0x09 0xc0 0x01>;
2236	status = "disabled";	2236	status = "disabled";
2237	phandle = <0xe8>;	2237	phandle = <0xe8>;
2238	};	2238	};
2239		2239
2240	ticsi2rx@30102000 {	2240	ticsi2rx@30102000 {
2241	compatible = "ti,j721e-csi2rx-shim";	2241	compatible = "ti,j721e-csi2rx-shim";
2242	reg = <0x00 0x30102000 0x00 0x1000>;	2242	reg = <0x00 0x30102000 0x00 0x1000>;
2243	ranges;	2243	ranges;
2244	#address-cells = <0x02>;	2244	#address-cells = <0x02>;
2245	#size-cells = <0x02>;	2245	#size-cells = <0x02>;
2246	dmas = <0x24 0x00 0x5000 0x00 0x24 0x00 0x5001 0x00 0x24 0x00 0x5002 0x00 0x24 0x00 0x5003 0x00 0x24 0x00 0x5004 0x00 0x24 0x00 0x5005 0x00>;	2246	dmas = <0x24 0x00 0x5000 0x00 0x24 0x00 0x5001 0x00 0x24 0x00 0x5002 0x00 0x24 0x00 0x5003 0x00 0x24 0x00 0x5004 0x00 0x24 0x00 0x5005 0x00>;
2247	dma-names = "rx0\0rx1\0rx2\0rx3\0rx4\0rx5";	2247	dma-names = "rx0\0rx1\0rx2\0rx3\0rx4\0rx5";
2248	power-domains = <0x09 0xb6 0x01>;	2248	power-domains = <0x09 0xb6 0x01>;
2249	status = "disabled";	2249	status = "disabled";
2250	phandle = <0xe9>;	2250	phandle = <0xe9>;
2251		2251
2252	csi-bridge@30101000 {	2252	csi-bridge@30101000 {
2253	compatible = "ti,j721e-csi2rx\0cdns,csi2rx";	2253	compatible = "ti,j721e-csi2rx\0cdns,csi2rx";
2254	reg = <0x00 0x30101000 0x00 0x1000>;	2254	reg = <0x00 0x30101000 0x00 0x1000>;
2255	interrupts = <0x00 0x8f 0x04 0x00 0x8d 0x04>;	2255	interrupts = <0x00 0x8f 0x04 0x00 0x8d 0x04>;
2256	interrupt-names = "error_irq\0irq";	2256	interrupt-names = "error_irq\0irq";
2257	clocks = <0x07 0xb6 0x00 0x07 0xb6 0x03 0x07 0xb6 0x00 0x07 0xb6 0x00 0x07 0xb6 0x04 0x07 0xb6 0x04>;	2257	clocks = <0x07 0xb6 0x00 0x07 0xb6 0x03 0x07 0xb6 0x00 0x07 0xb6 0x00 0x07 0xb6 0x04 0x07 0xb6 0x04>;
2258	clock-names = "sys_clk\0p_clk\0pixel_if0_clk\0pixel_if1_clk\0pixel_if2_clk\0pixel_if3_clk";	2258	clock-names = "sys_clk\0p_clk\0pixel_if0_clk\0pixel_if1_clk\0pixel_if2_clk\0pixel_if3_clk";
2259	phys = <0x47>;	2259	phys = <0x47>;
2260	phy-names = "dphy";	2260	phy-names = "dphy";
2261	phandle = <0xea>;	2261	phandle = <0xea>;
2262		2262
2263	ports {	2263	ports {
2264	#address-cells = <0x01>;	2264	#address-cells = <0x01>;
2265	#size-cells = <0x00>;	2265	#size-cells = <0x00>;
2266		2266
2267	port@0 {	2267	port@0 {
2268	reg = <0x00>;	2268	reg = <0x00>;
2269	status = "disabled";	2269	status = "disabled";
2270	phandle = <0xeb>;	2270	phandle = <0xeb>;
2271	};	2271	};
2272		2272
2273	port@1 {	2273	port@1 {
2274	reg = <0x01>;	2274	reg = <0x01>;
2275	status = "disabled";	2275	status = "disabled";
2276	phandle = <0xec>;	2276	phandle = <0xec>;
2277	};	2277	};
2278		2278
2279	port@2 {	2279	port@2 {
2280	reg = <0x02>;	2280	reg = <0x02>;
2281	status = "disabled";	2281	status = "disabled";
2282	phandle = <0xed>;	2282	phandle = <0xed>;
2283	};	2283	};
2284		2284
2285	port@3 {	2285	port@3 {
2286	reg = <0x03>;	2286	reg = <0x03>;
2287	status = "disabled";	2287	status = "disabled";
2288	phandle = <0xee>;	2288	phandle = <0xee>;
2289	};	2289	};
2290		2290
2291	port@4 {	2291	port@4 {
2292	reg = <0x04>;	2292	reg = <0x04>;
2293	status = "disabled";	2293	status = "disabled";
2294	phandle = <0xef>;	2294	phandle = <0xef>;
2295	};	2295	};
2296	};	2296	};
2297	};	2297	};
2298	};	2298	};
2299		2299
2300	phy@30110000 {	2300	phy@30110000 {
2301	compatible = "cdns,dphy-rx";	2301	compatible = "cdns,dphy-rx";
2302	reg = <0x00 0x30110000 0x00 0x1100>;	2302	reg = <0x00 0x30110000 0x00 0x1100>;
2303	#phy-cells = <0x00>;	2303	#phy-cells = <0x00>;
2304	power-domains = <0x09 0xb9 0x01>;	2304	power-domains = <0x09 0xb9 0x01>;
2305	status = "disabled";	2305	status = "disabled";
2306	phandle = <0x47>;	2306	phandle = <0x47>;
2307	};	2307	};
2308		2308
2309	dss@30200000 {	2309	dss@30200000 {
2310	compatible = "ti,am62p51-dss";	2310	compatible = "ti,am62p51-dss";
2311	reg = <0x00 0x30200000 0x00 0x1000 0x00 0x30202000 0x00 0x1000 0x00 0x30206000 0x00 0x1000 0x00 0x30207000 0x00 0x1000 0x00 0x30208000 0x00 0x1000 0x00 0x3020a000 0x00 0x1000 0x00 0x3020b000 0x00 0x1000 0x00 0x30201000 0x00 0x1000>;	2311	reg = <0x00 0x30200000 0x00 0x1000 0x00 0x30202000 0x00 0x1000 0x00 0x30206000 0x00 0x1000 0x00 0x30207000 0x00 0x1000 0x00 0x30208000 0x00 0x1000 0x00 0x3020a000 0x00 0x1000 0x00 0x3020b000 0x00 0x1000 0x00 0x30201000 0x00 0x1000>;
2312	reg-names = "common\0vidl1\0vid\0ovr1\0ovr2\0vp1\0vp2\0common1";	2312	reg-names = "common\0vidl1\0vid\0ovr1\0ovr2\0vp1\0vp2\0common1";
2313	power-domains = <0x09 0xba 0x01 0x09 0xf3 0x01 0x09 0xf4 0x01>;	2313	power-domains = <0x09 0xba 0x01 0x09 0xf3 0x01 0x09 0xf4 0x01>;
2314	clocks = <0x07 0xba 0x06 0x48 0x07 0xba 0x02>;	2314	clocks = <0x07 0xba 0x06 0x48 0x07 0xba 0x02>;
2315	clock-names = "fck\0vp1\0vp2";	2315	clock-names = "fck\0vp1\0vp2";
2316	interrupts = <0x00 0x54 0x04>;	2316	interrupts = <0x00 0x54 0x04>;
2317	status = "disabled";	2317	status = "disabled";
2318	phandle = <0xf0>;	2318	phandle = <0xf0>;
2319		2319
2320	oldi-transmitters {	2320	oldi-transmitters {
2321	#address-cells = <0x01>;	2321	#address-cells = <0x01>;
2322	#size-cells = <0x00>;	2322	#size-cells = <0x00>;
2323		2323
2324	oldi@0 {	2324	oldi@0 {
2325	reg = <0x00>;	2325	reg = <0x00>;
2326	clocks = <0x07 0xba 0x00>;	2326	clocks = <0x07 0xba 0x00>;
2327	clock-names = "serial";	2327	clock-names = "serial";
2328	ti,oldi-io-ctrl = <0x49>;	2328	ti,oldi-io-ctrl = <0x49>;
2329	status = "disabled";	2329	status = "disabled";
2330	phandle = <0xf1>;	2330	phandle = <0xf1>;
2331		2331
2332	ports {	2332	ports {
2333	phandle = <0xf2>;	2333	phandle = <0xf2>;
2334	};	2334	};
2335	};	2335	};
2336		2336
2337	oldi@1 {	2337	oldi@1 {
2338	reg = <0x01>;	2338	reg = <0x01>;
2339	status = "disabled";	2339	status = "disabled";
2340	phandle = <0xf3>;	2340	phandle = <0xf3>;
2341		2341
2342	ports {	2342	ports {
2343	phandle = <0xf4>;	2343	phandle = <0xf4>;
2344	};	2344	};
2345	};	2345	};
2346	};	2346	};
2347		2347
2348	ports {	2348	ports {
2349	#address-cells = <0x01>;	2349	#address-cells = <0x01>;
2350	#size-cells = <0x00>;	2350	#size-cells = <0x00>;
2351	phandle = <0xf5>;	2351	phandle = <0xf5>;
2352	};	2352	};
2353	};	2353	};
2354		2354
2355	dss@30220000 {	2355	dss@30220000 {
2356	compatible = "ti,am62p52-dss";	2356	compatible = "ti,am62p52-dss";
2357	reg = <0x00 0x30220000 0x00 0x1000 0x00 0x30222000 0x00 0x1000 0x00 0x30226000 0x00 0x1000 0x00 0x30227000 0x00 0x1000 0x00 0x30228000 0x00 0x1000 0x00 0x3022a000 0x00 0x1000 0x00 0x3022b000 0x00 0x1000 0x00 0x30221000 0x00 0x1000>;	2357	reg = <0x00 0x30220000 0x00 0x1000 0x00 0x30222000 0x00 0x1000 0x00 0x30226000 0x00 0x1000 0x00 0x30227000 0x00 0x1000 0x00 0x30228000 0x00 0x1000 0x00 0x3022a000 0x00 0x1000 0x00 0x3022b000 0x00 0x1000 0x00 0x30221000 0x00 0x1000>;
2358	reg-names = "common\0vidl1\0vid\0ovr1\0ovr2\0vp1\0vp2\0common1";	2358	reg-names = "common\0vidl1\0vid\0ovr1\0ovr2\0vp1\0vp2\0common1";
2359	power-domains = <0x09 0xe8 0x01 0x09 0xf4 0x01>;	2359	power-domains = <0x09 0xe8 0x01 0x09 0xf4 0x01>;
2360	clocks = <0x07 0xe8 0x08 0x07 0xe8 0x00 0x07 0xe8 0x04>;	2360	clocks = <0x07 0xe8 0x08 0x07 0xe8 0x00 0x07 0xe8 0x04>;
2361	clock-names = "fck\0vp1\0vp2";	2361	clock-names = "fck\0vp1\0vp2";
2362	interrupts = <0x00 0x1e 0x04>;	2362	interrupts = <0x00 0x1e 0x04>;
2363	status = "okay";	2363	status = "okay";
2364	pinctrl-names = "default";	2364	pinctrl-names = "default";
2365	pinctrl-0 = <0x4a>;	2365	pinctrl-0 = <0x4a>;
2366	assigned-clocks = <0x07 0xf1 0x00 0x07 0xf0 0x00 0x07 0xf5 0x00>;	2366	assigned-clocks = <0x07 0xf1 0x00 0x07 0xf0 0x00 0x07 0xf5 0x00>;
2367	assigned-clock-parents = <0x07 0xf1 0x02 0x07 0xf0 0x01 0x07 0xf5 0x02>;	2367	assigned-clock-parents = <0x07 0xf1 0x02 0x07 0xf0 0x01 0x07 0xf5 0x02>;
2368	phandle = <0xf6>;	2368	phandle = <0xf6>;
2369		2369
2370	oldi-transmitters {	2370	oldi-transmitters {
2371	#address-cells = <0x01>;	2371	#address-cells = <0x01>;
2372	#size-cells = <0x00>;	2372	#size-cells = <0x00>;
2373		2373
2374	oldi@1 {	2374	oldi@1 {
2375	reg = <0x00>;	2375	reg = <0x00>;
2376	clocks = <0x07 0xe8 0x00>;	2376	clocks = <0x07 0xe8 0x00>;
2377	clock-names = "serial";	2377	clock-names = "serial";
2378	ti,oldi-io-ctrl = <0x49>;	2378	ti,oldi-io-ctrl = <0x49>;
2379	status = "disabled";	2379	status = "disabled";
2380	phandle = <0xf7>;	2380	phandle = <0xf7>;
2381		2381
2382	ports {	2382	ports {
2383	phandle = <0xf8>;	2383	phandle = <0xf8>;
2384	};	2384	};
2385	};	2385	};
2386	};	2386	};
2387		2387
2388	ports {	2388	ports {
2389	#address-cells = <0x01>;	2389	#address-cells = <0x01>;
2390	#size-cells = <0x00>;	2390	#size-cells = <0x00>;
2391	phandle = <0xf9>;	2391	phandle = <0xf9>;
2392		2392
2393	port@0 {	2393	port@0 {
2394	reg = <0x00>;	2394	reg = <0x00>;
2395		2395
2396	endpoint {	2396	endpoint {
2397	remote-endpoint = <0x4b>;	2397	remote-endpoint = <0x4b>;
2398	phandle = <0x30>;	2398	phandle = <0x30>;
2399	};	2399	};
2400	};	2400	};
2401		2401
2402	port@1 {	2402	port@1 {
2403	reg = <0x01>;	2403	reg = <0x01>;
2404		2404
2405	endpoint {	2405	endpoint {
2406	remote-endpoint = <0x4c>;	2406	remote-endpoint = <0x4c>;
2407	phandle = <0x4f>;	2407	phandle = <0x4f>;
2408	};	2408	};
2409	};	2409	};
2410	};	2410	};
2411	};	2411	};
2412		2412
2413	phy@301c0000 {	2413	phy@301c0000 {
2414	compatible = "ti,j721e-dphy";	2414	compatible = "ti,j721e-dphy";
2415	reg = <0x00 0x301c0000 0x00 0x1000>;	2415	reg = <0x00 0x301c0000 0x00 0x1000>;
2416	clocks = <0x07 0xee 0x10 0x07 0xee 0x01>;	2416	clocks = <0x07 0xee 0x10 0x07 0xee 0x01>;
2417	clock-names = "psm\0pll_ref";	2417	clock-names = "psm\0pll_ref";
2418	#phy-cells = <0x00>;	2418	#phy-cells = <0x00>;
2419	power-domains = <0x09 0xee 0x01>;	2419	power-domains = <0x09 0xee 0x01>;
2420	assigned-clocks = <0x07 0xee 0x01>;	2420	assigned-clocks = <0x07 0xee 0x01>;
2421	assigned-clock-parents = <0x07 0xee 0x02>;	2421	assigned-clock-parents = <0x07 0xee 0x02>;
2422	assigned-clock-rates = <0x17d7840>;	2422	assigned-clock-rates = <0x17d7840>;
2423	status = "okay";	2423	status = "okay";
2424	phandle = <0x4d>;	2424	phandle = <0x4d>;
2425	};	2425	};
2426		2426
2427	dsi@30500000 {	2427	dsi@30500000 {
2428	compatible = "ti,j721e-dsi";	2428	compatible = "ti,j721e-dsi";
2429	reg = <0x00 0x30500000 0x00 0x100000 0x00 0x30270000 0x00 0x100>;	2429	reg = <0x00 0x30500000 0x00 0x100000 0x00 0x30270000 0x00 0x100>;
2430	clocks = <0x07 0xe7 0x02 0x07 0xe7 0x05>;	2430	clocks = <0x07 0xe7 0x02 0x07 0xe7 0x05>;
2431	clock-names = "dsi_p_clk\0dsi_sys_clk";	2431	clock-names = "dsi_p_clk\0dsi_sys_clk";
2432	power-domains = <0x09 0xe7 0x01>;	2432	power-domains = <0x09 0xe7 0x01>;
2433	interrupt-parent = <0x01>;	2433	interrupt-parent = <0x01>;
2434	interrupts = <0x00 0x56 0x04>;	2434	interrupts = <0x00 0x56 0x04>;
2435	phys = <0x4d>;	2435	phys = <0x4d>;
2436	phy-names = "dphy";	2436	phy-names = "dphy";
2437	status = "okay";	2437	status = "okay";
2438	phandle = <0xfa>;	2438	phandle = <0xfa>;
2439		2439
2440	ports {	2440	ports {
2441	#address-cells = <0x01>;	2441	#address-cells = <0x01>;
2442	#size-cells = <0x00>;	2442	#size-cells = <0x00>;
2443		2443
2444	port@0 {	2444	port@0 {
2445	reg = <0x00>;	2445	reg = <0x00>;
2446		2446
2447	endpoint {	2447	endpoint {
2448	remote-endpoint = <0x4e>;	2448	remote-endpoint = <0x4e>;
2449	phandle = <0x34>;	2449	phandle = <0x34>;
2450	};	2450	};
2451	};	2451	};
2452		2452
2453	port@1 {	2453	port@1 {
2454	reg = <0x01>;	2454	reg = <0x01>;
2455		2455
2456	endpoint {	2456	endpoint {
2457	remote-endpoint = <0x4f>;	2457	remote-endpoint = <0x4f>;
2458	phandle = <0x4c>;	2458	phandle = <0x4c>;
2459	};	2459	};
2460	};	2460	};
2461	};	2461	};
2462	};	2462	};
2463		2463
2464	video-codec@30210000 {	2464	video-codec@30210000 {
2465	compatible = "ti,j721s2-wave521c\0cnm,wave521c";	2465	compatible = "ti,j721s2-wave521c\0cnm,wave521c";
2466	reg = <0x00 0x30210000 0x00 0x10000>;	2466	reg = <0x00 0x30210000 0x00 0x10000>;
2467	interrupts = <0x00 0xe1 0x04>;	2467	interrupts = <0x00 0xe1 0x04>;
2468	clocks = <0x07 0xcc 0x02>;	2468	clocks = <0x07 0xcc 0x02>;
2469	power-domains = <0x09 0xcc 0x01>;	2469	power-domains = <0x09 0xcc 0x01>;
2470	sram = <0x50>;	2470	sram = <0x50>;
2471	operating-points-v2 = <0x51>;	2471	operating-points-v2 = <0x51>;
2472	phandle = <0xfb>;	2472	phandle = <0xfb>;
2473		2473
2474	opp-table {	2474	opp-table {
2475	compatible = "operating-points-v2";	2475	compatible = "operating-points-v2";
2476	phandle = <0x51>;	2476	phandle = <0x51>;
2477		2477
2478	opp-20000000 {	2478	opp-20000000 {
2479	opp-hz = <0x00 0x1312d00>;	2479	opp-hz = <0x00 0x1312d00>;
2480	};	2480	};
2481		2481
2482	opp-100000000 {	2482	opp-100000000 {
2483	opp-hz = <0x00 0x5f5e100>;	2483	opp-hz = <0x00 0x5f5e100>;
2484	};	2484	};
2485		2485
2486	opp-200000000 {	2486	opp-200000000 {
2487	opp-hz = <0x00 0xbebc200>;	2487	opp-hz = <0x00 0xbebc200>;
2488	};	2488	};
2489		2489
2490	opp-400000000 {	2490	opp-400000000 {
2491	opp-hz = <0x00 0x17d78400>;	2491	opp-hz = <0x00 0x17d78400>;
2492	};	2492	};
2493		2493
2494	opp-500000000 {	2494	opp-500000000 {
2495	opp-hz = <0x00 0x1dcd6500>;	2495	opp-hz = <0x00 0x1dcd6500>;
2496	};	2496	};
2497	};	2497	};
2498	};	2498	};
2499		2499
2500	phy@f000000 {	2500	phy@f000000 {
2501	compatible = "ti,am64-wiz-10g";	2501	compatible = "ti,am64-wiz-10g";
2502	ranges = <0xf000000 0x00 0xf000000 0x10000>;	2502	ranges = <0xf000000 0x00 0xf000000 0x10000>;
2503	#address-cells = <0x01>;	2503	#address-cells = <0x01>;
2504	#size-cells = <0x01>;	2504	#size-cells = <0x01>;
2505	power-domains = <0x09 0x117 0x01>;	2505	power-domains = <0x09 0x117 0x01>;
2506	clocks = <0x07 0x117 0x00 0x07 0x117 0x01 0x52>;	2506	clocks = <0x07 0x117 0x00 0x07 0x117 0x01 0x52>;
2507	clock-names = "fck\0core_ref_clk\0ext_ref_clk";	2507	clock-names = "fck\0core_ref_clk\0ext_ref_clk";
2508	num-lanes = <0x01>;	2508	num-lanes = <0x01>;
2509	#reset-cells = <0x01>;	2509	#reset-cells = <0x01>;
2510	#clock-cells = <0x01>;	2510	#clock-cells = <0x01>;
2511	assigned-clocks = <0x07 0x117 0x01>;	2511	assigned-clocks = <0x07 0x117 0x01>;
2512	assigned-clock-parents = <0x07 0x117 0x05>;	2512	assigned-clock-parents = <0x07 0x117 0x05>;
2513	status = "okay";	2513	status = "okay";
2514	phandle = <0x53>;	2514	phandle = <0x53>;
2515		2515
2516	serdes@f000000 {	2516	serdes@f000000 {
2517	compatible = "ti,j721e-serdes-10g";	2517	compatible = "ti,j721e-serdes-10g";
2518	reg = <0xf000000 0x10000>;	2518	reg = <0xf000000 0x10000>;
2519	reg-names = "torrent_phy";	2519	reg-names = "torrent_phy";
2520	resets = <0x53 0x00>;	2520	resets = <0x53 0x00>;
2521	reset-names = "torrent_reset";	2521	reset-names = "torrent_reset";
2522	clocks = <0x53 0x00 0x53 0x10>;	2522	clocks = <0x53 0x00 0x53 0x10>;
2523	clock-names = "refclk\0phy_en_refclk";	2523	clock-names = "refclk\0phy_en_refclk";
2524	assigned-clocks = <0x53 0x00 0x53 0x01 0x53 0x02>;	2524	assigned-clocks = <0x53 0x00 0x53 0x01 0x53 0x02>;
2525	assigned-clock-parents = <0x07 0x117 0x01 0x07 0x117 0x01 0x07 0x117 0x01>;	2525	assigned-clock-parents = <0x07 0x117 0x01 0x07 0x117 0x01 0x07 0x117 0x01>;
2526	#address-cells = <0x01>;	2526	#address-cells = <0x01>;
2527	#size-cells = <0x00>;	2527	#size-cells = <0x00>;
2528	#clock-cells = <0x01>;	2528	#clock-cells = <0x01>;
2529	status = "okay";	2529	status = "okay";
2530	phandle = <0xfc>;	2530	phandle = <0xfc>;
2531		2531
2532	phy@0 {	2532	phy@0 {
2533	reg = <0x00>;	2533	reg = <0x00>;
2534	cdns,num-lanes = <0x01>;	2534	cdns,num-lanes = <0x01>;
2535	#phy-cells = <0x00>;	2535	#phy-cells = <0x00>;
2536	cdns,phy-type = <0x04>;	2536	cdns,phy-type = <0x04>;
2537	resets = <0x53 0x01>;	2537	resets = <0x53 0x01>;
2538	phandle = <0x5b>;	2538	phandle = <0x5b>;
2539	};	2539	};
2540	};	2540	};
2541	};	2541	};
2542		2542
2543	phy@f010000 {	2543	phy@f010000 {
2544	compatible = "ti,am64-wiz-10g";	2544	compatible = "ti,am64-wiz-10g";
2545	ranges = <0xf010000 0x00 0xf010000 0x10000>;	2545	ranges = <0xf010000 0x00 0xf010000 0x10000>;
2546	#address-cells = <0x01>;	2546	#address-cells = <0x01>;
2547	#size-cells = <0x01>;	2547	#size-cells = <0x01>;
2548	power-domains = <0x09 0x118 0x01>;	2548	power-domains = <0x09 0x118 0x01>;
2549	clocks = <0x07 0x118 0x00 0x07 0x118 0x01 0x52>;	2549	clocks = <0x07 0x118 0x00 0x07 0x118 0x01 0x52>;
2550	clock-names = "fck\0core_ref_clk\0ext_ref_clk";	2550	clock-names = "fck\0core_ref_clk\0ext_ref_clk";
2551	num-lanes = <0x01>;	2551	num-lanes = <0x01>;
2552	#reset-cells = <0x01>;	2552	#reset-cells = <0x01>;
2553	#clock-cells = <0x01>;	2553	#clock-cells = <0x01>;
2554	assigned-clocks = <0x07 0x118 0x01>;	2554	assigned-clocks = <0x07 0x118 0x01>;
2555	assigned-clock-parents = <0x07 0x118 0x05>;	2555	assigned-clock-parents = <0x07 0x118 0x05>;
2556	status = "okay";	2556	status = "okay";
2557	phandle = <0x54>;	2557	phandle = <0x54>;
2558		2558
2559	serdes@f010000 {	2559	serdes@f010000 {
2560	compatible = "ti,j721e-serdes-10g";	2560	compatible = "ti,j721e-serdes-10g";
2561	reg = <0xf010000 0x10000>;	2561	reg = <0xf010000 0x10000>;
2562	reg-names = "torrent_phy";	2562	reg-names = "torrent_phy";
2563	resets = <0x54 0x00>;	2563	resets = <0x54 0x00>;
2564	reset-names = "torrent_reset";	2564	reset-names = "torrent_reset";
2565	clocks = <0x54 0x00 0x54 0x10>;	2565	clocks = <0x54 0x00 0x54 0x10>;
2566	clock-names = "refclk\0phy_en_refclk";	2566	clock-names = "refclk\0phy_en_refclk";
2567	assigned-clocks = <0x54 0x00 0x54 0x01 0x54 0x02>;	2567	assigned-clocks = <0x54 0x00 0x54 0x01 0x54 0x02>;
2568	assigned-clock-parents = <0x07 0x118 0x01 0x07 0x118 0x01 0x07 0x118 0x01>;	2568	assigned-clock-parents = <0x07 0x118 0x01 0x07 0x118 0x01 0x07 0x118 0x01>;
2569	#address-cells = <0x01>;	2569	#address-cells = <0x01>;
2570	#size-cells = <0x00>;	2570	#size-cells = <0x00>;
2571	#clock-cells = <0x01>;	2571	#clock-cells = <0x01>;
2572	status = "okay";	2572	status = "okay";
2573	phandle = <0x55>;	2573	phandle = <0x55>;
2574		2574
2575	phy@0 {	2575	phy@0 {
2576	reg = <0x00>;	2576	reg = <0x00>;
2577	cdns,num-lanes = <0x01>;	2577	cdns,num-lanes = <0x01>;
2578	#phy-cells = <0x00>;	2578	#phy-cells = <0x00>;
2579	cdns,phy-type = <0x02>;	2579	cdns,phy-type = <0x02>;
2580	resets = <0x54 0x01>;	2580	resets = <0x54 0x01>;
2581	phandle = <0x59>;	2581	phandle = <0x59>;
2582	};	2582	};
2583	};	2583	};
2584	};	2584	};
2585		2585
2586	pcie@f102000 {	2586	pcie@f102000 {
2587	compatible = "ti,j722s-pcie-host\0ti,j721e-pcie-host";	2587	compatible = "ti,j722s-pcie-host\0ti,j721e-pcie-host";
2588	reg = <0x00 0xf102000 0x00 0x1000 0x00 0xf100000 0x00 0x400 0x00 0xd000000 0x00 0x800000 0x06 0x00 0x00 0x1000>;	2588	reg = <0x00 0xf102000 0x00 0x1000 0x00 0xf100000 0x00 0x400 0x00 0xd000000 0x00 0x800000 0x06 0x00 0x00 0x1000>;
2589	reg-names = "intd_cfg\0user_cfg\0reg\0cfg";	2589	reg-names = "intd_cfg\0user_cfg\0reg\0cfg";
2590	ranges = <0x1000000 0x00 0x1000 0x06 0x1000 0x00 0x100000 0x2000000 0x00 0x101000 0x06 0x101000 0x00 0xffeff000>;	2590	ranges = <0x1000000 0x00 0x1000 0x06 0x1000 0x00 0x100000 0x2000000 0x00 0x101000 0x06 0x101000 0x00 0xffeff000>;
2591	dma-ranges = <0x2000000 0x00 0x00 0x00 0x00 0x10000 0x00>;	2591	dma-ranges = <0x2000000 0x00 0x00 0x00 0x00 0x10000 0x00>;
2592	interrupt-names = "link_state";	2592	interrupt-names = "link_state";
2593	interrupts = <0x00 0x63 0x01>;	2593	interrupts = <0x00 0x63 0x01>;
2594	device_type = "pci";	2594	device_type = "pci";
2595	max-link-speed = <0x03>;	2595	max-link-speed = <0x03>;
2596	num-lanes = <0x01>;	2596	num-lanes = <0x01>;
2597	power-domains = <0x09 0x103 0x01>;	2597	power-domains = <0x09 0x103 0x01>;
2598	clocks = <0x07 0x103 0x00 0x55 0x00>;	2598	clocks = <0x07 0x103 0x00 0x55 0x00>;
2599	clock-names = "fck\0pcie_refclk";	2599	clock-names = "fck\0pcie_refclk";
2600	#address-cells = <0x03>;	2600	#address-cells = <0x03>;
2601	#size-cells = <0x02>;	2601	#size-cells = <0x02>;
2602	bus-range = <0x00 0xff>;	2602	bus-range = <0x00 0xff>;
2603	vendor-id = <0x104c>;	2603	vendor-id = <0x104c>;
2604	device-id = <0xb010>;	2604	device-id = <0xb010>;
2605	cdns,no-bar-match-nbits = <0x40>;	2605	cdns,no-bar-match-nbits = <0x40>;
2606	ti,syscon-pcie-ctrl = <0x56 0x00>;	2606	ti,syscon-pcie-ctrl = <0x56 0x00>;
2607	msi-map = <0x00 0x57 0x00 0x10000>;	2607	msi-map = <0x00 0x57 0x00 0x10000>;
2608	status = "okay";	2608	status = "okay";
2609	reset-gpios = <0x58 0x12 0x00>;	2609	reset-gpios = <0x58 0x12 0x00>;
2610	phys = <0x59>;	2610	phys = <0x59>;
2611	phy-names = "pcie-phy";	2611	phy-names = "pcie-phy";
2612	phandle = <0xfd>;	2612	phandle = <0xfd>;
2613	};	2613	};
2614		2614
2615	usb@f920000 {	2615	usb@f920000 {
2616	compatible = "ti,j721e-usb";	2616	compatible = "ti,j721e-usb";
2617	reg = <0x00 0xf920000 0x00 0x100>;	2617	reg = <0x00 0xf920000 0x00 0x100>;
2618	power-domains = <0x09 0x116 0x01>;	2618	power-domains = <0x09 0x116 0x01>;
2619	clocks = <0x07 0x116 0x03 0x07 0x116 0x01>;	2619	clocks = <0x07 0x116 0x03 0x07 0x116 0x01>;
2620	clock-names = "ref\0lpm";	2620	clock-names = "ref\0lpm";
2621	assigned-clocks = <0x07 0x116 0x03>;	2621	assigned-clocks = <0x07 0x116 0x03>;
2622	assigned-clock-parents = <0x07 0x116 0x04>;	2622	assigned-clock-parents = <0x07 0x116 0x04>;
2623	#address-cells = <0x02>;	2623	#address-cells = <0x02>;
2624	#size-cells = <0x02>;	2624	#size-cells = <0x02>;
2625	ranges;	2625	ranges;
2626	status = "okay";	2626	status = "okay";
2627	pinctrl-names = "default";	2627	pinctrl-names = "default";
2628	pinctrl-0 = <0x5a>;	2628	pinctrl-0 = <0x5a>;
2629	ti,vbus-divider;	2629	ti,vbus-divider;
2630	phandle = <0xfe>;	2630	phandle = <0xfe>;
2631		2631
2632	usb@31200000 {	2632	usb@31200000 {
2633	compatible = "cdns,usb3";	2633	compatible = "cdns,usb3";
2634	reg = <0x00 0x31200000 0x00 0x10000 0x00 0x31210000 0x00 0x10000 0x00 0x31220000 0x00 0x10000>;	2634	reg = <0x00 0x31200000 0x00 0x10000 0x00 0x31210000 0x00 0x10000 0x00 0x31220000 0x00 0x10000>;
2635	reg-names = "otg\0xhci\0dev";	2635	reg-names = "otg\0xhci\0dev";
2636	interrupts = <0x00 0xe2 0x04 0x00 0xe8 0x04 0x00 0xf5 0x04>;	2636	interrupts = <0x00 0xe2 0x04 0x00 0xe8 0x04 0x00 0xf5 0x04>;
2637	interrupt-names = "host\0peripheral\0otg";	2637	interrupt-names = "host\0peripheral\0otg";
2638	maximum-speed = "super-speed";	2638	maximum-speed = "super-speed";
2639	dr_mode = "host";	2639	dr_mode = "host";
2640	phys = <0x5b>;	2640	phys = <0x5b>;
2641	phy-names = "cdns3,usb3-phy";	2641	phy-names = "cdns3,usb3-phy";
2642	phandle = <0xff>;	2642	phandle = <0xff>;
2643	};	2643	};
2644	};	2644	};
2645		2645
2646	ticsi2rx@30122000 {	2646	ticsi2rx@30122000 {
2647	compatible = "ti,j721e-csi2rx-shim";	2647	compatible = "ti,j721e-csi2rx-shim";
2648	reg = <0x00 0x30122000 0x00 0x1000>;	2648	reg = <0x00 0x30122000 0x00 0x1000>;
2649	ranges;	2649	ranges;
2650	#address-cells = <0x02>;	2650	#address-cells = <0x02>;
2651	#size-cells = <0x02>;	2651	#size-cells = <0x02>;
2652	dmas = <0x24 0x00 0x5100 0x00 0x24 0x00 0x5101 0x00 0x24 0x00 0x5102 0x00 0x24 0x00 0x5103 0x00>;	2652	dmas = <0x24 0x00 0x5100 0x00 0x24 0x00 0x5101 0x00 0x24 0x00 0x5102 0x00 0x24 0x00 0x5103 0x00>;
2653	dma-names = "rx0\0rx1\0rx2\0rx3";	2653	dma-names = "rx0\0rx1\0rx2\0rx3";
2654	power-domains = <0x09 0xf7 0x01>;	2654	power-domains = <0x09 0xf7 0x01>;
2655	status = "disabled";	2655	status = "disabled";
2656	phandle = <0x100>;	2656	phandle = <0x100>;
2657		2657
2658	csi-bridge@30121000 {	2658	csi-bridge@30121000 {
2659	compatible = "ti,j721e-csi2rx\0cdns,csi2rx";	2659	compatible = "ti,j721e-csi2rx\0cdns,csi2rx";
2660	reg = <0x00 0x30121000 0x00 0x1000>;	2660	reg = <0x00 0x30121000 0x00 0x1000>;
2661	interrupts = <0x00 0x92 0x04 0x00 0x93 0x04>;	2661	interrupts = <0x00 0x92 0x04 0x00 0x93 0x04>;
2662	interrupt-names = "error_irq\0irq";	2662	interrupt-names = "error_irq\0irq";
2663	clocks = <0x07 0xf7 0x00 0x07 0xf7 0x03 0x07 0xf7 0x00 0x07 0xf7 0x00 0x07 0xf7 0x04 0x07 0xf7 0x04>;	2663	clocks = <0x07 0xf7 0x00 0x07 0xf7 0x03 0x07 0xf7 0x00 0x07 0xf7 0x00 0x07 0xf7 0x04 0x07 0xf7 0x04>;
2664	clock-names = "sys_clk\0p_clk\0pixel_if0_clk\0pixel_if1_clk\0pixel_if2_clk\0pixel_if3_clk";	2664	clock-names = "sys_clk\0p_clk\0pixel_if0_clk\0pixel_if1_clk\0pixel_if2_clk\0pixel_if3_clk";
2665	phys = <0x5c>;	2665	phys = <0x5c>;
2666	phy-names = "dphy";	2666	phy-names = "dphy";
2667	phandle = <0x101>;	2667	phandle = <0x101>;
2668		2668
2669	ports {	2669	ports {
2670	#address-cells = <0x01>;	2670	#address-cells = <0x01>;
2671	#size-cells = <0x00>;	2671	#size-cells = <0x00>;
2672		2672
2673	port@0 {	2673	port@0 {
2674	reg = <0x00>;	2674	reg = <0x00>;
2675	status = "disabled";	2675	status = "disabled";
2676	phandle = <0x102>;	2676	phandle = <0x102>;
2677	};	2677	};
2678		2678
2679	port@1 {	2679	port@1 {
2680	reg = <0x01>;	2680	reg = <0x01>;
2681	status = "disabled";	2681	status = "disabled";
2682	phandle = <0x103>;	2682	phandle = <0x103>;
2683	};	2683	};
2684		2684
2685	port@2 {	2685	port@2 {
2686	reg = <0x02>;	2686	reg = <0x02>;
2687	status = "disabled";	2687	status = "disabled";
2688	phandle = <0x104>;	2688	phandle = <0x104>;
2689	};	2689	};
2690		2690
2691	port@3 {	2691	port@3 {
2692	reg = <0x03>;	2692	reg = <0x03>;
2693	status = "disabled";	2693	status = "disabled";
2694	phandle = <0x105>;	2694	phandle = <0x105>;
2695	};	2695	};
2696		2696
2697	port@4 {	2697	port@4 {
2698	reg = <0x04>;	2698	reg = <0x04>;
2699	status = "disabled";	2699	status = "disabled";
2700	phandle = <0x106>;	2700	phandle = <0x106>;
2701	};	2701	};
2702	};	2702	};
2703	};	2703	};
2704	};	2704	};
2705		2705
2706	ticsi2rx@30142000 {	2706	ticsi2rx@30142000 {
2707	compatible = "ti,j721e-csi2rx-shim";	2707	compatible = "ti,j721e-csi2rx-shim";
2708	reg = <0x00 0x30142000 0x00 0x1000>;	2708	reg = <0x00 0x30142000 0x00 0x1000>;
2709	ranges;	2709	ranges;
2710	#address-cells = <0x02>;	2710	#address-cells = <0x02>;
2711	#size-cells = <0x02>;	2711	#size-cells = <0x02>;
2712	power-domains = <0x09 0xf8 0x01>;	2712	power-domains = <0x09 0xf8 0x01>;
2713	dmas = <0x24 0x00 0x5200 0x00 0x24 0x00 0x5201 0x00 0x24 0x00 0x5202 0x00 0x24 0x00 0x5203 0x00>;	2713	dmas = <0x24 0x00 0x5200 0x00 0x24 0x00 0x5201 0x00 0x24 0x00 0x5202 0x00 0x24 0x00 0x5203 0x00>;
2714	dma-names = "rx0\0rx1\0rx2\0rx3";	2714	dma-names = "rx0\0rx1\0rx2\0rx3";
2715	status = "disabled";	2715	status = "disabled";
2716	phandle = <0x107>;	2716	phandle = <0x107>;
2717		2717
2718	csi-bridge@30141000 {	2718	csi-bridge@30141000 {
2719	compatible = "ti,j721e-csi2rx\0cdns,csi2rx";	2719	compatible = "ti,j721e-csi2rx\0cdns,csi2rx";
2720	reg = <0x00 0x30141000 0x00 0x1000>;	2720	reg = <0x00 0x30141000 0x00 0x1000>;
2721	interrupts = <0x00 0xbb 0x04 0x00 0xc8 0x04>;	2721	interrupts = <0x00 0xbb 0x04 0x00 0xc8 0x04>;
2722	interrupt-names = "error_irq\0irq";	2722	interrupt-names = "error_irq\0irq";
2723	clocks = <0x07 0xf8 0x00 0x07 0xf8 0x03 0x07 0xf8 0x00 0x07 0xf8 0x00 0x07 0xf8 0x04 0x07 0xf8 0x04>;	2723	clocks = <0x07 0xf8 0x00 0x07 0xf8 0x03 0x07 0xf8 0x00 0x07 0xf8 0x00 0x07 0xf8 0x04 0x07 0xf8 0x04>;
2724	clock-names = "sys_clk\0p_clk\0pixel_if0_clk\0pixel_if1_clk\0pixel_if2_clk\0pixel_if3_clk";	2724	clock-names = "sys_clk\0p_clk\0pixel_if0_clk\0pixel_if1_clk\0pixel_if2_clk\0pixel_if3_clk";
2725	phys = <0x5d>;	2725	phys = <0x5d>;
2726	phy-names = "dphy";	2726	phy-names = "dphy";
2727	phandle = <0x108>;	2727	phandle = <0x108>;
2728		2728
2729	ports {	2729	ports {
2730	#address-cells = <0x01>;	2730	#address-cells = <0x01>;
2731	#size-cells = <0x00>;	2731	#size-cells = <0x00>;
2732		2732
2733	port@0 {	2733	port@0 {
2734	reg = <0x00>;	2734	reg = <0x00>;
2735	status = "disabled";	2735	status = "disabled";
2736	phandle = <0x109>;	2736	phandle = <0x109>;
2737	};	2737	};
2738		2738
2739	port@1 {	2739	port@1 {
2740	reg = <0x01>;	2740	reg = <0x01>;
2741	status = "disabled";	2741	status = "disabled";
2742	phandle = <0x10a>;	2742	phandle = <0x10a>;
2743	};	2743	};
2744		2744
2745	port@2 {	2745	port@2 {
2746	reg = <0x02>;	2746	reg = <0x02>;
2747	status = "disabled";	2747	status = "disabled";
2748	phandle = <0x10b>;	2748	phandle = <0x10b>;
2749	};	2749	};
2750		2750
2751	port@3 {	2751	port@3 {
2752	reg = <0x03>;	2752	reg = <0x03>;
2753	status = "disabled";	2753	status = "disabled";
2754	phandle = <0x10c>;	2754	phandle = <0x10c>;
2755	};	2755	};
2756		2756
2757	port@4 {	2757	port@4 {
2758	reg = <0x04>;	2758	reg = <0x04>;
2759	status = "disabled";	2759	status = "disabled";
2760	phandle = <0x10d>;	2760	phandle = <0x10d>;
2761	};	2761	};
2762	};	2762	};
2763	};	2763	};
2764	};	2764	};
2765		2765
2766	ticsi2rx@30162000 {	2766	ticsi2rx@30162000 {
2767	compatible = "ti,j721e-csi2rx-shim";	2767	compatible = "ti,j721e-csi2rx-shim";
2768	reg = <0x00 0x30162000 0x00 0x1000>;	2768	reg = <0x00 0x30162000 0x00 0x1000>;
2769	ranges;	2769	ranges;
2770	#address-cells = <0x02>;	2770	#address-cells = <0x02>;
2771	#size-cells = <0x02>;	2771	#size-cells = <0x02>;
2772	dmas = <0x24 0x00 0x5300 0x00 0x24 0x00 0x5301 0x00 0x24 0x00 0x5302 0x00 0x24 0x00 0x5303 0x00>;	2772	dmas = <0x24 0x00 0x5300 0x00 0x24 0x00 0x5301 0x00 0x24 0x00 0x5302 0x00 0x24 0x00 0x5303 0x00>;
2773	dma-names = "rx0\0rx1\0rx2\0rx3";	2773	dma-names = "rx0\0rx1\0rx2\0rx3";
2774	power-domains = <0x09 0xf9 0x01>;	2774	power-domains = <0x09 0xf9 0x01>;
2775	status = "disabled";	2775	status = "disabled";
2776	phandle = <0x10e>;	2776	phandle = <0x10e>;
2777		2777
2778	csi-bridge@30161000 {	2778	csi-bridge@30161000 {
2779	compatible = "ti,j721e-csi2rx\0cdns,csi2rx";	2779	compatible = "ti,j721e-csi2rx\0cdns,csi2rx";
2780	reg = <0x00 0x30161000 0x00 0x1000>;	2780	reg = <0x00 0x30161000 0x00 0x1000>;
2781	interrupts = <0x00 0xd9 0x04 0x00 0xda 0x04>;	2781	interrupts = <0x00 0xd9 0x04 0x00 0xda 0x04>;
2782	interrupt-names = "error_irq\0irq";	2782	interrupt-names = "error_irq\0irq";
2783	clocks = <0x07 0xf9 0x00 0x07 0xf9 0x03 0x07 0xf9 0x00 0x07 0xf9 0x00 0x07 0xf9 0x04 0x07 0xf9 0x04>;	2783	clocks = <0x07 0xf9 0x00 0x07 0xf9 0x03 0x07 0xf9 0x00 0x07 0xf9 0x00 0x07 0xf9 0x04 0x07 0xf9 0x04>;
2784	clock-names = "sys_clk\0p_clk\0pixel_if0_clk\0pixel_if1_clk\0pixel_if2_clk\0pixel_if3_clk";	2784	clock-names = "sys_clk\0p_clk\0pixel_if0_clk\0pixel_if1_clk\0pixel_if2_clk\0pixel_if3_clk";
2785	phys = <0x5e>;	2785	phys = <0x5e>;
2786	phy-names = "dphy";	2786	phy-names = "dphy";
2787	phandle = <0x10f>;	2787	phandle = <0x10f>;
2788		2788
2789	ports {	2789	ports {
2790	#address-cells = <0x01>;	2790	#address-cells = <0x01>;
2791	#size-cells = <0x00>;	2791	#size-cells = <0x00>;
2792		2792
2793	port@0 {	2793	port@0 {
2794	reg = <0x00>;	2794	reg = <0x00>;
2795	status = "disabled";	2795	status = "disabled";
2796	phandle = <0x110>;	2796	phandle = <0x110>;
2797	};	2797	};
2798		2798
2799	port@1 {	2799	port@1 {
2800	reg = <0x01>;	2800	reg = <0x01>;
2801	status = "disabled";	2801	status = "disabled";
2802	phandle = <0x111>;	2802	phandle = <0x111>;
2803	};	2803	};
2804		2804
2805	port@2 {	2805	port@2 {
2806	reg = <0x02>;	2806	reg = <0x02>;
2807	status = "disabled";	2807	status = "disabled";
2808	phandle = <0x112>;	2808	phandle = <0x112>;
2809	};	2809	};
2810		2810
2811	port@3 {	2811	port@3 {
2812	reg = <0x03>;	2812	reg = <0x03>;
2813	status = "disabled";	2813	status = "disabled";
2814	phandle = <0x113>;	2814	phandle = <0x113>;
2815	};	2815	};
2816		2816
2817	port@4 {	2817	port@4 {
2818	reg = <0x04>;	2818	reg = <0x04>;
2819	status = "disabled";	2819	status = "disabled";
2820	phandle = <0x114>;	2820	phandle = <0x114>;
2821	};	2821	};
2822	};	2822	};
2823	};	2823	};
2824	};	2824	};
2825		2825
2826	phy@30130000 {	2826	phy@30130000 {
2827	compatible = "cdns,dphy-rx";	2827	compatible = "cdns,dphy-rx";
2828	reg = <0x00 0x30130000 0x00 0x1100>;	2828	reg = <0x00 0x30130000 0x00 0x1100>;
2829	#phy-cells = <0x00>;	2829	#phy-cells = <0x00>;
2830	power-domains = <0x09 0xfb 0x01>;	2830	power-domains = <0x09 0xfb 0x01>;
2831	status = "disabled";	2831	status = "disabled";
2832	phandle = <0x5c>;	2832	phandle = <0x5c>;
2833	};	2833	};
2834		2834
2835	phy@30150000 {	2835	phy@30150000 {
2836	compatible = "cdns,dphy-rx";	2836	compatible = "cdns,dphy-rx";
2837	reg = <0x00 0x30150000 0x00 0x1100>;	2837	reg = <0x00 0x30150000 0x00 0x1100>;
2838	#phy-cells = <0x00>;	2838	#phy-cells = <0x00>;
2839	power-domains = <0x09 0xfc 0x01>;	2839	power-domains = <0x09 0xfc 0x01>;
2840	status = "disabled";	2840	status = "disabled";
2841	phandle = <0x5d>;	2841	phandle = <0x5d>;
2842	};	2842	};
2843		2843
2844	phy@30170000 {	2844	phy@30170000 {
2845	compatible = "cdns,dphy-rx";	2845	compatible = "cdns,dphy-rx";
2846	reg = <0x00 0x30170000 0x00 0x1100>;	2846	reg = <0x00 0x30170000 0x00 0x1100>;
2847	#phy-cells = <0x00>;	2847	#phy-cells = <0x00>;
2848	power-domains = <0x09 0xfd 0x01>;	2848	power-domains = <0x09 0xfd 0x01>;
2849	status = "disabled";	2849	status = "disabled";
2850	phandle = <0x5e>;	2850	phandle = <0x5e>;
2851	};	2851	};
2852		2852
2853	r5fss@78400000 {	2853	r5fss@78400000 {
2854	compatible = "ti,am62-r5fss";	2854	compatible = "ti,am62-r5fss";
2855	#address-cells = <0x01>;	2855	#address-cells = <0x01>;
2856	#size-cells = <0x01>;	2856	#size-cells = <0x01>;
2857	ranges = <0x78400000 0x00 0x78400000 0x8000 0x78500000 0x00 0x78500000 0x8000>;	2857	ranges = <0x78400000 0x00 0x78400000 0x8000 0x78500000 0x00 0x78500000 0x8000>;
2858	power-domains = <0x09 0x105 0x01>;	2858	power-domains = <0x09 0x105 0x01>;
2859	status = "okay";	2859	status = "okay";
2860	phandle = <0x115>;	2860	phandle = <0x115>;
2861		2861
2862	r5f@78400000 {	2862	r5f@78400000 {
2863	compatible = "ti,am62-r5f";	2863	compatible = "ti,am62-r5f";
2864	reg = <0x78400000 0x8000 0x78500000 0x8000>;	2864	reg = <0x78400000 0x8000 0x78500000 0x8000>;
2865	reg-names = "atcm\0btcm";	2865	reg-names = "atcm\0btcm";
2866	resets = <0x12 0x106 0x01>;	2866	resets = <0x12 0x106 0x01>;
2867	firmware-name = "j722s-main-r5f0_0-fw";	2867	firmware-name = "j722s-main-r5f0_0-fw";
2868	ti,sci = <0x0b>;	2868	ti,sci = <0x0b>;
2869	ti,sci-dev-id = <0x106>;	2869	ti,sci-dev-id = <0x106>;
2870	ti,sci-proc-ids = <0x04 0xff>;	2870	ti,sci-proc-ids = <0x04 0xff>;
2871	ti,atcm-enable = <0x01>;	2871	ti,atcm-enable = <0x01>;
2872	ti,btcm-enable = <0x01>;	2872	ti,btcm-enable = <0x01>;
2873	ti,loczrama = <0x01>;	2873	ti,loczrama = <0x01>;
2874	mboxes = <0x5f 0x60>;	2874	mboxes = <0x5f 0x60>;
2875	memory-region = <0x61 0x62>;	2875	memory-region = <0x61 0x62>;
2876	phandle = <0x116>;	2876	phandle = <0x116>;
2877	};	2877	};
2878	};	2878	};
2879		2879
2880	dsp@7e000000 {	2880	dsp@7e000000 {
2881	compatible = "ti,j722s-c7xv-dsp";	2881	compatible = "ti,j722s-c7xv-dsp";
2882	reg = <0x00 0x7e000000 0x00 0x200000>;	2882	reg = <0x00 0x7e000000 0x00 0x200000>;
2883	reg-names = "l2sram";	2883	reg-names = "l2sram";
2884	resets = <0x12 0xd0 0x01>;	2884	resets = <0x12 0xd0 0x01>;
2885	firmware-name = "j722s-c71_0-fw";	2885	firmware-name = "j722s-c71_0-fw";
2886	ti,sci = <0x0b>;	2886	ti,sci = <0x0b>;
2887	ti,sci-dev-id = <0xd0>;	2887	ti,sci-dev-id = <0xd0>;
2888	ti,sci-proc-ids = <0x30 0xff>;	2888	ti,sci-proc-ids = <0x30 0xff>;
2889	status = "okay";	2889	status = "okay";
2890	mboxes = <0x63 0x64>;	2890	mboxes = <0x63 0x64>;
2891	memory-region = <0x65 0x66>;	2891	memory-region = <0x65 0x66>;
2892	phandle = <0x117>;	2892	phandle = <0x117>;
2893	};	2893	};
2894		2894
2895	dsp@7e200000 {	2895	dsp@7e200000 {
2896	compatible = "ti,j722s-c7xv-dsp";	2896	compatible = "ti,j722s-c7xv-dsp";
2897	reg = <0x00 0x7e200000 0x00 0x200000>;	2897	reg = <0x00 0x7e200000 0x00 0x200000>;
2898	reg-names = "l2sram";	2898	reg-names = "l2sram";
2899	resets = <0x12 0x10c 0x01>;	2899	resets = <0x12 0x10c 0x01>;
2900	firmware-name = "j722s-c71_1-fw";	2900	firmware-name = "j722s-c71_1-fw";
2901	ti,sci = <0x0b>;	2901	ti,sci = <0x0b>;
2902	ti,sci-dev-id = <0x10c>;	2902	ti,sci-dev-id = <0x10c>;
2903	ti,sci-proc-ids = <0x31 0xff>;	2903	ti,sci-proc-ids = <0x31 0xff>;
2904	status = "okay";	2904	status = "okay";
2905	mboxes = <0x5f 0x67>;	2905	mboxes = <0x5f 0x67>;
2906	memory-region = <0x68 0x69>;	2906	memory-region = <0x68 0x69>;
2907	phandle = <0x118>;	2907	phandle = <0x118>;
2908	};	2908	};
2909		2909
2910	e5010@fd20000 {	2910	e5010@fd20000 {
2911	compatible = "img,e5010-jpeg-enc";	2911	compatible = "img,e5010-jpeg-enc";
2912	reg = <0x00 0xfd20000 0x00 0x100 0x00 0xfd20200 0x00 0x200>;	2912	reg = <0x00 0xfd20000 0x00 0x100 0x00 0xfd20200 0x00 0x200>;
2913	reg-names = "core\0mmu";	2913	reg-names = "core\0mmu";
2914	clocks = <0x07 0xc9 0x00>;	2914	clocks = <0x07 0xc9 0x00>;
2915	clock-names = "core_clk";	2915	clock-names = "core_clk";
2916	power-domains = <0x09 0xc9 0x01>;	2916	power-domains = <0x09 0xc9 0x01>;
2917	interrupts = <0x00 0x62 0x04>;	2917	interrupts = <0x00 0x62 0x04>;
2918	phandle = <0x119>;	2918	phandle = <0x119>;
2919	};	2919	};
2920	};	2920	};
2921		2921
2922	clock-divider-oldi-dss0 {	2922	clock-divider-oldi-dss0 {
2923	compatible = "fixed-factor-clock";	2923	compatible = "fixed-factor-clock";
2924	clocks = <0x07 0xba 0x00>;	2924	clocks = <0x07 0xba 0x00>;
2925	#clock-cells = <0x00>;	2925	#clock-cells = <0x00>;
2926	clock-div = <0x07>;	2926	clock-div = <0x07>;
2927	clock-mult = <0x01>;	2927	clock-mult = <0x01>;
2928	phandle = <0x48>;	2928	phandle = <0x48>;
2929	};	2929	};
2930		2930
2931	clock-divider-oldi-dss1 {	2931	clock-divider-oldi-dss1 {
2932	compatible = "fixed-factor-clock";	2932	compatible = "fixed-factor-clock";
2933	clocks = <0x07 0xe8 0x00>;	2933	clocks = <0x07 0xe8 0x00>;
2934	#clock-cells = <0x00>;	2934	#clock-cells = <0x00>;
2935	clock-div = <0x07>;	2935	clock-div = <0x07>;
2936	clock-mult = <0x01>;	2936	clock-mult = <0x01>;
2937	phandle = <0x11a>;	2937	phandle = <0x11a>;
2938	};	2938	};
2939		2939
2940	thermal-zones {	2940	thermal-zones {
2941	phandle = <0x11b>;	2941	phandle = <0x11b>;
2942		2942
2943	main0-thermal {	2943	main0-thermal {
2944	polling-delay-passive = <0xfa>;	2944	polling-delay-passive = <0xfa>;
2945	polling-delay = <0x1f4>;	2945	polling-delay = <0x1f4>;
2946	thermal-sensors = <0x6a 0x00>;	2946	thermal-sensors = <0x6a 0x00>;
2947	phandle = <0x11c>;	2947	phandle = <0x11c>;
2948		2948
2949	trips {	2949	trips {
2950		2950
2951	main0-crit {	2951	main0-crit {
2952	temperature = <0x1e848>;	2952	temperature = <0x1e848>;
2953	hysteresis = <0x7d0>;	2953	hysteresis = <0x7d0>;
2954	type = "critical";	2954	type = "critical";
2955	phandle = <0x11d>;	2955	phandle = <0x11d>;
2956	};	2956	};
2957	};	2957	};
2958	};	2958	};
2959		2959
2960	main1-thermal {	2960	main1-thermal {
2961	polling-delay-passive = <0xfa>;	2961	polling-delay-passive = <0xfa>;
2962	polling-delay = <0x1f4>;	2962	polling-delay = <0x1f4>;
2963	thermal-sensors = <0x6a 0x01>;	2963	thermal-sensors = <0x6a 0x01>;
2964	phandle = <0x11e>;	2964	phandle = <0x11e>;
2965		2965
2966	trips {	2966	trips {
2967		2967
2968	main1-crit {	2968	main1-crit {
2969	temperature = <0x1e848>;	2969	temperature = <0x1e848>;
2970	hysteresis = <0x7d0>;	2970	hysteresis = <0x7d0>;
2971	type = "critical";	2971	type = "critical";
2972	phandle = <0x11f>;	2972	phandle = <0x11f>;
2973	};	2973	};
2974	};	2974	};
2975	};	2975	};
2976		2976
2977	main2-thermal {	2977	main2-thermal {
2978	polling-delay-passive = <0xfa>;	2978	polling-delay-passive = <0xfa>;
2979	polling-delay = <0x1f4>;	2979	polling-delay = <0x1f4>;
2980	thermal-sensors = <0x6a 0x02>;	2980	thermal-sensors = <0x6a 0x02>;
2981	phandle = <0x120>;	2981	phandle = <0x120>;
2982		2982
2983	trips {	2983	trips {
2984		2984
2985	main2-crit {	2985	main2-crit {
2986	temperature = <0x1e848>;	2986	temperature = <0x1e848>;
2987	hysteresis = <0x7d0>;	2987	hysteresis = <0x7d0>;
2988	type = "critical";	2988	type = "critical";
2989	phandle = <0x121>;	2989	phandle = <0x121>;
2990	};	2990	};
2991	};	2991	};
2992	};	2992	};
2993	};	2993	};
2994		2994
2995	clk-0 {	2995	clk-0 {
2996	compatible = "fixed-clock";	2996	compatible = "fixed-clock";
2997	#clock-cells = <0x00>;	2997	#clock-cells = <0x00>;
2998	clock-frequency = <0x00>;	2998	clock-frequency = <0x00>;
2999	phandle = <0x52>;	2999	phandle = <0x52>;
3000	};	3000	};
3001		3001
3002	aliases {	3002	aliases {
3003	serial0 = "/bus@f0000/bus@b00000/target-module@2b300050/serial@0";	3003	serial0 = "/bus@f0000/bus@b00000/target-module@2b300050/serial@0";
3004	serial2 = "/bus@f0000/serial@2800000";	3004	serial2 = "/bus@f0000/serial@2800000";
3005	serial3 = "/bus@f0000/serial@2850000";	3005	serial3 = "/bus@f0000/serial@2850000";
3006	mmc0 = "/bus@f0000/mmc@fa10000";	3006	mmc0 = "/bus@f0000/mmc@fa10000";
3007	mmc1 = "/bus@f0000/mmc@fa00000";	3007	mmc1 = "/bus@f0000/mmc@fa00000";
3008	};	3008	};
3009		3009
3010	chosen {	3010	chosen {
3011	stdout-path = "/bus@f0000/serial@2800000";	3011	stdout-path = "/bus@f0000/serial@2800000";
3012	};	3012	};
3013		3013
3014	memory@80000000 {	3014	memory@80000000 {
3015	reg = <0x00 0x80000000 0x00 0x80000000 0x08 0x80000000 0x01 0x80000000>;	3015	reg = <0x00 0x80000000 0x00 0x80000000 0x08 0x80000000 0x01 0x80000000>;
3016	device_type = "memory";	3016	device_type = "memory";
3017	bootph-pre-ram;	3017	bootph-pre-ram;
3018	};	3018	};
3019		3019
3020	reserved-memory {	3020	reserved-memory {
3021	#address-cells = <0x02>;	3021	#address-cells = <0x02>;
3022	#size-cells = <0x02>;	3022	#size-cells = <0x02>;
3023	ranges;	3023	ranges;
3024	phandle = <0x122>;	3024	phandle = <0x122>;
3025		3025
3026	linux,cma {	3026	linux,cma {
3027	compatible = "shared-dma-pool";	3027	compatible = "shared-dma-pool";
3028	reusable;	3028	reusable;
3029	size = <0x00 0x38000000>;	3029	size = <0x00 0x38000000>;
3030	linux,cma-default;	3030	linux,cma-default;
3031	};	3031	};
3032		3032
3033	tfa@9e780000 {	3033	tfa@9e780000 {
3034	reg = <0x00 0x9e780000 0x00 0x80000>;	3034	reg = <0x00 0x9e780000 0x00 0x80000>;
3035	no-map;	3035	no-map;
3036	phandle = <0x123>;	3036	phandle = <0x123>;
3037	};	3037	};
3038		3038
3039	optee@9e800000 {	3039	optee@9e800000 {
3040	reg = <0x00 0x9e800000 0x00 0x1800000>;	3040	reg = <0x00 0x9e800000 0x00 0x1800000>;
3041	no-map;	3041	no-map;
3042	phandle = <0x124>;	3042	phandle = <0x124>;
3043	};	3043	};
3044		3044
3045	r5f-dma-memory@a0000000 {	3045	r5f-dma-memory@a0000000 {
3046	compatible = "shared-dma-pool";	3046	compatible = "shared-dma-pool";
3047	reg = <0x00 0xa0000000 0x00 0x100000>;	3047	reg = <0x00 0xa0000000 0x00 0x100000>;
3048	no-map;	3048	no-map;
3049	phandle = <0x1f>;	3049	phandle = <0x1f>;
3050	};	3050	};
3051		3051
3052	r5f-memory@a0100000 {	3052	r5f-memory@a0100000 {
3053	compatible = "shared-dma-pool";	3053	compatible = "shared-dma-pool";
3054	reg = <0x00 0xa0100000 0x00 0xf00000>;	3054	reg = <0x00 0xa0100000 0x00 0xf00000>;
3055	no-map;	3055	no-map;
3056	phandle = <0x20>;	3056	phandle = <0x20>;
3057	};	3057	};
3058		3058
3059	mcu-r5fss-dma-memory-region@a1000000 {	3059	mcu-r5fss-dma-memory-region@a1000000 {
3060	compatible = "shared-dma-pool";	3060	compatible = "shared-dma-pool";
3061	reg = <0x00 0xa1000000 0x00 0x100000>;	3061	reg = <0x00 0xa1000000 0x00 0x100000>;
3062	no-map;	3062	no-map;
3063	phandle = <0x16>;	3063	phandle = <0x16>;
3064	};	3064	};
3065		3065
3066	mcu-r5fss-memory-region@a1100000 {	3066	mcu-r5fss-memory-region@a1100000 {
3067	compatible = "shared-dma-pool";	3067	compatible = "shared-dma-pool";
3068	reg = <0x00 0xa1100000 0x00 0xf00000>;	3068	reg = <0x00 0xa1100000 0x00 0xf00000>;
3069	no-map;	3069	no-map;
3070	phandle = <0x17>;	3070	phandle = <0x17>;
3071	};	3071	};
3072		3072
3073	main-r5fss-dma-memory-region@a2000000 {	3073	main-r5fss-dma-memory-region@a2000000 {
3074	compatible = "shared-dma-pool";	3074	compatible = "shared-dma-pool";
3075	reg = <0x00 0xa2000000 0x00 0x100000>;	3075	reg = <0x00 0xa2000000 0x00 0x100000>;
3076	no-map;	3076	no-map;
3077	phandle = <0x61>;	3077	phandle = <0x61>;
3078	};	3078	};
3079		3079
3080	main-r5fss-memory-region@a2100000 {	3080	main-r5fss-memory-region@a2100000 {
3081	compatible = "shared-dma-pool";	3081	compatible = "shared-dma-pool";
3082	reg = <0x00 0xa2100000 0x00 0xf00000>;	3082	reg = <0x00 0xa2100000 0x00 0xf00000>;
3083	no-map;	3083	no-map;
3084	phandle = <0x62>;	3084	phandle = <0x62>;
3085	};	3085	};
3086		3086
3087	c7x-dma-memory@a3000000 {	3087	c7x-dma-memory@a3000000 {
3088	compatible = "shared-dma-pool";	3088	compatible = "shared-dma-pool";
3089	reg = <0x00 0xa3000000 0x00 0x100000>;	3089	reg = <0x00 0xa3000000 0x00 0x100000>;
3090	no-map;	3090	no-map;
3091	phandle = <0x65>;	3091	phandle = <0x65>;
3092	};	3092	};
3093		3093
3094	c7x-memory@a3100000 {	3094	c7x-memory@a3100000 {
3095	compatible = "shared-dma-pool";	3095	compatible = "shared-dma-pool";
3096	reg = <0x00 0xa3100000 0x00 0xf00000>;	3096	reg = <0x00 0xa3100000 0x00 0xf00000>;
3097	no-map;	3097	no-map;
3098	phandle = <0x66>;	3098	phandle = <0x66>;
3099	};	3099	};
3100		3100
3101	c7x-dma-memory@a4000000 {	3101	c7x-dma-memory@a4000000 {
3102	compatible = "shared-dma-pool";	3102	compatible = "shared-dma-pool";
3103	reg = <0x00 0xa4000000 0x00 0x100000>;	3103	reg = <0x00 0xa4000000 0x00 0x100000>;
3104	no-map;	3104	no-map;
3105	phandle = <0x68>;	3105	phandle = <0x68>;
3106	};	3106	};
3107		3107
3108	c7x-memory@a4100000 {	3108	c7x-memory@a4100000 {
3109	compatible = "shared-dma-pool";	3109	compatible = "shared-dma-pool";
3110	reg = <0x00 0xa4100000 0x00 0xf00000>;	3110	reg = <0x00 0xa4100000 0x00 0xf00000>;
3111	no-map;	3111	no-map;
3112	phandle = <0x69>;	3112	phandle = <0x69>;
3113	};	3113	};
3114		3114
3115	ipc-memories@a5000000 {	3115	ipc-memories@a5000000 {
3116	reg = <0x00 0xa5000000 0x00 0x1c00000>;	3116	reg = <0x00 0xa5000000 0x00 0x1c00000>;
3117	alignment = <0x1000>;	3117	alignment = <0x1000>;
3118	no-map;	3118	no-map;
3119	phandle = <0x125>;	3119	phandle = <0x125>;
3120	};	3120	};
3121	};	3121	};
3122		3122
3123	regulator-0 {	3123	regulator-0 {
3124	compatible = "regulator-fixed";	3124	compatible = "regulator-fixed";
3125	regulator-name = "vmain_pd";	3125	regulator-name = "vmain_pd";
3126	regulator-min-microvolt = <0x4c4b40>;	3126	regulator-min-microvolt = <0x4c4b40>;
3127	regulator-max-microvolt = <0x4c4b40>;	3127	regulator-max-microvolt = <0x4c4b40>;
3128	regulator-always-on;	3128	regulator-always-on;
3129	regulator-boot-on;	3129	regulator-boot-on;
3130	bootph-all;	3130	bootph-all;
3131	phandle = <0x6b>;	3131	phandle = <0x6b>;
3132	};	3132	};
3133		3133
3134	regulator-vsys5v0 {	3134	regulator-vsys5v0 {
3135	compatible = "regulator-fixed";	3135	compatible = "regulator-fixed";
3136	regulator-name = "vsys_5v0";	3136	regulator-name = "vsys_5v0";
3137	regulator-min-microvolt = <0x4c4b40>;	3137	regulator-min-microvolt = <0x4c4b40>;
3138	regulator-max-microvolt = <0x4c4b40>;	3138	regulator-max-microvolt = <0x4c4b40>;
3139	vin-supply = <0x6b>;	3139	vin-supply = <0x6b>;
3140	regulator-always-on;	3140	regulator-always-on;
3141	regulator-boot-on;	3141	regulator-boot-on;
3142	phandle = <0x6d>;	3142	phandle = <0x6d>;
3143	};	3143	};
3144		3144
3145	regulator-mmc1 {	3145	regulator-mmc1 {
3146	compatible = "regulator-fixed";	3146	compatible = "regulator-fixed";
3147	regulator-name = "vdd_mmc1";	3147	regulator-name = "vdd_mmc1";
3148	regulator-min-microvolt = <0x325aa0>;	3148	regulator-min-microvolt = <0x325aa0>;
3149	regulator-max-microvolt = <0x325aa0>;	3149	regulator-max-microvolt = <0x325aa0>;
3150	regulator-boot-on;	3150	regulator-boot-on;
3151	enable-active-high;	3151	enable-active-high;
3152	gpio = <0x58 0x0f 0x00>;	3152	gpio = <0x58 0x0f 0x00>;
3153	bootph-all;	3153	bootph-all;
3154	phandle = <0x39>;	3154	phandle = <0x39>;
3155	};	3155	};
3156		3156
3157	regulator-TLV71033 {	3157	regulator-TLV71033 {
3158	compatible = "regulator-gpio";	3158	compatible = "regulator-gpio";
3159	regulator-name = "tlv71033";	3159	regulator-name = "tlv71033";
3160	pinctrl-names = "default";	3160	pinctrl-names = "default";
3161	pinctrl-0 = <0x6c>;	3161	pinctrl-0 = <0x6c>;
3162	regulator-min-microvolt = <0x1b7740>;	3162	regulator-min-microvolt = <0x1b7740>;
3163	regulator-max-microvolt = <0x325aa0>;	3163	regulator-max-microvolt = <0x325aa0>;
3164	regulator-boot-on;	3164	regulator-boot-on;
3165	vin-supply = <0x6d>;	3165	vin-supply = <0x6d>;
3166	gpios = <0x1b 0x46 0x00>;	3166	gpios = <0x1b 0x46 0x00>;
3167	states = <0x1b7740 0x00 0x325aa0 0x01>;	3167	states = <0x1b7740 0x00 0x325aa0 0x01>;
3168	phandle = <0x3a>;	3168	phandle = <0x3a>;
3169	};	3169	};
3170		3170
3171	regulator-vsys-io-3v3 {	3171	regulator-vsys-io-3v3 {
3172	compatible = "regulator-fixed";	3172	compatible = "regulator-fixed";
3173	regulator-name = "vsys_io_3v3";	3173	regulator-name = "vsys_io_3v3";
3174	regulator-min-microvolt = <0x325aa0>;	3174	regulator-min-microvolt = <0x325aa0>;
3175	regulator-max-microvolt = <0x325aa0>;	3175	regulator-max-microvolt = <0x325aa0>;
3176	regulator-always-on;	3176	regulator-always-on;
3177	regulator-boot-on;	3177	regulator-boot-on;
3178	phandle = <0x1c>;	3178	phandle = <0x1c>;
3179	};	3179	};
3180		3180
3181	regulator-vsys-io-1v8 {	3181	regulator-vsys-io-1v8 {
3182	compatible = "regulator-fixed";	3182	compatible = "regulator-fixed";
3183	regulator-name = "vsys_io_1v8";	3183	regulator-name = "vsys_io_1v8";
3184	regulator-min-microvolt = <0x1b7740>;	3184	regulator-min-microvolt = <0x1b7740>;
3185	regulator-max-microvolt = <0x1b7740>;	3185	regulator-max-microvolt = <0x1b7740>;
3186	regulator-always-on;	3186	regulator-always-on;
3187	regulator-boot-on;	3187	regulator-boot-on;
3188	phandle = <0x2c>;	3188	phandle = <0x2c>;
3189	};	3189	};
3190		3190
3191	regulator-vsys-io-1v2 {	3191	regulator-vsys-io-1v2 {
3192	compatible = "regulator-fixed";	3192	compatible = "regulator-fixed";
3193	regulator-name = "vsys_io_1v2";	3193	regulator-name = "vsys_io_1v2";
3194	regulator-min-microvolt = <0x124f80>;	3194	regulator-min-microvolt = <0x124f80>;
3195	regulator-max-microvolt = <0x124f80>;	3195	regulator-max-microvolt = <0x124f80>;
3196	regulator-always-on;	3196	regulator-always-on;
3197	regulator-boot-on;	3197	regulator-boot-on;
3198	phandle = <0x33>;	3198	phandle = <0x33>;
3199	};	3199	};
3200		3200
3201	sound {	3201	sound {
3202	compatible = "simple-audio-card";	3202	compatible = "simple-audio-card";
3203	simple-audio-card,name = "J722S-EVM";	3203	simple-audio-card,name = "J722S-EVM";
3204	simple-audio-card,widgets = "Headphone\0Headphone Jack\0Line\0Line In\0Microphone\0Microphone Jack";	3204	simple-audio-card,widgets = "Headphone\0Headphone Jack\0Line\0Line In\0Microphone\0Microphone Jack";
3205	simple-audio-card,routing = "Headphone Jack\0HPLOUT\0Headphone Jack\0HPROUT\0LINE1L\0Line In\0LINE1R\0Line In\0MIC3R\0Microphone Jack\0Microphone Jack\0Mic Bias";	3205	simple-audio-card,routing = "Headphone Jack\0HPLOUT\0Headphone Jack\0HPROUT\0LINE1L\0Line In\0LINE1R\0Line In\0MIC3R\0Microphone Jack\0Microphone Jack\0Mic Bias";
3206	simple-audio-card,format = "dsp_b";	3206	simple-audio-card,format = "dsp_b";
3207	simple-audio-card,bitclock-master = <0x6e>;	3207	simple-audio-card,bitclock-master = <0x6e>;
3208	simple-audio-card,frame-master = <0x6e>;	3208	simple-audio-card,frame-master = <0x6e>;
3209	simple-audio-card,bitclock-inversion;	3209	simple-audio-card,bitclock-inversion;
3210	phandle = <0x126>;	3210	phandle = <0x126>;
3211		3211
3212	simple-audio-card,cpu {	3212	simple-audio-card,cpu {
3213	sound-dai = <0x6f>;	3213	sound-dai = <0x6f>;
3214	};	3214	};
3215		3215
3216	simple-audio-card,codec {	3216	simple-audio-card,codec {
3217	sound-dai = <0x70>;	3217	sound-dai = <0x70>;
3218	clocks = <0x71>;	3218	clocks = <0x71>;
3219	phandle = <0x6e>;	3219	phandle = <0x6e>;
3220	};	3220	};
3221	};	3221	};
3222		3222
3223	can-phy0 {	3223	can-phy0 {
3224	compatible = "ti,tcan1042";	3224	compatible = "ti,tcan1042";
3225	#phy-cells = <0x00>;	3225	#phy-cells = <0x00>;
3226	max-bitrate = <0x4c4b40>;	3226	max-bitrate = <0x4c4b40>;
3227	pinctrl-names = "default";	3227	pinctrl-names = "default";
3228	pinctrl-0 = <0x72>;	3228	pinctrl-0 = <0x72>;
3229	standby-gpios = <0x73 0x0c 0x00>;	3229	standby-gpios = <0x73 0x0c 0x00>;
3230	phandle = <0x0f>;	3230	phandle = <0x0f>;
3231	};	3231	};
3232		3232
3233	can-phy1 {	3233	can-phy1 {
3234	compatible = "ti,tcan1042";	3234	compatible = "ti,tcan1042";
3235	#phy-cells = <0x00>;	3235	#phy-cells = <0x00>;
3236	max-bitrate = <0x4c4b40>;	3236	max-bitrate = <0x4c4b40>;
3237	phandle = <0x11>;	3237	phandle = <0x11>;
3238	};	3238	};
3239		3239
3240	can-phy2 {	3240	can-phy2 {
3241	compatible = "ti,tcan1042";	3241	compatible = "ti,tcan1042";
3242	#phy-cells = <0x00>;	3242	#phy-cells = <0x00>;
3243	max-bitrate = <0x4c4b40>;	3243	max-bitrate = <0x4c4b40>;
3244	standby-gpios = <0x58 0x11 0x00>;	3244	standby-gpios = <0x58 0x11 0x00>;
3245	phandle = <0x44>;	3245	phandle = <0x44>;
.		3246	status = "disabled";
3246	};	3247	};
3247		3248
3248	connector-hdmi {	3249	connector-hdmi {
3249	compatible = "hdmi-connector";	3250	compatible = "hdmi-connector";
3250	label = "hdmi";	3251	label = "hdmi";
3251	type = "a";	3252	type = "a";
3252	phandle = <0x127>;	3253	phandle = <0x127>;
3253		3254
3254	port {	3255	port {
3255		3256
3256	endpoint {	3257	endpoint {
3257	remote-endpoint = <0x74>;	3258	remote-endpoint = <0x74>;
3258	phandle = <0x31>;	3259	phandle = <0x31>;
3259	};	3260	};
3260	};	3261	};
3261	};	3262	};
3262		3263
3263	clock-edp0-refclk {	3264	clock-edp0-refclk {
3264	#clock-cells = <0x00>;	3265	#clock-cells = <0x00>;
3265	compatible = "fixed-clock";	3266	compatible = "fixed-clock";
3266	clock-frequency = <0x124f800>;	3267	clock-frequency = <0x124f800>;
3267	phandle = <0x32>;	3268	phandle = <0x32>;
3268	};	3269	};
3269		3270
3270	regulator-dp0-prw {	3271	regulator-dp0-prw {
3271	compatible = "regulator-fixed";	3272	compatible = "regulator-fixed";
3272	regulator-name = "dp0-pwr";	3273	regulator-name = "dp0-pwr";
3273	regulator-min-microvolt = <0x325aa0>;	3274	regulator-min-microvolt = <0x325aa0>;
3274	regulator-max-microvolt = <0x325aa0>;	3275	regulator-max-microvolt = <0x325aa0>;
3275	gpio = <0x2f 0x02 0x00>;	3276	gpio = <0x2f 0x02 0x00>;
3276	enable-active-high;	3277	enable-active-high;
3277	regulator-always-on;	3278	regulator-always-on;
3278	phandle = <0x75>;	3279	phandle = <0x75>;
3279	};	3280	};
3280		3281
3281	connector-dp0 {	3282	connector-dp0 {
3282	compatible = "dp-connector";	3283	compatible = "dp-connector";
3283	label = "DP0";	3284	label = "DP0";
3284	type = "full-size";	3285	type = "full-size";
3285	dp-pwr-supply = <0x75>;	3286	dp-pwr-supply = <0x75>;
3286	phandle = <0x128>;	3287	phandle = <0x128>;
3287		3288
3288	port {	3289	port {
3289		3290
3290	endpoint {	3291	endpoint {
3291	remote-endpoint = <0x76>;	3292	remote-endpoint = <0x76>;
3292	phandle = <0x35>;	3293	phandle = <0x35>;
3293	};	3294	};
3294	};	3295	};
3295	};	3296	};
3296		3297
3297	__symbols__ {	3298	__symbols__ {
3298	cluster0 = "/cpus/cpu-map/cluster0";	3299	cluster0 = "/cpus/cpu-map/cluster0";
3299	cpu0 = "/cpus/cpu@0";	3300	cpu0 = "/cpus/cpu@0";
3300	cpu1 = "/cpus/cpu@1";	3301	cpu1 = "/cpus/cpu@1";
3301	cpu2 = "/cpus/cpu@2";	3302	cpu2 = "/cpus/cpu@2";
3302	cpu3 = "/cpus/cpu@3";	3303	cpu3 = "/cpus/cpu@3";
3303	l2_0 = "/l2-cache0";	3304	l2_0 = "/l2-cache0";
3304	psci = "/firmware/psci";	3305	psci = "/firmware/psci";
3305	a53_timer0 = "/timer-cl0-cpu0";	3306	a53_timer0 = "/timer-cl0-cpu0";
3306	pmu = "/pmu";	3307	pmu = "/pmu";
3307	cbass_main = "/bus@f0000";	3308	cbass_main = "/bus@f0000";
3308	cbass_mcu = "/bus@f0000/bus@4000000";	3309	cbass_mcu = "/bus@f0000/bus@4000000";
3309	mcu_ram = "/bus@f0000/bus@4000000/sram@79100000";	3310	mcu_ram = "/bus@f0000/bus@4000000/sram@79100000";
3310	mcu_pmx0 = "/bus@f0000/bus@4000000/pinctrl@4084000";	3311	mcu_pmx0 = "/bus@f0000/bus@4000000/pinctrl@4084000";
3311	mcu_pmx_range = "/bus@f0000/bus@4000000/pinctrl@4084000/gpio-range";	3312	mcu_pmx_range = "/bus@f0000/bus@4000000/pinctrl@4084000/gpio-range";
3312	mcu_i2c0_pins_default = "/bus@f0000/bus@4000000/pinctrl@4084000/mcu-i2c0-default-pins";	3313	mcu_i2c0_pins_default = "/bus@f0000/bus@4000000/pinctrl@4084000/mcu-i2c0-default-pins";
3313	mcu_mcan0_pins_default = "/bus@f0000/bus@4000000/pinctrl@4084000/mcu-mcan0-default-pins";	3314	mcu_mcan0_pins_default = "/bus@f0000/bus@4000000/pinctrl@4084000/mcu-mcan0-default-pins";
3314	mcu_mcan1_pins_default = "/bus@f0000/bus@4000000/pinctrl@4084000/mcu-mcan1-default-pins";	3315	mcu_mcan1_pins_default = "/bus@f0000/bus@4000000/pinctrl@4084000/mcu-mcan1-default-pins";
3315	mcu_mcan0_gpio_pins_default = "/bus@f0000/bus@4000000/pinctrl@4084000/mcu-mcan0-gpio-default-pins";	3316	mcu_mcan0_gpio_pins_default = "/bus@f0000/bus@4000000/pinctrl@4084000/mcu-mcan0-gpio-default-pins";
3316	wkup_uart0_pins_default = "/bus@f0000/bus@4000000/pinctrl@4084000/wkup-uart0-default-pins";	3317	wkup_uart0_pins_default = "/bus@f0000/bus@4000000/pinctrl@4084000/wkup-uart0-default-pins";
3317	wkup_i2c0_pins_default = "/bus@f0000/bus@4000000/pinctrl@4084000/wkup-i2c0-default-pins";	3318	wkup_i2c0_pins_default = "/bus@f0000/bus@4000000/pinctrl@4084000/wkup-i2c0-default-pins";
3318	mcu_esm = "/bus@f0000/bus@4000000/esm@4100000";	3319	mcu_esm = "/bus@f0000/bus@4000000/esm@4100000";
3319	mcu_timer0 = "/bus@f0000/bus@4000000/timer@4800000";	3320	mcu_timer0 = "/bus@f0000/bus@4000000/timer@4800000";
3320	mcu_timer1 = "/bus@f0000/bus@4000000/timer@4810000";	3321	mcu_timer1 = "/bus@f0000/bus@4000000/timer@4810000";
3321	mcu_timer2 = "/bus@f0000/bus@4000000/timer@4820000";	3322	mcu_timer2 = "/bus@f0000/bus@4000000/timer@4820000";
3322	mcu_timer3 = "/bus@f0000/bus@4000000/timer@4830000";	3323	mcu_timer3 = "/bus@f0000/bus@4000000/timer@4830000";
3323	mcu_uart0 = "/bus@f0000/bus@4000000/serial@4a00000";	3324	mcu_uart0 = "/bus@f0000/bus@4000000/serial@4a00000";
3324	mcu_i2c0 = "/bus@f0000/bus@4000000/i2c@4900000";	3325	mcu_i2c0 = "/bus@f0000/bus@4000000/i2c@4900000";
3325	mcu_spi0 = "/bus@f0000/bus@4000000/spi@4b00000";	3326	mcu_spi0 = "/bus@f0000/bus@4000000/spi@4b00000";
3326	mcu_spi1 = "/bus@f0000/bus@4000000/spi@4b10000";	3327	mcu_spi1 = "/bus@f0000/bus@4000000/spi@4b10000";
3327	mcu_gpio_intr = "/bus@f0000/bus@4000000/interrupt-controller@4210000";	3328	mcu_gpio_intr = "/bus@f0000/bus@4000000/interrupt-controller@4210000";
3328	mcu_gpio0 = "/bus@f0000/bus@4000000/gpio@4201000";	3329	mcu_gpio0 = "/bus@f0000/bus@4000000/gpio@4201000";
3329	mcu_rti0 = "/bus@f0000/bus@4000000/watchdog@4880000";	3330	mcu_rti0 = "/bus@f0000/bus@4000000/watchdog@4880000";
3330	mcu_mcan0 = "/bus@f0000/bus@4000000/can@4e08000";	3331	mcu_mcan0 = "/bus@f0000/bus@4000000/can@4e08000";
3331	mcu_mcan1 = "/bus@f0000/bus@4000000/can@4e18000";	3332	mcu_mcan1 = "/bus@f0000/bus@4000000/can@4e18000";
3332	mcu_r5fss0 = "/bus@f0000/bus@4000000/r5fss@79000000";	3333	mcu_r5fss0 = "/bus@f0000/bus@4000000/r5fss@79000000";
3333	mcu_r5fss0_core0 = "/bus@f0000/bus@4000000/r5fss@79000000/r5f@79000000";	3334	mcu_r5fss0_core0 = "/bus@f0000/bus@4000000/r5fss@79000000/r5f@79000000";
3334	cbass_wakeup = "/bus@f0000/bus@b00000";	3335	cbass_wakeup = "/bus@f0000/bus@b00000";
3335	wkup_conf = "/bus@f0000/bus@b00000/bus@43000000";	3336	wkup_conf = "/bus@f0000/bus@b00000/bus@43000000";
3336	chipid = "/bus@f0000/bus@b00000/bus@43000000/chipid@14";	3337	chipid = "/bus@f0000/bus@b00000/bus@43000000/chipid@14";
3337	opp_efuse_table = "/bus@f0000/bus@b00000/bus@43000000/syscon@18";	3338	opp_efuse_table = "/bus@f0000/bus@b00000/bus@43000000/syscon@18";
3338	cpsw_mac_syscon = "/bus@f0000/bus@b00000/bus@43000000/ethernet-mac-syscon@200";	3339	cpsw_mac_syscon = "/bus@f0000/bus@b00000/bus@43000000/ethernet-mac-syscon@200";
3339	usb0_phy_ctrl = "/bus@f0000/bus@b00000/bus@43000000/syscon@4008";	3340	usb0_phy_ctrl = "/bus@f0000/bus@b00000/bus@43000000/syscon@4008";
3340	usb1_phy_ctrl = "/bus@f0000/bus@b00000/bus@43000000/syscon@4018";	3341	usb1_phy_ctrl = "/bus@f0000/bus@b00000/bus@43000000/syscon@4018";
3341	ddr_pmctrl = "/bus@f0000/bus@b00000/bus@43000000/syscon@80d0";	3342	ddr_pmctrl = "/bus@f0000/bus@b00000/bus@43000000/syscon@80d0";
3342	canuart_wake = "/bus@f0000/bus@b00000/bus@43000000/syscon@18300";	3343	canuart_wake = "/bus@f0000/bus@b00000/bus@43000000/syscon@18300";
3343	pcie0_ctrl = "/bus@f0000/bus@b00000/bus@43000000/pcie0-ctrl@4070";	3344	pcie0_ctrl = "/bus@f0000/bus@b00000/bus@43000000/pcie0-ctrl@4070";
3344	wkup_uart0 = "/bus@f0000/bus@b00000/target-module@2b300050/serial@0";	3345	wkup_uart0 = "/bus@f0000/bus@b00000/target-module@2b300050/serial@0";
3345	wkup_i2c0 = "/bus@f0000/bus@b00000/i2c@2b200000";	3346	wkup_i2c0 = "/bus@f0000/bus@b00000/i2c@2b200000";
3346	tps65224 = "/bus@f0000/bus@b00000/i2c@2b200000/pmic@48";	3347	tps65224 = "/bus@f0000/bus@b00000/i2c@2b200000/pmic@48";
3347	buck1 = "/bus@f0000/bus@b00000/i2c@2b200000/pmic@48/regulators/buck1";	3348	buck1 = "/bus@f0000/bus@b00000/i2c@2b200000/pmic@48/regulators/buck1";
3348	buck2 = "/bus@f0000/bus@b00000/i2c@2b200000/pmic@48/regulators/buck2";	3349	buck2 = "/bus@f0000/bus@b00000/i2c@2b200000/pmic@48/regulators/buck2";
3349	buck3 = "/bus@f0000/bus@b00000/i2c@2b200000/pmic@48/regulators/buck3";	3350	buck3 = "/bus@f0000/bus@b00000/i2c@2b200000/pmic@48/regulators/buck3";
3350	buck4 = "/bus@f0000/bus@b00000/i2c@2b200000/pmic@48/regulators/buck4";	3351	buck4 = "/bus@f0000/bus@b00000/i2c@2b200000/pmic@48/regulators/buck4";
3351	ldo1 = "/bus@f0000/bus@b00000/i2c@2b200000/pmic@48/regulators/ldo1";	3352	ldo1 = "/bus@f0000/bus@b00000/i2c@2b200000/pmic@48/regulators/ldo1";
3352	ldo2 = "/bus@f0000/bus@b00000/i2c@2b200000/pmic@48/regulators/ldo2";	3353	ldo2 = "/bus@f0000/bus@b00000/i2c@2b200000/pmic@48/regulators/ldo2";
3353	ldo3 = "/bus@f0000/bus@b00000/i2c@2b200000/pmic@48/regulators/ldo3";	3354	ldo3 = "/bus@f0000/bus@b00000/i2c@2b200000/pmic@48/regulators/ldo3";
3354	wkup_rtc0 = "/bus@f0000/bus@b00000/rtc@2b1f0000";	3355	wkup_rtc0 = "/bus@f0000/bus@b00000/rtc@2b1f0000";
3355	wkup_rti0 = "/bus@f0000/bus@b00000/watchdog@2b000000";	3356	wkup_rti0 = "/bus@f0000/bus@b00000/watchdog@2b000000";
3356	wkup_vtm0 = "/bus@f0000/bus@b00000/temperature-sensor@b00000";	3357	wkup_vtm0 = "/bus@f0000/bus@b00000/temperature-sensor@b00000";
3357	wkup_r5fss0 = "/bus@f0000/bus@b00000/r5fss@78000000";	3358	wkup_r5fss0 = "/bus@f0000/bus@b00000/r5fss@78000000";
3358	wkup_r5fss0_core0 = "/bus@f0000/bus@b00000/r5fss@78000000/r5f@78000000";	3359	wkup_r5fss0_core0 = "/bus@f0000/bus@b00000/r5fss@78000000/r5f@78000000";
3359	oc_sram = "/bus@f0000/sram@70000000";	3360	oc_sram = "/bus@f0000/sram@70000000";
3360	gic500 = "/bus@f0000/interrupt-controller@1800000";	3361	gic500 = "/bus@f0000/interrupt-controller@1800000";
3361	gic_its = "/bus@f0000/interrupt-controller@1800000/msi-controller@1820000";	3362	gic_its = "/bus@f0000/interrupt-controller@1800000/msi-controller@1820000";
3362	main_conf = "/bus@f0000/bus@100000";	3363	main_conf = "/bus@f0000/bus@100000";
3363	phy_gmii_sel = "/bus@f0000/bus@100000/phy@4044";	3364	phy_gmii_sel = "/bus@f0000/bus@100000/phy@4044";
3364	epwm_tbclk = "/bus@f0000/bus@100000/clock-controller@4130";	3365	epwm_tbclk = "/bus@f0000/bus@100000/clock-controller@4130";
3365	dss_oldi_io_ctrl = "/bus@f0000/bus@100000/dss-oldi-io-ctrl@8600";	3366	dss_oldi_io_ctrl = "/bus@f0000/bus@100000/dss-oldi-io-ctrl@8600";
3366	serdes_ln_ctrl = "/bus@f0000/bus@100000/mux-controller@4080";	3367	serdes_ln_ctrl = "/bus@f0000/bus@100000/mux-controller@4080";
3367	audio_refclk1 = "/bus@f0000/bus@100000/clock@82e4";	3368	audio_refclk1 = "/bus@f0000/bus@100000/clock@82e4";
3368	dmss = "/bus@f0000/bus@48000000";	3369	dmss = "/bus@f0000/bus@48000000";
3369	secure_proxy_main = "/bus@f0000/bus@48000000/mailbox@4d000000";	3370	secure_proxy_main = "/bus@f0000/bus@48000000/mailbox@4d000000";
3370	inta_main_dmss = "/bus@f0000/bus@48000000/interrupt-controller@48000000";	3371	inta_main_dmss = "/bus@f0000/bus@48000000/interrupt-controller@48000000";
3371	main_bcdma = "/bus@f0000/bus@48000000/dma-controller@485c0100";	3372	main_bcdma = "/bus@f0000/bus@48000000/dma-controller@485c0100";
3372	main_pktdma = "/bus@f0000/bus@48000000/dma-controller@485c0000";	3373	main_pktdma = "/bus@f0000/bus@48000000/dma-controller@485c0000";
3373	dmss_csi = "/bus@f0000/bus@4e000000";	3374	dmss_csi = "/bus@f0000/bus@4e000000";
3374	inta_main_dmss_csi = "/bus@f0000/bus@4e000000/interrupt-controller@4e400000";	3375	inta_main_dmss_csi = "/bus@f0000/bus@4e000000/interrupt-controller@4e400000";
3375	main_bcdma_csi = "/bus@f0000/bus@4e000000/dma-controller@4e230000";	3376	main_bcdma_csi = "/bus@f0000/bus@4e000000/dma-controller@4e230000";
3376	dmsc = "/bus@f0000/system-controller@44043000";	3377	dmsc = "/bus@f0000/system-controller@44043000";
3377	k3_pds = "/bus@f0000/system-controller@44043000/power-controller";	3378	k3_pds = "/bus@f0000/system-controller@44043000/power-controller";
3378	k3_clks = "/bus@f0000/system-controller@44043000/clock-controller";	3379	k3_clks = "/bus@f0000/system-controller@44043000/clock-controller";
3379	k3_reset = "/bus@f0000/system-controller@44043000/reset-controller";	3380	k3_reset = "/bus@f0000/system-controller@44043000/reset-controller";
3380	crypto = "/bus@f0000/crypto@40900000";	3381	crypto = "/bus@f0000/crypto@40900000";
3381	crc = "/bus@f0000/crc@30300000";	3382	crc = "/bus@f0000/crc@30300000";
3382	secure_proxy_sa3 = "/bus@f0000/mailbox@43600000";	3383	secure_proxy_sa3 = "/bus@f0000/mailbox@43600000";
3383	main_pmx0 = "/bus@f0000/pinctrl@f4000";	3384	main_pmx0 = "/bus@f0000/pinctrl@f4000";
3384	main_pmx0_range = "/bus@f0000/pinctrl@f4000/gpio-range";	3385	main_pmx0_range = "/bus@f0000/pinctrl@f4000/gpio-range";
3385	main_mcan0_pins_default = "/bus@f0000/pinctrl@f4000/main-mcan0-default-pins";	3386	main_mcan0_pins_default = "/bus@f0000/pinctrl@f4000/main-mcan0-default-pins";
3386	main_i2c0_pins_default = "/bus@f0000/pinctrl@f4000/main-i2c0-default-pins";	3387	main_i2c0_pins_default = "/bus@f0000/pinctrl@f4000/main-i2c0-default-pins";
3387	main_i2c1_pins_default = "/bus@f0000/pinctrl@f4000/main-i2c1-default-pins";	3388	main_i2c1_pins_default = "/bus@f0000/pinctrl@f4000/main-i2c1-default-pins";
3388	main_i2c2_pins_default = "/bus@f0000/pinctrl@f4000/main-i2c2-default-pins";	3389	main_i2c2_pins_default = "/bus@f0000/pinctrl@f4000/main-i2c2-default-pins";
3389	main_uart0_pins_default = "/bus@f0000/pinctrl@f4000/main-uart0-default-pins";	3390	main_uart0_pins_default = "/bus@f0000/pinctrl@f4000/main-uart0-default-pins";
3390	main_uart5_pins_default = "/bus@f0000/pinctrl@f4000/main-uart5-default-pins";	3391	main_uart5_pins_default = "/bus@f0000/pinctrl@f4000/main-uart5-default-pins";
3391	vdd_sd_dv_pins_default = "/bus@f0000/pinctrl@f4000/vdd-sd-dv-default-pins";	3392	vdd_sd_dv_pins_default = "/bus@f0000/pinctrl@f4000/vdd-sd-dv-default-pins";
3392	main_mmc1_pins_default = "/bus@f0000/pinctrl@f4000/main-mmc1-default-pins";	3393	main_mmc1_pins_default = "/bus@f0000/pinctrl@f4000/main-mmc1-default-pins";
3393	mdio_pins_default = "/bus@f0000/pinctrl@f4000/mdio-default-pins";	3394	mdio_pins_default = "/bus@f0000/pinctrl@f4000/mdio-default-pins";
3394	ospi0_pins_default = "/bus@f0000/pinctrl@f4000/ospi0-default-pins";	3395	ospi0_pins_default = "/bus@f0000/pinctrl@f4000/ospi0-default-pins";
3395	rgmii1_pins_default = "/bus@f0000/pinctrl@f4000/rgmii1-default-pins";	3396	rgmii1_pins_default = "/bus@f0000/pinctrl@f4000/rgmii1-default-pins";
3396	main_usb1_pins_default = "/bus@f0000/pinctrl@f4000/main-usb1-default-pins";	3397	main_usb1_pins_default = "/bus@f0000/pinctrl@f4000/main-usb1-default-pins";
3397	main_mcasp1_pins_default = "/bus@f0000/pinctrl@f4000/main-mcasp1-default-pins";	3398	main_mcasp1_pins_default = "/bus@f0000/pinctrl@f4000/main-mcasp1-default-pins";
3398	audio_ext_refclk1_pins_default = "/bus@f0000/pinctrl@f4000/audio-ext-refclk1-default-pins";	3399	audio_ext_refclk1_pins_default = "/bus@f0000/pinctrl@f4000/audio-ext-refclk1-default-pins";
3399	pmic_irq_pins_default = "/bus@f0000/pinctrl@f4000/pmic-irq-default-pins";	3400	pmic_irq_pins_default = "/bus@f0000/pinctrl@f4000/pmic-irq-default-pins";
3400	main_gpio0_ioexp_intr_pins_default = "/bus@f0000/pinctrl@f4000/main-gpio0-ioexp-intr-default-pins";	3401	main_gpio0_ioexp_intr_pins_default = "/bus@f0000/pinctrl@f4000/main-gpio0-ioexp-intr-default-pins";
3401	main_dpi_pins_default = "/bus@f0000/pinctrl@f4000/main-dpi-default-pins";	3402	main_dpi_pins_default = "/bus@f0000/pinctrl@f4000/main-dpi-default-pins";
3402	main_esm = "/bus@f0000/esm@420000";	3403	main_esm = "/bus@f0000/esm@420000";
3403	main_timer0 = "/bus@f0000/timer@2400000";	3404	main_timer0 = "/bus@f0000/timer@2400000";
3404	main_timer1 = "/bus@f0000/timer@2410000";	3405	main_timer1 = "/bus@f0000/timer@2410000";
3405	main_timer2 = "/bus@f0000/timer@2420000";	3406	main_timer2 = "/bus@f0000/timer@2420000";
3406	main_timer3 = "/bus@f0000/timer@2430000";	3407	main_timer3 = "/bus@f0000/timer@2430000";
3407	main_timer4 = "/bus@f0000/timer@2440000";	3408	main_timer4 = "/bus@f0000/timer@2440000";
3408	main_timer5 = "/bus@f0000/timer@2450000";	3409	main_timer5 = "/bus@f0000/timer@2450000";
3409	main_timer6 = "/bus@f0000/timer@2460000";	3410	main_timer6 = "/bus@f0000/timer@2460000";
3410	main_timer7 = "/bus@f0000/timer@2470000";	3411	main_timer7 = "/bus@f0000/timer@2470000";
3411	main_uart0 = "/bus@f0000/serial@2800000";	3412	main_uart0 = "/bus@f0000/serial@2800000";
3412	main_uart1 = "/bus@f0000/serial@2810000";	3413	main_uart1 = "/bus@f0000/serial@2810000";
3413	main_uart2 = "/bus@f0000/serial@2820000";	3414	main_uart2 = "/bus@f0000/serial@2820000";
3414	main_uart3 = "/bus@f0000/serial@2830000";	3415	main_uart3 = "/bus@f0000/serial@2830000";
3415	main_uart4 = "/bus@f0000/serial@2840000";	3416	main_uart4 = "/bus@f0000/serial@2840000";
3416	main_uart5 = "/bus@f0000/serial@2850000";	3417	main_uart5 = "/bus@f0000/serial@2850000";
3417	main_uart6 = "/bus@f0000/serial@2860000";	3418	main_uart6 = "/bus@f0000/serial@2860000";
3418	main_i2c0 = "/bus@f0000/i2c@20000000";	3419	main_i2c0 = "/bus@f0000/i2c@20000000";
3419	exp1 = "/bus@f0000/i2c@20000000/gpio@23";	3420	exp1 = "/bus@f0000/i2c@20000000/gpio@23";
3420	p01_hog = "/bus@f0000/i2c@20000000/gpio@23/p01-hog";	3421	p01_hog = "/bus@f0000/i2c@20000000/gpio@23/p01-hog";
3421	p02_hog = "/bus@f0000/i2c@20000000/gpio@23/p02-hog";	3422	p02_hog = "/bus@f0000/i2c@20000000/gpio@23/p02-hog";
3422	p13_hog = "/bus@f0000/i2c@20000000/gpio@23/p13-hog";	3423	p13_hog = "/bus@f0000/i2c@20000000/gpio@23/p13-hog";
3423	tlv320aic3106 = "/bus@f0000/i2c@20000000/audio-codec@1b";	3424	tlv320aic3106 = "/bus@f0000/i2c@20000000/audio-codec@1b";
3424	main_i2c1 = "/bus@f0000/i2c@20010000";	3425	main_i2c1 = "/bus@f0000/i2c@20010000";
3425	exp2 = "/bus@f0000/i2c@20010000/gpio@20";	3426	exp2 = "/bus@f0000/i2c@20010000/gpio@20";
3426	sii9022 = "/bus@f0000/i2c@20010000/bridge-hdmi@3b";	3427	sii9022 = "/bus@f0000/i2c@20010000/bridge-hdmi@3b";
3427	hdmi_tx_ports = "/bus@f0000/i2c@20010000/bridge-hdmi@3b/ports";	3428	hdmi_tx_ports = "/bus@f0000/i2c@20010000/bridge-hdmi@3b/ports";
3428	sii9022_in = "/bus@f0000/i2c@20010000/bridge-hdmi@3b/ports/port@0/endpoint";	3429	sii9022_in = "/bus@f0000/i2c@20010000/bridge-hdmi@3b/ports/port@0/endpoint";
3429	sii9022_out = "/bus@f0000/i2c@20010000/bridge-hdmi@3b/ports/port@1/endpoint";	3430	sii9022_out = "/bus@f0000/i2c@20010000/bridge-hdmi@3b/ports/port@1/endpoint";
3430	dsi_edp_bridge = "/bus@f0000/i2c@20010000/dsi-edp-bridge@2c";	3431	dsi_edp_bridge = "/bus@f0000/i2c@20010000/dsi-edp-bridge@2c";
3431	dsi_edp_bridge_ports = "/bus@f0000/i2c@20010000/dsi-edp-bridge@2c/ports";	3432	dsi_edp_bridge_ports = "/bus@f0000/i2c@20010000/dsi-edp-bridge@2c/ports";
3432	dp0_in = "/bus@f0000/i2c@20010000/dsi-edp-bridge@2c/ports/port@0/endpoint";	3433	dp0_in = "/bus@f0000/i2c@20010000/dsi-edp-bridge@2c/ports/port@0/endpoint";
3433	dp0_out = "/bus@f0000/i2c@20010000/dsi-edp-bridge@2c/ports/port@1/endpoint";	3434	dp0_out = "/bus@f0000/i2c@20010000/dsi-edp-bridge@2c/ports/port@1/endpoint";
3434	main_i2c2 = "/bus@f0000/i2c@20020000";	3435	main_i2c2 = "/bus@f0000/i2c@20020000";
3435	pca9543_0 = "/bus@f0000/i2c@20020000/i2c-mux@70";	3436	pca9543_0 = "/bus@f0000/i2c@20020000/i2c-mux@70";
3436	pca9543_1 = "/bus@f0000/i2c@20020000/i2c-mux@71";	3437	pca9543_1 = "/bus@f0000/i2c@20020000/i2c-mux@71";
3437	main_i2c3 = "/bus@f0000/i2c@20030000";	3438	main_i2c3 = "/bus@f0000/i2c@20030000";
3438	main_spi0 = "/bus@f0000/spi@20100000";	3439	main_spi0 = "/bus@f0000/spi@20100000";
3439	main_spi1 = "/bus@f0000/spi@20110000";	3440	main_spi1 = "/bus@f0000/spi@20110000";
3440	main_spi2 = "/bus@f0000/spi@20120000";	3441	main_spi2 = "/bus@f0000/spi@20120000";
3441	main_gpio_intr = "/bus@f0000/interrupt-controller@a00000";	3442	main_gpio_intr = "/bus@f0000/interrupt-controller@a00000";
3442	main_gpio0 = "/bus@f0000/gpio@600000";	3443	main_gpio0 = "/bus@f0000/gpio@600000";
3443	main_gpio1 = "/bus@f0000/gpio@601000";	3444	main_gpio1 = "/bus@f0000/gpio@601000";
3444	sdhci0 = "/bus@f0000/mmc@fa10000";	3445	sdhci0 = "/bus@f0000/mmc@fa10000";
3445	sdhci1 = "/bus@f0000/mmc@fa00000";	3446	sdhci1 = "/bus@f0000/mmc@fa00000";
3446	sdhci2 = "/bus@f0000/mmc@fa20000";	3447	sdhci2 = "/bus@f0000/mmc@fa20000";
3447	usbss0 = "/bus@f0000/usb@f900000";	3448	usbss0 = "/bus@f0000/usb@f900000";
3448	usb0 = "/bus@f0000/usb@f900000/usb@31000000";	3449	usb0 = "/bus@f0000/usb@f900000/usb@31000000";
3449	fss = "/bus@f0000/bus@fc00000";	3450	fss = "/bus@f0000/bus@fc00000";
3450	ospi0 = "/bus@f0000/bus@fc00000/spi@fc40000";	3451	ospi0 = "/bus@f0000/bus@fc00000/spi@fc40000";
3451	ospi0_nand = "/bus@f0000/bus@fc00000/spi@fc40000/nand@0";	3452	ospi0_nand = "/bus@f0000/bus@fc00000/spi@fc40000/nand@0";
3452	cpsw3g = "/bus@f0000/ethernet@8000000";	3453	cpsw3g = "/bus@f0000/ethernet@8000000";
3453	cpsw_port1 = "/bus@f0000/ethernet@8000000/ethernet-ports/port@1";	3454	cpsw_port1 = "/bus@f0000/ethernet@8000000/ethernet-ports/port@1";
3454	cpsw_port2 = "/bus@f0000/ethernet@8000000/ethernet-ports/port@2";	3455	cpsw_port2 = "/bus@f0000/ethernet@8000000/ethernet-ports/port@2";
3455	cpsw3g_mdio = "/bus@f0000/ethernet@8000000/mdio@f00";	3456	cpsw3g_mdio = "/bus@f0000/ethernet@8000000/mdio@f00";
3456	cpsw3g_phy0 = "/bus@f0000/ethernet@8000000/mdio@f00/ethernet-phy@0";	3457	cpsw3g_phy0 = "/bus@f0000/ethernet@8000000/mdio@f00/ethernet-phy@0";
3457	gpu = "/bus@f0000/gpu@fd80000";	3458	gpu = "/bus@f0000/gpu@fd80000";
3458	hwspinlock = "/bus@f0000/spinlock@2a000000";	3459	hwspinlock = "/bus@f0000/spinlock@2a000000";
3459	timesync_router = "/bus@f0000/mux-controller@a40000";	3460	timesync_router = "/bus@f0000/mux-controller@a40000";
3460	mailbox0_cluster0 = "/bus@f0000/mailbox@29000000";	3461	mailbox0_cluster0 = "/bus@f0000/mailbox@29000000";
3461	mbox_wkup_r5_0 = "/bus@f0000/mailbox@29000000/mbox-wkup-r5-0";	3462	mbox_wkup_r5_0 = "/bus@f0000/mailbox@29000000/mbox-wkup-r5-0";
3462	mailbox0_cluster1 = "/bus@f0000/mailbox@29010000";	3463	mailbox0_cluster1 = "/bus@f0000/mailbox@29010000";
3463	mbox_mcu_r5_0 = "/bus@f0000/mailbox@29010000/mbox-mcu-r5-0";	3464	mbox_mcu_r5_0 = "/bus@f0000/mailbox@29010000/mbox-mcu-r5-0";
3464	mailbox0_cluster2 = "/bus@f0000/mailbox@29020000";	3465	mailbox0_cluster2 = "/bus@f0000/mailbox@29020000";
3465	mbox_c7x_0 = "/bus@f0000/mailbox@29020000/mbox-c7x-0";	3466	mbox_c7x_0 = "/bus@f0000/mailbox@29020000/mbox-c7x-0";
3466	mailbox0_cluster3 = "/bus@f0000/mailbox@29030000";	3467	mailbox0_cluster3 = "/bus@f0000/mailbox@29030000";
3467	mbox_main_r5_0 = "/bus@f0000/mailbox@29030000/mbox-main-r5-0";	3468	mbox_main_r5_0 = "/bus@f0000/mailbox@29030000/mbox-main-r5-0";
3468	mbox_c7x_1 = "/bus@f0000/mailbox@29030000/mbox-c7x-1";	3469	mbox_c7x_1 = "/bus@f0000/mailbox@29030000/mbox-c7x-1";
3469	ecap0 = "/bus@f0000/pwm@23100000";	3470	ecap0 = "/bus@f0000/pwm@23100000";
3470	ecap1 = "/bus@f0000/pwm@23110000";	3471	ecap1 = "/bus@f0000/pwm@23110000";
3471	ecap2 = "/bus@f0000/pwm@23120000";	3472	ecap2 = "/bus@f0000/pwm@23120000";
3472	eqep0 = "/bus@f0000/counter@23200000";	3473	eqep0 = "/bus@f0000/counter@23200000";
3473	eqep1 = "/bus@f0000/counter@23210000";	3474	eqep1 = "/bus@f0000/counter@23210000";
3474	eqep2 = "/bus@f0000/counter@23220000";	3475	eqep2 = "/bus@f0000/counter@23220000";
3475	main_mcan0 = "/bus@f0000/can@20701000";	3476	main_mcan0 = "/bus@f0000/can@20701000";
3476	main_mcan1 = "/bus@f0000/can@20711000";	3477	main_mcan1 = "/bus@f0000/can@20711000";
3477	main_rti0 = "/bus@f0000/watchdog@e000000";	3478	main_rti0 = "/bus@f0000/watchdog@e000000";
3478	main_rti1 = "/bus@f0000/watchdog@e010000";	3479	main_rti1 = "/bus@f0000/watchdog@e010000";
3479	main_rti2 = "/bus@f0000/watchdog@e020000";	3480	main_rti2 = "/bus@f0000/watchdog@e020000";
3480	main_rti3 = "/bus@f0000/watchdog@e030000";	3481	main_rti3 = "/bus@f0000/watchdog@e030000";
3481	main_rti15 = "/bus@f0000/watchdog@e0f0000";	3482	main_rti15 = "/bus@f0000/watchdog@e0f0000";
3482	epwm0 = "/bus@f0000/pwm@23000000";	3483	epwm0 = "/bus@f0000/pwm@23000000";
3483	epwm1 = "/bus@f0000/pwm@23010000";	3484	epwm1 = "/bus@f0000/pwm@23010000";
3484	epwm2 = "/bus@f0000/pwm@23020000";	3485	epwm2 = "/bus@f0000/pwm@23020000";
3485	mcasp0 = "/bus@f0000/audio-controller@2b00000";	3486	mcasp0 = "/bus@f0000/audio-controller@2b00000";
3486	mcasp1 = "/bus@f0000/audio-controller@2b10000";	3487	mcasp1 = "/bus@f0000/audio-controller@2b10000";
3487	mcasp2 = "/bus@f0000/audio-controller@2b20000";	3488	mcasp2 = "/bus@f0000/audio-controller@2b20000";
3488	ti_csi2rx0 = "/bus@f0000/ticsi2rx@30102000";	3489	ti_csi2rx0 = "/bus@f0000/ticsi2rx@30102000";
3489	cdns_csi2rx0 = "/bus@f0000/ticsi2rx@30102000/csi-bridge@30101000";	3490	cdns_csi2rx0 = "/bus@f0000/ticsi2rx@30102000/csi-bridge@30101000";
3490	csi0_port0 = "/bus@f0000/ticsi2rx@30102000/csi-bridge@30101000/ports/port@0";	3491	csi0_port0 = "/bus@f0000/ticsi2rx@30102000/csi-bridge@30101000/ports/port@0";
3491	csi0_port1 = "/bus@f0000/ticsi2rx@30102000/csi-bridge@30101000/ports/port@1";	3492	csi0_port1 = "/bus@f0000/ticsi2rx@30102000/csi-bridge@30101000/ports/port@1";
3492	csi0_port2 = "/bus@f0000/ticsi2rx@30102000/csi-bridge@30101000/ports/port@2";	3493	csi0_port2 = "/bus@f0000/ticsi2rx@30102000/csi-bridge@30101000/ports/port@2";
3493	csi0_port3 = "/bus@f0000/ticsi2rx@30102000/csi-bridge@30101000/ports/port@3";	3494	csi0_port3 = "/bus@f0000/ticsi2rx@30102000/csi-bridge@30101000/ports/port@3";
3494	csi0_port4 = "/bus@f0000/ticsi2rx@30102000/csi-bridge@30101000/ports/port@4";	3495	csi0_port4 = "/bus@f0000/ticsi2rx@30102000/csi-bridge@30101000/ports/port@4";
3495	dphy0 = "/bus@f0000/phy@30110000";	3496	dphy0 = "/bus@f0000/phy@30110000";
3496	dss0 = "/bus@f0000/dss@30200000";	3497	dss0 = "/bus@f0000/dss@30200000";
3497	oldi0_dss0 = "/bus@f0000/dss@30200000/oldi-transmitters/oldi@0";	3498	oldi0_dss0 = "/bus@f0000/dss@30200000/oldi-transmitters/oldi@0";
3498	oldi0_dss0_ports = "/bus@f0000/dss@30200000/oldi-transmitters/oldi@0/ports";	3499	oldi0_dss0_ports = "/bus@f0000/dss@30200000/oldi-transmitters/oldi@0/ports";
3499	oldi1_dss0 = "/bus@f0000/dss@30200000/oldi-transmitters/oldi@1";	3500	oldi1_dss0 = "/bus@f0000/dss@30200000/oldi-transmitters/oldi@1";
3500	oldi1_dss0_ports = "/bus@f0000/dss@30200000/oldi-transmitters/oldi@1/ports";	3501	oldi1_dss0_ports = "/bus@f0000/dss@30200000/oldi-transmitters/oldi@1/ports";
3501	dss0_ports = "/bus@f0000/dss@30200000/ports";	3502	dss0_ports = "/bus@f0000/dss@30200000/ports";
3502	dss1 = "/bus@f0000/dss@30220000";	3503	dss1 = "/bus@f0000/dss@30220000";
3503	oldi1_dss1 = "/bus@f0000/dss@30220000/oldi-transmitters/oldi@1";	3504	oldi1_dss1 = "/bus@f0000/dss@30220000/oldi-transmitters/oldi@1";
3504	oldi1_dss1_ports = "/bus@f0000/dss@30220000/oldi-transmitters/oldi@1/ports";	3505	oldi1_dss1_ports = "/bus@f0000/dss@30220000/oldi-transmitters/oldi@1/ports";
3505	dss1_ports = "/bus@f0000/dss@30220000/ports";	3506	dss1_ports = "/bus@f0000/dss@30220000/ports";
3506	dss1_dpi0_out = "/bus@f0000/dss@30220000/ports/port@0/endpoint";	3507	dss1_dpi0_out = "/bus@f0000/dss@30220000/ports/port@0/endpoint";
3507	dss1_dpi1_out = "/bus@f0000/dss@30220000/ports/port@1/endpoint";	3508	dss1_dpi1_out = "/bus@f0000/dss@30220000/ports/port@1/endpoint";
3508	dphy_tx0 = "/bus@f0000/phy@301c0000";	3509	dphy_tx0 = "/bus@f0000/phy@301c0000";
3509	dsi0 = "/bus@f0000/dsi@30500000";	3510	dsi0 = "/bus@f0000/dsi@30500000";
3510	dsi0_out = "/bus@f0000/dsi@30500000/ports/port@0/endpoint";	3511	dsi0_out = "/bus@f0000/dsi@30500000/ports/port@0/endpoint";
3511	dsi0_in = "/bus@f0000/dsi@30500000/ports/port@1/endpoint";	3512	dsi0_in = "/bus@f0000/dsi@30500000/ports/port@1/endpoint";
3512	vpu = "/bus@f0000/video-codec@30210000";	3513	vpu = "/bus@f0000/video-codec@30210000";
3513	vpu_opp_table = "/bus@f0000/video-codec@30210000/opp-table";	3514	vpu_opp_table = "/bus@f0000/video-codec@30210000/opp-table";
3514	serdes_wiz0 = "/bus@f0000/phy@f000000";	3515	serdes_wiz0 = "/bus@f0000/phy@f000000";
3515	serdes0 = "/bus@f0000/phy@f000000/serdes@f000000";	3516	serdes0 = "/bus@f0000/phy@f000000/serdes@f000000";
3516	serdes0_usb_link = "/bus@f0000/phy@f000000/serdes@f000000/phy@0";	3517	serdes0_usb_link = "/bus@f0000/phy@f000000/serdes@f000000/phy@0";
3517	serdes_wiz1 = "/bus@f0000/phy@f010000";	3518	serdes_wiz1 = "/bus@f0000/phy@f010000";
3518	serdes1 = "/bus@f0000/phy@f010000/serdes@f010000";	3519	serdes1 = "/bus@f0000/phy@f010000/serdes@f010000";
3519	serdes1_pcie_link = "/bus@f0000/phy@f010000/serdes@f010000/phy@0";	3520	serdes1_pcie_link = "/bus@f0000/phy@f010000/serdes@f010000/phy@0";
3520	pcie0_rc = "/bus@f0000/pcie@f102000";	3521	pcie0_rc = "/bus@f0000/pcie@f102000";
3521	usbss1 = "/bus@f0000/usb@f920000";	3522	usbss1 = "/bus@f0000/usb@f920000";
3522	usb1 = "/bus@f0000/usb@f920000/usb@31200000";	3523	usb1 = "/bus@f0000/usb@f920000/usb@31200000";
3523	ti_csi2rx1 = "/bus@f0000/ticsi2rx@30122000";	3524	ti_csi2rx1 = "/bus@f0000/ticsi2rx@30122000";
3524	cdns_csi2rx1 = "/bus@f0000/ticsi2rx@30122000/csi-bridge@30121000";	3525	cdns_csi2rx1 = "/bus@f0000/ticsi2rx@30122000/csi-bridge@30121000";
3525	csi1_port0 = "/bus@f0000/ticsi2rx@30122000/csi-bridge@30121000/ports/port@0";	3526	csi1_port0 = "/bus@f0000/ticsi2rx@30122000/csi-bridge@30121000/ports/port@0";
3526	csi1_port1 = "/bus@f0000/ticsi2rx@30122000/csi-bridge@30121000/ports/port@1";	3527	csi1_port1 = "/bus@f0000/ticsi2rx@30122000/csi-bridge@30121000/ports/port@1";
3527	csi1_port2 = "/bus@f0000/ticsi2rx@30122000/csi-bridge@30121000/ports/port@2";	3528	csi1_port2 = "/bus@f0000/ticsi2rx@30122000/csi-bridge@30121000/ports/port@2";
3528	csi1_port3 = "/bus@f0000/ticsi2rx@30122000/csi-bridge@30121000/ports/port@3";	3529	csi1_port3 = "/bus@f0000/ticsi2rx@30122000/csi-bridge@30121000/ports/port@3";
3529	csi1_port4 = "/bus@f0000/ticsi2rx@30122000/csi-bridge@30121000/ports/port@4";	3530	csi1_port4 = "/bus@f0000/ticsi2rx@30122000/csi-bridge@30121000/ports/port@4";
3530	ti_csi2rx2 = "/bus@f0000/ticsi2rx@30142000";	3531	ti_csi2rx2 = "/bus@f0000/ticsi2rx@30142000";
3531	cdns_csi2rx2 = "/bus@f0000/ticsi2rx@30142000/csi-bridge@30141000";	3532	cdns_csi2rx2 = "/bus@f0000/ticsi2rx@30142000/csi-bridge@30141000";
3532	csi2_port0 = "/bus@f0000/ticsi2rx@30142000/csi-bridge@30141000/ports/port@0";	3533	csi2_port0 = "/bus@f0000/ticsi2rx@30142000/csi-bridge@30141000/ports/port@0";
3533	csi2_port1 = "/bus@f0000/ticsi2rx@30142000/csi-bridge@30141000/ports/port@1";	3534	csi2_port1 = "/bus@f0000/ticsi2rx@30142000/csi-bridge@30141000/ports/port@1";
3534	csi2_port2 = "/bus@f0000/ticsi2rx@30142000/csi-bridge@30141000/ports/port@2";	3535	csi2_port2 = "/bus@f0000/ticsi2rx@30142000/csi-bridge@30141000/ports/port@2";
3535	csi2_port3 = "/bus@f0000/ticsi2rx@30142000/csi-bridge@30141000/ports/port@3";	3536	csi2_port3 = "/bus@f0000/ticsi2rx@30142000/csi-bridge@30141000/ports/port@3";
3536	csi2_port4 = "/bus@f0000/ticsi2rx@30142000/csi-bridge@30141000/ports/port@4";	3537	csi2_port4 = "/bus@f0000/ticsi2rx@30142000/csi-bridge@30141000/ports/port@4";
3537	ti_csi2rx3 = "/bus@f0000/ticsi2rx@30162000";	3538	ti_csi2rx3 = "/bus@f0000/ticsi2rx@30162000";
3538	cdns_csi2rx3 = "/bus@f0000/ticsi2rx@30162000/csi-bridge@30161000";	3539	cdns_csi2rx3 = "/bus@f0000/ticsi2rx@30162000/csi-bridge@30161000";
3539	csi3_port0 = "/bus@f0000/ticsi2rx@30162000/csi-bridge@30161000/ports/port@0";	3540	csi3_port0 = "/bus@f0000/ticsi2rx@30162000/csi-bridge@30161000/ports/port@0";
3540	csi3_port1 = "/bus@f0000/ticsi2rx@30162000/csi-bridge@30161000/ports/port@1";	3541	csi3_port1 = "/bus@f0000/ticsi2rx@30162000/csi-bridge@30161000/ports/port@1";
3541	csi3_port2 = "/bus@f0000/ticsi2rx@30162000/csi-bridge@30161000/ports/port@2";	3542	csi3_port2 = "/bus@f0000/ticsi2rx@30162000/csi-bridge@30161000/ports/port@2";
3542	csi3_port3 = "/bus@f0000/ticsi2rx@30162000/csi-bridge@30161000/ports/port@3";	3543	csi3_port3 = "/bus@f0000/ticsi2rx@30162000/csi-bridge@30161000/ports/port@3";
3543	csi3_port4 = "/bus@f0000/ticsi2rx@30162000/csi-bridge@30161000/ports/port@4";	3544	csi3_port4 = "/bus@f0000/ticsi2rx@30162000/csi-bridge@30161000/ports/port@4";
3544	dphy1 = "/bus@f0000/phy@30130000";	3545	dphy1 = "/bus@f0000/phy@30130000";
3545	dphy2 = "/bus@f0000/phy@30150000";	3546	dphy2 = "/bus@f0000/phy@30150000";
3546	dphy3 = "/bus@f0000/phy@30170000";	3547	dphy3 = "/bus@f0000/phy@30170000";
3547	main_r5fss0 = "/bus@f0000/r5fss@78400000";	3548	main_r5fss0 = "/bus@f0000/r5fss@78400000";
3548	main_r5fss0_core0 = "/bus@f0000/r5fss@78400000/r5f@78400000";	3549	main_r5fss0_core0 = "/bus@f0000/r5fss@78400000/r5f@78400000";
3549	c7x_0 = "/bus@f0000/dsp@7e000000";	3550	c7x_0 = "/bus@f0000/dsp@7e000000";
3550	c7x_1 = "/bus@f0000/dsp@7e200000";	3551	c7x_1 = "/bus@f0000/dsp@7e200000";
3551	e5010 = "/bus@f0000/e5010@fd20000";	3552	e5010 = "/bus@f0000/e5010@fd20000";
3552	dss0_vp1_clk = "/clock-divider-oldi-dss0";	3553	dss0_vp1_clk = "/clock-divider-oldi-dss0";
3553	dss1_vp1_clk = "/clock-divider-oldi-dss1";	3554	dss1_vp1_clk = "/clock-divider-oldi-dss1";
3554	thermal_zones = "/thermal-zones";	3555	thermal_zones = "/thermal-zones";
3555	main0_thermal = "/thermal-zones/main0-thermal";	3556	main0_thermal = "/thermal-zones/main0-thermal";
3556	main0_crit = "/thermal-zones/main0-thermal/trips/main0-crit";	3557	main0_crit = "/thermal-zones/main0-thermal/trips/main0-crit";
3557	main1_thermal = "/thermal-zones/main1-thermal";	3558	main1_thermal = "/thermal-zones/main1-thermal";
3558	main1_crit = "/thermal-zones/main1-thermal/trips/main1-crit";	3559	main1_crit = "/thermal-zones/main1-thermal/trips/main1-crit";
3559	main2_thermal = "/thermal-zones/main2-thermal";	3560	main2_thermal = "/thermal-zones/main2-thermal";
3560	main2_crit = "/thermal-zones/main2-thermal/trips/main2-crit";	3561	main2_crit = "/thermal-zones/main2-thermal/trips/main2-crit";
3561	serdes_refclk = "/clk-0";	3562	serdes_refclk = "/clk-0";
3562	reserved_memory = "/reserved-memory";	3563	reserved_memory = "/reserved-memory";
3563	secure_tfa_ddr = "/reserved-memory/tfa@9e780000";	3564	secure_tfa_ddr = "/reserved-memory/tfa@9e780000";
3564	secure_ddr = "/reserved-memory/optee@9e800000";	3565	secure_ddr = "/reserved-memory/optee@9e800000";
3565	wkup_r5fss0_core0_dma_memory_region = "/reserved-memory/r5f-dma-memory@a0000000";	3566	wkup_r5fss0_core0_dma_memory_region = "/reserved-memory/r5f-dma-memory@a0000000";
3566	wkup_r5fss0_core0_memory_region = "/reserved-memory/r5f-memory@a0100000";	3567	wkup_r5fss0_core0_memory_region = "/reserved-memory/r5f-memory@a0100000";
3567	mcu_r5fss0_core0_dma_memory_region = "/reserved-memory/mcu-r5fss-dma-memory-region@a1000000";	3568	mcu_r5fss0_core0_dma_memory_region = "/reserved-memory/mcu-r5fss-dma-memory-region@a1000000";
3568	mcu_r5fss0_core0_memory_region = "/reserved-memory/mcu-r5fss-memory-region@a1100000";	3569	mcu_r5fss0_core0_memory_region = "/reserved-memory/mcu-r5fss-memory-region@a1100000";
3569	main_r5fss0_core0_dma_memory_region = "/reserved-memory/main-r5fss-dma-memory-region@a2000000";	3570	main_r5fss0_core0_dma_memory_region = "/reserved-memory/main-r5fss-dma-memory-region@a2000000";
3570	main_r5fss0_core0_memory_region = "/reserved-memory/main-r5fss-memory-region@a2100000";	3571	main_r5fss0_core0_memory_region = "/reserved-memory/main-r5fss-memory-region@a2100000";
3571	c7x_0_dma_memory_region = "/reserved-memory/c7x-dma-memory@a3000000";	3572	c7x_0_dma_memory_region = "/reserved-memory/c7x-dma-memory@a3000000";
3572	c7x_0_memory_region = "/reserved-memory/c7x-memory@a3100000";	3573	c7x_0_memory_region = "/reserved-memory/c7x-memory@a3100000";
3573	c7x_1_dma_memory_region = "/reserved-memory/c7x-dma-memory@a4000000";	3574	c7x_1_dma_memory_region = "/reserved-memory/c7x-dma-memory@a4000000";
3574	c7x_1_memory_region = "/reserved-memory/c7x-memory@a4100000";	3575	c7x_1_memory_region = "/reserved-memory/c7x-memory@a4100000";
3575	rtos_ipc_memory_region = "/reserved-memory/ipc-memories@a5000000";	3576	rtos_ipc_memory_region = "/reserved-memory/ipc-memories@a5000000";
3576	vmain_pd = "/regulator-0";	3577	vmain_pd = "/regulator-0";
3577	vsys_5v0 = "/regulator-vsys5v0";	3578	vsys_5v0 = "/regulator-vsys5v0";
3578	vdd_mmc1 = "/regulator-mmc1";	3579	vdd_mmc1 = "/regulator-mmc1";
3579	vdd_sd_dv = "/regulator-TLV71033";	3580	vdd_sd_dv = "/regulator-TLV71033";
3580	vsys_io_3v3 = "/regulator-vsys-io-3v3";	3581	vsys_io_3v3 = "/regulator-vsys-io-3v3";
3581	vsys_io_1v8 = "/regulator-vsys-io-1v8";	3582	vsys_io_1v8 = "/regulator-vsys-io-1v8";
3582	vsys_io_1v2 = "/regulator-vsys-io-1v2";	3583	vsys_io_1v2 = "/regulator-vsys-io-1v2";
3583	codec_audio = "/sound";	3584	codec_audio = "/sound";
3584	sound_master = "/sound/simple-audio-card,codec";	3585	sound_master = "/sound/simple-audio-card,codec";
3585	transceiver0 = "/can-phy0";	3586	transceiver0 = "/can-phy0";
3586	transceiver1 = "/can-phy1";	3587	transceiver1 = "/can-phy1";
3587	transceiver2 = "/can-phy2";	3588	transceiver2 = "/can-phy2";
3588	hdmi0 = "/connector-hdmi";	3589	hdmi0 = "/connector-hdmi";
3589	hdmi_connector_in = "/connector-hdmi/port/endpoint";	3590	hdmi_connector_in = "/connector-hdmi/port/endpoint";
3590	edp0_refclk = "/clock-edp0-refclk";	3591	edp0_refclk = "/clock-edp0-refclk";
3591	dp0_pwr_3v3 = "/regulator-dp0-prw";	3592	dp0_pwr_3v3 = "/regulator-dp0-prw";
3592	dp0 = "/connector-dp0";	3593	dp0 = "/connector-dp0";
3593	dp0_connector_in = "/connector-dp0/port/endpoint";	3594	dp0_connector_in = "/connector-dp0/port/endpoint";
3594	};	3595	};
3595	};	3596	};
3596		3597