s/tidlModelImport$ ./out/tidl_model_import.out ../../test/testvecs/abc/import_cfg_int16.txt 
========================= [Model Compilation Started] =========================

Model compilation will perform the following stages:
1. Parsing
2. Graph Optimization
3. Quantization & Calibration
4. Memory Planning

============================== [Version Summary] ==============================

-------------------------------------------------------------------------------
|          TIDL Tools Version          |              10_01_00_01             |
-------------------------------------------------------------------------------
|         C7x Firmware Version         |              10_00_02_00             |
-------------------------------------------------------------------------------

ONNX model (Proto) file      : ../../test/testvecs/abc/model.onnx  
TIDL network file            : ../../test/testvecs/abc/artifacts_int16/tidl_net_abc.bin  
TIDL IO info file            : ../../test/testvecs/abc/artifacts_int16/tidl_io_abc_  
Current ONNX OpSet version   : 16  
============================ [Optimization started] ============================

Running tidl_optimizeNet 
 S.No|Layer Type                    |Input Data                                        |Output Data                                       |In Id|Out Id|
    0|TIDL_DataLayer                |                                                  |input1                                            |    0|    0|
    1|TIDL_DataLayer                |                                                  |input2                                            |    0|    1|
    2|TIDL_CustomLayer              |input1                                            |output                                            |    0|    2|
    3|TIDL_DataLayer                |output                                            |output                                            |    2|    0|
----------------------------- Optimization Summary -----------------------------
-------------------------------------------------------------------------------------
|            Layer           | Nodes before optimization | Nodes after optimization |
-------------------------------------------------------------------------------------
| TIDL_CustomLayer           |                         1 |                        1 |
-------------------------------------------------------------------------------------

--------------------- Layer mapping to TIDL Network Layers ---------------------
Completed tidl_optimizeNet 
=========================== [Optimization completed] ===========================

Raw data format used is same as inElementType 2 
Raw data format used is same as inElementType 2 
Raw data format used is same as inElementType 2 
Raw data format used is same as inElementType 2 
Raw data format used is same as inElementType 2 
Raw data format used is same as inElementType 2 
Raw data format used is same as inElementType 2 
Raw data format used is same as inElementType 2 
Raw data format used is same as inElementType 2 
Raw data format used is same as inElementType 2 
Raw data format used is same as inElementType 2 
Raw data format used is same as inElementType 2 
Raw data format used is same as inElementType 2 
Raw data format used is same as inElementType 2 
Raw data format used is same as inElementType 2 
Raw data format used is same as inElementType 2 
Raw data format used is same as inElementType 2 
Raw data format used is same as inElementType 2 
Raw data format used is same as inElementType 2 
Raw data format used is same as inElementType 2 
Raw data format used is same as inElementType 2 
Raw data format used is same as inElementType 2 
Raw data format used is same as inElementType 2 
Raw data format used is same as inElementType 2 
Raw data format used is same as inElementType 2 
Raw data format used is same as inElementType 2 
Raw data format used is same as inElementType 2 
Raw data format used is same as inElementType 2 
Raw data format used is same as inElementType 2 
Raw data format used is same as inElementType 2 
Empty prototxt path, running calibration
Num of Layer Detected :   4 

--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

  Num|TIDL Layer Name               |Out Data Name                                     |Group |#Ins  |#Outs |Inbuf Ids                       |Outbuf Id |In NCHW                             |Out NCHW                            |MACS       |

--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

    0|TIDL_DataLayer                |input1                                            |     0|    -1|     1|  x   x   x   x   x   x   x   x |  0       |       0        0        0        0        0        0 |       1        1        1        3       32       32 |         0 |

    1|TIDL_DataLayer                |input2                                            |     0|    -1|     1|  x   x   x   x   x   x   x   x |  1       |       0        0        0        0        0        0 |       1        1        1        3       32       32 |         0 |

    2|TIDL_CustomLayer              |output                                            |     0|     2|     1|  0   1   x   x   x   x   x   x |  2       |       1        1        1        3       32       32 |       1        1        1        3       32       32 |         0 |

    3|TIDL_DataLayer                |output                                            |     0|     1|    -1|  2   x   x   x   x   x   x   x |  0       |       1        1        1        3       32       32 |       0        0        0        0        0        0 |         0 |

--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

Total Giga Macs : 0.0000

--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

Num of Layer Detected :   4 

--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

  Num|TIDL Layer Name               |Out Data Name                                     |Group |#Ins  |#Outs |Inbuf Ids                       |Outbuf Id |In NCHW                             |Out NCHW                            |MACS       |

--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

    0|TIDL_DataLayer                |input1                                            |     0|    -1|     1|  x   x   x   x   x   x   x   x |  0       |       0        0        0        0        0        0 |       1        1        1        3       32       32 |         0 |

    1|TIDL_DataLayer                |input2                                            |     0|    -1|     1|  x   x   x   x   x   x   x   x |  1       |       0        0        0        0        0        0 |       1        1        1        3       32       32 |         0 |

    2|TIDL_CustomLayer              |output                                            |     0|     2|     1|  0   1   x   x   x   x   x   x |  2       |       1        1        1        3       32       32 |       1        1        1        3       32       32 |         0 |

    3|TIDL_DataLayer                |output                                            |     0|     1|    -1|  2   x   x   x   x   x   x   x |  0       |       1        1        1        3       32       32 |       0        0        0        0        0        0 |         0 |

--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

Total Giga Macs : 0.0000

--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------


-------- Running Calibration in Float Mode to Collect Tensor Statistics --------
cd /work/ti-processor-sdk-rtos-j784s4-evm-10_01_00_04/c7x-mma-tidl/ti_dl/test && ./PC_dsp_test_dl_algo.out s:/work/ti-processor-sdk-rtos-j784s4-evm-10_01_00_04/c7x-mma-tidl/ti_dl/test/testvecs/abc/artifacts_int16/import_cfg_int16.txt.qunat_stats_config.txt
Input : dataId=0, name=input1, elementType 6, scale=0.093457, zero point=0, layout=0
Input : dataId=1, name=input2, elementType 6, scale=0.100531, zero point=0, layout=0
Ouput : dataId=2, name=output, elementType 6, scale=1.000000, zero point=0, layout=0 
     22999616,     21.934 0x7f3fd1f82010
worstCaseDelay for Pre-emption is 0.0000000 
Network File Read done
Calling algAlloc
TIDL_initDebugTraceParams Done 

--------------------------------------------
TIDL Memory size requiement (record wise):
MemRecNum   , Space               , Attribute   , Alignment   , Size(KBytes), BasePtr     
0           , DDR Cacheable       , Persistent  ,  128, 19.67   , 0x00000000
1           , DDR Cacheable       , Persistent  ,  128, 0.65    , 0x00000000
2           , DDR Cacheable       , Scratch     ,  128, 16.00   , 0x00000000
3           , DDR Cacheable       , Scratch     ,  128, 4.00    , 0x00000000
4           , DDR Cacheable       , Scratch     ,  128, 56.00   , 0x00000000
5           , DDR Cacheable       , Persistent  ,  128, 320.50  , 0x00000000
6           , DDR Cacheable       , Scratch     ,  128, 0.50    , 0x00000000
7           , DDR Cacheable       , Scratch     ,  128, 0.12    , 0x00000000
8           , DDR Cacheable       , Scratch     ,  128, 0.25    , 0x00000000
9           , DDR Cacheable       , Scratch     ,  128, 27.00   , 0x00000000
10          , DDR Cacheable       , Persistent  ,  128, 255.59  , 0x00000000
11          , DDR Cacheable       , Scratch     ,  128, 512.25  , 0x00000000
12          , DDR Cacheable       , Persistent  ,  128, 0.12    , 0x00000000
13          , DDR Cacheable       , Persistent  ,  128, 22460.69, 0x00000000
14          , DDR Cacheable       , Persistent  ,  128, 0.00    , 0x00000000
15          , DDR Cacheable       , Persistent  ,  128, 0.12    , 0x00000000
--------------------------------------------
Total memory size requirement (space wise):
Mem Space , Size(KBytes)
DDR Cacheable, 23673.47
--------------------------------------------
NOTE: Memory requirement in host emulation can be different from the same on EVM
      To get the actual TIDL memory requirement make sure to run on EVM with 
      debugTraceLevel = 2

--------------------------------------------
Num,    Space,     SizeinBytes,   SineInMB
   0,    17,        20144,      0.019 0x55de6344e200
   1,    17,          664,      0.001 0x55de6344d280
   2,    17,        16384,      0.016 0x55de63453200
   3,    17,         4096,      0.004 0x55de63457280
   4,    17,        57344,      0.055 0x55de63458380
   5,    17,       328196,      0.313 0x7f3fd1f31080
   6,    17,          512,      0.000 0x55de63466400
   7,    17,          128,      0.000 0x55de63466700
   8,    17,          256,      0.000 0x55de63466800
   9,    17,        27648,      0.026 0x55de63466a00
  10,    17,       261720,      0.250 0x7f3fd1ef1080
  11,    17,       524544,      0.500 0x7f3fd1e70080
  12,    17,          128,      0.000 0x55de6346d680
  13,    17,     22999744,     21.934 0x7f3fd0880080
  14,    17,            1,      0.000 0x55de6346d800
  15,    17,          128,      0.000 0x55de6346d880
Total External Memory (DDR) Size =     24241637,     23.119 
TIDL init call from ivision API 

--------------------------------------------
TIDL Memory size requiement (record wise):
MemRecNum   , Space               , Attribute   , Alignment   , Size(KBytes), BasePtr     
0           , DDR Cacheable       , Persistent  ,  128, 19.67   , 0x6344e200
1           , DDR Cacheable       , Persistent  ,  128, 0.65    , 0x6344d280
2           , DDR Cacheable       , Scratch     ,  128, 16.00   , 0x63453200
3           , DDR Cacheable       , Scratch     ,  128, 4.00    , 0x63457280
4           , DDR Cacheable       , Scratch     ,  128, 56.00   , 0x63458380
5           , DDR Cacheable       , Persistent  ,  128, 320.50  , 0xd1f31080
6           , DDR Cacheable       , Scratch     ,  128, 0.50    , 0x63466400
7           , DDR Cacheable       , Scratch     ,  128, 0.12    , 0x63466700
8           , DDR Cacheable       , Scratch     ,  128, 0.25    , 0x63466800
9           , DDR Cacheable       , Scratch     ,  128, 27.00   , 0x63466a00
10          , DDR Cacheable       , Persistent  ,  128, 255.59  , 0xd1ef1080
11          , DDR Cacheable       , Scratch     ,  128, 512.25  , 0xd1e70080
12          , DDR Cacheable       , Persistent  ,  128, 0.12    , 0x6346d680
13          , DDR Cacheable       , Persistent  ,  128, 22460.69, 0xd0880080
14          , DDR Cacheable       , Persistent  ,  128, 0.00    , 0x6346d800
15          , DDR Cacheable       , Persistent  ,  128, 0.12    , 0x6346d880
--------------------------------------------
Total memory size requirement (space wise):
Mem Space , Size(KBytes)
DDR Cacheable, 23673.47
--------------------------------------------
NOTE: Memory requirement in host emulation can be different from the same on EVM
      To get the actual TIDL memory requirement make sure to run on EVM with 
      debugTraceLevel = 2

--------------------------------------------
Alg Init for Layer # -    2
PREEMPTION: Adding a new priority object for targetPriority = 0, handle = 0x55de6344e200
PREEMPTION: Now total number of priority objects = 1 at priorityId = 0,    with new memRec of base = 0x55de6346d680 and size = 128
PREEMPTION: Requesting context memory addr for handle 0x55de6344e200, return Addr = 0x55de31f4ba58
 Freeing memory for user provided Net

 Instance created for  /work/ti-processor-sdk-rtos-j784s4-evm-10_01_00_04/c7x-mma-tidl/ti_dl/test/testvecs/abc/artifacts_int16/import_cfg_int16.txt.qunat_stats_config.txt

Processing Cnt :    0, InstCnt :    0 /work/ti-processor-sdk-rtos-j784s4-evm-10_01_00_04/c7x-mma-tidl/ti_dl/test/testvecs/abc/artifacts_int16/tidl_net_abc.bin!
TIDL_RT: Set default TIDLRT tensor done
TIDL_RT: Set default TIDLRT tensor done
TIDL_RT: Set default TIDLRT tensor done
       32768,      0.031 0x55de6347ad80
       32768,      0.031 0x55de63482e00
       65536,      0.062 0x55de6348ae80
Skipping static gen-set function==============================================] 100 %
TIDL_process is started with handle : 0x55de6344e200 
TIDL_activate is called with handle : 0x55de6344e200 - Copying handle of size 20144 from 0x55de6344e200 to 0x55de63458400 
Coreid 0 Layerid to execute = 0 
Core 0 Alg Process for Layer # -    0, layer type 0
Coreid 0 Layerid to execute = 1 
Core 0 Alg Process for Layer # -    1, layer type 0
Coreid 0 Layerid to execute = 2 
Core 0 Alg Process for Layer # -    2, layer type 30
Processing Layer # -    2
Core 0 End of Layer # -    2 with outPtrs[0] = 0x55de6348ae80
Coreid 0 Layerid to execute = 3 
Core 0 Alg Process for Layer # -    3, layer type 0
Coreid 0 Layerid to execute = -1 
TIDL_process is completed with handle : 0x55de6344e200 
Skipping static gen-set function
TIDL_deactivate is called with handle : 0x55de6344e200 - Copying handle of size 20144 from 0x55de63458400 to 0x55de6344e200 


------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------
Empty prototxt path, running calibration
Num of Layer Detected :   4 

--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

  Num|TIDL Layer Name               |Out Data Name                                     |Group |#Ins  |#Outs |Inbuf Ids                       |Outbuf Id |In NCHW                             |Out NCHW                            |MACS       |

--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

    0|TIDL_DataLayer                |input1                                            |     0|    -1|     1|  x   x   x   x   x   x   x   x |  0       |       0        0        0        0        0        0 |       1        1        1        3       32       32 |         0 |

    1|TIDL_DataLayer                |input2                                            |     0|    -1|     1|  x   x   x   x   x   x   x   x |  1       |       0        0        0        0        0        0 |       1        1        1        3       32       32 |         0 |

    2|TIDL_CustomLayer              |output                                            |     0|     2|     1|  0   1   x   x   x   x   x   x |  2       |       1        1        1        3       32       32 |       1        1        1        3       32       32 |         0 |

    3|TIDL_DataLayer                |output                                            |     0|     1|    -1|  2   x   x   x   x   x   x   x |  0       |       1        1        1        3       32       32 |       0        0        0        0        0        0 |         0 |

--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

Total Giga Macs : 0.0000

--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

cd /work/ti-processor-sdk-rtos-j784s4-evm-10_01_00_04/c7x-mma-tidl/ti_dl/test && ./PC_dsp_test_dl_algo.out s:/work/ti-processor-sdk-rtos-j784s4-evm-10_01_00_04/c7x-mma-tidl/ti_dl/test/testvecs/abc/artifacts_int16/import_cfg_int16.txt.qunat_stats_config.txt
Input : dataId=0, name=input1, elementType 3, scale=0.093457, zero point=0, layout=0
Input : dataId=1, name=input2, elementType 3, scale=0.100531, zero point=0, layout=0
Ouput : dataId=2, name=output, elementType 3, scale=1.000000, zero point=0, layout=0 
     22999616,     21.934 0x7f368f076010
worstCaseDelay for Pre-emption is 0.0000000 
Network File Read done
Calling algAlloc
TIDL_initDebugTraceParams Done 

--------------------------------------------
TIDL Memory size requiement (record wise):
MemRecNum   , Space               , Attribute   , Alignment   , Size(KBytes), BasePtr     
0           , DDR Cacheable       , Persistent  ,  128, 19.67   , 0x00000000
1           , DDR Cacheable       , Persistent  ,  128, 0.65    , 0x00000000
2           , DDR Cacheable       , Scratch     ,  128, 16.00   , 0x00000000
3           , DDR Cacheable       , Scratch     ,  128, 4.00    , 0x00000000
4           , DDR Cacheable       , Scratch     ,  128, 56.00   , 0x00000000
5           , DDR Cacheable       , Persistent  ,  128, 320.50  , 0x00000000
6           , DDR Cacheable       , Scratch     ,  128, 0.50    , 0x00000000
7           , DDR Cacheable       , Scratch     ,  128, 0.12    , 0x00000000
8           , DDR Cacheable       , Scratch     ,  128, 0.25    , 0x00000000
9           , DDR Cacheable       , Scratch     ,  128, 15.00   , 0x00000000
10          , DDR Cacheable       , Persistent  ,  128, 255.59  , 0x00000000
11          , DDR Cacheable       , Scratch     ,  128, 512.25  , 0x00000000
12          , DDR Cacheable       , Persistent  ,  128, 0.12    , 0x00000000
13          , DDR Cacheable       , Persistent  ,  128, 22460.69, 0x00000000
14          , DDR Cacheable       , Persistent  ,  128, 0.00    , 0x00000000
15          , DDR Cacheable       , Persistent  ,  128, 0.12    , 0x00000000
--------------------------------------------
Total memory size requirement (space wise):
Mem Space , Size(KBytes)
DDR Cacheable, 23661.47
--------------------------------------------
NOTE: Memory requirement in host emulation can be different from the same on EVM
      To get the actual TIDL memory requirement make sure to run on EVM with 
      debugTraceLevel = 2

--------------------------------------------
Num,    Space,     SizeinBytes,   SineInMB
   0,    17,        20144,      0.019 0x55be669c2200
   1,    17,          664,      0.001 0x55be669c1280
   2,    17,        16384,      0.016 0x55be669c7200
   3,    17,         4096,      0.004 0x55be669cb280
   4,    17,        57344,      0.055 0x55be669cc380
   5,    17,       328196,      0.313 0x7f368f025080
   6,    17,          512,      0.000 0x55be669da400
   7,    17,          128,      0.000 0x55be669da700
   8,    17,          256,      0.000 0x55be669da800
   9,    17,        15360,      0.015 0x55be669daa00
  10,    17,       261720,      0.250 0x7f368efe5080
  11,    17,       524544,      0.500 0x7f368ef64080
  12,    17,          128,      0.000 0x55be669de680
  13,    17,     22999744,     21.934 0x7f368d974080
  14,    17,            1,      0.000 0x55be669de800
  15,    17,          128,      0.000 0x55be669de880
Total External Memory (DDR) Size =     24229349,     23.107 
TIDL init call from ivision API 

--------------------------------------------
TIDL Memory size requiement (record wise):
MemRecNum   , Space               , Attribute   , Alignment   , Size(KBytes), BasePtr     
0           , DDR Cacheable       , Persistent  ,  128, 19.67   , 0x669c2200
1           , DDR Cacheable       , Persistent  ,  128, 0.65    , 0x669c1280
2           , DDR Cacheable       , Scratch     ,  128, 16.00   , 0x669c7200
3           , DDR Cacheable       , Scratch     ,  128, 4.00    , 0x669cb280
4           , DDR Cacheable       , Scratch     ,  128, 56.00   , 0x669cc380
5           , DDR Cacheable       , Persistent  ,  128, 320.50  , 0x8f025080
6           , DDR Cacheable       , Scratch     ,  128, 0.50    , 0x669da400
7           , DDR Cacheable       , Scratch     ,  128, 0.12    , 0x669da700
8           , DDR Cacheable       , Scratch     ,  128, 0.25    , 0x669da800
9           , DDR Cacheable       , Scratch     ,  128, 15.00   , 0x669daa00
10          , DDR Cacheable       , Persistent  ,  128, 255.59  , 0x8efe5080
11          , DDR Cacheable       , Scratch     ,  128, 512.25  , 0x8ef64080
12          , DDR Cacheable       , Persistent  ,  128, 0.12    , 0x669de680
13          , DDR Cacheable       , Persistent  ,  128, 22460.69, 0x8d974080
14          , DDR Cacheable       , Persistent  ,  128, 0.00    , 0x669de800
15          , DDR Cacheable       , Persistent  ,  128, 0.12    , 0x669de880
--------------------------------------------
Total memory size requirement (space wise):
Mem Space , Size(KBytes)
DDR Cacheable, 23661.47
--------------------------------------------
NOTE: Memory requirement in host emulation can be different from the same on EVM
      To get the actual TIDL memory requirement make sure to run on EVM with 
      debugTraceLevel = 2

--------------------------------------------
Alg Init for Layer # -    2
PREEMPTION: Adding a new priority object for targetPriority = 0, handle = 0x55be669c2200
PREEMPTION: Now total number of priority objects = 1 at priorityId = 0,    with new memRec of base = 0x55be669de680 and size = 128
PREEMPTION: Requesting context memory addr for handle 0x55be669c2200, return Addr = 0x55be42851a58
 Freeing memory for user provided Net

 Instance created for  /work/ti-processor-sdk-rtos-j784s4-evm-10_01_00_04/c7x-mma-tidl/ti_dl/test/testvecs/abc/artifacts_int16/import_cfg_int16.txt.qunat_stats_config.txt

Processing Cnt :    0, InstCnt :    0 /work/ti-processor-sdk-rtos-j784s4-evm-10_01_00_04/c7x-mma-tidl/ti_dl/test/testvecs/abc/artifacts_int16/tidl_net_abc.bin!
TIDL_RT: Set default TIDLRT tensor done
TIDL_RT: Set default TIDLRT tensor done
TIDL_RT: Set default TIDLRT tensor done
       16384,      0.016 0x55be669e7580
       16384,      0.016 0x55be669eb600
       16384,      0.016 0x55be669ef680
Skipping static gen-set function==============================================] 100 %
TIDL_process is started with handle : 0x55be669c2200 
TIDL_activate is called with handle : 0x55be669c2200 - Copying handle of size 20144 from 0x55be669c2200 to 0x55be669cc400 
Coreid 0 Layerid to execute = 0 
Core 0 Alg Process for Layer # -    0, layer type 0
Coreid 0 Layerid to execute = 1 
Core 0 Alg Process for Layer # -    1, layer type 0
Coreid 0 Layerid to execute = 2 
Core 0 Alg Process for Layer # -    2, layer type 30
Processing Layer # -    2
Core 0 End of Layer # -    2 with outPtrs[0] = 0x55be669ef680
Coreid 0 Layerid to execute = 3 
Core 0 Alg Process for Layer # -    3, layer type 0
Coreid 0 Layerid to execute = -1 
TIDL_process is completed with handle : 0x55be669c2200 
Skipping static gen-set function
TIDL_deactivate is called with handle : 0x55be669c2200 - Copying handle of size 20144 from 0x55be669cc400 to 0x55be669c2200 


Empty prototxt path, running calibration
Num of Layer Detected :   4 

--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

  Num|TIDL Layer Name               |Out Data Name                                     |Group |#Ins  |#Outs |Inbuf Ids                       |Outbuf Id |In NCHW                             |Out NCHW                            |MACS       |

--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

    0|TIDL_DataLayer                |input1                                            |     0|    -1|     1|  x   x   x   x   x   x   x   x |  0       |       0        0        0        0        0        0 |       1        1        1        3       32       32 |         0 |

    1|TIDL_DataLayer                |input2                                            |     0|    -1|     1|  x   x   x   x   x   x   x   x |  1       |       0        0        0        0        0        0 |       1        1        1        3       32       32 |         0 |

    2|TIDL_CustomLayer              |output                                            |     0|     2|     1|  0   1   x   x   x   x   x   x |  2       |       1        1        1        3       32       32 |       1        1        1        3       32       32 |         0 |

    3|TIDL_DataLayer                |output                                            |     0|     1|    -1|  2   x   x   x   x   x   x   x |  0       |       1        1        1        3       32       32 |       0        0        0        0        0        0 |         0 |

--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

Total Giga Macs : 0.0000

--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

==================== [Quantization & Calibration Completed] ====================

cp /work/ti-processor-sdk-rtos-j784s4-evm-10_01_00_04/c7x-mma-tidl/ti_dl/test/testvecs/config/import/device_config.cfg /work/ti-processor-sdk-rtos-j784s4-evm-10_01_00_04/c7x-mma-tidl/ti_dl/test/testvecs/abc/artifacts_int16/import_cfg_int16.txt.perf_sim_config.txt
cd /work/ti-processor-sdk-rtos-j784s4-evm-10_01_00_04/c7x-mma-tidl/ti_dl/utils/perfsim && ./ti_cnnperfsim.out /work/ti-processor-sdk-rtos-j784s4-evm-10_01_00_04/c7x-mma-tidl/ti_dl/test/testvecs/abc/artifacts_int16/import_cfg_int16.txt.perf_sim_config.txt 1601 0 2
========================== [Memory Planning Started] ==========================


------------------------- Network Compiler Traces ------------------------------
Successful Memory Allocation
Successful Workload Creation

========================= [Memory Planning Completed] =========================

Network buffer segments:
buf(0), offset(       0), size(    7488)
buf(1), offset(  824832), size(      64)
buf(2), offset(    7488), size(  817344)
buf(3), offset(  824896), size(  451020)
/work/ti-processor-sdk-rtos-j784s4-evm-10_01_00_04/c7x-mma-tidl/ti_dl/utils/tidlModelGraphviz/out/tidl_graphVisualiser.out ../../test/testvecs/abc/artifacts_int16/tidl_net_abc.bin
/work/ti-processor-sdk-rtos-j784s4-evm-10_01_00_04/c7x-mma-tidl/ti_dl/utils/tidlModelDump/out/tidl_dump.out -model ../../test/testvecs/abc/artifacts_int16/tidl_net_abc.bin -io ../../test/testvecs/abc/artifacts_int16/tidl_io_abc_1.bin -perfsim -o ../../test/testvecs/abc/artifacts_int16/tidl_net_abc.bin.txt
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**               TIDL Model Checker               **
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======================== Subgraph Compiled Successfully ========================


