------Layer #(Type) [Exec ID , Data ID] --[Ni x inW x inH] => [No x outW x outH] [Ni/G] [dataflowType] [preFetch, preFetchAlign, firstTransferRemainder, procSize, inPlaneSize] [dmaFreq] [dmaFreqWt] [kernelFreq] [In Data Ids] -----
------  1(TIDL_BatchNormLayer) [1, 1] --[1 x 1 x  1] => [1 x 1 x  1] *** [1] ***[ COL] ***[0, 0, 0, 2, 2]**** [1], [0],[1] -[0 ]---
  IN: DDR, DMA,      2(     2),      2(     2),    1(    1),    480(   1152),   0,        0 ||||  L2, DMA,      2(     2),      2(     2),    1(    1),     80(    128),   0,        0 
 OUT:MSMC, CPU,      2(     2),      2(     2),    2(    2),     80(    128),   0,        0 |||| DDR, DMA,      2(     2),      2(     2),    1(    1),    480(   1152),   0,      480 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
