C66xx_0: GEL Output: ******************************************************************************************************* C66xx_0: GEL Output: ********************************** GENERAL HW CONFIGURATION REGISTERS SNAPSHOT ****************************************************** C66xx_0: GEL Output: ******************************************************************************************************* C66xx_0: GEL Output: ********************************** Peripheral Settings Control Register (PER_SET_CNTL) ****************************************************** C66xx_0: GEL Output: SERDES0_PRBS_OVR[0] ---> ##Normal## (doesnt disable physical layer ENTX0 and ENRX0 control) C66xx_0: GEL Output: SERDES1_PRBS_OVR[1] ---> ##Normal## (doesnt disable physical layer ENTX0 and ENRX0 control) C66xx_0: GEL Output: SERDES2_PRBS_OVR[2] ---> ##Normal## (doesnt disable physical layer ENTX0 and ENRX0 control) C66xx_0: GEL Output: SERDES3_PRBS_OVR[3] ---> ##Normal## (doesnt disable physical layer ENTX0 and ENRX0 control) C66xx_0: GEL Output: PRESCALER_SELECT[7:4] ---> Sets the internal clock frequency Min 44.7 and Max 89.5 C66xx_0: GEL Output: CBA_TRANS_PRI[11:9] ---> 4 C66xx_0: GEL Output: TX_PRI0_WM[14:12] ---> 8, 7, 6, 5, 4 C66xx_0: GEL Output: TX_PRI1_WM[14:12] ---> 8, 7, 6, 5, 4, 3 C66xx_0: GEL Output: TX_PRI2_WM[14:12] ---> 8, 7, 6, 5, 4, 3, 2 C66xx_0: GEL Output: PROMOTE_DIS[24] ---> ##NORMAL## C66xx_0: GEL Output: LEND_SWAP_MODE[23:22] ---> Mode A C66xx_0: GEL Output: BOOT_COMPLETE[24] ---> Write to read-only registers **DISABLED** C66xx_0: GEL Output: LOG_TGT_ID_DIS[27] ---> All non-matching packets are ##DESTROYED## C66xx_0: GEL Output: LEND_SWAP_MODE[29:28] ---> Mode A C66xx_0: GEL Output: LEND_SWAP_MODE[31:30] ---> Mode A C66xx_0: GEL Output: ********************************** Peripheral Settings Control Register 1 (PER_SET_CNTL1) ****************************************************** C66xx_0: GEL Output: SYS_CLK_SEL => TX0 is the source C66xx_0: GEL Output: LOOPBACK(Lane0) => ##Normal## operation C66xx_0: GEL Output: LOOPBACK(Lane1) => ##Normal## operation C66xx_0: GEL Output: LOOPBACK(Lane2) => ##Normal## operation C66xx_0: GEL Output: LOOPBACK(Lane3) => ##Normal## operation C66xx_0: GEL Output: COS_EN => Class of Service(COS) is **NOT A PART** of the segmentation context for the RXU C66xx_0: GEL Output: ********************************** RapidIO DEVICEID Registers Configuration ****************************************************** C66xx_0: GEL Output: RIO_DEVID0.16BNODEID ---> 0x0000 C66xx_0: GEL Output: RIO_DEVID0.8BNODEID ---> 0x00 C66xx_0: GEL Output: RIO_DEVID1.16BNODEID ---> 0x0000 C66xx_0: GEL Output: RIO_DEVID1.8BNODEID ---> 0x00 C66xx_0: GEL Output: RIO_DEVID2.16BNODEID ---> 0x0000 C66xx_0: GEL Output: RIO_DEVID2.8BNODEID ---> 0x00 C66xx_0: GEL Output: RIO_DEVID3.16BNODEID ---> 0x0000 C66xx_0: GEL Output: RIO_DEVID3.8BNODEID ---> 0x00 C66xx_0: GEL Output: RIO_DEVID4.16BNODEID ---> 0x0000 C66xx_0: GEL Output: RIO_DEVID4.8BNODEID ---> 0x00 C66xx_0: GEL Output: RIO_DEVID5.16BNODEID ---> 0x0000 C66xx_0: GEL Output: RIO_DEVID5.8BNODEID ---> 0x00 C66xx_0: GEL Output: RIO_DEVID6.16BNODEID ---> 0x0000 C66xx_0: GEL Output: RIO_DEVID6.8BNODEID ---> 0x00 C66xx_0: GEL Output: RIO_DEVID7.16BNODEID ---> 0x0000 C66xx_0: GEL Output: RIO_DEVID7.8BNODEID ---> 0x00 C66xx_0: GEL Output: RIO_DEVID8.16BNODEID ---> 0x0000 C66xx_0: GEL Output: RIO_DEVID8.8BNODEID ---> 0x00 C66xx_0: GEL Output: RIO_DEVID9.16BNODEID ---> 0x0000 C66xx_0: GEL Output: RIO_DEVID9.8BNODEID ---> 0x00 C66xx_0: GEL Output: RIO_DEVID10.16BNODEID ---> 0x0000 C66xx_0: GEL Output: RIO_DEVID10.8BNODEID ---> 0x00 C66xx_0: GEL Output: RIO_DEVID11.16BNODEID ---> 0x0000 C66xx_0: GEL Output: RIO_DEVID11.8BNODEID ---> 0x00 C66xx_0: GEL Output: RIO_DEVID12.16BNODEID ---> 0x0000 C66xx_0: GEL Output: RIO_DEVID12.8BNODEID ---> 0x00 C66xx_0: GEL Output: RIO_DEVID13.16BNODEID ---> 0x0000 C66xx_0: GEL Output: RIO_DEVID13.8BNODEID ---> 0x00 C66xx_0: GEL Output: RIO_DEVID14.16BNODEID ---> 0x0000 C66xx_0: GEL Output: RIO_DEVID14.8BNODEID ---> 0x00 C66xx_0: GEL Output: RIO_DEVID15.16BNODEID ---> 0x0000 C66xx_0: GEL Output: RIO_DEVID15.8BNODEID ---> 0x00 C66xx_0: GEL Output: ********************************** RapidIO MULTI_ID Registers Configuration ****************************************************** C66xx_0: GEL Output: RIO_MULT_ID1.16BNODEID ---> 0xFFFF C66xx_0: GEL Output: RIO_MULT_ID1.8BNODEID ---> 0xFF C66xx_0: GEL Output: RIO_MULT_ID2.16BNODEID ---> 0xFFFF C66xx_0: GEL Output: RIO_MULT_ID2.8BNODEID ---> 0xFF C66xx_0: GEL Output: RIO_MULT_ID3.16BNODEID ---> 0xFFFF C66xx_0: GEL Output: RIO_MULT_ID3.8BNODEID ---> 0xFF C66xx_0: GEL Output: RIO_MULT_ID4.16BNODEID ---> 0xFFFF C66xx_0: GEL Output: RIO_MULT_ID4.8BNODEID ---> 0xFF C66xx_0: GEL Output: RIO_MULT_ID5.16BNODEID ---> 0xFFFF C66xx_0: GEL Output: RIO_MULT_ID5.8BNODEID ---> 0xFF C66xx_0: GEL Output: RIO_MULT_ID6.16BNODEID ---> 0xFFFF C66xx_0: GEL Output: RIO_MULT_ID6.8BNODEID ---> 0xFF C66xx_0: GEL Output: RIO_MULT_ID7.16BNODEID ---> 0xFFFF C66xx_0: GEL Output: RIO_MULT_ID7.8BNODEID ---> 0xFF C66xx_0: GEL Output: RIO_MULT_ID8.16BNODEID ---> 0xFFFF C66xx_0: GEL Output: RIO_MULT_ID8.8BNODEID ---> 0xFF C66xx_0: GEL Output: ********************************** Peripheral Global Enable Register (GBL_EN) ****************************************************** C66xx_0: GEL Output: EN[0] ---> 0x00000001 => The peripheral is to be ##ENABLED## C66xx_0: GEL Output: ********************************** Block n Enable Register (BLKn_EN) ****************************************************** C66xx_0: GEL Output: Block0 enable[0] ---> 0x00000001 => 'set of memory-mapped registers (MMRs) for the SRIO peripheral' is to be ##ENABLED## with its clock running. C66xx_0: GEL Output: Block1 enable[0] ---> 0x00000001 => Load/Store module(LSU) is to be ##ENABLED## with its clock running. C66xx_0: GEL Output: Block2 enable[0] ---> 0x00000001 => memory access unit (MAU) is to be ##ENABLED## with its clock running. C66xx_0: GEL Output: Block3 enable[0] ---> 0x00000001 => message transmit unit (TXU) is to be ##ENABLED## with its clock running. C66xx_0: GEL Output: Block4 enable[0] ---> 0x00000001 => message receive unit (RXU) is to be ##ENABLED## with its clock running. C66xx_0: GEL Output: Block5 enable[0] ---> 0x00000001 => SRIO port 0 is to be ##ENABLED## with its clock running. C66xx_0: GEL Output: Block6 enable[0] ---> 0x00000001 => SRIO port 1 is to be ##ENABLED## with its clock running. C66xx_0: GEL Output: Block7 enable[0] ---> 0x00000001 => SRIO port 2 is to be ##ENABLED## with its clock running. C66xx_0: GEL Output: Block8 enable[0] ---> 0x00000001 => SRIO port 3 is to be ##ENABLED## with its clock running. C66xx_0: GEL Output: Block9 enable[0] ---> 0x00000001 => Block9(TODO:add block descrip) is to be ##ENABLED## with its clock running. C66xx_0: GEL Output: ********************************** Peripheral Identification Register (PID) ****************************************************** C66xx_0: GEL Output: MINOR[5:0] (Minor revision ID) ---> 0x00000001 C66xx_0: GEL Output: CUSTOM[7:6] (Custom revision ID) ---> 0x00000000 C66xx_0: GEL Output: MAJOR[10:8] (Major revision ID) ---> 0x00000001 C66xx_0: GEL Output: RTL[15:11] (RTL revision ID) ---> 0x00000004 C66xx_0: GEL Output: FUNC[27:16] (Peripheral Functional class) ---> 0x000004AB C66xx_0: GEL Output: SCHEME[31:30] (Peripheral scheme field. Fixed to 0x1) ---> 0x00000001 C66xx_0: GEL Output: ********************************** Peripheral Control Register (PCR) ****************************************************** C66xx_0: GEL Output: LOCAL_DIS[3] ---> 0x00000000 => Local RX traffic is **DISCARDED** C66xx_0: GEL Output: PEREN[2] ---> 0x00000001 => Data flow control is ##ENABLED## C66xx_0: GEL Output: SOFT[1] ---> 0x00000000 => Hard stop. All status registers are frozen in default state. (This mode is not supported on the SRIO peripheral.) C66xx_0: GEL Output: FREE[0] ---> 0x00000001 => Free run. Peripheral ignores the emulation suspend signal and functions normally C66xx_0: GEL Output: ******************************************************************************************************* C66xx_0: GEL Output: ********************************** PACKET FORWARDING AND FLOW CONTROL REGISTERS SNAPSHOT ****************************************************** C66xx_0: GEL Output: ******************************************************************************************************* C66xx_0: GEL Output: ********************************** Packet Forwarding Register n for 16-Bit Device IDs (PF_16B_CNTLn) ****************************************************** C66xx_0: GEL Output: Packets received with devid in the range: 0xFFFF to 0xFFFF are forwarded to Port3 C66xx_0: GEL Output: Packets received with devid in the range: 0xFFFF to 0xFFFF are forwarded to Port3 C66xx_0: GEL Output: Packets received with devid in the range: 0xFFFF to 0xFFFF are forwarded to Port3 C66xx_0: GEL Output: Packets received with devid in the range: 0xFFFF to 0xFFFF are forwarded to Port3 C66xx_0: GEL Output: Packets received with devid in the range: 0xFFFF to 0xFFFF are forwarded to Port3 C66xx_0: GEL Output: Packets received with devid in the range: 0xFFFF to 0xFFFF are forwarded to Port3 C66xx_0: GEL Output: Packets received with devid in the range: 0xFFFF to 0xFFFF are forwarded to Port3 C66xx_0: GEL Output: Packets received with devid in the range: 0xFFFF to 0xFFFF are forwarded to Port3 C66xx_0: GEL Output: ********************************** Packet Forwarding Register n for 8-Bit Device IDs (PF_8B_CNTLn) ****************************************************** C66xx_0: GEL Output: Packets received with devid in the range: 0xFF to 0xFF are forwarded to Port3 C66xx_0: GEL Output: Packets received with devid in the range: 0xFF to 0xFF are forwarded to Port3 C66xx_0: GEL Output: Packets received with devid in the range: 0xFF to 0xFF are forwarded to Port3 C66xx_0: GEL Output: Packets received with devid in the range: 0xFF to 0xFF are forwarded to Port3 C66xx_0: GEL Output: Packets received with devid in the range: 0xFF to 0xFF are forwarded to Port3 C66xx_0: GEL Output: Packets received with devid in the range: 0xFF to 0xFF are forwarded to Port3 C66xx_0: GEL Output: Packets received with devid in the range: 0xFF to 0xFF are forwarded to Port3 C66xx_0: GEL Output: Packets received with devid in the range: 0xFF to 0xFF are forwarded to Port3 C66xx_0: GEL Output: ********************************** Flow Control Table Entry Register n (FLOW_CNTLn) ****************************************************** C66xx_0: GEL Output: FLOW CNTRL CONFIG REG0: FLOW_CNTL_ID ---> 0x0000 ** TT => 16 bit device IDs C66xx_0: GEL Output: FLOW CNTRL CONFIG REG1: FLOW_CNTL_ID ---> 0x0000 ** TT => 16 bit device IDs C66xx_0: GEL Output: FLOW CNTRL CONFIG REG2: FLOW_CNTL_ID ---> 0x0000 ** TT => 16 bit device IDs C66xx_0: GEL Output: FLOW CNTRL CONFIG REG3: FLOW_CNTL_ID ---> 0x0000 ** TT => 16 bit device IDs C66xx_0: GEL Output: FLOW CNTRL CONFIG REG4: FLOW_CNTL_ID ---> 0x0000 ** TT => 16 bit device IDs C66xx_0: GEL Output: FLOW CNTRL CONFIG REG5: FLOW_CNTL_ID ---> 0x0000 ** TT => 16 bit device IDs C66xx_0: GEL Output: FLOW CNTRL CONFIG REG6: FLOW_CNTL_ID ---> 0x0000 ** TT => 16 bit device IDs C66xx_0: GEL Output: FLOW CNTRL CONFIG REG7: FLOW_CNTL_ID ---> 0x0000 ** TT => 16 bit device IDs C66xx_0: GEL Output: FLOW CNTRL CONFIG REG8: FLOW_CNTL_ID ---> 0x0000 ** TT => 16 bit device IDs C66xx_0: GEL Output: FLOW CNTRL CONFIG REG9: FLOW_CNTL_ID ---> 0x0000 ** TT => 16 bit device IDs C66xx_0: GEL Output: FLOW CNTRL CONFIG REG10: FLOW_CNTL_ID ---> 0x0000 ** TT => 16 bit device IDs C66xx_0: GEL Output: FLOW CNTRL CONFIG REG11: FLOW_CNTL_ID ---> 0x0000 ** TT => 16 bit device IDs C66xx_0: GEL Output: FLOW CNTRL CONFIG REG12: FLOW_CNTL_ID ---> 0x0000 ** TT => 16 bit device IDs C66xx_0: GEL Output: FLOW CNTRL CONFIG REG13: FLOW_CNTL_ID ---> 0x0000 ** TT => 16 bit device IDs C66xx_0: GEL Output: FLOW CNTRL CONFIG REG14: FLOW_CNTL_ID ---> 0x0000 ** TT => 16 bit device IDs C66xx_0: GEL Output: FLOW CNTRL CONFIG REG15: FLOW_CNTL_ID ---> 0x0000 ** TT => 16 bit device IDs C66xx_0: GEL Output: ******************************************************************************************************* C66xx_0: GEL Output: ********************************** PHYSICAL LAYER REGISTERS SNAPSHOT ****************************************************** C66xx_0: GEL Output: ******************************************************************************************************* C66xx_0: GEL Output: ********************************** Device Identity CAR (DEV_ID) ****************************************************** C66xx_0: GEL Output: DEVICE_VENDORIDENTITY[15:0] ---> 0x00000030 C66xx_0: GEL Output: DEVICEIDENTITY[31:16] ---> 0x0000BEEF C66xx_0: GEL Output: ********************************** Device Information CAR (DEV_INFO) ****************************************************** C66xx_0: GEL Output: DEVICEREV[31:0] ---> 0x00000000 C66xx_0: GEL Output: ********************************** Assembly Identity CAR (ASBLY_ID) ****************************************************** C66xx_0: GEL Output: ASSY_VENDORIDENTITY[15:0] ---> 0x00000030 C66xx_0: GEL Output: ASSY_IDENTITY[31:16] ---> 0x00000000 C66xx_0: GEL Output: ********************************** Assembly Information CAR (ASBLY_INFO) ****************************************************** C66xx_0: GEL Output: EXTENDEDFEATURESPTR[15:0] ---> 0x00000100 C66xx_0: GEL Output: ASSYREV[31:16] ---> 0x00000000 C66xx_0: GEL Output: ********************************** Processing Element Features CAR (PE_FEAT) ****************************************************** C66xx_0: GEL Output: EXTENDED_ADDRESSING_SUPPORT[2:0] ---> 0x00000001 C66xx_0: GEL Output: EXTENDED_FEATURES[3] ---> 0x00000001 C66xx_0: GEL Output: LARGE_SUPPORT[4] ---> 0x00000001 C66xx_0: GEL Output: CRF_SUPPORT[5] ---> 0x00000000 C66xx_0: GEL Output: RETRANSMIT_SUPPRESS[6] ---> 0x00000000 C66xx_0: GEL Output: FLOW_CONTROL_SUPPORT[7] ---> 0x00000001 C66xx_0: GEL Output: SWITCH[28] ---> 0x00000000 C66xx_0: GEL Output: PROCESSOR[29] ---> 0x00000001 C66xx_0: GEL Output: MEMORY[30] ---> 0x00000000 C66xx_0: GEL Output: BRIDGE[31] ---> 0x00000000 C66xx_0: GEL Output: ********************************** Switch Port Information (SW_PORT) ****************************************************** C66xx_0: GEL Output: PORT_NUM ---> 0 C66xx_0: GEL Output: PORT_TOTAL ---> 4 RIO Ports C66xx_0: GEL Output: ********************************** Source Operations CAR (SRC_OP) ****************************************************** C66xx_0: GEL Output: IMPLMNT_DEFINED_1[1:0] ---> 0x00000000 C66xx_0: GEL Output: PORT_WRITE[2] ---> 0x00000001 C66xx_0: GEL Output: ATOMIC_CLEAR[4] ---> 0x00000001 C66xx_0: GEL Output: ATOMIC_SET[5] ---> 0x00000001 C66xx_0: GEL Output: ATOMIC_DCRMNT[6] ---> 0x00000001 C66xx_0: GEL Output: ATOMIC_INCRMNT[7] ---> 0x00000001 C66xx_0: GEL Output: ATOMIC_TEST_AND_SWAP[8] ---> 0x00000001 C66xx_0: GEL Output: DOORBELL[10] ---> 0x00000001 C66xx_0: GEL Output: DATA_MESS[11] ---> 0x00000001 C66xx_0: GEL Output: WRITE_WITH_RESP[12] ---> 0x00000001 C66xx_0: GEL Output: STREAM_WRITE[13] ---> 0x00000001 C66xx_0: GEL Output: WRITE[14] ---> 0x00000001 C66xx_0: GEL Output: READ[15] ---> 0x00000001 C66xx_0: GEL Output: IMPLMNT_DEFINED_2[17:16] ---> 0x00000000 C66xx_0: GEL Output: ********************************** Destination Operations CAR (DEST_OP) ****************************************************** C66xx_0: GEL Output: IMPLMNT_DEFINED_1[1:0] ---> 0x00000000 C66xx_0: GEL Output: PORT_WRITE[2] ---> 0x00000001 C66xx_0: GEL Output: ATOMIC_CLEAR[4] ---> 0x00000000 C66xx_0: GEL Output: ATOMIC_SET[5] ---> 0x00000000 C66xx_0: GEL Output: ATOMIC_DCRMNT[6] ---> 0x00000000 C66xx_0: GEL Output: ATOMIC_INCRMNT[7] ---> 0x00000000 C66xx_0: GEL Output: ATOMIC_TEST_AND_SWAP[8] ---> 0x00000000 C66xx_0: GEL Output: DOORBELL[10] ---> 0x00000001 C66xx_0: GEL Output: DATA_MESS[11] ---> 0x00000001 C66xx_0: GEL Output: WRITE_WITH_RESP[12] ---> 0x00000001 C66xx_0: GEL Output: STREAM_WRITE[13] ---> 0x00000001 C66xx_0: GEL Output: WRITE[14] ---> 0x00000001 C66xx_0: GEL Output: READ[15] ---> 0x00000001 C66xx_0: GEL Output: IMPLMNT_DEFINED_2[17:16] ---> 0x00000000 C66xx_0: GEL Output: ********************************** Local Configuration Space Base Address 0 CSR (LCL_CFG_HBAR) ****************************************************** C66xx_0: GEL Output: LCSBA[30:0] ---> 0x50600001 C66xx_0: GEL Output: ********************************** Local Configuration Space Base Address 1 CSR (LCL_CFG_BAR) ****************************************************** C66xx_0: GEL Output: LCSBA[31:0] ---> 0x00000000 C66xx_0: GEL Output: ********************************** Base Device ID CSR (BASE_ID) ****************************************************** C66xx_0: GEL Output: LARGE_BASE_DEVICEID[15:0] ---> 0x0000BEEF C66xx_0: GEL Output: BASE_DEVICEID[23:16] ---> 0x000000AB C66xx_0: GEL Output: ********************************** Host Base Device ID Lock CSR (HOST_BASE_ID_LOCK) ****************************************************** C66xx_0: GEL Output: HOST_BASE_DEVICEID[15:0] ---> 0x0000BEEF C66xx_0: GEL Output: ********************************** Component Tag CSR (COMP_TAG) ****************************************************** C66xx_0: GEL Output: COMPONENT_TAG[31:0] ---> 0x00000000 C66xx_0: GEL Output: ********************************** 1x/4x LP Serial Port Maintenance Block Header Register (SP_MB_HEAD) ****************************************************** C66xx_0: GEL Output: EF_ID[15:0] ---> 0x00000002 C66xx_0: GEL Output: EF_PTR[31:16] ---> 0x00001000 C66xx_0: GEL Output: ******************************************************************************************************* C66xx_0: GEL Output: ********************************** COMMON PORT CONFIGURATION REGISTERS SNAPSHOT ****************************************************** C66xx_0: GEL Output: ******************************************************************************************************* C66xx_0: GEL Output: ********************************** Port Link Time-Out Control CSR (SP_LT_CTL) ****************************************************** C66xx_0: GEL Output: TVAL ---> 0.0 to 0.0 sec (srio_ip_clk - 312.5 MHz) C66xx_0: GEL Output: ********************************** Port Response Time-Out Control CSR (SP_RT_CTL) ****************************************************** C66xx_0: GEL Output: TIMEOUT_VALUE[31:8] ---> 0x00000000FF => 7650.0 ns C66xx_0: GEL Output: ********************************** Port General Control CSR (SP_GEN_CTL) ****************************************************** C66xx_0: GEL Output: DISCOVERED[29] ---> 0x00000000 => The device has not been previously discovered C66xx_0: GEL Output: MASTER_ENABLE[30] ---> 0x00000001 => Processing element can issue requests C66xx_0: GEL Output: HOST[31] ---> 0x00000000 => Agent or Slave device C66xx_0: GEL Output: ********************************** Port-Write Target Device ID CSR (PW_TGT_ID) ****************************************************** C66xx_0: GEL Output: ID_LARGE[15] ---> 0x00000000 => 8-bit device ID for port-write operation C66xx_0: GEL Output: DEVICEID[23:16] ---> 0x00000000 C66xx_0: GEL Output: DEVICEID_MSB[31:24] ---> 0x00000000 C66xx_0: GEL Output: *******************SRIO PORT0 CONFIGURATION ******************* C66xx_0: GEL Output: *******************Port0 Control CSR configuration******************* C66xx_0: GEL Output: SP0_CTL.PORT_TYPE[0] => This port is a ##SERIAL PORT## C66xx_0: GEL Output: SP0_CTL.PORT_LOCKOUT[1] => The port is ##ENABLED## to issue any packets C66xx_0: GEL Output: SP0_CTL.DROP_PACKET_ENABLE[2] => The output port ##CONTINUES TO## try to transmit packets that have been rejected due to transmission errors C66xx_0: GEL Output: SP0_CTL.STOP_PORT_FLD_ENC_ENABLE[3] => Even when the Output Failed-encountered bit is set, the port ##CONTINUES TO ATTEMPT## to transmit packets C66xx_0: GEL Output: SP0_CTL.MULTICAST_PARTICIPANT[19] => Multicast-event control symbols **CANNOT BE ACCEPTED** by this port C66xx_0: GEL Output: SP0_CTL.ERROR_CHECK_DISABLE[20] => RapidIO transmission error checking and recovery are ##ENABLED## C66xx_0: GEL Output: SP0_CTL.INPUT_PORT_ENABLE[21] => Port is ##ENABLED## to respond to any packet C66xx_0: GEL Output: SP0_CTL.OUTPUT_PORT_ENABLE[22] => The port is ##ENABLED## to issue any packets C66xx_0: GEL Output: SP0_CTL.PORT_DISABLE[23] => Port receivers/drivers are ##ENABLED## C66xx_0: GEL Output: SP0_CTL.OVER_PWIDTH[26:24] => No override C66xx_0: GEL Output: SP0_CTL.INIT_PWIDTH[29:27] => Four-lane port C66xx_0: GEL Output: SP0_CTL.PORT_WIDTH_BIT1[30] => 4x mode ##SUPPORTED## C66xx_0: GEL Output: SP0_CTL.PORT_WIDTH_BIT0[31] => 2x mode ##SUPPORTED## C66xx_0: GEL Output: ******************* Port0 Control2 CSR configuration ******************* C66xx_0: GEL Output: RTEC_EN => Remote transmit emphasis control is **DISABLED** C66xx_0: GEL Output: RTEC => The port **DOES NOT** support remote transmit emphasis adjustment in the connected port C66xx_0: GEL Output: D_SCRM_DIS => Transmit data scrambler and receive data descrambler are ##ENABLED## C66xx_0: GEL Output: INACT_EN => Lanes assigned to the port but not used by the port have their outputs **DISABLED** C66xx_0: GEL Output: GB_6p25_EN => 6.25 GBaud operation **DISABLED** C66xx_0: GEL Output: GB_6p25 => 6.25 GBaud operation ##SUPPORTED## C66xx_0: GEL Output: GB_5p0_EN => 5 GBaud operation **DISABLED** C66xx_0: GEL Output: GB_5p0 => 5 GBaud operation ##SUPPORTED## C66xx_0: GEL Output: GB_3p125_EN => 3.125 GBaud operation **DISABLED** C66xx_0: GEL Output: GB_3p125 => 3.125 GBaud operation ##SUPPORTED## C66xx_0: GEL Output: GB_2p5_EN => 2.5 GBaud operation **DISABLED** C66xx_0: GEL Output: GB_2p5 => 2.5 GBaud operation ##SUPPORTED## C66xx_0: GEL Output: GB_1p25_EN => 1.25 GBaud operation **DISABLED** C66xx_0: GEL Output: GB_1p25 => 1.25 GBaud operation ##SUPPORTED## C66xx_0: GEL Output: BAUD_DISC => Automatic baud rate discovery **NOT SUPPORTED** C66xx_0: GEL Output: BAUD_SEL => No rate selected C66xx_0: GEL Output: *******************Port0 Error Rate Enable CSR configuration******************* C66xx_0: GEL Output: SP0_RATE_EN.LINK_TIMEOUT_EN[0] => **DISABLE** error rate counting of link timeout errors C66xx_0: GEL Output: SP0_RATE_EN.UNSOLICITED_ACK_CNTL_SYM_EN[1] => **DISABLE** error rate counting of unsolicited acknowledge control symbols. C66xx_0: GEL Output: SP0_RATE_EN.DELINEATION_ERROR_EN[2] => **DISABLE** error rate counting of delineation errors C66xx_0: GEL Output: SP0_RATE_EN.PROTOCOL_ERROR_EN[4] => **DISABLE** error rate counting of protocol errors C66xx_0: GEL Output: SP0_RATE_EN.NON_OUTSTANDING_ACKID_EN[5] => **DISABLE** error rate counting of link-responses received with an ackID that is not outstanding. C66xx_0: GEL Output: SP0_RATE_EN.DSCRAM_LOS_EN[14] => **DISABLE** error rate counting of the loss of receiver de-scrambler synchronization C66xx_0: GEL Output: SP0_RATE_EN.RCVED_PKT_OVER_276B_EN[17] => **DISABLE** error rate counting of packets that exceed the maximum allowed size C66xx_0: GEL Output: SP0_RATE_EN.RCVED_PKT_WITH_BAD_CRC_EN[18] => **DISABLE** error rate counting of packets with a bad CRC values C66xx_0: GEL Output: SP0_RATE_EN.PKT_UNEXPECTED_ACKID_EN[19] => **DISABLE** error rate counting of packets with unexpected/out-of-sequence ackIDs C66xx_0: GEL Output: SP0_RATE_EN.RCVED_PKT_NOT_ACCPT_EN[20] => **DISABLE** error rate counting of received packet-not-accepted control symbols. C66xx_0: GEL Output: SP0_RATE_EN.CNTL_SYM_UNEXPECTED_ACKID_EN[21] => **DISABLE** error rate counting of an acknowledge control symbol with an unexpected ackID C66xx_0: GEL Output: SP0_RATE_EN.CORRUPT_CNTL_SYM_ENABLE[22] => **DISABLE** error rate counting of a corrupt control symbol C66xx_0: GEL Output: SP0_RATE_EN.EN_IMP_SPECIFIC[31] => **DISABLE** error rate counting of implementation specific errors C66xx_0: GEL Output: *******************Port0 Error Rate CSR configuration******************* C66xx_0: GEL Output: SP0_ERR_RATE.ERROR_RATE_BIAS[31:24] => Reserved C66xx_0: GEL Output: SP0_ERR_RATE.ERROR_RATE_RECOVERY[17:16] => Only count 2 errors & above C66xx_0: GEL Output: *******************Port0 Error Rate Threshold CSR configuration******************* C66xx_0: GEL Output: SP0_ERR_THRESH.ERROR_RATE_DEGRADED_THRESH[23:16] ---> 255 C66xx_0: GEL Output: SP0_ERR_THRESH.ERROR_RATE_FAILED_THRESH[31:24] ---> 255 C66xx_0: GEL Output: *******************SRIO PORT1 CONFIGURATION ******************* C66xx_0: GEL Output: *******************Port1 Control CSR configuration******************* C66xx_0: GEL Output: SP1_CTL.PORT_TYPE[0] => This port is a ##SERIAL PORT## C66xx_0: GEL Output: SP1_CTL.PORT_LOCKOUT[1] => The port is ##ENABLED## to issue any packets C66xx_0: GEL Output: SP1_CTL.DROP_PACKET_ENABLE[2] => The output port ##CONTINUES TO## try to transmit packets that have been rejected due to transmission errors C66xx_0: GEL Output: SP1_CTL.STOP_PORT_FLD_ENC_ENABLE[3] => Even when the Output Failed-encountered bit is set, the port ##CONTINUES TO ATTEMPT## to transmit packets C66xx_0: GEL Output: SP1_CTL.MULTICAST_PARTICIPANT[19] => Multicast-event control symbols **CANNOT BE ACCEPTED** by this port C66xx_0: GEL Output: SP1_CTL.ERROR_CHECK_DISABLE[20] => RapidIO transmission error checking and recovery are ##ENABLED## C66xx_0: GEL Output: SP1_CTL.INPUT_PORT_ENABLE[21] => Port is ##ENABLED## to respond to any packet C66xx_0: GEL Output: SP1_CTL.OUTPUT_PORT_ENABLE[22] => The port is ##ENABLED## to issue any packets C66xx_0: GEL Output: SP1_CTL.PORT_DISABLE[23] => Port receivers/drivers are ##ENABLED## C66xx_0: GEL Output: SP1_CTL.OVER_PWIDTH[26:24] => No override C66xx_0: GEL Output: SP1_CTL.INIT_PWIDTH[29:27] => Single-lane port, lane 0 C66xx_0: GEL Output: SP1_CTL.PORT_WIDTH_BIT1[30] => 4x mode **NOT SUPPORTED** C66xx_0: GEL Output: SP1_CTL.PORT_WIDTH_BIT0[31] => 2x mode **NOT SUPPORTED** C66xx_0: GEL Output: ******************* Port1 Control2 CSR configuration ******************* C66xx_0: GEL Output: RTEC_EN => Remote transmit emphasis control is **DISABLED** C66xx_0: GEL Output: RTEC => The port **DOES NOT** support remote transmit emphasis adjustment in the connected port C66xx_0: GEL Output: D_SCRM_DIS => Transmit data scrambler and receive data descrambler are ##ENABLED## C66xx_0: GEL Output: INACT_EN => Lanes assigned to the port but not used by the port have their outputs **DISABLED** C66xx_0: GEL Output: GB_6p25_EN => 6.25 GBaud operation **DISABLED** C66xx_0: GEL Output: GB_6p25 => 6.25 GBaud operation ##SUPPORTED## C66xx_0: GEL Output: GB_5p0_EN => 5 GBaud operation **DISABLED** C66xx_0: GEL Output: GB_5p0 => 5 GBaud operation ##SUPPORTED## C66xx_0: GEL Output: GB_3p125_EN => 3.125 GBaud operation **DISABLED** C66xx_0: GEL Output: GB_3p125 => 3.125 GBaud operation ##SUPPORTED## C66xx_0: GEL Output: GB_2p5_EN => 2.5 GBaud operation **DISABLED** C66xx_0: GEL Output: GB_2p5 => 2.5 GBaud operation ##SUPPORTED## C66xx_0: GEL Output: GB_1p25_EN => 1.25 GBaud operation **DISABLED** C66xx_0: GEL Output: GB_1p25 => 1.25 GBaud operation ##SUPPORTED## C66xx_0: GEL Output: BAUD_DISC => Automatic baud rate discovery **NOT SUPPORTED** C66xx_0: GEL Output: BAUD_SEL => No rate selected C66xx_0: GEL Output: *******************Port1 Error Rate Enable CSR configuration******************* C66xx_0: GEL Output: SP1_RATE_EN.LINK_TIMEOUT_EN[0] => **DISABLE** error rate counting of link timeout errors C66xx_0: GEL Output: SP1_RATE_EN.UNSOLICITED_ACK_CNTL_SYM_EN[1] => **DISABLE** error rate counting of unsolicited acknowledge control symbols. C66xx_0: GEL Output: SP1_RATE_EN.DELINEATION_ERROR_EN[2] => **DISABLE** error rate counting of delineation errors C66xx_0: GEL Output: SP1_RATE_EN.PROTOCOL_ERROR_EN[4] => **DISABLE** error rate counting of protocol errors C66xx_0: GEL Output: SP1_RATE_EN.NON_OUTSTANDING_ACKID_EN[5] => **DISABLE** error rate counting of link-responses received with an ackID that is not outstanding. C66xx_0: GEL Output: SP1_RATE_EN.DSCRAM_LOS_EN[14] => **DISABLE** error rate counting of the loss of receiver de-scrambler synchronization C66xx_0: GEL Output: SP1_RATE_EN.RCVED_PKT_OVER_276B_EN[17] => **DISABLE** error rate counting of packets that exceed the maximum allowed size C66xx_0: GEL Output: SP1_RATE_EN.RCVED_PKT_WITH_BAD_CRC_EN[18] => **DISABLE** error rate counting of packets with a bad CRC values C66xx_0: GEL Output: SP1_RATE_EN.PKT_UNEXPECTED_ACKID_EN[19] => **DISABLE** error rate counting of packets with unexpected/out-of-sequence ackIDs C66xx_0: GEL Output: SP1_RATE_EN.RCVED_PKT_NOT_ACCPT_EN[20] => **DISABLE** error rate counting of received packet-not-accepted control symbols. C66xx_0: GEL Output: SP1_RATE_EN.CNTL_SYM_UNEXPECTED_ACKID_EN[21] => **DISABLE** error rate counting of an acknowledge control symbol with an unexpected ackID C66xx_0: GEL Output: SP1_RATE_EN.CORRUPT_CNTL_SYM_ENABLE[22] => **DISABLE** error rate counting of a corrupt control symbol C66xx_0: GEL Output: SP1_RATE_EN.EN_IMP_SPECIFIC[31] => **DISABLE** error rate counting of implementation specific errors C66xx_0: GEL Output: *******************Port1 Error Rate CSR configuration******************* C66xx_0: GEL Output: SP1_ERR_RATE.ERROR_RATE_BIAS[31:24] => Reserved C66xx_0: GEL Output: SP1_ERR_RATE.ERROR_RATE_RECOVERY[17:16] => Only count 2 errors & above C66xx_0: GEL Output: *******************Port1 Error Rate Threshold CSR configuration******************* C66xx_0: GEL Output: SP1_ERR_THRESH.ERROR_RATE_DEGRADED_THRESH[23:16] ---> 255 C66xx_0: GEL Output: SP1_ERR_THRESH.ERROR_RATE_FAILED_THRESH[31:24] ---> 255 C66xx_0: GEL Output: *******************SRIO PORT2 CONFIGURATION ******************* C66xx_0: GEL Output: *******************Port2 Control CSR configuration******************* C66xx_0: GEL Output: SP2_CTL.PORT_TYPE[0] => This port is a ##SERIAL PORT## C66xx_0: GEL Output: SP2_CTL.PORT_LOCKOUT[1] => The port is ##ENABLED## to issue any packets C66xx_0: GEL Output: SP2_CTL.DROP_PACKET_ENABLE[2] => The output port ##CONTINUES TO## try to transmit packets that have been rejected due to transmission errors C66xx_0: GEL Output: SP2_CTL.STOP_PORT_FLD_ENC_ENABLE[3] => Even when the Output Failed-encountered bit is set, the port ##CONTINUES TO ATTEMPT## to transmit packets C66xx_0: GEL Output: SP2_CTL.MULTICAST_PARTICIPANT[19] => Multicast-event control symbols **CANNOT BE ACCEPTED** by this port C66xx_0: GEL Output: SP2_CTL.ERROR_CHECK_DISABLE[20] => RapidIO transmission error checking and recovery are ##ENABLED## C66xx_0: GEL Output: SP2_CTL.INPUT_PORT_ENABLE[21] => Port is ##ENABLED## to respond to any packet C66xx_0: GEL Output: SP2_CTL.OUTPUT_PORT_ENABLE[22] => The port is ##ENABLED## to issue any packets C66xx_0: GEL Output: SP2_CTL.PORT_DISABLE[23] => Port receivers/drivers are ##ENABLED## C66xx_0: GEL Output: SP2_CTL.OVER_PWIDTH[26:24] => No override C66xx_0: GEL Output: SP2_CTL.INIT_PWIDTH[29:27] => Single-lane port, lane 0 C66xx_0: GEL Output: SP2_CTL.PORT_WIDTH_BIT1[30] => 4x mode **NOT SUPPORTED** C66xx_0: GEL Output: SP2_CTL.PORT_WIDTH_BIT0[31] => 2x mode **NOT SUPPORTED** C66xx_0: GEL Output: ******************* Port2 Control2 CSR configuration ******************* C66xx_0: GEL Output: RTEC_EN => Remote transmit emphasis control is **DISABLED** C66xx_0: GEL Output: RTEC => The port **DOES NOT** support remote transmit emphasis adjustment in the connected port C66xx_0: GEL Output: D_SCRM_DIS => Transmit data scrambler and receive data descrambler are ##ENABLED## C66xx_0: GEL Output: INACT_EN => Lanes assigned to the port but not used by the port have their outputs **DISABLED** C66xx_0: GEL Output: GB_6p25_EN => 6.25 GBaud operation **DISABLED** C66xx_0: GEL Output: GB_6p25 => 6.25 GBaud operation ##SUPPORTED## C66xx_0: GEL Output: GB_5p0_EN => 5 GBaud operation **DISABLED** C66xx_0: GEL Output: GB_5p0 => 5 GBaud operation ##SUPPORTED## C66xx_0: GEL Output: GB_3p125_EN => 3.125 GBaud operation **DISABLED** C66xx_0: GEL Output: GB_3p125 => 3.125 GBaud operation ##SUPPORTED## C66xx_0: GEL Output: GB_2p5_EN => 2.5 GBaud operation **DISABLED** C66xx_0: GEL Output: GB_2p5 => 2.5 GBaud operation ##SUPPORTED## C66xx_0: GEL Output: GB_1p25_EN => 1.25 GBaud operation **DISABLED** C66xx_0: GEL Output: GB_1p25 => 1.25 GBaud operation ##SUPPORTED## C66xx_0: GEL Output: BAUD_DISC => Automatic baud rate discovery **NOT SUPPORTED** C66xx_0: GEL Output: BAUD_SEL => No rate selected C66xx_0: GEL Output: *******************Port2 Error Rate Enable CSR configuration******************* C66xx_0: GEL Output: SP2_RATE_EN.LINK_TIMEOUT_EN[0] => **DISABLE** error rate counting of link timeout errors C66xx_0: GEL Output: SP2_RATE_EN.UNSOLICITED_ACK_CNTL_SYM_EN[1] => **DISABLE** error rate counting of unsolicited acknowledge control symbols. C66xx_0: GEL Output: SP2_RATE_EN.DELINEATION_ERROR_EN[2] => **DISABLE** error rate counting of delineation errors C66xx_0: GEL Output: SP2_RATE_EN.PROTOCOL_ERROR_EN[4] => **DISABLE** error rate counting of protocol errors C66xx_0: GEL Output: SP2_RATE_EN.NON_OUTSTANDING_ACKID_EN[5] => **DISABLE** error rate counting of link-responses received with an ackID that is not outstanding. C66xx_0: GEL Output: SP2_RATE_EN.DSCRAM_LOS_EN[14] => **DISABLE** error rate counting of the loss of receiver de-scrambler synchronization C66xx_0: GEL Output: SP2_RATE_EN.RCVED_PKT_OVER_276B_EN[17] => **DISABLE** error rate counting of packets that exceed the maximum allowed size C66xx_0: GEL Output: SP2_RATE_EN.RCVED_PKT_WITH_BAD_CRC_EN[18] => **DISABLE** error rate counting of packets with a bad CRC values C66xx_0: GEL Output: SP2_RATE_EN.PKT_UNEXPECTED_ACKID_EN[19] => **DISABLE** error rate counting of packets with unexpected/out-of-sequence ackIDs C66xx_0: GEL Output: SP2_RATE_EN.RCVED_PKT_NOT_ACCPT_EN[20] => **DISABLE** error rate counting of received packet-not-accepted control symbols. C66xx_0: GEL Output: SP2_RATE_EN.CNTL_SYM_UNEXPECTED_ACKID_EN[21] => **DISABLE** error rate counting of an acknowledge control symbol with an unexpected ackID C66xx_0: GEL Output: SP2_RATE_EN.CORRUPT_CNTL_SYM_ENABLE[22] => **DISABLE** error rate counting of a corrupt control symbol C66xx_0: GEL Output: SP2_RATE_EN.EN_IMP_SPECIFIC[31] => **DISABLE** error rate counting of implementation specific errors C66xx_0: GEL Output: *******************Port2 Error Rate CSR configuration******************* C66xx_0: GEL Output: SP2_ERR_RATE.ERROR_RATE_BIAS[31:24] => Reserved C66xx_0: GEL Output: SP2_ERR_RATE.ERROR_RATE_RECOVERY[17:16] => Only count 2 errors & above C66xx_0: GEL Output: *******************Port2 Error Rate Threshold CSR configuration******************* C66xx_0: GEL Output: SP2_ERR_THRESH.ERROR_RATE_DEGRADED_THRESH[23:16] ---> 255 C66xx_0: GEL Output: SP2_ERR_THRESH.ERROR_RATE_FAILED_THRESH[31:24] ---> 255 C66xx_0: GEL Output: *******************SRIO PORT3 CONFIGURATION ******************* C66xx_0: GEL Output: *******************Port3 Control CSR configuration******************* C66xx_0: GEL Output: SP3_CTL.PORT_TYPE[0] => This port is a ##SERIAL PORT## C66xx_0: GEL Output: SP3_CTL.PORT_LOCKOUT[1] => The port is ##ENABLED## to issue any packets C66xx_0: GEL Output: SP3_CTL.DROP_PACKET_ENABLE[2] => The output port ##CONTINUES TO## try to transmit packets that have been rejected due to transmission errors C66xx_0: GEL Output: SP3_CTL.STOP_PORT_FLD_ENC_ENABLE[3] => Even when the Output Failed-encountered bit is set, the port ##CONTINUES TO ATTEMPT## to transmit packets C66xx_0: GEL Output: SP3_CTL.MULTICAST_PARTICIPANT[19] => Multicast-event control symbols **CANNOT BE ACCEPTED** by this port C66xx_0: GEL Output: SP3_CTL.ERROR_CHECK_DISABLE[20] => RapidIO transmission error checking and recovery are ##ENABLED## C66xx_0: GEL Output: SP3_CTL.INPUT_PORT_ENABLE[21] => Port is ##ENABLED## to respond to any packet C66xx_0: GEL Output: SP3_CTL.OUTPUT_PORT_ENABLE[22] => The port is ##ENABLED## to issue any packets C66xx_0: GEL Output: SP3_CTL.PORT_DISABLE[23] => Port receivers/drivers are ##ENABLED## C66xx_0: GEL Output: SP3_CTL.OVER_PWIDTH[26:24] => No override C66xx_0: GEL Output: SP3_CTL.INIT_PWIDTH[29:27] => Single-lane port, lane 0 C66xx_0: GEL Output: SP3_CTL.PORT_WIDTH_BIT1[30] => 4x mode **NOT SUPPORTED** C66xx_0: GEL Output: SP3_CTL.PORT_WIDTH_BIT0[31] => 2x mode **NOT SUPPORTED** C66xx_0: GEL Output: ******************* Port3 Control2 CSR configuration ******************* C66xx_0: GEL Output: RTEC_EN => Remote transmit emphasis control is **DISABLED** C66xx_0: GEL Output: RTEC => The port **DOES NOT** support remote transmit emphasis adjustment in the connected port C66xx_0: GEL Output: D_SCRM_DIS => Transmit data scrambler and receive data descrambler are ##ENABLED## C66xx_0: GEL Output: INACT_EN => Lanes assigned to the port but not used by the port have their outputs **DISABLED** C66xx_0: GEL Output: GB_6p25_EN => 6.25 GBaud operation **DISABLED** C66xx_0: GEL Output: GB_6p25 => 6.25 GBaud operation ##SUPPORTED## C66xx_0: GEL Output: GB_5p0_EN => 5 GBaud operation **DISABLED** C66xx_0: GEL Output: GB_5p0 => 5 GBaud operation ##SUPPORTED## C66xx_0: GEL Output: GB_3p125_EN => 3.125 GBaud operation **DISABLED** C66xx_0: GEL Output: GB_3p125 => 3.125 GBaud operation ##SUPPORTED## C66xx_0: GEL Output: GB_2p5_EN => 2.5 GBaud operation **DISABLED** C66xx_0: GEL Output: GB_2p5 => 2.5 GBaud operation ##SUPPORTED## C66xx_0: GEL Output: GB_1p25_EN => 1.25 GBaud operation **DISABLED** C66xx_0: GEL Output: GB_1p25 => 1.25 GBaud operation ##SUPPORTED## C66xx_0: GEL Output: BAUD_DISC => Automatic baud rate discovery **NOT SUPPORTED** C66xx_0: GEL Output: BAUD_SEL => No rate selected C66xx_0: GEL Output: *******************Port3 Error Rate Enable CSR configuration******************* C66xx_0: GEL Output: SP3_RATE_EN.LINK_TIMEOUT_EN[0] => **DISABLE** error rate counting of link timeout errors C66xx_0: GEL Output: SP3_RATE_EN.UNSOLICITED_ACK_CNTL_SYM_EN[1] => **DISABLE** error rate counting of unsolicited acknowledge control symbols. C66xx_0: GEL Output: SP3_RATE_EN.DELINEATION_ERROR_EN[2] => **DISABLE** error rate counting of delineation errors C66xx_0: GEL Output: SP3_RATE_EN.PROTOCOL_ERROR_EN[4] => **DISABLE** error rate counting of protocol errors C66xx_0: GEL Output: SP3_RATE_EN.NON_OUTSTANDING_ACKID_EN[5] => **DISABLE** error rate counting of link-responses received with an ackID that is not outstanding. C66xx_0: GEL Output: SP3_RATE_EN.DSCRAM_LOS_EN[14] => **DISABLE** error rate counting of the loss of receiver de-scrambler synchronization C66xx_0: GEL Output: SP3_RATE_EN.RCVED_PKT_OVER_276B_EN[17] => **DISABLE** error rate counting of packets that exceed the maximum allowed size C66xx_0: GEL Output: SP3_RATE_EN.RCVED_PKT_WITH_BAD_CRC_EN[18] => **DISABLE** error rate counting of packets with a bad CRC values C66xx_0: GEL Output: SP3_RATE_EN.PKT_UNEXPECTED_ACKID_EN[19] => **DISABLE** error rate counting of packets with unexpected/out-of-sequence ackIDs C66xx_0: GEL Output: SP3_RATE_EN.RCVED_PKT_NOT_ACCPT_EN[20] => **DISABLE** error rate counting of received packet-not-accepted control symbols. C66xx_0: GEL Output: SP3_RATE_EN.CNTL_SYM_UNEXPECTED_ACKID_EN[21] => **DISABLE** error rate counting of an acknowledge control symbol with an unexpected ackID C66xx_0: GEL Output: SP3_RATE_EN.CORRUPT_CNTL_SYM_ENABLE[22] => **DISABLE** error rate counting of a corrupt control symbol C66xx_0: GEL Output: SP3_RATE_EN.EN_IMP_SPECIFIC[31] => **DISABLE** error rate counting of implementation specific errors C66xx_0: GEL Output: *******************Port3 Error Rate CSR configuration******************* C66xx_0: GEL Output: SP3_ERR_RATE.ERROR_RATE_BIAS[31:24] => Reserved C66xx_0: GEL Output: SP3_ERR_RATE.ERROR_RATE_RECOVERY[17:16] => Only count 2 errors & above C66xx_0: GEL Output: *******************Port3 Error Rate Threshold CSR configuration******************* C66xx_0: GEL Output: SP3_ERR_THRESH.ERROR_RATE_DEGRADED_THRESH[23:16] ---> 255 C66xx_0: GEL Output: SP3_ERR_THRESH.ERROR_RATE_FAILED_THRESH[31:24] ---> 255 C66xx_0: GEL Output: ********************************** Logical/Transport Layer Error Enable CSR (ERR_EN) ****************************************************** C66xx_0: GEL Output: RX_IO_SECURITY_ENABLE[6] => **DISABLE** reporting of attempt at unauthorized access to a memory location. C66xx_0: GEL Output: RX_CPPI_SECURITY_ENABLE[7] => **DISABLE** reporting of an attempt at unauthorized access to a RX queue C66xx_0: GEL Output: UNSUPPORTED_TRANS_ENABLE[22] => **DISABLE** reporting of an unsupported transaction error C66xx_0: GEL Output: UNSOLICITED_RESP_ENABLE[23] => **DISABLE** reporting of an unsolicited response error C66xx_0: GEL Output: PKT_RESP_TIMEOUT_ENABLE[24] => **DISABLE** reporting of a packet response time-out error C66xx_0: GEL Output: MSG_REQ_TIMEOUT_ENABLE[25] => **DISABLE** reporting of a message request time-out error C66xx_0: GEL Output: ILL_TRANS_DECODE_ENABLE[27] => **DISABLE** reporting of an illegal transaction decode error C66xx_0: GEL Output: ERR_MSG_FORMAT_ENABLE[28] => **DISABLE** reporting of a message format error C66xx_0: GEL Output: MSG_ERR_RESP_ENABLE[30] => **DISABLE** reporting of a message error response C66xx_0: GEL Output: IO_ERR_RESP_ENABLE[31] => **DISABLE** reporting of an IO error response C66xx_0: GEL Output: ********************************** Processing Element Logical Layer Control CSR (PE_LL_CTL) ****************************************************** C66xx_0: GEL Output: EXTENDED_ADDRESSING_CONTROL[8] => PE supports 34 bit addresses C66xx_0: GEL Output: *****************************SRIO HW Global Enable Status***************************** C66xx_0: GEL Output: Global enable status ---> 0x00000001 => The peripheral is enabled with all its clocks running C66xx_0: GEL Output: Block0 enable status ---> 0x00000001 => 'set of memory-mapped registers (MMRs) for the SRIO peripheral' is enabled with its clock running. C66xx_0: GEL Output: Block1 enable status ---> 0x00000001 => Load/Store module(LSU) is enabled with its clock running. C66xx_0: GEL Output: Block2 enable status ---> 0x00000001 => memory access unit (MAU) is enabled with its clock running. C66xx_0: GEL Output: Block3 enable status ---> 0x00000001 => message transmit unit (TXU) is enabled with its clock running. C66xx_0: GEL Output: Block4 enable status ---> 0x00000001 => message receive unit (RXU) is enabled with its clock running. C66xx_0: GEL Output: Block5 enable status ---> 0x00000001 => SRIO port 0 is enabled with its clock running. C66xx_0: GEL Output: Block6 enable status ---> 0x00000001 => SRIO port 1 is enabled with its clock running. C66xx_0: GEL Output: Block7 enable status ---> 0x00000001 => SRIO port 2 is enabled with its clock running. C66xx_0: GEL Output: Block8 enable status ---> 0x00000001 => SRIO port 3 is enabled with its clock running. C66xx_0: GEL Output: Block9 enable status ---> 0x00000001 => Block9 is enabled with its clock running. C66xx_0: GEL Output: ******************************************************************************************************* C66xx_0: GEL Output: ********************************** SRIO PORT STATUS ****************************************************** C66xx_0: GEL Output: ******************************************************************************************************* C66xx_0: GEL Output: ********************************** SRIO PORT0 STATUS ****************************************************** C66xx_0: GEL Output: *******************Port0 Error and Status CSR******************* C66xx_0: GEL Output: PORT_UNINITIALIZED => Input and output ports ##ARE INITIALIZED## C66xx_0: GEL Output: PORT_OK => Port ##OK## condition C66xx_0: GEL Output: PORT_ERROR => The input or output port ##HAS NOT ENCOUNTERED## an unrecoverable HW error C66xx_0: GEL Output: PORT_UNAVL => The port is ##AVAILABLE## for use C66xx_0: GEL Output: PORT_WRITE_PND => The port ##HAS NOT ENCOUNTERED## a condition which required it to initiate a Maintenance Port-write operation C66xx_0: GEL Output: INPUT_ERROR_STP => The input port ##IS NOT## in the 'input error-stopped' state C66xx_0: GEL Output: INPUT_ERROR_ENC => The input port ##HAS NOT ENCOUNTERED## a transmission error C66xx_0: GEL Output: INPUT_RETRY_STP => The input port ##IS NOT## in the 'input retry-stopped' state C66xx_0: GEL Output: OUTPUT_ERROR_STP => The output port ##IS NOT## in the 'output error-stopped' state C66xx_0: GEL Output: OUTPUT_ERROR_ENC => The output port ##HAS NOT ENCOUNTERED## a transmission error C66xx_0: GEL Output: OUTPUT_RETRY_STP => The output port ##HAS NOT RECEIVED## a packet-retry control symbol and/or is not in the 'output retry-stopped' state. C66xx_0: GEL Output: OUTPUT_RETRIED => The output port ##HAS NOT RECEIVED## a packet-retry control symbol and cannot make forward progress. C66xx_0: GEL Output: OUTPUT_RETRY_ENC => The output port ##HAS NOT ENCOUNTERED## a retry condition C66xx_0: GEL Output: OUTPUT_DEGRD_ENC => The output port ##HAS NOT ENCOUNTERED## a degraded condition C66xx_0: GEL Output: OUTPUT_FLD_ENC => The output port ##HAS NOT ENCOUNTERED## a failed condition C66xx_0: GEL Output: OUTPUT_PKT_DROP => The output port ##HAS NOT DISCARDED## a packet C66xx_0: GEL Output: TXFC => Receiver-based flow control C66xx_0: GEL Output: IDLE_SEQ => Idle sequence 1 is active. C66xx_0: GEL Output: IDLE2_EN => Idle sequence 2 **DISABLED** for baud rates < 5.5 GBaud C66xx_0: GEL Output: IDLE2 => Idle sequence 2 **NOT SUPPORTED** for baud rates < 5.5 GBaud C66xx_0: GEL Output: *******************Port0 Error Detect CSR******************* C66xx_0: GEL Output: LINK_TIMEOUT => The port ##DID NOT EXPERIENCE## a link timeout C66xx_0: GEL Output: UNSOLICITED_ACK_CNTL_SYM => The port ##DID NOT RECEIVE## an unexpected acknowledge control symbol C66xx_0: GEL Output: DELINEATION_ERROR => The port ##DID NOT DETECT## a delineation error C66xx_0: GEL Output: PROTOCOL_ERROR => The port ##DID NOT RECEIVE## an unexpected packet or control symbol C66xx_0: GEL Output: NON_OUTSTANDING_ACKID => The port ##DID NOT RECEIVE## a link response with a non-outstanding ackID C66xx_0: GEL Output: DSCRAM_LOS => Receiver de-scrambler synchronization is ##NOT LOST## C66xx_0: GEL Output: RCVD_PKT_OVER_276B => The port ##DID NOT RECEIVE## packet that exceeds the maximum allowed size. C66xx_0: GEL Output: RCVD_PKT_WITH_BAD_CRC => The port ##DID NOT RECEIVE## a packet with a bad CRC value C66xx_0: GEL Output: PKT_UNEXPECTED_ACKID => The port ##DID NOT RECEIVE## a packet with unexpected/out-of-sequence ackID C66xx_0: GEL Output: RCVD_PKT_NOT_ACCPT => The port ##DID NOT RECEIVE## a packet-not-accepted acknowledge control symbol. C66xx_0: GEL Output: CNTL_SYM_UNEXPECTED_ACKID => The port ##DID NOT RECEIVE## an acknowledge control symbol with an unexpected ackID (packet-accepted or packet-retry) C66xx_0: GEL Output: CORRUPT_CNTL_SYM => The port ##DID NOT RECEIVE## a control symbol with a bad CRC value C66xx_0: GEL Output: ERR_IMP_SPECIFIC => An implementation specific error ##HAS NOT BEEN## detected C66xx_0: GEL Output: *******************Port0 Error rate CSR******************* C66xx_0: GEL Output: ERROR_RATE_COUNTER ---> 0 C66xx_0: GEL Output: PEAK_ERROR_RATE ---> 0 C66xx_0: GEL Output: *******************Port0 Link Maintenance Response CSR data******************* C66xx_0: GEL Output: LINK_STATUS ---> Reserved C66xx_0: GEL Output: ACKID_STATUS ---> 0x00 C66xx_0: GEL Output: RESPONSE_VALID ---> Response ##IS NOT## valid C66xx_0: GEL Output: *******************Port0 Local AckId Status CSR******************* C66xx_0: GEL Output: OUTBOUND_ACKID ---> 0x0C C66xx_0: GEL Output: OUTSTANDING_ACKID ---> 0x0C C66xx_0: GEL Output: INBOUND_ACKID ---> 0x01 C66xx_0: GEL Output: *******************Port0 Attributes Error Capture CSR******************* C66xx_0: GEL Output: CAPTURE_VALID_INFO ---> The packet/control symbol capture registers ##DO NOT CONTAIN## valid information. C66xx_0: GEL Output: IMP_SPECIFIC ---> 0x00000000 C66xx_0: GEL Output: ERROR_TYPE ---> 0x00 C66xx_0: GEL Output: INFO_TYPE ---> Packet C66xx_0: GEL Output: CAPTURE0 ---> 0x00000000 C66xx_0: GEL Output: CAPTURE1 ---> 0x00000000 C66xx_0: GEL Output: CAPTURE2 ---> 0x00000000 C66xx_0: GEL Output: CAPTURE3 ---> 0x00000000 C66xx_0: GEL Output: ********************************** SRIO PORT1 STATUS ****************************************************** C66xx_0: GEL Output: *******************Port1 Error and Status CSR******************* C66xx_0: GEL Output: PORT_UNINITIALIZED => Input and output ports are **NOT INITIALIZED** C66xx_0: GEL Output: PORT_OK => Port **NOT-OK** condition C66xx_0: GEL Output: PORT_ERROR => The input or output port ##HAS NOT ENCOUNTERED## an unrecoverable HW error C66xx_0: GEL Output: PORT_UNAVL => The port is **NOT AVAILABLE** for use C66xx_0: GEL Output: PORT_WRITE_PND => The port ##HAS NOT ENCOUNTERED## a condition which required it to initiate a Maintenance Port-write operation C66xx_0: GEL Output: INPUT_ERROR_STP => The input port ##IS NOT## in the 'input error-stopped' state C66xx_0: GEL Output: INPUT_ERROR_ENC => The input port ##HAS NOT ENCOUNTERED## a transmission error C66xx_0: GEL Output: INPUT_RETRY_STP => The input port ##IS NOT## in the 'input retry-stopped' state C66xx_0: GEL Output: OUTPUT_ERROR_STP => The output port ##IS NOT## in the 'output error-stopped' state C66xx_0: GEL Output: OUTPUT_ERROR_ENC => The output port ##HAS NOT ENCOUNTERED## a transmission error C66xx_0: GEL Output: OUTPUT_RETRY_STP => The output port ##HAS NOT RECEIVED## a packet-retry control symbol and/or is not in the 'output retry-stopped' state. C66xx_0: GEL Output: OUTPUT_RETRIED => The output port ##HAS NOT RECEIVED## a packet-retry control symbol and cannot make forward progress. C66xx_0: GEL Output: OUTPUT_RETRY_ENC => The output port ##HAS NOT ENCOUNTERED## a retry condition C66xx_0: GEL Output: OUTPUT_DEGRD_ENC => The output port ##HAS NOT ENCOUNTERED## a degraded condition C66xx_0: GEL Output: OUTPUT_FLD_ENC => The output port ##HAS NOT ENCOUNTERED## a failed condition C66xx_0: GEL Output: OUTPUT_PKT_DROP => The output port ##HAS NOT DISCARDED## a packet C66xx_0: GEL Output: TXFC => Receiver-based flow control C66xx_0: GEL Output: IDLE_SEQ => Idle sequence 1 is active. C66xx_0: GEL Output: IDLE2_EN => Idle sequence 2 **DISABLED** for baud rates < 5.5 GBaud C66xx_0: GEL Output: IDLE2 => Idle sequence 2 **NOT SUPPORTED** for baud rates < 5.5 GBaud C66xx_0: GEL Output: *******************Port1 Error Detect CSR******************* C66xx_0: GEL Output: LINK_TIMEOUT => The port ##DID NOT EXPERIENCE## a link timeout C66xx_0: GEL Output: UNSOLICITED_ACK_CNTL_SYM => The port ##DID NOT RECEIVE## an unexpected acknowledge control symbol C66xx_0: GEL Output: DELINEATION_ERROR => The port ##DID NOT DETECT## a delineation error C66xx_0: GEL Output: PROTOCOL_ERROR => The port ##DID NOT RECEIVE## an unexpected packet or control symbol C66xx_0: GEL Output: NON_OUTSTANDING_ACKID => The port ##DID NOT RECEIVE## a link response with a non-outstanding ackID C66xx_0: GEL Output: DSCRAM_LOS => Receiver de-scrambler synchronization is ##NOT LOST## C66xx_0: GEL Output: RCVD_PKT_OVER_276B => The port ##DID NOT RECEIVE## packet that exceeds the maximum allowed size. C66xx_0: GEL Output: RCVD_PKT_WITH_BAD_CRC => The port ##DID NOT RECEIVE## a packet with a bad CRC value C66xx_0: GEL Output: PKT_UNEXPECTED_ACKID => The port ##DID NOT RECEIVE## a packet with unexpected/out-of-sequence ackID C66xx_0: GEL Output: RCVD_PKT_NOT_ACCPT => The port ##DID NOT RECEIVE## a packet-not-accepted acknowledge control symbol. C66xx_0: GEL Output: CNTL_SYM_UNEXPECTED_ACKID => The port ##DID NOT RECEIVE## an acknowledge control symbol with an unexpected ackID (packet-accepted or packet-retry) C66xx_0: GEL Output: CORRUPT_CNTL_SYM => The port ##DID NOT RECEIVE## a control symbol with a bad CRC value C66xx_0: GEL Output: ERR_IMP_SPECIFIC => An implementation specific error ##HAS NOT BEEN## detected C66xx_0: GEL Output: *******************Port1 Error rate CSR******************* C66xx_0: GEL Output: ERROR_RATE_COUNTER ---> 0 C66xx_0: GEL Output: PEAK_ERROR_RATE ---> 0 C66xx_0: GEL Output: *******************Port1 Link Maintenance Response CSR data******************* C66xx_0: GEL Output: LINK_STATUS ---> Reserved C66xx_0: GEL Output: ACKID_STATUS ---> 0x00 C66xx_0: GEL Output: RESPONSE_VALID ---> Response ##IS NOT## valid C66xx_0: GEL Output: *******************Port1 Local AckId Status CSR******************* C66xx_0: GEL Output: OUTBOUND_ACKID ---> 0x00 C66xx_0: GEL Output: OUTSTANDING_ACKID ---> 0x00 C66xx_0: GEL Output: INBOUND_ACKID ---> 0x00 C66xx_0: GEL Output: *******************Port1 Attributes Error Capture CSR******************* C66xx_0: GEL Output: CAPTURE_VALID_INFO ---> The packet/control symbol capture registers ##DO NOT CONTAIN## valid information. C66xx_0: GEL Output: IMP_SPECIFIC ---> 0x00000000 C66xx_0: GEL Output: ERROR_TYPE ---> 0x00 C66xx_0: GEL Output: INFO_TYPE ---> Implementation specific C66xx_0: GEL Output: CAPTURE0 ---> 0xFFFF0000 C66xx_0: GEL Output: CAPTURE1 ---> 0x00000000 C66xx_0: GEL Output: CAPTURE2 ---> 0x00000000 C66xx_0: GEL Output: CAPTURE3 ---> 0x00000000 C66xx_0: GEL Output: ********************************** SRIO PORT2 STATUS ****************************************************** C66xx_0: GEL Output: *******************Port2 Error and Status CSR******************* C66xx_0: GEL Output: PORT_UNINITIALIZED => Input and output ports are **NOT INITIALIZED** C66xx_0: GEL Output: PORT_OK => Port **NOT-OK** condition C66xx_0: GEL Output: PORT_ERROR => The input or output port ##HAS NOT ENCOUNTERED## an unrecoverable HW error C66xx_0: GEL Output: PORT_UNAVL => The port is **NOT AVAILABLE** for use C66xx_0: GEL Output: PORT_WRITE_PND => The port ##HAS NOT ENCOUNTERED## a condition which required it to initiate a Maintenance Port-write operation C66xx_0: GEL Output: INPUT_ERROR_STP => The input port ##IS NOT## in the 'input error-stopped' state C66xx_0: GEL Output: INPUT_ERROR_ENC => The input port ##HAS NOT ENCOUNTERED## a transmission error C66xx_0: GEL Output: INPUT_RETRY_STP => The input port ##IS NOT## in the 'input retry-stopped' state C66xx_0: GEL Output: OUTPUT_ERROR_STP => The output port ##IS NOT## in the 'output error-stopped' state C66xx_0: GEL Output: OUTPUT_ERROR_ENC => The output port ##HAS NOT ENCOUNTERED## a transmission error C66xx_0: GEL Output: OUTPUT_RETRY_STP => The output port ##HAS NOT RECEIVED## a packet-retry control symbol and/or is not in the 'output retry-stopped' state. C66xx_0: GEL Output: OUTPUT_RETRIED => The output port ##HAS NOT RECEIVED## a packet-retry control symbol and cannot make forward progress. C66xx_0: GEL Output: OUTPUT_RETRY_ENC => The output port ##HAS NOT ENCOUNTERED## a retry condition C66xx_0: GEL Output: OUTPUT_DEGRD_ENC => The output port ##HAS NOT ENCOUNTERED## a degraded condition C66xx_0: GEL Output: OUTPUT_FLD_ENC => The output port ##HAS NOT ENCOUNTERED## a failed condition C66xx_0: GEL Output: OUTPUT_PKT_DROP => The output port ##HAS NOT DISCARDED## a packet C66xx_0: GEL Output: TXFC => Receiver-based flow control C66xx_0: GEL Output: IDLE_SEQ => Idle sequence 1 is active. C66xx_0: GEL Output: IDLE2_EN => Idle sequence 2 **DISABLED** for baud rates < 5.5 GBaud C66xx_0: GEL Output: IDLE2 => Idle sequence 2 **NOT SUPPORTED** for baud rates < 5.5 GBaud C66xx_0: GEL Output: *******************Port2 Error Detect CSR******************* C66xx_0: GEL Output: LINK_TIMEOUT => The port ##DID NOT EXPERIENCE## a link timeout C66xx_0: GEL Output: UNSOLICITED_ACK_CNTL_SYM => The port ##DID NOT RECEIVE## an unexpected acknowledge control symbol C66xx_0: GEL Output: DELINEATION_ERROR => The port ##DID NOT DETECT## a delineation error C66xx_0: GEL Output: PROTOCOL_ERROR => The port ##DID NOT RECEIVE## an unexpected packet or control symbol C66xx_0: GEL Output: NON_OUTSTANDING_ACKID => The port ##DID NOT RECEIVE## a link response with a non-outstanding ackID C66xx_0: GEL Output: DSCRAM_LOS => Receiver de-scrambler synchronization is ##NOT LOST## C66xx_0: GEL Output: RCVD_PKT_OVER_276B => The port ##DID NOT RECEIVE## packet that exceeds the maximum allowed size. C66xx_0: GEL Output: RCVD_PKT_WITH_BAD_CRC => The port ##DID NOT RECEIVE## a packet with a bad CRC value C66xx_0: GEL Output: PKT_UNEXPECTED_ACKID => The port ##DID NOT RECEIVE## a packet with unexpected/out-of-sequence ackID C66xx_0: GEL Output: RCVD_PKT_NOT_ACCPT => The port ##DID NOT RECEIVE## a packet-not-accepted acknowledge control symbol. C66xx_0: GEL Output: CNTL_SYM_UNEXPECTED_ACKID => The port ##DID NOT RECEIVE## an acknowledge control symbol with an unexpected ackID (packet-accepted or packet-retry) C66xx_0: GEL Output: CORRUPT_CNTL_SYM => The port ##DID NOT RECEIVE## a control symbol with a bad CRC value C66xx_0: GEL Output: ERR_IMP_SPECIFIC => An implementation specific error ##HAS NOT BEEN## detected C66xx_0: GEL Output: *******************Port2 Error rate CSR******************* C66xx_0: GEL Output: ERROR_RATE_COUNTER ---> 0 C66xx_0: GEL Output: PEAK_ERROR_RATE ---> 0 C66xx_0: GEL Output: *******************Port2 Link Maintenance Response CSR data******************* C66xx_0: GEL Output: LINK_STATUS ---> Reserved C66xx_0: GEL Output: ACKID_STATUS ---> 0x00 C66xx_0: GEL Output: RESPONSE_VALID ---> Response ##IS NOT## valid C66xx_0: GEL Output: *******************Port2 Local AckId Status CSR******************* C66xx_0: GEL Output: OUTBOUND_ACKID ---> 0x00 C66xx_0: GEL Output: OUTSTANDING_ACKID ---> 0x00 C66xx_0: GEL Output: INBOUND_ACKID ---> 0x00 C66xx_0: GEL Output: *******************Port2 Attributes Error Capture CSR******************* C66xx_0: GEL Output: CAPTURE_VALID_INFO ---> The packet/control symbol capture registers ##DO NOT CONTAIN## valid information. C66xx_0: GEL Output: IMP_SPECIFIC ---> 0x00000000 C66xx_0: GEL Output: ERROR_TYPE ---> 0x00 C66xx_0: GEL Output: INFO_TYPE ---> Packet C66xx_0: GEL Output: CAPTURE0 ---> 0x00000000 C66xx_0: GEL Output: CAPTURE1 ---> 0x00000000 C66xx_0: GEL Output: CAPTURE2 ---> 0x00000000 C66xx_0: GEL Output: CAPTURE3 ---> 0x00000000 C66xx_0: GEL Output: ********************************** SRIO PORT3 STATUS ****************************************************** C66xx_0: GEL Output: *******************Port3 Error and Status CSR******************* C66xx_0: GEL Output: PORT_UNINITIALIZED => Input and output ports are **NOT INITIALIZED** C66xx_0: GEL Output: PORT_OK => Port **NOT-OK** condition C66xx_0: GEL Output: PORT_ERROR => The input or output port ##HAS NOT ENCOUNTERED## an unrecoverable HW error C66xx_0: GEL Output: PORT_UNAVL => The port is **NOT AVAILABLE** for use C66xx_0: GEL Output: PORT_WRITE_PND => The port ##HAS NOT ENCOUNTERED## a condition which required it to initiate a Maintenance Port-write operation C66xx_0: GEL Output: INPUT_ERROR_STP => The input port ##IS NOT## in the 'input error-stopped' state C66xx_0: GEL Output: INPUT_ERROR_ENC => The input port ##HAS NOT ENCOUNTERED## a transmission error C66xx_0: GEL Output: INPUT_RETRY_STP => The input port ##IS NOT## in the 'input retry-stopped' state C66xx_0: GEL Output: OUTPUT_ERROR_STP => The output port ##IS NOT## in the 'output error-stopped' state C66xx_0: GEL Output: OUTPUT_ERROR_ENC => The output port ##HAS NOT ENCOUNTERED## a transmission error C66xx_0: GEL Output: OUTPUT_RETRY_STP => The output port ##HAS NOT RECEIVED## a packet-retry control symbol and/or is not in the 'output retry-stopped' state. C66xx_0: GEL Output: OUTPUT_RETRIED => The output port ##HAS NOT RECEIVED## a packet-retry control symbol and cannot make forward progress. C66xx_0: GEL Output: OUTPUT_RETRY_ENC => The output port ##HAS NOT ENCOUNTERED## a retry condition C66xx_0: GEL Output: OUTPUT_DEGRD_ENC => The output port ##HAS NOT ENCOUNTERED## a degraded condition C66xx_0: GEL Output: OUTPUT_FLD_ENC => The output port ##HAS NOT ENCOUNTERED## a failed condition C66xx_0: GEL Output: OUTPUT_PKT_DROP => The output port ##HAS NOT DISCARDED## a packet C66xx_0: GEL Output: TXFC => Receiver-based flow control C66xx_0: GEL Output: IDLE_SEQ => Idle sequence 1 is active. C66xx_0: GEL Output: IDLE2_EN => Idle sequence 2 **DISABLED** for baud rates < 5.5 GBaud C66xx_0: GEL Output: IDLE2 => Idle sequence 2 **NOT SUPPORTED** for baud rates < 5.5 GBaud C66xx_0: GEL Output: *******************Port3 Error Detect CSR******************* C66xx_0: GEL Output: LINK_TIMEOUT => The port ##DID NOT EXPERIENCE## a link timeout C66xx_0: GEL Output: UNSOLICITED_ACK_CNTL_SYM => The port ##DID NOT RECEIVE## an unexpected acknowledge control symbol C66xx_0: GEL Output: DELINEATION_ERROR => The port ##DID NOT DETECT## a delineation error C66xx_0: GEL Output: PROTOCOL_ERROR => The port ##DID NOT RECEIVE## an unexpected packet or control symbol C66xx_0: GEL Output: NON_OUTSTANDING_ACKID => The port ##DID NOT RECEIVE## a link response with a non-outstanding ackID C66xx_0: GEL Output: DSCRAM_LOS => Receiver de-scrambler synchronization is ##NOT LOST## C66xx_0: GEL Output: RCVD_PKT_OVER_276B => The port ##DID NOT RECEIVE## packet that exceeds the maximum allowed size. C66xx_0: GEL Output: RCVD_PKT_WITH_BAD_CRC => The port ##DID NOT RECEIVE## a packet with a bad CRC value C66xx_0: GEL Output: PKT_UNEXPECTED_ACKID => The port ##DID NOT RECEIVE## a packet with unexpected/out-of-sequence ackID C66xx_0: GEL Output: RCVD_PKT_NOT_ACCPT => The port ##DID NOT RECEIVE## a packet-not-accepted acknowledge control symbol. C66xx_0: GEL Output: CNTL_SYM_UNEXPECTED_ACKID => The port ##DID NOT RECEIVE## an acknowledge control symbol with an unexpected ackID (packet-accepted or packet-retry) C66xx_0: GEL Output: CORRUPT_CNTL_SYM => The port ##DID NOT RECEIVE## a control symbol with a bad CRC value C66xx_0: GEL Output: ERR_IMP_SPECIFIC => An implementation specific error ##HAS NOT BEEN## detected C66xx_0: GEL Output: *******************Port3 Error rate CSR******************* C66xx_0: GEL Output: ERROR_RATE_COUNTER ---> 0 C66xx_0: GEL Output: PEAK_ERROR_RATE ---> 0 C66xx_0: GEL Output: *******************Port3 Link Maintenance Response CSR data******************* C66xx_0: GEL Output: LINK_STATUS ---> Reserved C66xx_0: GEL Output: ACKID_STATUS ---> 0x00 C66xx_0: GEL Output: RESPONSE_VALID ---> Response ##IS NOT## valid C66xx_0: GEL Output: *******************Port3 Local AckId Status CSR******************* C66xx_0: GEL Output: OUTBOUND_ACKID ---> 0x00 C66xx_0: GEL Output: OUTSTANDING_ACKID ---> 0x00 C66xx_0: GEL Output: INBOUND_ACKID ---> 0x00 C66xx_0: GEL Output: *******************Port3 Attributes Error Capture CSR******************* C66xx_0: GEL Output: CAPTURE_VALID_INFO ---> The packet/control symbol capture registers ##DO NOT CONTAIN## valid information. C66xx_0: GEL Output: IMP_SPECIFIC ---> 0x00000000 C66xx_0: GEL Output: ERROR_TYPE ---> 0x00 C66xx_0: GEL Output: INFO_TYPE ---> Implementation specific C66xx_0: GEL Output: CAPTURE0 ---> 0xFFFF0000 C66xx_0: GEL Output: CAPTURE1 ---> 0x00000000 C66xx_0: GEL Output: CAPTURE2 ---> 0x00000000 C66xx_0: GEL Output: CAPTURE3 ---> 0x00000000 C66xx_0: GEL Output: ******************************************************************************************************* C66xx_0: GEL Output: ********************************** SRIO LOGICAL AND TRANSPORT ERROR STATUS ****************************************************** C66xx_0: GEL Output: ******************************************************************************************************* C66xx_0: GEL Output: ********************************** Logical/Transport Layer Error Detect CSR (ERR_DET) ****************************************************** C66xx_0: GEL Output: RX_IO_DMA_ACCESS => A DMA access to the MAU has ##NOT## been blocked C66xx_0: GEL Output: RX_CPPI_SECURITY => The RXU has ##NOT## detected an access block C66xx_0: GEL Output: UNSUPPORTED_TRANS => The MAU has ##NOT## received an unsupported transaction C66xx_0: GEL Output: UNSOLICITED_RSPNS => An unsolicited response packet has ##NOT## been received by an LSU or the TXU C66xx_0: GEL Output: PKT_RSPNS_TIMEOUT => A timeout has ##NOT## been detected by an LSU or the TXU C66xx_0: GEL Output: MSG_REQ_TIMEOUT => A timeout has ##NOT## been detected by RXU C66xx_0: GEL Output: ILL_TRANS_DECODE => The LSU/TXU did ##NOT## receive illegal fields in the response packet The MAU/RXU did ##NOT## receive illegal fields in the request packet C66xx_0: GEL Output: ERR_MSG_FORMAT => The RXU did ##NOT## receive a message data payload with an invalid size or segment. C66xx_0: GEL Output: MSG_ERR_RSPNS => The TXU did ##NOT## receive an ERROR response to a message logical layer request C66xx_0: GEL Output: IO_ERR_RSPNS => An LSU did ##NOT## receive an ERROR response to an I/O logical layer request C66xx_0: GEL Output: ********************************** Logical/Transport Layer Device ID Capture CSR (ID_CAPT) ****************************************************** C66xx_0: GEL Output: No occurence of logical layer errors or logical layer error capture disabled C66xx_0: GEL Output: ********************************** Logical/Transport Layer Control Capture CSR (CTRL_CAPT) ****************************************************** C66xx_0: GEL Output: IMP_SPECIFIC ---> 0x0000 C66xx_0: GEL Output: MSGINFO ---> 0x00 C66xx_0: GEL Output: PKT_TYPE ---> Not a valid packet type C66xx_0: GEL Output: ********************************** Logical/Transport Layer High Address Capture CSR (H_ADDR_CAPT) ****************************************************** C66xx_0: GEL Output: ADDRESS_63_32 ---> 0x00000000 C66xx_0: GEL Output: ********************************** Logical/Transport Layer Address Capture CSR (ADDR_CAPT) ****************************************************** C66xx_0: GEL Output: XAMSBS ---> 0x00 C66xx_0: GEL Output: ADDRESS_31_3 ---> 0x00000000 C66xx_0: GEL Output: ******************************************************************************************************* C66xx_0: GEL Output: ********************************** FARADAY SRIO INTERRUPTS ROUTING INFO ****************************************************** C66xx_0: GEL Output: ******************************************************************************************************* C66xx_0: GEL Output: ********************************** DOORBELLn Interrupt Condition Routing Registers (DOORBELLn_ICRR and DOORBELLn_ICRR2) ****************************************************** C66xx_0: GEL Output: DOORBELL REG0 INTERRUPT CONDITION ROUTING REGISTER: C66xx_0: GEL Output: DOORBELL0_ICRR.ICR0 ---> 2 => INTDST2 C66xx_0: GEL Output: DOORBELL0_ICRR.ICR1 ---> 2 => INTDST2 C66xx_0: GEL Output: DOORBELL0_ICRR.ICR2 ---> 2 => INTDST2 C66xx_0: GEL Output: DOORBELL0_ICRR.ICR3 ---> 2 => INTDST2 C66xx_0: GEL Output: DOORBELL0_ICRR.ICR4 ---> 2 => INTDST2 C66xx_0: GEL Output: DOORBELL0_ICRR.ICR5 ---> 2 => INTDST2 C66xx_0: GEL Output: DOORBELL0_ICRR.ICR6 ---> 2 => INTDST2 C66xx_0: GEL Output: DOORBELL0_ICRR.ICR7 ---> 2 => INTDST2 C66xx_0: GEL Output: DOORBELL0_ICRR2.ICR8 ---> 2 => INTDST2 C66xx_0: GEL Output: DOORBELL0_ICRR2.ICR9 ---> 2 => INTDST2 C66xx_0: GEL Output: DOORBELL0_ICRR2.ICR10 ---> 2 => INTDST2 C66xx_0: GEL Output: DOORBELL0_ICRR2.ICR11 ---> 2 => INTDST2 C66xx_0: GEL Output: DOORBELL0_ICRR2.ICR12 ---> 2 => INTDST2 C66xx_0: GEL Output: DOORBELL0_ICRR2.ICR13 ---> 2 => INTDST2 C66xx_0: GEL Output: DOORBELL0_ICRR2.ICR14 ---> 2 => INTDST2 C66xx_0: GEL Output: DOORBELL0_ICRR2.ICR15 ---> 2 => INTDST2 C66xx_0: GEL Output: DOORBELL REG1 INTERRUPT CONDITION ROUTING REGISTER: C66xx_0: GEL Output: DOORBELL1_ICRR.ICR0 ---> 3 => INTDST3 C66xx_0: GEL Output: DOORBELL1_ICRR.ICR1 ---> 3 => INTDST3 C66xx_0: GEL Output: DOORBELL1_ICRR.ICR2 ---> 3 => INTDST3 C66xx_0: GEL Output: DOORBELL1_ICRR.ICR3 ---> 3 => INTDST3 C66xx_0: GEL Output: DOORBELL1_ICRR.ICR4 ---> 3 => INTDST3 C66xx_0: GEL Output: DOORBELL1_ICRR.ICR5 ---> 3 => INTDST3 C66xx_0: GEL Output: DOORBELL1_ICRR.ICR6 ---> 3 => INTDST3 C66xx_0: GEL Output: DOORBELL1_ICRR.ICR7 ---> 3 => INTDST3 C66xx_0: GEL Output: DOORBELL1_ICRR2.ICR8 ---> 0 => INTDST0 C66xx_0: GEL Output: DOORBELL1_ICRR2.ICR9 ---> 0 => INTDST0 C66xx_0: GEL Output: DOORBELL1_ICRR2.ICR10 ---> 0 => INTDST0 C66xx_0: GEL Output: DOORBELL1_ICRR2.ICR11 ---> 0 => INTDST0 C66xx_0: GEL Output: DOORBELL1_ICRR2.ICR12 ---> 0 => INTDST0 C66xx_0: GEL Output: DOORBELL1_ICRR2.ICR13 ---> 0 => INTDST0 C66xx_0: GEL Output: DOORBELL1_ICRR2.ICR14 ---> 0 => INTDST0 C66xx_0: GEL Output: DOORBELL1_ICRR2.ICR15 ---> 0 => INTDST0 C66xx_0: GEL Output: DOORBELL REG2 INTERRUPT CONDITION ROUTING REGISTER: C66xx_0: GEL Output: DOORBELL2_ICRR.ICR0 ---> 0 => INTDST0 C66xx_0: GEL Output: DOORBELL2_ICRR.ICR1 ---> 0 => INTDST0 C66xx_0: GEL Output: DOORBELL2_ICRR.ICR2 ---> 0 => INTDST0 C66xx_0: GEL Output: DOORBELL2_ICRR.ICR3 ---> 0 => INTDST0 C66xx_0: GEL Output: DOORBELL2_ICRR.ICR4 ---> 0 => INTDST0 C66xx_0: GEL Output: DOORBELL2_ICRR.ICR5 ---> 0 => INTDST0 C66xx_0: GEL Output: DOORBELL2_ICRR.ICR6 ---> 0 => INTDST0 C66xx_0: GEL Output: DOORBELL2_ICRR.ICR7 ---> 0 => INTDST0 C66xx_0: GEL Output: DOORBELL2_ICRR2.ICR8 ---> 5 => INTDST4 C66xx_0: GEL Output: DOORBELL2_ICRR2.ICR9 ---> 5 => INTDST4 C66xx_0: GEL Output: DOORBELL2_ICRR2.ICR10 ---> 5 => INTDST4 C66xx_0: GEL Output: DOORBELL2_ICRR2.ICR11 ---> 5 => INTDST4 C66xx_0: GEL Output: DOORBELL2_ICRR2.ICR12 ---> 5 => INTDST4 C66xx_0: GEL Output: DOORBELL2_ICRR2.ICR13 ---> 5 => INTDST4 C66xx_0: GEL Output: DOORBELL2_ICRR2.ICR14 ---> 5 => INTDST4 C66xx_0: GEL Output: DOORBELL2_ICRR2.ICR15 ---> 5 => INTDST4 C66xx_0: GEL Output: DOORBELL REG3 INTERRUPT CONDITION ROUTING REGISTER: C66xx_0: GEL Output: DOORBELL3_ICRR.ICR0 ---> 0 => INTDST0 C66xx_0: GEL Output: DOORBELL3_ICRR.ICR1 ---> 0 => INTDST0 C66xx_0: GEL Output: DOORBELL3_ICRR.ICR2 ---> 0 => INTDST0 C66xx_0: GEL Output: DOORBELL3_ICRR.ICR3 ---> 0 => INTDST0 C66xx_0: GEL Output: DOORBELL3_ICRR.ICR4 ---> 0 => INTDST0 C66xx_0: GEL Output: DOORBELL3_ICRR.ICR5 ---> 0 => INTDST0 C66xx_0: GEL Output: DOORBELL3_ICRR.ICR6 ---> 0 => INTDST0 C66xx_0: GEL Output: DOORBELL3_ICRR.ICR7 ---> 0 => INTDST0 C66xx_0: GEL Output: DOORBELL3_ICRR2.ICR8 ---> 0 => INTDST0 C66xx_0: GEL Output: DOORBELL3_ICRR2.ICR9 ---> 0 => INTDST0 C66xx_0: GEL Output: DOORBELL3_ICRR2.ICR10 ---> 0 => INTDST0 C66xx_0: GEL Output: DOORBELL3_ICRR2.ICR11 ---> 0 => INTDST0 C66xx_0: GEL Output: DOORBELL3_ICRR2.ICR12 ---> 0 => INTDST0 C66xx_0: GEL Output: DOORBELL3_ICRR2.ICR13 ---> 0 => INTDST0 C66xx_0: GEL Output: DOORBELL3_ICRR2.ICR14 ---> 0 => INTDST0 C66xx_0: GEL Output: DOORBELL3_ICRR2.ICR15 ---> 0 => INTDST0 C66xx_0: GEL Output: ********************************** LSU0 Interrupt Condition Routing Registers (LSU0_ICRR0-LSU0_ICRR3) ****************************************************** C66xx_0: GEL Output: LSU0_ICRR0.ICR0 ---> 0 => INTDST0 C66xx_0: GEL Output: LSU0_ICRR0.ICR1 ---> 0 => INTDST0 C66xx_0: GEL Output: LSU0_ICRR0.ICR2 ---> 0 => INTDST0 C66xx_0: GEL Output: LSU0_ICRR0.ICR3 ---> 0 => INTDST0 C66xx_0: GEL Output: LSU0_ICRR0.ICR4 ---> 0 => INTDST0 C66xx_0: GEL Output: LSU0_ICRR0.ICR5 ---> 0 => INTDST0 C66xx_0: GEL Output: LSU0_ICRR0.ICR6 ---> 0 => INTDST0 C66xx_0: GEL Output: LSU0_ICRR0.ICR7 ---> 0 => INTDST0 C66xx_0: GEL Output: LSU0_ICRR1.ICR8 ---> 0 => INTDST0 C66xx_0: GEL Output: LSU0_ICRR1.ICR9 ---> 0 => INTDST0 C66xx_0: GEL Output: LSU0_ICRR1.ICR10 ---> 0 => INTDST0 C66xx_0: GEL Output: LSU0_ICRR1.ICR11 ---> 0 => INTDST0 C66xx_0: GEL Output: LSU0_ICRR1.ICR12 ---> 0 => INTDST0 C66xx_0: GEL Output: LSU0_ICRR1.ICR13 ---> 0 => INTDST0 C66xx_0: GEL Output: LSU0_ICRR1.ICR14 ---> 0 => INTDST0 C66xx_0: GEL Output: LSU0_ICRR1.ICR15 ---> 0 => INTDST0 C66xx_0: GEL Output: LSU0_ICRR2.ICR16 ---> 0 => INTDST0 C66xx_0: GEL Output: LSU0_ICRR2.ICR17 ---> 0 => INTDST0 C66xx_0: GEL Output: LSU0_ICRR2.ICR18 ---> 0 => INTDST0 C66xx_0: GEL Output: LSU0_ICRR2.ICR19 ---> 0 => INTDST0 C66xx_0: GEL Output: LSU0_ICRR2.ICR20 ---> 0 => INTDST0 C66xx_0: GEL Output: LSU0_ICRR2.ICR21 ---> 0 => INTDST0 C66xx_0: GEL Output: LSU0_ICRR2.ICR22 ---> 0 => INTDST0 C66xx_0: GEL Output: LSU0_ICRR2.ICR23 ---> 0 => INTDST0 C66xx_0: GEL Output: LSU0_ICRR3.ICR24 ---> 0 => INTDST0 C66xx_0: GEL Output: LSU0_ICRR3.ICR25 ---> 0 => INTDST0 C66xx_0: GEL Output: LSU0_ICRR3.ICR26 ---> 0 => INTDST0 C66xx_0: GEL Output: LSU0_ICRR3.ICR27 ---> 0 => INTDST0 C66xx_0: GEL Output: LSU0_ICRR3.ICR28 ---> 0 => INTDST0 C66xx_0: GEL Output: LSU0_ICRR3.ICR29 ---> 0 => INTDST0 C66xx_0: GEL Output: LSU0_ICRR3.ICR30 ---> 0 => INTDST0 C66xx_0: GEL Output: LSU0_ICRR3.ICR31 ---> 0 => INTDST0 C66xx_0: GEL Output: ********************************** LSU1 Interrupt Condition Routing Registers (LSU1_ICRR1) ****************************************************** C66xx_0: GEL Output: LSU1_ICRR1.ICR0 ---> 0 => INTDST0 C66xx_0: GEL Output: LSU1_ICRR1.ICR1 ---> 0 => INTDST0 C66xx_0: GEL Output: LSU1_ICRR1.ICR2 ---> 0 => INTDST0 C66xx_0: GEL Output: LSU1_ICRR1.ICR3 ---> 0 => INTDST0 C66xx_0: GEL Output: LSU1_ICRR1.ICR4 ---> 0 => INTDST0 C66xx_0: GEL Output: LSU1_ICRR1.ICR5 ---> 0 => INTDST0 C66xx_0: GEL Output: LSU1_ICRR1.ICR6 ---> 0 => INTDST0 C66xx_0: GEL Output: LSU1_ICRR1.ICR7 ---> 0 => INTDST0 C66xx_0: GEL Output: ********************************** Error, Reset, and Special Event Interrupt Condition Routing Registers (ERR_RST_EVNT_ICRR, ERR_RST_EVNT_ICRR2, and ERR_RST_EVNT_ICRR3) ****************************************************** C66xx_0: GEL Output: ERR_RST_EVNT_ICRR.ICR0 ---> 0 => INTDST0 C66xx_0: GEL Output: ERR_RST_EVNT_ICRR.ICR1 ---> 0 => INTDST0 C66xx_0: GEL Output: ERR_RST_EVNT_ICRR.ICR2 ---> 0 => INTDST0 C66xx_0: GEL Output: ERR_RST_EVNT_ICRR2.ICR0 ---> 0 => INTDST0 C66xx_0: GEL Output: ERR_RST_EVNT_ICRR2.ICR1 ---> 0 => INTDST0 C66xx_0: GEL Output: ERR_RST_EVNT_ICRR2.ICR2 ---> 0 => INTDST0 C66xx_0: GEL Output: ERR_RST_EVNT_ICRR2.ICR3 ---> 0 => INTDST0 C66xx_0: GEL Output: ERR_RST_EVNT_ICRR3.ICR16 ---> 0 => INTDST0 C66xx_0: GEL Output: ******************************************************************************************************* C66xx_0: GEL Output: ********************************** FARADAY SRIO INTERRUPTS STATUS ****************************************************** C66xx_0: GEL Output: ******************************************************************************************************* C66xx_0: GEL Output: ********************************** DOORBELLn Interrupt Condition Status Register (DOORBELLn_ICSR) ****************************************************** C66xx_0: GEL Output: DOORBELL REG0 INTERRUPT CONDITION STATUS REGISTER: C66xx_0: GEL Output: DOORBELL0_ICSR.ICS0 ---> 0 => Doorbell Interrupt0 is ##NOT RECEIVED## C66xx_0: GEL Output: DOORBELL0_ICSR.ICS1 ---> 0 => Doorbell Interrupt1 is ##NOT RECEIVED## C66xx_0: GEL Output: DOORBELL0_ICSR.ICS2 ---> 0 => Doorbell Interrupt2 is ##NOT RECEIVED## C66xx_0: GEL Output: DOORBELL0_ICSR.ICS3 ---> 0 => Doorbell Interrupt3 is ##NOT RECEIVED## C66xx_0: GEL Output: DOORBELL0_ICSR.ICS4 ---> 0 => Doorbell Interrupt4 is ##NOT RECEIVED## C66xx_0: GEL Output: DOORBELL0_ICSR.ICS5 ---> 0 => Doorbell Interrupt5 is ##NOT RECEIVED## C66xx_0: GEL Output: DOORBELL0_ICSR.ICS6 ---> 0 => Doorbell Interrupt6 is ##NOT RECEIVED## C66xx_0: GEL Output: DOORBELL0_ICSR.ICS7 ---> 0 => Doorbell Interrupt7 is ##NOT RECEIVED## C66xx_0: GEL Output: DOORBELL0_ICSR.ICS8 ---> 0 => Doorbell Interrupt8 is ##NOT RECEIVED## C66xx_0: GEL Output: DOORBELL0_ICSR.ICS9 ---> 0 => Doorbell Interrupt9 is ##NOT RECEIVED## C66xx_0: GEL Output: DOORBELL0_ICSR.ICS10 ---> 0 => Doorbell Interrupt10 is ##NOT RECEIVED## C66xx_0: GEL Output: DOORBELL0_ICSR.ICS11 ---> 0 => Doorbell Interrupt11 is ##NOT RECEIVED## C66xx_0: GEL Output: DOORBELL0_ICSR.ICS12 ---> 0 => Doorbell Interrupt12 is ##NOT RECEIVED## C66xx_0: GEL Output: DOORBELL0_ICSR.ICS13 ---> 0 => Doorbell Interrupt13 is ##NOT RECEIVED## C66xx_0: GEL Output: DOORBELL0_ICSR.ICS14 ---> 0 => Doorbell Interrupt14 is ##NOT RECEIVED## C66xx_0: GEL Output: DOORBELL0_ICSR.ICS15 ---> 0 => Doorbell Interrupt15 is ##NOT RECEIVED## C66xx_0: GEL Output: DOORBELL REG1 INTERRUPT CONDITION STATUS REGISTER: C66xx_0: GEL Output: DOORBELL1_ICSR.ICS0 ---> 0 => Doorbell Interrupt16 is ##NOT RECEIVED## C66xx_0: GEL Output: DOORBELL1_ICSR.ICS1 ---> 0 => Doorbell Interrupt17 is ##NOT RECEIVED## C66xx_0: GEL Output: DOORBELL1_ICSR.ICS2 ---> 0 => Doorbell Interrupt18 is ##NOT RECEIVED## C66xx_0: GEL Output: DOORBELL1_ICSR.ICS3 ---> 0 => Doorbell Interrupt19 is ##NOT RECEIVED## C66xx_0: GEL Output: DOORBELL1_ICSR.ICS4 ---> 0 => Doorbell Interrupt20 is ##NOT RECEIVED## C66xx_0: GEL Output: DOORBELL1_ICSR.ICS5 ---> 0 => Doorbell Interrupt21 is ##NOT RECEIVED## C66xx_0: GEL Output: DOORBELL1_ICSR.ICS6 ---> 0 => Doorbell Interrupt22 is ##NOT RECEIVED## C66xx_0: GEL Output: DOORBELL1_ICSR.ICS7 ---> 0 => Doorbell Interrupt23 is ##NOT RECEIVED## C66xx_0: GEL Output: DOORBELL1_ICSR.ICS8 ---> 0 => Doorbell Interrupt24 is ##NOT RECEIVED## C66xx_0: GEL Output: DOORBELL1_ICSR.ICS9 ---> 0 => Doorbell Interrupt25 is ##NOT RECEIVED## C66xx_0: GEL Output: DOORBELL1_ICSR.ICS10 ---> 0 => Doorbell Interrupt26 is ##NOT RECEIVED## C66xx_0: GEL Output: DOORBELL1_ICSR.ICS11 ---> 0 => Doorbell Interrupt27 is ##NOT RECEIVED## C66xx_0: GEL Output: DOORBELL1_ICSR.ICS12 ---> 0 => Doorbell Interrupt28 is ##NOT RECEIVED## C66xx_0: GEL Output: DOORBELL1_ICSR.ICS13 ---> 0 => Doorbell Interrupt29 is ##NOT RECEIVED## C66xx_0: GEL Output: DOORBELL1_ICSR.ICS14 ---> 0 => Doorbell Interrupt30 is ##NOT RECEIVED## C66xx_0: GEL Output: DOORBELL1_ICSR.ICS15 ---> 0 => Doorbell Interrupt31 is ##NOT RECEIVED## C66xx_0: GEL Output: DOORBELL REG2 INTERRUPT CONDITION STATUS REGISTER: C66xx_0: GEL Output: DOORBELL2_ICSR.ICS0 ---> 0 => Doorbell Interrupt32 is ##NOT RECEIVED## C66xx_0: GEL Output: DOORBELL2_ICSR.ICS1 ---> 0 => Doorbell Interrupt33 is ##NOT RECEIVED## C66xx_0: GEL Output: DOORBELL2_ICSR.ICS2 ---> 0 => Doorbell Interrupt34 is ##NOT RECEIVED## C66xx_0: GEL Output: DOORBELL2_ICSR.ICS3 ---> 0 => Doorbell Interrupt35 is ##NOT RECEIVED## C66xx_0: GEL Output: DOORBELL2_ICSR.ICS4 ---> 0 => Doorbell Interrupt36 is ##NOT RECEIVED## C66xx_0: GEL Output: DOORBELL2_ICSR.ICS5 ---> 0 => Doorbell Interrupt37 is ##NOT RECEIVED## C66xx_0: GEL Output: DOORBELL2_ICSR.ICS6 ---> 0 => Doorbell Interrupt38 is ##NOT RECEIVED## C66xx_0: GEL Output: DOORBELL2_ICSR.ICS7 ---> 0 => Doorbell Interrupt39 is ##NOT RECEIVED## C66xx_0: GEL Output: DOORBELL2_ICSR.ICS8 ---> 0 => Doorbell Interrupt40 is ##NOT RECEIVED## C66xx_0: GEL Output: DOORBELL2_ICSR.ICS9 ---> 0 => Doorbell Interrupt41 is ##NOT RECEIVED## C66xx_0: GEL Output: DOORBELL2_ICSR.ICS10 ---> 0 => Doorbell Interrupt42 is ##NOT RECEIVED## C66xx_0: GEL Output: DOORBELL2_ICSR.ICS11 ---> 0 => Doorbell Interrupt43 is ##NOT RECEIVED## C66xx_0: GEL Output: DOORBELL2_ICSR.ICS12 ---> 0 => Doorbell Interrupt44 is ##NOT RECEIVED## C66xx_0: GEL Output: DOORBELL2_ICSR.ICS13 ---> 0 => Doorbell Interrupt45 is ##NOT RECEIVED## C66xx_0: GEL Output: DOORBELL2_ICSR.ICS14 ---> 0 => Doorbell Interrupt46 is ##NOT RECEIVED## C66xx_0: GEL Output: DOORBELL2_ICSR.ICS15 ---> 0 => Doorbell Interrupt47 is ##NOT RECEIVED## C66xx_0: GEL Output: DOORBELL REG3 INTERRUPT CONDITION STATUS REGISTER: C66xx_0: GEL Output: DOORBELL3_ICSR.ICS0 ---> 0 => Doorbell Interrupt48 is ##NOT RECEIVED## C66xx_0: GEL Output: DOORBELL3_ICSR.ICS1 ---> 0 => Doorbell Interrupt49 is ##NOT RECEIVED## C66xx_0: GEL Output: DOORBELL3_ICSR.ICS2 ---> 0 => Doorbell Interrupt50 is ##NOT RECEIVED## C66xx_0: GEL Output: DOORBELL3_ICSR.ICS3 ---> 0 => Doorbell Interrupt51 is ##NOT RECEIVED## C66xx_0: GEL Output: DOORBELL3_ICSR.ICS4 ---> 0 => Doorbell Interrupt52 is ##NOT RECEIVED## C66xx_0: GEL Output: DOORBELL3_ICSR.ICS5 ---> 0 => Doorbell Interrupt53 is ##NOT RECEIVED## C66xx_0: GEL Output: DOORBELL3_ICSR.ICS6 ---> 0 => Doorbell Interrupt54 is ##NOT RECEIVED## C66xx_0: GEL Output: DOORBELL3_ICSR.ICS7 ---> 0 => Doorbell Interrupt55 is ##NOT RECEIVED## C66xx_0: GEL Output: DOORBELL3_ICSR.ICS8 ---> 0 => Doorbell Interrupt56 is ##NOT RECEIVED## C66xx_0: GEL Output: DOORBELL3_ICSR.ICS9 ---> 0 => Doorbell Interrupt57 is ##NOT RECEIVED## C66xx_0: GEL Output: DOORBELL3_ICSR.ICS10 ---> 0 => Doorbell Interrupt58 is ##NOT RECEIVED## C66xx_0: GEL Output: DOORBELL3_ICSR.ICS11 ---> 0 => Doorbell Interrupt59 is ##NOT RECEIVED## C66xx_0: GEL Output: DOORBELL3_ICSR.ICS12 ---> 0 => Doorbell Interrupt60 is ##NOT RECEIVED## C66xx_0: GEL Output: DOORBELL3_ICSR.ICS13 ---> 0 => Doorbell Interrupt61 is ##NOT RECEIVED## C66xx_0: GEL Output: DOORBELL3_ICSR.ICS14 ---> 0 => Doorbell Interrupt62 is ##NOT RECEIVED## C66xx_0: GEL Output: DOORBELL3_ICSR.ICS15 ---> 0 => Doorbell Interrupt63 is ##NOT RECEIVED## C66xx_0: GEL Output: ********************************** LSU0 Interrupt Condition Status Register (LSU0_ICSR) ****************************************************** C66xx_0: GEL Output: PER SRCID BASED INTERRUPTS: C66xx_0: GEL Output: LSU GOOD INTERRUPTS: C66xx_0: GEL Output: LSU0_ICSR.ICS0 ---> 0 => SRCID0: Transaction **NOT COMPLETE** , No Errors (Posted/Non-posted) C66xx_0: GEL Output: LSU0_ICSR.ICS1 ---> 0 => SRCID1: Transaction **NOT COMPLETE** , No Errors (Posted/Non-posted) C66xx_0: GEL Output: LSU0_ICSR.ICS2 ---> 0 => SRCID2: Transaction **NOT COMPLETE** , No Errors (Posted/Non-posted) C66xx_0: GEL Output: LSU0_ICSR.ICS3 ---> 0 => SRCID3: Transaction **NOT COMPLETE** , No Errors (Posted/Non-posted) C66xx_0: GEL Output: LSU0_ICSR.ICS4 ---> 0 => SRCID4: Transaction **NOT COMPLETE** , No Errors (Posted/Non-posted) C66xx_0: GEL Output: LSU0_ICSR.ICS5 ---> 0 => SRCID5: Transaction **NOT COMPLETE** , No Errors (Posted/Non-posted) C66xx_0: GEL Output: LSU0_ICSR.ICS6 ---> 0 => SRCID6: Transaction **NOT COMPLETE** , No Errors (Posted/Non-posted) C66xx_0: GEL Output: LSU0_ICSR.ICS7 ---> 0 => SRCID7: Transaction **NOT COMPLETE** , No Errors (Posted/Non-posted) C66xx_0: GEL Output: LSU0_ICSR.ICS8 ---> 0 => SRCID8: Transaction **NOT COMPLETE** , No Errors (Posted/Non-posted) C66xx_0: GEL Output: LSU0_ICSR.ICS9 ---> 0 => SRCID9: Transaction **NOT COMPLETE** , No Errors (Posted/Non-posted) C66xx_0: GEL Output: LSU0_ICSR.ICS10 ---> 0 => SRCID10: Transaction **NOT COMPLETE** , No Errors (Posted/Non-posted) C66xx_0: GEL Output: LSU0_ICSR.ICS11 ---> 0 => SRCID11: Transaction **NOT COMPLETE** , No Errors (Posted/Non-posted) C66xx_0: GEL Output: LSU0_ICSR.ICS12 ---> 0 => SRCID12: Transaction **NOT COMPLETE** , No Errors (Posted/Non-posted) C66xx_0: GEL Output: LSU0_ICSR.ICS13 ---> 0 => SRCID13: Transaction **NOT COMPLETE** , No Errors (Posted/Non-posted) C66xx_0: GEL Output: LSU0_ICSR.ICS14 ---> 0 => SRCID14: Transaction **NOT COMPLETE** , No Errors (Posted/Non-posted) C66xx_0: GEL Output: LSU0_ICSR.ICS15 ---> 0 => SRCID15: Transaction **NOT COMPLETE** , No Errors (Posted/Non-posted) C66xx_0: GEL Output: LSU BAD INTERRUPTS: C66xx_0: GEL Output: LSU0_ICSR.ICS16 ---> 0 => SRCID0: Transaction **NOT COMPLETE** , No Errors (Posted/Non-posted) C66xx_0: GEL Output: LSU0_ICSR.ICS17 ---> 0 => SRCID1: Transaction **NOT COMPLETE** , No Errors (Posted/Non-posted) C66xx_0: GEL Output: LSU0_ICSR.ICS18 ---> 0 => SRCID2: Transaction **NOT COMPLETE** , No Errors (Posted/Non-posted) C66xx_0: GEL Output: LSU0_ICSR.ICS19 ---> 0 => SRCID3: Transaction **NOT COMPLETE** , No Errors (Posted/Non-posted) C66xx_0: GEL Output: LSU0_ICSR.ICS20 ---> 0 => SRCID4: Transaction **NOT COMPLETE** , No Errors (Posted/Non-posted) C66xx_0: GEL Output: LSU0_ICSR.ICS21 ---> 0 => SRCID5: Transaction **NOT COMPLETE** , No Errors (Posted/Non-posted) C66xx_0: GEL Output: LSU0_ICSR.ICS22 ---> 0 => SRCID6: Transaction **NOT COMPLETE** , No Errors (Posted/Non-posted) C66xx_0: GEL Output: LSU0_ICSR.ICS23 ---> 0 => SRCID7: Transaction **NOT COMPLETE** , No Errors (Posted/Non-posted) C66xx_0: GEL Output: LSU0_ICSR.ICS24 ---> 0 => SRCID8: Transaction **NOT COMPLETE** , No Errors (Posted/Non-posted) C66xx_0: GEL Output: LSU0_ICSR.ICS25 ---> 0 => SRCID9: Transaction **NOT COMPLETE** , No Errors (Posted/Non-posted) C66xx_0: GEL Output: LSU0_ICSR.ICS26 ---> 0 => SRCID10: Transaction **NOT COMPLETE** , No Errors (Posted/Non-posted) C66xx_0: GEL Output: LSU0_ICSR.ICS27 ---> 0 => SRCID11: Transaction **NOT COMPLETE** , No Errors (Posted/Non-posted) C66xx_0: GEL Output: LSU0_ICSR.ICS28 ---> 0 => SRCID12: Transaction **NOT COMPLETE** , No Errors (Posted/Non-posted) C66xx_0: GEL Output: LSU0_ICSR.ICS29 ---> 0 => SRCID13: Transaction **NOT COMPLETE** , No Errors (Posted/Non-posted) C66xx_0: GEL Output: LSU0_ICSR.ICS30 ---> 0 => SRCID14: Transaction **NOT COMPLETE** , No Errors (Posted/Non-posted) C66xx_0: GEL Output: LSU0_ICSR.ICS31 ---> 0 => SRCID15: Transaction **NOT COMPLETE** , No Errors (Posted/Non-posted) C66xx_0: GEL Output: ********************************** LSU1 Interrupt Condition Status Register (LSU1_ICSR) ****************************************************** C66xx_0: GEL Output: PER LSU BASED INTERRUPTS: C66xx_0: GEL Output: LSU1_ICSR.ICS0 ---> 0 => LSU0, Transaction **NOT COMPLETE** , No Errors (Posted/Non-posted) C66xx_0: GEL Output: LSU1_ICSR.ICS1 ---> 0 => LSU1, Transaction **NOT COMPLETE** , No Errors (Posted/Non-posted) C66xx_0: GEL Output: LSU1_ICSR.ICS2 ---> 0 => LSU2, Transaction **NOT COMPLETE** , No Errors (Posted/Non-posted) C66xx_0: GEL Output: LSU1_ICSR.ICS3 ---> 0 => LSU3, Transaction **NOT COMPLETE** , No Errors (Posted/Non-posted) C66xx_0: GEL Output: LSU1_ICSR.ICS4 ---> 0 => LSU4, Transaction **NOT COMPLETE** , No Errors (Posted/Non-posted) C66xx_0: GEL Output: LSU1_ICSR.ICS5 ---> 0 => LSU5, Transaction **NOT COMPLETE** , No Errors (Posted/Non-posted) C66xx_0: GEL Output: LSU1_ICSR.ICS6 ---> 0 => LSU6, Transaction **NOT COMPLETE** , No Errors (Posted/Non-posted) C66xx_0: GEL Output: LSU1_ICSR.ICS7 ---> 0 => LSU7, Transaction **NOT COMPLETE** , No Errors (Posted/Non-posted) C66xx_0: GEL Output: ********************************** Error, Reset, and Special Event Interrupt Condition Status Register (ERR_RST_EVNT_ICSR) ****************************************************** C66xx_0: GEL Output: ERR_RST_EVNT_ICSR.ICS0 ---> 0 => Multi-cast event control symbol interrupt ##NOT RECEIVED## on any port C66xx_0: GEL Output: ERR_RST_EVNT_ICSR.ICS1 ---> 0 => Port-write-in request ##NOT RECEIVED## on any port C66xx_0: GEL Output: ERR_RST_EVNT_ICSR.ICS2 ---> 0 => Logical layer error management event capture ##NOT DETECTED## C66xx_0: GEL Output: ERR_RST_EVNT_ICSR.ICS8 ---> 0 => Error ##NOT DETECTED## on port 0 C66xx_0: GEL Output: ERR_RST_EVNT_ICSR.ICS9 ---> 0 => Error ##NOT DETECTED## on port 1 C66xx_0: GEL Output: ERR_RST_EVNT_ICSR.ICS10 ---> 0 => Error ##NOT DETECTED## on port 2 C66xx_0: GEL Output: ERR_RST_EVNT_ICSR.ICS11 ---> 0 => Error ##NOT DETECTED## on port 3 C66xx_0: GEL Output: ERR_RST_EVNT_ICSR.ICS16 ---> 0 => Device reset interrupt ##NOT RECEIVED## from any port C66xx_0: GEL Output: ********************************** Interrupt Status Decode Register (INTDSTn_DECODE) ****************************************************** C66xx_0: GEL Output: INTERRUPT DST0 STATUS DECODE REGISTER: C66xx_0: GEL Output: INTDST0_DECODE.ISD0 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST0_DECODE.ISD1 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST0_DECODE.ISD2 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST0_DECODE.ISD3 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST0_DECODE.ISD4 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST0_DECODE.ISD5 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST0_DECODE.ISD6 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST0_DECODE.ISD7 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST0_DECODE.ISD8 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST0_DECODE.ISD9 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST0_DECODE.ISD10 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST0_DECODE.ISD11 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST0_DECODE.ISD12 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST0_DECODE.ISD13 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST0_DECODE.ISD14 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST0_DECODE.ISD15 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST0_DECODE.ISD16 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST0_DECODE.ISD17 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST0_DECODE.ISD18 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST0_DECODE.ISD20 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTERRUPT DST1 STATUS DECODE REGISTER: C66xx_0: GEL Output: INTDST1_DECODE.ISD0 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST1_DECODE.ISD1 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST1_DECODE.ISD2 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST1_DECODE.ISD3 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST1_DECODE.ISD4 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST1_DECODE.ISD5 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST1_DECODE.ISD6 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST1_DECODE.ISD7 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST1_DECODE.ISD8 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST1_DECODE.ISD9 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST1_DECODE.ISD10 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST1_DECODE.ISD11 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST1_DECODE.ISD12 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST1_DECODE.ISD13 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST1_DECODE.ISD14 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST1_DECODE.ISD15 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST1_DECODE.ISD16 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST1_DECODE.ISD17 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST1_DECODE.ISD18 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST1_DECODE.ISD20 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTERRUPT DST2 STATUS DECODE REGISTER: C66xx_0: GEL Output: INTDST2_DECODE.ISD0 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST2_DECODE.ISD1 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST2_DECODE.ISD2 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST2_DECODE.ISD3 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST2_DECODE.ISD4 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST2_DECODE.ISD5 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST2_DECODE.ISD6 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST2_DECODE.ISD7 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST2_DECODE.ISD8 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST2_DECODE.ISD9 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST2_DECODE.ISD10 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST2_DECODE.ISD11 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST2_DECODE.ISD12 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST2_DECODE.ISD13 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST2_DECODE.ISD14 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST2_DECODE.ISD15 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST2_DECODE.ISD16 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST2_DECODE.ISD17 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST2_DECODE.ISD18 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST2_DECODE.ISD20 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTERRUPT DST3 STATUS DECODE REGISTER: C66xx_0: GEL Output: INTDST3_DECODE.ISD0 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST3_DECODE.ISD1 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST3_DECODE.ISD2 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST3_DECODE.ISD3 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST3_DECODE.ISD4 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST3_DECODE.ISD5 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST3_DECODE.ISD6 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST3_DECODE.ISD7 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST3_DECODE.ISD8 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST3_DECODE.ISD9 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST3_DECODE.ISD10 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST3_DECODE.ISD11 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST3_DECODE.ISD12 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST3_DECODE.ISD13 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST3_DECODE.ISD14 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST3_DECODE.ISD15 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST3_DECODE.ISD16 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST3_DECODE.ISD17 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST3_DECODE.ISD18 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST3_DECODE.ISD20 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTERRUPT DST4 STATUS DECODE REGISTER: C66xx_0: GEL Output: INTDST4_DECODE.ISD0 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST4_DECODE.ISD1 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST4_DECODE.ISD2 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST4_DECODE.ISD3 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST4_DECODE.ISD4 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST4_DECODE.ISD5 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST4_DECODE.ISD6 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST4_DECODE.ISD7 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST4_DECODE.ISD8 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST4_DECODE.ISD9 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST4_DECODE.ISD10 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST4_DECODE.ISD11 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST4_DECODE.ISD12 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST4_DECODE.ISD13 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST4_DECODE.ISD14 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST4_DECODE.ISD15 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST4_DECODE.ISD16 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST4_DECODE.ISD17 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST4_DECODE.ISD18 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST4_DECODE.ISD20 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTERRUPT DST5 STATUS DECODE REGISTER: C66xx_0: GEL Output: INTDST5_DECODE.ISD0 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST5_DECODE.ISD1 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST5_DECODE.ISD2 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST5_DECODE.ISD3 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST5_DECODE.ISD4 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST5_DECODE.ISD5 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST5_DECODE.ISD6 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST5_DECODE.ISD7 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST5_DECODE.ISD8 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST5_DECODE.ISD9 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST5_DECODE.ISD10 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST5_DECODE.ISD11 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST5_DECODE.ISD12 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST5_DECODE.ISD13 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST5_DECODE.ISD14 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST5_DECODE.ISD15 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST5_DECODE.ISD16 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST5_DECODE.ISD17 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST5_DECODE.ISD18 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST5_DECODE.ISD20 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTERRUPT DST6 STATUS DECODE REGISTER: C66xx_0: GEL Output: INTDST6_DECODE.ISD0 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST6_DECODE.ISD1 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST6_DECODE.ISD2 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST6_DECODE.ISD3 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST6_DECODE.ISD4 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST6_DECODE.ISD5 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST6_DECODE.ISD6 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST6_DECODE.ISD7 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST6_DECODE.ISD8 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST6_DECODE.ISD9 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST6_DECODE.ISD10 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST6_DECODE.ISD11 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST6_DECODE.ISD12 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST6_DECODE.ISD13 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST6_DECODE.ISD14 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST6_DECODE.ISD15 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST6_DECODE.ISD16 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST6_DECODE.ISD17 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST6_DECODE.ISD18 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST6_DECODE.ISD20 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTERRUPT DST7 STATUS DECODE REGISTER: C66xx_0: GEL Output: INTDST7_DECODE.ISD0 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST7_DECODE.ISD1 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST7_DECODE.ISD2 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST7_DECODE.ISD3 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST7_DECODE.ISD4 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST7_DECODE.ISD5 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST7_DECODE.ISD6 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST7_DECODE.ISD7 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST7_DECODE.ISD8 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST7_DECODE.ISD9 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST7_DECODE.ISD10 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST7_DECODE.ISD11 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST7_DECODE.ISD12 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST7_DECODE.ISD13 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST7_DECODE.ISD14 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST7_DECODE.ISD15 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST7_DECODE.ISD16 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST7_DECODE.ISD17 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST7_DECODE.ISD18 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST7_DECODE.ISD20 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTERRUPT DST8 STATUS DECODE REGISTER: C66xx_0: GEL Output: INTDST8_DECODE.ISD0 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST8_DECODE.ISD1 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST8_DECODE.ISD2 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST8_DECODE.ISD3 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST8_DECODE.ISD4 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST8_DECODE.ISD5 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST8_DECODE.ISD6 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST8_DECODE.ISD7 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST8_DECODE.ISD8 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST8_DECODE.ISD9 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST8_DECODE.ISD10 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST8_DECODE.ISD11 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST8_DECODE.ISD12 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST8_DECODE.ISD13 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST8_DECODE.ISD14 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST8_DECODE.ISD15 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST8_DECODE.ISD16 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST8_DECODE.ISD17 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST8_DECODE.ISD18 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST8_DECODE.ISD20 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTERRUPT DST9 STATUS DECODE REGISTER: C66xx_0: GEL Output: INTDST9_DECODE.ISD0 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST9_DECODE.ISD1 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST9_DECODE.ISD2 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST9_DECODE.ISD3 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST9_DECODE.ISD4 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST9_DECODE.ISD5 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST9_DECODE.ISD6 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST9_DECODE.ISD7 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST9_DECODE.ISD8 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST9_DECODE.ISD9 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST9_DECODE.ISD10 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST9_DECODE.ISD11 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST9_DECODE.ISD12 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST9_DECODE.ISD13 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST9_DECODE.ISD14 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST9_DECODE.ISD15 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST9_DECODE.ISD16 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST9_DECODE.ISD17 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST9_DECODE.ISD18 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST9_DECODE.ISD20 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTERRUPT DST10 STATUS DECODE REGISTER: C66xx_0: GEL Output: INTDST10_DECODE.ISD0 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST10_DECODE.ISD1 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST10_DECODE.ISD2 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST10_DECODE.ISD3 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST10_DECODE.ISD4 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST10_DECODE.ISD5 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST10_DECODE.ISD6 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST10_DECODE.ISD7 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST10_DECODE.ISD8 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST10_DECODE.ISD9 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST10_DECODE.ISD10 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST10_DECODE.ISD11 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST10_DECODE.ISD12 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST10_DECODE.ISD13 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST10_DECODE.ISD14 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST10_DECODE.ISD15 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST10_DECODE.ISD16 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST10_DECODE.ISD17 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST10_DECODE.ISD18 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST10_DECODE.ISD20 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTERRUPT DST11 STATUS DECODE REGISTER: C66xx_0: GEL Output: INTDST11_DECODE.ISD0 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST11_DECODE.ISD1 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST11_DECODE.ISD2 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST11_DECODE.ISD3 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST11_DECODE.ISD4 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST11_DECODE.ISD5 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST11_DECODE.ISD6 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST11_DECODE.ISD7 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST11_DECODE.ISD8 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST11_DECODE.ISD9 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST11_DECODE.ISD10 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST11_DECODE.ISD11 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST11_DECODE.ISD12 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST11_DECODE.ISD13 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST11_DECODE.ISD14 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST11_DECODE.ISD15 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST11_DECODE.ISD16 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST11_DECODE.ISD17 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST11_DECODE.ISD18 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST11_DECODE.ISD20 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTERRUPT DST12 STATUS DECODE REGISTER: C66xx_0: GEL Output: INTDST12_DECODE.ISD0 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST12_DECODE.ISD1 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST12_DECODE.ISD2 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST12_DECODE.ISD3 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST12_DECODE.ISD4 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST12_DECODE.ISD5 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST12_DECODE.ISD6 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST12_DECODE.ISD7 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST12_DECODE.ISD8 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST12_DECODE.ISD9 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST12_DECODE.ISD10 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST12_DECODE.ISD11 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST12_DECODE.ISD12 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST12_DECODE.ISD13 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST12_DECODE.ISD14 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST12_DECODE.ISD15 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST12_DECODE.ISD16 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST12_DECODE.ISD17 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST12_DECODE.ISD18 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST12_DECODE.ISD20 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTERRUPT DST13 STATUS DECODE REGISTER: C66xx_0: GEL Output: INTDST13_DECODE.ISD0 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST13_DECODE.ISD1 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST13_DECODE.ISD2 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST13_DECODE.ISD3 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST13_DECODE.ISD4 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST13_DECODE.ISD5 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST13_DECODE.ISD6 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST13_DECODE.ISD7 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST13_DECODE.ISD8 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST13_DECODE.ISD9 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST13_DECODE.ISD10 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST13_DECODE.ISD11 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST13_DECODE.ISD12 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST13_DECODE.ISD13 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST13_DECODE.ISD14 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST13_DECODE.ISD15 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST13_DECODE.ISD16 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST13_DECODE.ISD17 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST13_DECODE.ISD18 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST13_DECODE.ISD20 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTERRUPT DST14 STATUS DECODE REGISTER: C66xx_0: GEL Output: INTDST14_DECODE.ISD0 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST14_DECODE.ISD1 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST14_DECODE.ISD2 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST14_DECODE.ISD3 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST14_DECODE.ISD4 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST14_DECODE.ISD5 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST14_DECODE.ISD6 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST14_DECODE.ISD7 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST14_DECODE.ISD8 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST14_DECODE.ISD9 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST14_DECODE.ISD10 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST14_DECODE.ISD11 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST14_DECODE.ISD12 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST14_DECODE.ISD13 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST14_DECODE.ISD14 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST14_DECODE.ISD15 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST14_DECODE.ISD16 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST14_DECODE.ISD17 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST14_DECODE.ISD18 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST14_DECODE.ISD20 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTERRUPT DST15 STATUS DECODE REGISTER: C66xx_0: GEL Output: INTDST15_DECODE.ISD0 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST15_DECODE.ISD1 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST15_DECODE.ISD2 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST15_DECODE.ISD3 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST15_DECODE.ISD4 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST15_DECODE.ISD5 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST15_DECODE.ISD6 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST15_DECODE.ISD7 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST15_DECODE.ISD8 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST15_DECODE.ISD9 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST15_DECODE.ISD10 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST15_DECODE.ISD11 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST15_DECODE.ISD12 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST15_DECODE.ISD13 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST15_DECODE.ISD14 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST15_DECODE.ISD15 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST15_DECODE.ISD16 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST15_DECODE.ISD17 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST15_DECODE.ISD18 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST15_DECODE.ISD20 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTERRUPT DST16 STATUS DECODE REGISTER: C66xx_0: GEL Output: INTDST16_DECODE.ISD0 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST16_DECODE.ISD1 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST16_DECODE.ISD2 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST16_DECODE.ISD3 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST16_DECODE.ISD4 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST16_DECODE.ISD5 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST16_DECODE.ISD6 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST16_DECODE.ISD7 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST16_DECODE.ISD8 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST16_DECODE.ISD9 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST16_DECODE.ISD10 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST16_DECODE.ISD11 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST16_DECODE.ISD12 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST16_DECODE.ISD13 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST16_DECODE.ISD14 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST16_DECODE.ISD15 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST16_DECODE.ISD16 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST16_DECODE.ISD17 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST16_DECODE.ISD18 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST16_DECODE.ISD20 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTERRUPT DST17 STATUS DECODE REGISTER: C66xx_0: GEL Output: INTDST17_DECODE.ISD0 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST17_DECODE.ISD1 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST17_DECODE.ISD2 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST17_DECODE.ISD3 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST17_DECODE.ISD4 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST17_DECODE.ISD5 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST17_DECODE.ISD6 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST17_DECODE.ISD7 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST17_DECODE.ISD8 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST17_DECODE.ISD9 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST17_DECODE.ISD10 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST17_DECODE.ISD11 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST17_DECODE.ISD12 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST17_DECODE.ISD13 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST17_DECODE.ISD14 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST17_DECODE.ISD15 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST17_DECODE.ISD16 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST17_DECODE.ISD17 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST17_DECODE.ISD18 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST17_DECODE.ISD20 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTERRUPT DST18 STATUS DECODE REGISTER: C66xx_0: GEL Output: INTDST18_DECODE.ISD0 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST18_DECODE.ISD1 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST18_DECODE.ISD2 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST18_DECODE.ISD3 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST18_DECODE.ISD4 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST18_DECODE.ISD5 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST18_DECODE.ISD6 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST18_DECODE.ISD7 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST18_DECODE.ISD8 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST18_DECODE.ISD9 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST18_DECODE.ISD10 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST18_DECODE.ISD11 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST18_DECODE.ISD12 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST18_DECODE.ISD13 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST18_DECODE.ISD14 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST18_DECODE.ISD15 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST18_DECODE.ISD16 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST18_DECODE.ISD17 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST18_DECODE.ISD18 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST18_DECODE.ISD20 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTERRUPT DST19 STATUS DECODE REGISTER: C66xx_0: GEL Output: INTDST19_DECODE.ISD0 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST19_DECODE.ISD1 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST19_DECODE.ISD2 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST19_DECODE.ISD3 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST19_DECODE.ISD4 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST19_DECODE.ISD5 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST19_DECODE.ISD6 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST19_DECODE.ISD7 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST19_DECODE.ISD8 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST19_DECODE.ISD9 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST19_DECODE.ISD10 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST19_DECODE.ISD11 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST19_DECODE.ISD12 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST19_DECODE.ISD13 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST19_DECODE.ISD14 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST19_DECODE.ISD15 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST19_DECODE.ISD16 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST19_DECODE.ISD17 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST19_DECODE.ISD18 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST19_DECODE.ISD20 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTERRUPT DST20 STATUS DECODE REGISTER: C66xx_0: GEL Output: INTDST20_DECODE.ISD0 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST20_DECODE.ISD1 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST20_DECODE.ISD2 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST20_DECODE.ISD3 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST20_DECODE.ISD4 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST20_DECODE.ISD5 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST20_DECODE.ISD6 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST20_DECODE.ISD7 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST20_DECODE.ISD8 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST20_DECODE.ISD9 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST20_DECODE.ISD10 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST20_DECODE.ISD11 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST20_DECODE.ISD12 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST20_DECODE.ISD13 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST20_DECODE.ISD14 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST20_DECODE.ISD15 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST20_DECODE.ISD16 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST20_DECODE.ISD17 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST20_DECODE.ISD18 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST20_DECODE.ISD20 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTERRUPT DST21 STATUS DECODE REGISTER: C66xx_0: GEL Output: INTDST21_DECODE.ISD0 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST21_DECODE.ISD1 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST21_DECODE.ISD2 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST21_DECODE.ISD3 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST21_DECODE.ISD4 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST21_DECODE.ISD5 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST21_DECODE.ISD6 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST21_DECODE.ISD7 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST21_DECODE.ISD8 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST21_DECODE.ISD9 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST21_DECODE.ISD10 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST21_DECODE.ISD11 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST21_DECODE.ISD12 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST21_DECODE.ISD13 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST21_DECODE.ISD14 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST21_DECODE.ISD15 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST21_DECODE.ISD16 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST21_DECODE.ISD17 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST21_DECODE.ISD18 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST21_DECODE.ISD20 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTERRUPT DST22 STATUS DECODE REGISTER: C66xx_0: GEL Output: INTDST22_DECODE.ISD0 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST22_DECODE.ISD1 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST22_DECODE.ISD2 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST22_DECODE.ISD3 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST22_DECODE.ISD4 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST22_DECODE.ISD5 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST22_DECODE.ISD6 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST22_DECODE.ISD7 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST22_DECODE.ISD8 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST22_DECODE.ISD9 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST22_DECODE.ISD10 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST22_DECODE.ISD11 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST22_DECODE.ISD12 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST22_DECODE.ISD13 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST22_DECODE.ISD14 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST22_DECODE.ISD15 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST22_DECODE.ISD16 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST22_DECODE.ISD17 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST22_DECODE.ISD18 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST22_DECODE.ISD20 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTERRUPT DST23 STATUS DECODE REGISTER: C66xx_0: GEL Output: INTDST23_DECODE.ISD0 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST23_DECODE.ISD1 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST23_DECODE.ISD2 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST23_DECODE.ISD3 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST23_DECODE.ISD4 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST23_DECODE.ISD5 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST23_DECODE.ISD6 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST23_DECODE.ISD7 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST23_DECODE.ISD8 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST23_DECODE.ISD9 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST23_DECODE.ISD10 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST23_DECODE.ISD11 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST23_DECODE.ISD12 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST23_DECODE.ISD13 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST23_DECODE.ISD14 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST23_DECODE.ISD15 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST23_DECODE.ISD16 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST23_DECODE.ISD17 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST23_DECODE.ISD18 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: INTDST23_DECODE.ISD20 ---> 0 => ##NO INTERRUPT REQUEST ROUTED## to this bit. C66xx_0: GEL Output: ******************************************************************************************************* C66xx_0: GEL Output: ********************************** SRIO LSU CONFIGURATION****************************************************** C66xx_0: GEL Output: ******************************************************************************************************* C66xx_0: GEL Output: ********************************** SRIO LSU0 CONFIGURATION****************************************************** C66xx_0: GEL Output: The total number of shadow registers associated with the LSU0 => 4 C66xx_0: GEL Output: LSU0_EDMA => Cmd completion will be signalled as an interrupt based on the SRCID C66xx_0: GEL Output: TIMEOUT_CNT => After an error condition, Timecode changes only once before the LSU transaction is discarded and a new transaction is loaded from the shadow register C66xx_0: GEL Output: *********** DIO PKT DETAILS *********** C66xx_0: GEL Output: ADDRESS_MSB ---> 0x00000000 C66xx_0: GEL Output: ADDRESS_LSB/CONFIG_OFFSET ---> 0x00000648 C66xx_0: GEL Output: LSUn_REG2.DSP_ADDRESS ---> 0x80228670 C66xx_0: GEL Output: BYTE_COUNT ---> 0 C66xx_0: GEL Output: Drbll_val ---> A doorbell pkt with drbll_info is ##NOT SENT## after succesfully sending a DIO pkt C66xx_0: GEL Output: INTERRUPT_REQ ---> Interrupt not requested upon completion of command C66xx_0: GEL Output: XAMSB ---> 0x00 C66xx_0: GEL Output: PRIORITY ---> VC: 0, PRIO: 0, CRF: 0 C66xx_0: GEL Output: OUTPORT_ID ---> Port0 C66xx_0: GEL Output: ID_SIZE ---> 16 bit device IDs C66xx_0: GEL Output: SRC_ID(RIO_DEVID0) ---> 0x0000 C66xx_0: GEL Output: DESTID ---> 0x0077 C66xx_0: GEL Output: PKT_TYPE ---> NWRITE packet C66xx_0: GEL Output: HOP_COUNT ---> 0x00 C66xx_0: GEL Output: DRBLL_INFO ---> 0x0000 C66xx_0: GEL Output: FLOW_MASK ---> 0xFFFF C66xx_0: GEL Output: ********************************** SRIO LSU1 CONFIGURATION****************************************************** C66xx_0: GEL Output: The total number of shadow registers associated with the LSU1 => 4 C66xx_0: GEL Output: LSU1_EDMA => Cmd completion will be signalled as an interrupt based on the SRCID C66xx_0: GEL Output: TIMEOUT_CNT => After an error condition, Timecode changes only once before the LSU transaction is discarded and a new transaction is loaded from the shadow register C66xx_0: GEL Output: *********** DIO PKT DETAILS *********** C66xx_0: GEL Output: ADDRESS_MSB ---> 0x00000000 C66xx_0: GEL Output: ADDRESS_LSB/CONFIG_OFFSET ---> 0x00000000 C66xx_0: GEL Output: LSUn_REG2.DSP_ADDRESS ---> 0x00000000 C66xx_0: GEL Output: BYTE_COUNT ---> 0 C66xx_0: GEL Output: Drbll_val ---> A doorbell pkt with drbll_info is ##NOT SENT## after succesfully sending a DIO pkt C66xx_0: GEL Output: INTERRUPT_REQ ---> Interrupt not requested upon completion of command C66xx_0: GEL Output: XAMSB ---> 0x00 C66xx_0: GEL Output: PRIORITY ---> VC: 0, PRIO: 0, CRF: 0 C66xx_0: GEL Output: OUTPORT_ID ---> Port0 C66xx_0: GEL Output: ID_SIZE ---> 8 bit device IDs C66xx_0: GEL Output: SRC_ID(RIO_DEVID0) ---> 0x00 C66xx_0: GEL Output: DESTID ---> 0x0077 C66xx_0: GEL Output: PKT_TYPE ---> NWRITE packet C66xx_0: GEL Output: HOP_COUNT ---> 0x00 C66xx_0: GEL Output: DRBLL_INFO ---> 0x0000 C66xx_0: GEL Output: FLOW_MASK ---> 0xFFFF C66xx_0: GEL Output: ********************************** SRIO LSU2 CONFIGURATION****************************************************** C66xx_0: GEL Output: The total number of shadow registers associated with the LSU2 => 4 C66xx_0: GEL Output: LSU2_EDMA => Cmd completion will be signalled as an interrupt based on the SRCID C66xx_0: GEL Output: TIMEOUT_CNT => After an error condition, Timecode changes only once before the LSU transaction is discarded and a new transaction is loaded from the shadow register C66xx_0: GEL Output: *********** DIO PKT DETAILS *********** C66xx_0: GEL Output: ADDRESS_MSB ---> 0x00000000 C66xx_0: GEL Output: ADDRESS_LSB/CONFIG_OFFSET ---> 0x00000000 C66xx_0: GEL Output: LSUn_REG2.DSP_ADDRESS ---> 0x00000000 C66xx_0: GEL Output: BYTE_COUNT ---> 0 C66xx_0: GEL Output: Drbll_val ---> A doorbell pkt with drbll_info is ##NOT SENT## after succesfully sending a DIO pkt C66xx_0: GEL Output: INTERRUPT_REQ ---> Interrupt not requested upon completion of command C66xx_0: GEL Output: XAMSB ---> 0x00 C66xx_0: GEL Output: PRIORITY ---> VC: 0, PRIO: 0, CRF: 0 C66xx_0: GEL Output: OUTPORT_ID ---> Port0 C66xx_0: GEL Output: ID_SIZE ---> 8 bit device IDs C66xx_0: GEL Output: SRC_ID(RIO_DEVID0) ---> 0x00 C66xx_0: GEL Output: DESTID ---> 0x0077 C66xx_0: GEL Output: PKT_TYPE ---> NWRITE packet C66xx_0: GEL Output: HOP_COUNT ---> 0x00 C66xx_0: GEL Output: DRBLL_INFO ---> 0x0000 C66xx_0: GEL Output: FLOW_MASK ---> 0xFFFF C66xx_0: GEL Output: ********************************** SRIO LSU3 CONFIGURATION****************************************************** C66xx_0: GEL Output: The total number of shadow registers associated with the LSU3 => 4 C66xx_0: GEL Output: LSU3_EDMA => Cmd completion will be signalled as an interrupt based on the SRCID C66xx_0: GEL Output: TIMEOUT_CNT => After an error condition, Timecode changes only once before the LSU transaction is discarded and a new transaction is loaded from the shadow register C66xx_0: GEL Output: *********** DIO PKT DETAILS *********** C66xx_0: GEL Output: ADDRESS_MSB ---> 0x00000000 C66xx_0: GEL Output: ADDRESS_LSB/CONFIG_OFFSET ---> 0x00000000 C66xx_0: GEL Output: LSUn_REG2.DSP_ADDRESS ---> 0x00000000 C66xx_0: GEL Output: BYTE_COUNT ---> 0 C66xx_0: GEL Output: Drbll_val ---> A doorbell pkt with drbll_info is ##NOT SENT## after succesfully sending a DIO pkt C66xx_0: GEL Output: INTERRUPT_REQ ---> Interrupt not requested upon completion of command C66xx_0: GEL Output: XAMSB ---> 0x00 C66xx_0: GEL Output: PRIORITY ---> VC: 0, PRIO: 0, CRF: 0 C66xx_0: GEL Output: OUTPORT_ID ---> Port0 C66xx_0: GEL Output: ID_SIZE ---> 8 bit device IDs C66xx_0: GEL Output: SRC_ID(RIO_DEVID0) ---> 0x00 C66xx_0: GEL Output: DESTID ---> 0x0077 C66xx_0: GEL Output: PKT_TYPE ---> NWRITE packet C66xx_0: GEL Output: HOP_COUNT ---> 0x00 C66xx_0: GEL Output: DRBLL_INFO ---> 0x0000 C66xx_0: GEL Output: FLOW_MASK ---> 0xFFFF C66xx_0: GEL Output: ********************************** SRIO LSU4 CONFIGURATION****************************************************** C66xx_0: GEL Output: The total number of shadow registers associated with the LSU4 => 4 C66xx_0: GEL Output: LSU4_EDMA => Cmd completion will be signalled as an interrupt based on the SRCID C66xx_0: GEL Output: TIMEOUT_CNT => After an error condition, Timecode changes only once before the LSU transaction is discarded and a new transaction is loaded from the shadow register C66xx_0: GEL Output: *********** DIO PKT DETAILS *********** C66xx_0: GEL Output: ADDRESS_MSB ---> 0x00000000 C66xx_0: GEL Output: ADDRESS_LSB/CONFIG_OFFSET ---> 0x00000000 C66xx_0: GEL Output: LSUn_REG2.DSP_ADDRESS ---> 0x00000000 C66xx_0: GEL Output: BYTE_COUNT ---> 0 C66xx_0: GEL Output: Drbll_val ---> A doorbell pkt with drbll_info is ##NOT SENT## after succesfully sending a DIO pkt C66xx_0: GEL Output: INTERRUPT_REQ ---> Interrupt not requested upon completion of command C66xx_0: GEL Output: XAMSB ---> 0x00 C66xx_0: GEL Output: PRIORITY ---> VC: 0, PRIO: 0, CRF: 0 C66xx_0: GEL Output: OUTPORT_ID ---> Port0 C66xx_0: GEL Output: ID_SIZE ---> 8 bit device IDs C66xx_0: GEL Output: SRC_ID(RIO_DEVID0) ---> 0x00 C66xx_0: GEL Output: DESTID ---> 0x0077 C66xx_0: GEL Output: PKT_TYPE ---> NWRITE packet C66xx_0: GEL Output: HOP_COUNT ---> 0x00 C66xx_0: GEL Output: DRBLL_INFO ---> 0x0000 C66xx_0: GEL Output: FLOW_MASK ---> 0xFFFF C66xx_0: GEL Output: ********************************** SRIO LSU5 CONFIGURATION****************************************************** C66xx_0: GEL Output: The total number of shadow registers associated with the LSU5 => 4 C66xx_0: GEL Output: LSU5_EDMA => Cmd completion will be signalled as an interrupt based on the SRCID C66xx_0: GEL Output: TIMEOUT_CNT => After an error condition, Timecode changes only once before the LSU transaction is discarded and a new transaction is loaded from the shadow register C66xx_0: GEL Output: *********** DIO PKT DETAILS *********** C66xx_0: GEL Output: ADDRESS_MSB ---> 0x00000000 C66xx_0: GEL Output: ADDRESS_LSB/CONFIG_OFFSET ---> 0x00000000 C66xx_0: GEL Output: LSUn_REG2.DSP_ADDRESS ---> 0x00000000 C66xx_0: GEL Output: BYTE_COUNT ---> 0 C66xx_0: GEL Output: Drbll_val ---> A doorbell pkt with drbll_info is ##NOT SENT## after succesfully sending a DIO pkt C66xx_0: GEL Output: INTERRUPT_REQ ---> Interrupt not requested upon completion of command C66xx_0: GEL Output: XAMSB ---> 0x00 C66xx_0: GEL Output: PRIORITY ---> VC: 0, PRIO: 0, CRF: 0 C66xx_0: GEL Output: OUTPORT_ID ---> Port0 C66xx_0: GEL Output: ID_SIZE ---> 8 bit device IDs C66xx_0: GEL Output: SRC_ID(RIO_DEVID0) ---> 0x00 C66xx_0: GEL Output: DESTID ---> 0x0077 C66xx_0: GEL Output: PKT_TYPE ---> NWRITE packet C66xx_0: GEL Output: HOP_COUNT ---> 0x00 C66xx_0: GEL Output: DRBLL_INFO ---> 0x0000 C66xx_0: GEL Output: FLOW_MASK ---> 0xFFFF C66xx_0: GEL Output: ********************************** SRIO LSU6 CONFIGURATION****************************************************** C66xx_0: GEL Output: The total number of shadow registers associated with the LSU6 => 4 C66xx_0: GEL Output: LSU6_EDMA => Cmd completion will be signalled as an interrupt based on the SRCID C66xx_0: GEL Output: TIMEOUT_CNT => After an error condition, Timecode changes only once before the LSU transaction is discarded and a new transaction is loaded from the shadow register C66xx_0: GEL Output: *********** DIO PKT DETAILS *********** C66xx_0: GEL Output: ADDRESS_MSB ---> 0x00000000 C66xx_0: GEL Output: ADDRESS_LSB/CONFIG_OFFSET ---> 0x00000000 C66xx_0: GEL Output: LSUn_REG2.DSP_ADDRESS ---> 0x00000000 C66xx_0: GEL Output: BYTE_COUNT ---> 0 C66xx_0: GEL Output: Drbll_val ---> A doorbell pkt with drbll_info is ##NOT SENT## after succesfully sending a DIO pkt C66xx_0: GEL Output: INTERRUPT_REQ ---> Interrupt not requested upon completion of command C66xx_0: GEL Output: XAMSB ---> 0x00 C66xx_0: GEL Output: PRIORITY ---> VC: 0, PRIO: 0, CRF: 0 C66xx_0: GEL Output: OUTPORT_ID ---> Port0 C66xx_0: GEL Output: ID_SIZE ---> 8 bit device IDs C66xx_0: GEL Output: SRC_ID(RIO_DEVID0) ---> 0x00 C66xx_0: GEL Output: DESTID ---> 0x0077 C66xx_0: GEL Output: PKT_TYPE ---> NWRITE packet C66xx_0: GEL Output: HOP_COUNT ---> 0x00 C66xx_0: GEL Output: DRBLL_INFO ---> 0x0000 C66xx_0: GEL Output: FLOW_MASK ---> 0xFFFF C66xx_0: GEL Output: ********************************** SRIO LSU7 CONFIGURATION****************************************************** C66xx_0: GEL Output: The total number of shadow registers associated with the LSU7 => 4 C66xx_0: GEL Output: LSU7_EDMA => Cmd completion will be signalled as an interrupt based on the SRCID C66xx_0: GEL Output: TIMEOUT_CNT => After an error condition, Timecode changes only once before the LSU transaction is discarded and a new transaction is loaded from the shadow register C66xx_0: GEL Output: *********** DIO PKT DETAILS *********** C66xx_0: GEL Output: ADDRESS_MSB ---> 0x00000000 C66xx_0: GEL Output: ADDRESS_LSB/CONFIG_OFFSET ---> 0x00000000 C66xx_0: GEL Output: LSUn_REG2.DSP_ADDRESS ---> 0x00000000 C66xx_0: GEL Output: BYTE_COUNT ---> 0 C66xx_0: GEL Output: Drbll_val ---> A doorbell pkt with drbll_info is ##NOT SENT## after succesfully sending a DIO pkt C66xx_0: GEL Output: INTERRUPT_REQ ---> Interrupt not requested upon completion of command C66xx_0: GEL Output: XAMSB ---> 0x00 C66xx_0: GEL Output: PRIORITY ---> VC: 0, PRIO: 0, CRF: 0 C66xx_0: GEL Output: OUTPORT_ID ---> Port0 C66xx_0: GEL Output: ID_SIZE ---> 8 bit device IDs C66xx_0: GEL Output: SRC_ID(RIO_DEVID0) ---> 0x00 C66xx_0: GEL Output: DESTID ---> 0x0077 C66xx_0: GEL Output: PKT_TYPE ---> NWRITE packet C66xx_0: GEL Output: HOP_COUNT ---> 0x00 C66xx_0: GEL Output: DRBLL_INFO ---> 0x0000 C66xx_0: GEL Output: FLOW_MASK ---> 0xFFFF C66xx_0: GEL Output: ******************************************************************************************************* C66xx_0: GEL Output: ********************************** SRIO LSU STATUS ****************************************************** C66xx_0: GEL Output: ******************************************************************************************************* C66xx_0: GEL Output: ********************************** SRIO LSU0 STATUS ****************************************************** C66xx_0: GEL Output: BUSY => LSU0 is ##AVAILABLE## C66xx_0: GEL Output: FULL => LSU0 shadow registers are ##AVAILABLE## C66xx_0: GEL Output: CURRENT_LTID => Current shadow register in use: 0 C66xx_0: GEL Output: CURRENT_LCB => This transaction is the previous/next one having LTID: 0 C66xx_0: GEL Output: *********** LSU0 SHADOW REGISTERS STATUS: *********** C66xx_0: GEL Output: LCB => This transaction is the current one having LTID: 0 C66xx_0: GEL Output: CC => Transaction complete, No Errors (Posted/Non-posted) C66xx_0: GEL Output: LCB => This transaction is the current one having LTID: 1 C66xx_0: GEL Output: CC => Transaction complete, No Errors (Posted/Non-posted) C66xx_0: GEL Output: LCB => This transaction is the current one having LTID: 2 C66xx_0: GEL Output: CC => Transaction complete, No Errors (Posted/Non-posted) C66xx_0: GEL Output: LCB => This transaction is the current one having LTID: 3 C66xx_0: GEL Output: CC => Transaction complete, No Errors (Posted/Non-posted) C66xx_0: GEL Output: ********************************** SRIO LSU1 STATUS ****************************************************** C66xx_0: GEL Output: BUSY => LSU1 is ##AVAILABLE## C66xx_0: GEL Output: FULL => LSU1 shadow registers are ##AVAILABLE## C66xx_0: GEL Output: CURRENT_LTID => Current shadow register in use: 0 C66xx_0: GEL Output: CURRENT_LCB => This transaction is the current one having LTID: 0 C66xx_0: GEL Output: *********** LSU1 SHADOW REGISTERS STATUS: *********** C66xx_0: GEL Output: LCB => This transaction is the previous/next one having LTID: 0 C66xx_0: GEL Output: CC => Transaction complete, No Errors (Posted/Non-posted) C66xx_0: GEL Output: LCB => This transaction is the previous/next one having LTID: 1 C66xx_0: GEL Output: CC => Transaction complete, No Errors (Posted/Non-posted) C66xx_0: GEL Output: LCB => This transaction is the previous/next one having LTID: 2 C66xx_0: GEL Output: CC => Transaction complete, No Errors (Posted/Non-posted) C66xx_0: GEL Output: LCB => This transaction is the previous/next one having LTID: 3 C66xx_0: GEL Output: CC => Transaction complete, No Errors (Posted/Non-posted) C66xx_0: GEL Output: ********************************** SRIO LSU2 STATUS ****************************************************** C66xx_0: GEL Output: BUSY => LSU2 is ##AVAILABLE## C66xx_0: GEL Output: FULL => LSU2 shadow registers are ##AVAILABLE## C66xx_0: GEL Output: CURRENT_LTID => Current shadow register in use: 0 C66xx_0: GEL Output: CURRENT_LCB => This transaction is the current one having LTID: 0 C66xx_0: GEL Output: *********** LSU2 SHADOW REGISTERS STATUS: *********** C66xx_0: GEL Output: LCB => This transaction is the previous/next one having LTID: 0 C66xx_0: GEL Output: CC => Transaction complete, No Errors (Posted/Non-posted) C66xx_0: GEL Output: LCB => This transaction is the previous/next one having LTID: 0 C66xx_0: GEL Output: CC => Transaction complete, No Errors (Posted/Non-posted) C66xx_0: GEL Output: LCB => This transaction is the previous/next one having LTID: 1 C66xx_0: GEL Output: CC => Transaction complete, No Errors (Posted/Non-posted) C66xx_0: GEL Output: LCB => This transaction is the previous/next one having LTID: 2 C66xx_0: GEL Output: CC => Transaction complete, No Errors (Posted/Non-posted) C66xx_0: GEL Output: ********************************** SRIO LSU3 STATUS ****************************************************** C66xx_0: GEL Output: BUSY => LSU3 is ##AVAILABLE## C66xx_0: GEL Output: FULL => LSU3 shadow registers are ##AVAILABLE## C66xx_0: GEL Output: CURRENT_LTID => Current shadow register in use: 0 C66xx_0: GEL Output: CURRENT_LCB => This transaction is the current one having LTID: 0 C66xx_0: GEL Output: *********** LSU3 SHADOW REGISTERS STATUS: *********** C66xx_0: GEL Output: LCB => This transaction is the previous/next one having LTID: 0 C66xx_0: GEL Output: CC => Transaction complete, No Errors (Posted/Non-posted) C66xx_0: GEL Output: LCB => This transaction is the previous/next one having LTID: 1 C66xx_0: GEL Output: CC => Transaction complete, No Errors (Posted/Non-posted) C66xx_0: GEL Output: LCB => This transaction is the previous/next one having LTID: 2 C66xx_0: GEL Output: CC => Transaction complete, No Errors (Posted/Non-posted) C66xx_0: GEL Output: LCB => This transaction is the previous/next one having LTID: 3 C66xx_0: GEL Output: CC => Transaction complete, No Errors (Posted/Non-posted) C66xx_0: GEL Output: ********************************** SRIO LSU4 STATUS ****************************************************** C66xx_0: GEL Output: BUSY => LSU4 is ##AVAILABLE## C66xx_0: GEL Output: FULL => LSU4 shadow registers are ##AVAILABLE## C66xx_0: GEL Output: CURRENT_LTID => Current shadow register in use: 0 C66xx_0: GEL Output: CURRENT_LCB => This transaction is the current one having LTID: 0 C66xx_0: GEL Output: *********** LSU4 SHADOW REGISTERS STATUS: *********** C66xx_0: GEL Output: LCB => This transaction is the previous/next one having LTID: 0 C66xx_0: GEL Output: CC => Transaction complete, No Errors (Posted/Non-posted) C66xx_0: GEL Output: LCB => This transaction is the previous/next one having LTID: 1 C66xx_0: GEL Output: CC => Transaction complete, No Errors (Posted/Non-posted) C66xx_0: GEL Output: LCB => This transaction is the previous/next one having LTID: 2 C66xx_0: GEL Output: CC => Transaction complete, No Errors (Posted/Non-posted) C66xx_0: GEL Output: LCB => This transaction is the previous/next one having LTID: 3 C66xx_0: GEL Output: CC => Transaction complete, No Errors (Posted/Non-posted) C66xx_0: GEL Output: ********************************** SRIO LSU5 STATUS ****************************************************** C66xx_0: GEL Output: BUSY => LSU5 is ##AVAILABLE## C66xx_0: GEL Output: FULL => LSU5 shadow registers are ##AVAILABLE## C66xx_0: GEL Output: CURRENT_LTID => Current shadow register in use: 0 C66xx_0: GEL Output: CURRENT_LCB => This transaction is the current one having LTID: 0 C66xx_0: GEL Output: *********** LSU5 SHADOW REGISTERS STATUS: *********** C66xx_0: GEL Output: LCB => This transaction is the previous/next one having LTID: 0 C66xx_0: GEL Output: CC => Transaction complete, No Errors (Posted/Non-posted) C66xx_0: GEL Output: LCB => This transaction is the previous/next one having LTID: 1 C66xx_0: GEL Output: CC => Transaction complete, No Errors (Posted/Non-posted) C66xx_0: GEL Output: LCB => This transaction is the previous/next one having LTID: 2 C66xx_0: GEL Output: CC => Transaction complete, No Errors (Posted/Non-posted) C66xx_0: GEL Output: LCB => This transaction is the previous/next one having LTID: 3 C66xx_0: GEL Output: CC => Transaction complete, No Errors (Posted/Non-posted) C66xx_0: GEL Output: ********************************** SRIO LSU6 STATUS ****************************************************** C66xx_0: GEL Output: BUSY => LSU6 is ##AVAILABLE## C66xx_0: GEL Output: FULL => LSU6 shadow registers are ##AVAILABLE## C66xx_0: GEL Output: CURRENT_LTID => Current shadow register in use: 0 C66xx_0: GEL Output: CURRENT_LCB => This transaction is the current one having LTID: 0 C66xx_0: GEL Output: *********** LSU6 SHADOW REGISTERS STATUS: *********** C66xx_0: GEL Output: LCB => This transaction is the previous/next one having LTID: 0 C66xx_0: GEL Output: CC => Transaction complete, No Errors (Posted/Non-posted) C66xx_0: GEL Output: LCB => This transaction is the previous/next one having LTID: 0 C66xx_0: GEL Output: CC => Transaction complete, No Errors (Posted/Non-posted) C66xx_0: GEL Output: LCB => This transaction is the previous/next one having LTID: 1 C66xx_0: GEL Output: CC => Transaction complete, No Errors (Posted/Non-posted) C66xx_0: GEL Output: LCB => This transaction is the previous/next one having LTID: 2 C66xx_0: GEL Output: CC => Transaction complete, No Errors (Posted/Non-posted) C66xx_0: GEL Output: ********************************** SRIO LSU7 STATUS ****************************************************** C66xx_0: GEL Output: BUSY => LSU7 is ##AVAILABLE## C66xx_0: GEL Output: FULL => LSU7 shadow registers are ##AVAILABLE## C66xx_0: GEL Output: CURRENT_LTID => Current shadow register in use: 0 C66xx_0: GEL Output: CURRENT_LCB => This transaction is the current one having LTID: 0 C66xx_0: GEL Output: *********** LSU7 SHADOW REGISTERS STATUS: *********** C66xx_0: GEL Output: LCB => This transaction is the previous/next one having LTID: 0 C66xx_0: GEL Output: CC => Transaction complete, No Errors (Posted/Non-posted) C66xx_0: GEL Output: LCB => This transaction is the previous/next one having LTID: 1 C66xx_0: GEL Output: CC => Transaction complete, No Errors (Posted/Non-posted) C66xx_0: GEL Output: LCB => This transaction is the previous/next one having LTID: 2 C66xx_0: GEL Output: CC => Transaction complete, No Errors (Posted/Non-posted) C66xx_0: GEL Output: LCB => This transaction is the previous/next one having LTID: 3 C66xx_0: GEL Output: CC => Transaction complete, No Errors (Posted/Non-posted) C66xx_0: GEL Output: ******************************************************************************************************* C66xx_0: GEL Output: ********************************** SRIO TX CPPI CONFIGURATION ****************************************************** C66xx_0: GEL Output: ******************************************************************************************************* C66xx_0: GEL Output: ********************************** Transmit CPPI Supported Flow Mask Registers (TX_CPPI_FLOW_MASKS[0-7]) ****************************************************** C66xx_0: GEL Output: TX_CPPI_FLOW_MASKS0.QUEUE0_FLOW_MASK ---> 0xFFFF C66xx_0: GEL Output: TX_CPPI_FLOW_MASKS0.QUEUE1_FLOW_MASK ---> 0xFFFF C66xx_0: GEL Output: TX_CPPI_FLOW_MASKS1.QUEUE2_FLOW_MASK ---> 0xFFFF C66xx_0: GEL Output: TX_CPPI_FLOW_MASKS1.QUEUE3_FLOW_MASK ---> 0xFFFF C66xx_0: GEL Output: TX_CPPI_FLOW_MASKS2.QUEUE4_FLOW_MASK ---> 0xFFFF C66xx_0: GEL Output: TX_CPPI_FLOW_MASKS2.QUEUE5_FLOW_MASK ---> 0xFFFF C66xx_0: GEL Output: TX_CPPI_FLOW_MASKS3.QUEUE6_FLOW_MASK ---> 0xFFFF C66xx_0: GEL Output: TX_CPPI_FLOW_MASKS3.QUEUE7_FLOW_MASK ---> 0xFFFF C66xx_0: GEL Output: TX_CPPI_FLOW_MASKS4.QUEUE8_FLOW_MASK ---> 0xFFFF C66xx_0: GEL Output: TX_CPPI_FLOW_MASKS4.QUEUE9_FLOW_MASK ---> 0xFFFF C66xx_0: GEL Output: TX_CPPI_FLOW_MASKS5.QUEUE10_FLOW_MASK ---> 0xFFFF C66xx_0: GEL Output: TX_CPPI_FLOW_MASKS5.QUEUE11_FLOW_MASK ---> 0xFFFF C66xx_0: GEL Output: TX_CPPI_FLOW_MASKS6.QUEUE12_FLOW_MASK ---> 0xFFFF C66xx_0: GEL Output: TX_CPPI_FLOW_MASKS6.QUEUE13_FLOW_MASK ---> 0xFFFF C66xx_0: GEL Output: TX_CPPI_FLOW_MASKS7.QUEUE14_FLOW_MASK ---> 0x0606 C66xx_0: GEL Output: TX_CPPI_FLOW_MASKS7.QUEUE15_FLOW_MASK ---> 0x0606 C66xx_0: GEL Output: ********************************** Transmit QUEUE Scheduling Info (TX_QUEUE_SCH_INFO[1-4]) ****************************************************** C66xx_0: GEL Output: Q0_SCH_INFO : PRIORITY:- CRF:0 PRIO:3 VC:0 PORT_OUT:Port0 C66xx_0: GEL Output: Q1_SCH_INFO : PRIORITY:- CRF:0 PRIO:3 VC:0 PORT_OUT:Port0 C66xx_0: GEL Output: Q2_SCH_INFO : PRIORITY:- CRF:0 PRIO:3 VC:0 PORT_OUT:Port0 C66xx_0: GEL Output: Q3_SCH_INFO : PRIORITY:- CRF:0 PRIO:3 VC:0 PORT_OUT:Port0 C66xx_0: GEL Output: Q4_SCH_INFO : PRIORITY:- CRF:0 PRIO:3 VC:0 PORT_OUT:Port0 C66xx_0: GEL Output: Q5_SCH_INFO : PRIORITY:- CRF:0 PRIO:3 VC:0 PORT_OUT:Port0 C66xx_0: GEL Output: Q6_SCH_INFO : PRIORITY:- CRF:0 PRIO:3 VC:0 PORT_OUT:Port0 C66xx_0: GEL Output: Q7_SCH_INFO : PRIORITY:- CRF:0 PRIO:3 VC:0 PORT_OUT:Port0 C66xx_0: GEL Output: Q8_SCH_INFO : PRIORITY:- CRF:0 PRIO:3 VC:0 PORT_OUT:Port0 C66xx_0: GEL Output: Q9_SCH_INFO : PRIORITY:- CRF:0 PRIO:3 VC:0 PORT_OUT:Port0 C66xx_0: GEL Output: Q10_SCH_INFO : PRIORITY:- CRF:0 PRIO:3 VC:0 PORT_OUT:Port0 C66xx_0: GEL Output: Q11_SCH_INFO : PRIORITY:- CRF:0 PRIO:3 VC:0 PORT_OUT:Port0 C66xx_0: GEL Output: Q12_SCH_INFO : PRIORITY:- CRF:0 PRIO:3 VC:0 PORT_OUT:Port0 C66xx_0: GEL Output: Q13_SCH_INFO : PRIORITY:- CRF:0 PRIO:3 VC:0 PORT_OUT:Port0 C66xx_0: GEL Output: Q14_SCH_INFO : PRIORITY:- CRF:0 PRIO:3 VC:0 PORT_OUT:Port0 C66xx_0: GEL Output: Q15_SCH_INFO : PRIORITY:- CRF:0 PRIO:3 VC:0 PORT_OUT:Port0 C66xx_0: GEL Output: ******************************************************************************************************* C66xx_0: GEL Output: ********************************** SRIO RX CPPI CONFIGURATION ****************************************************** C66xx_0: GEL Output: ******************************************************************************************************* C66xx_0: GEL Output: ********************************** Mailbox to Queue Mapping Registers (RXU_MAPn_L, RXU_MAPn_H and RXU_MAPn_QID) ****************************************************** C66xx_0: GEL Output: MapReg0 :SrcId:0x0000 DestId:0x0000 Mbox:0 Letter:0 MBox_Mask:0x3F Letter_Mask:0x03 QId:0 FlowId:0 Single-segment msg*check sourceID*check destID C66xx_0: GEL Output: MapReg1 :SrcId:0x0000 DestId:0x0000 Mbox:0 Letter:0 MBox_Mask:0x3F Letter_Mask:0x03 QId:0 FlowId:0 Single-segment msg*check sourceID*check destID C66xx_0: GEL Output: MapReg2 :SrcId:0x0000 DestId:0x0000 Mbox:0 Letter:0 MBox_Mask:0x3F Letter_Mask:0x03 QId:0 FlowId:0 Single-segment msg*check sourceID*check destID C66xx_0: GEL Output: MapReg3 :SrcId:0x0000 DestId:0x0000 Mbox:0 Letter:0 MBox_Mask:0x3F Letter_Mask:0x03 QId:0 FlowId:0 Single-segment msg*check sourceID*check destID C66xx_0: GEL Output: MapReg4 :SrcId:0x0000 DestId:0x0000 Mbox:0 Letter:0 MBox_Mask:0x3F Letter_Mask:0x03 QId:0 FlowId:0 Single-segment msg*check sourceID*check destID C66xx_0: GEL Output: MapReg5 :SrcId:0x0000 DestId:0x0000 Mbox:0 Letter:0 MBox_Mask:0x3F Letter_Mask:0x03 QId:0 FlowId:0 Single-segment msg*check sourceID*check destID C66xx_0: GEL Output: MapReg6 :SrcId:0x0000 DestId:0x0000 Mbox:0 Letter:0 MBox_Mask:0x3F Letter_Mask:0x03 QId:0 FlowId:0 Single-segment msg*check sourceID*check destID C66xx_0: GEL Output: MapReg7 :SrcId:0x0000 DestId:0x0000 Mbox:0 Letter:0 MBox_Mask:0x3F Letter_Mask:0x03 QId:0 FlowId:0 Single-segment msg*check sourceID*check destID C66xx_0: GEL Output: MapReg8 :SrcId:0x0000 DestId:0x0000 Mbox:0 Letter:0 MBox_Mask:0x3F Letter_Mask:0x03 QId:0 FlowId:0 Single-segment msg*check sourceID*check destID C66xx_0: GEL Output: MapReg9 :SrcId:0x0000 DestId:0x0000 Mbox:0 Letter:0 MBox_Mask:0x3F Letter_Mask:0x03 QId:0 FlowId:0 Single-segment msg*check sourceID*check destID C66xx_0: GEL Output: MapReg10:SrcId:0x0000 DestId:0x0000 Mbox:0 Letter:0 MBox_Mask:0x3F Letter_Mask:0x03 QId:0 FlowId:0 Single-segment msg*check sourceID*check destID C66xx_0: GEL Output: MapReg11:SrcId:0x0000 DestId:0x0000 Mbox:0 Letter:0 MBox_Mask:0x3F Letter_Mask:0x03 QId:0 FlowId:0 Single-segment msg*check sourceID*check destID C66xx_0: GEL Output: MapReg12:SrcId:0x0000 DestId:0x0000 Mbox:0 Letter:0 MBox_Mask:0x3F Letter_Mask:0x03 QId:0 FlowId:0 Single-segment msg*check sourceID*check destID C66xx_0: GEL Output: MapReg13:SrcId:0x0000 DestId:0x0000 Mbox:0 Letter:0 MBox_Mask:0x3F Letter_Mask:0x03 QId:0 FlowId:0 Single-segment msg*check sourceID*check destID C66xx_0: GEL Output: MapReg14:SrcId:0x0000 DestId:0x0000 Mbox:0 Letter:0 MBox_Mask:0x3F Letter_Mask:0x03 QId:0 FlowId:0 Single-segment msg*check sourceID*check destID C66xx_0: GEL Output: MapReg15:SrcId:0x0000 DestId:0x0000 Mbox:0 Letter:0 MBox_Mask:0x3F Letter_Mask:0x03 QId:0 FlowId:0 Single-segment msg*check sourceID*check destID C66xx_0: GEL Output: MapReg16:SrcId:0x0000 DestId:0x0000 Mbox:0 Letter:0 MBox_Mask:0x3F Letter_Mask:0x03 QId:0 FlowId:0 Single-segment msg*check sourceID*check destID C66xx_0: GEL Output: MapReg17:SrcId:0x0000 DestId:0x0000 Mbox:0 Letter:0 MBox_Mask:0x3F Letter_Mask:0x03 QId:0 FlowId:0 Single-segment msg*check sourceID*check destID C66xx_0: GEL Output: MapReg18:SrcId:0x0000 DestId:0x0000 Mbox:0 Letter:0 MBox_Mask:0x3F Letter_Mask:0x03 QId:0 FlowId:0 Single-segment msg*check sourceID*check destID C66xx_0: GEL Output: MapReg19:SrcId:0x0000 DestId:0x0000 Mbox:0 Letter:0 MBox_Mask:0x3F Letter_Mask:0x03 QId:0 FlowId:0 Single-segment msg*check sourceID*check destID C66xx_0: GEL Output: MapReg20:SrcId:0x0000 DestId:0x0000 Mbox:0 Letter:0 MBox_Mask:0x3F Letter_Mask:0x03 QId:0 FlowId:0 Single-segment msg*check sourceID*check destID C66xx_0: GEL Output: MapReg21:SrcId:0x0000 DestId:0x0000 Mbox:0 Letter:0 MBox_Mask:0x3F Letter_Mask:0x03 QId:0 FlowId:0 Single-segment msg*check sourceID*check destID C66xx_0: GEL Output: MapReg22:SrcId:0x0000 DestId:0x0000 Mbox:0 Letter:0 MBox_Mask:0x3F Letter_Mask:0x03 QId:0 FlowId:0 Single-segment msg*check sourceID*check destID C66xx_0: GEL Output: MapReg23:SrcId:0x0000 DestId:0x0000 Mbox:0 Letter:0 MBox_Mask:0x3F Letter_Mask:0x03 QId:0 FlowId:0 Single-segment msg*check sourceID*check destID C66xx_0: GEL Output: MapReg24:SrcId:0x0000 DestId:0x0000 Mbox:0 Letter:0 MBox_Mask:0x3F Letter_Mask:0x03 QId:0 FlowId:0 Single-segment msg*check sourceID*check destID C66xx_0: GEL Output: MapReg25:SrcId:0x0000 DestId:0x0000 Mbox:0 Letter:0 MBox_Mask:0x3F Letter_Mask:0x03 QId:0 FlowId:0 Single-segment msg*check sourceID*check destID C66xx_0: GEL Output: MapReg26:SrcId:0x0000 DestId:0x0000 Mbox:0 Letter:0 MBox_Mask:0x3F Letter_Mask:0x03 QId:0 FlowId:0 Single-segment msg*check sourceID*check destID C66xx_0: GEL Output: MapReg27:SrcId:0x0000 DestId:0x0000 Mbox:0 Letter:0 MBox_Mask:0x3F Letter_Mask:0x03 QId:0 FlowId:0 Single-segment msg*check sourceID*check destID C66xx_0: GEL Output: MapReg28:SrcId:0x0000 DestId:0x0000 Mbox:0 Letter:0 MBox_Mask:0x3F Letter_Mask:0x03 QId:0 FlowId:0 Single-segment msg*check sourceID*check destID C66xx_0: GEL Output: MapReg29:SrcId:0x0000 DestId:0x0000 Mbox:0 Letter:0 MBox_Mask:0x3F Letter_Mask:0x03 QId:0 FlowId:0 Single-segment msg*check sourceID*check destID C66xx_0: GEL Output: MapReg30:SrcId:0x0000 DestId:0x0000 Mbox:0 Letter:0 MBox_Mask:0x3F Letter_Mask:0x03 QId:0 FlowId:0 Single-segment msg*check sourceID*check destID C66xx_0: GEL Output: MapReg31:SrcId:0x0000 DestId:0x0000 Mbox:0 Letter:0 MBox_Mask:0x3F Letter_Mask:0x03 QId:0 FlowId:0 Single-segment msg*check sourceID*check destID C66xx_0: GEL Output: MapReg32:SrcId:0x0000 DestId:0x0000 Mbox:0 Letter:0 MBox_Mask:0x3F Letter_Mask:0x03 QId:0 FlowId:0 Single-segment msg*check sourceID*check destID C66xx_0: GEL Output: MapReg33:SrcId:0x0000 DestId:0x0000 Mbox:0 Letter:0 MBox_Mask:0x3F Letter_Mask:0x03 QId:0 FlowId:0 Single-segment msg*check sourceID*check destID C66xx_0: GEL Output: MapReg34:SrcId:0x0000 DestId:0x0000 Mbox:0 Letter:0 MBox_Mask:0x3F Letter_Mask:0x03 QId:0 FlowId:0 Single-segment msg*check sourceID*check destID C66xx_0: GEL Output: MapReg35:SrcId:0x0000 DestId:0x0000 Mbox:0 Letter:0 MBox_Mask:0x3F Letter_Mask:0x03 QId:0 FlowId:0 Single-segment msg*check sourceID*check destID C66xx_0: GEL Output: MapReg36:SrcId:0x0000 DestId:0x0000 Mbox:0 Letter:0 MBox_Mask:0x3F Letter_Mask:0x03 QId:0 FlowId:0 Single-segment msg*check sourceID*check destID C66xx_0: GEL Output: MapReg37:SrcId:0x0000 DestId:0x0000 Mbox:0 Letter:0 MBox_Mask:0x3F Letter_Mask:0x03 QId:0 FlowId:0 Single-segment msg*check sourceID*check destID C66xx_0: GEL Output: MapReg38:SrcId:0x0000 DestId:0x0000 Mbox:0 Letter:0 MBox_Mask:0x3F Letter_Mask:0x03 QId:0 FlowId:0 Single-segment msg*check sourceID*check destID C66xx_0: GEL Output: MapReg39:SrcId:0x0000 DestId:0x0000 Mbox:0 Letter:0 MBox_Mask:0x3F Letter_Mask:0x03 QId:0 FlowId:0 Single-segment msg*check sourceID*check destID C66xx_0: GEL Output: MapReg40:SrcId:0x0000 DestId:0x0000 Mbox:0 Letter:0 MBox_Mask:0x3F Letter_Mask:0x03 QId:0 FlowId:0 Single-segment msg*check sourceID*check destID C66xx_0: GEL Output: MapReg41:SrcId:0x0000 DestId:0x0000 Mbox:0 Letter:0 MBox_Mask:0x3F Letter_Mask:0x03 QId:0 FlowId:0 Single-segment msg*check sourceID*check destID C66xx_0: GEL Output: MapReg42:SrcId:0x0000 DestId:0x0000 Mbox:0 Letter:0 MBox_Mask:0x3F Letter_Mask:0x03 QId:0 FlowId:0 Single-segment msg*check sourceID*check destID C66xx_0: GEL Output: MapReg43:SrcId:0x0000 DestId:0x0000 Mbox:0 Letter:0 MBox_Mask:0x3F Letter_Mask:0x03 QId:0 FlowId:0 Single-segment msg*check sourceID*check destID C66xx_0: GEL Output: MapReg44:SrcId:0x0000 DestId:0x0000 Mbox:0 Letter:0 MBox_Mask:0x3F Letter_Mask:0x03 QId:0 FlowId:0 Single-segment msg*check sourceID*check destID C66xx_0: GEL Output: MapReg45:SrcId:0x0000 DestId:0x0000 Mbox:0 Letter:0 MBox_Mask:0x3F Letter_Mask:0x03 QId:0 FlowId:0 Single-segment msg*check sourceID*check destID C66xx_0: GEL Output: MapReg46:SrcId:0x0000 DestId:0x0000 Mbox:0 Letter:0 MBox_Mask:0x3F Letter_Mask:0x03 QId:0 FlowId:0 Single-segment msg*check sourceID*check destID C66xx_0: GEL Output: MapReg47:SrcId:0x0000 DestId:0x0000 Mbox:0 Letter:0 MBox_Mask:0x3F Letter_Mask:0x03 QId:0 FlowId:0 Single-segment msg*check sourceID*check destID C66xx_0: GEL Output: MapReg48:SrcId:0x0000 DestId:0x0000 Mbox:0 Letter:0 MBox_Mask:0x3F Letter_Mask:0x03 QId:0 FlowId:0 Single-segment msg*check sourceID*check destID C66xx_0: GEL Output: MapReg49:SrcId:0x0000 DestId:0x0000 Mbox:0 Letter:0 MBox_Mask:0x3F Letter_Mask:0x03 QId:0 FlowId:0 Single-segment msg*check sourceID*check destID C66xx_0: GEL Output: MapReg50:SrcId:0x0000 DestId:0x0000 Mbox:0 Letter:0 MBox_Mask:0x3F Letter_Mask:0x03 QId:0 FlowId:0 Single-segment msg*check sourceID*check destID C66xx_0: GEL Output: MapReg51:SrcId:0x0000 DestId:0x0000 Mbox:0 Letter:0 MBox_Mask:0x3F Letter_Mask:0x03 QId:0 FlowId:0 Single-segment msg*check sourceID*check destID C66xx_0: GEL Output: MapReg52:SrcId:0x0000 DestId:0x0000 Mbox:0 Letter:0 MBox_Mask:0x3F Letter_Mask:0x03 QId:0 FlowId:0 Single-segment msg*check sourceID*check destID C66xx_0: GEL Output: MapReg53:SrcId:0x0000 DestId:0x0000 Mbox:0 Letter:0 MBox_Mask:0x3F Letter_Mask:0x03 QId:0 FlowId:0 Single-segment msg*check sourceID*check destID C66xx_0: GEL Output: MapReg54:SrcId:0x0000 DestId:0x0000 Mbox:0 Letter:0 MBox_Mask:0x3F Letter_Mask:0x03 QId:0 FlowId:0 Single-segment msg*check sourceID*check destID C66xx_0: GEL Output: MapReg55:SrcId:0x0000 DestId:0x0000 Mbox:0 Letter:0 MBox_Mask:0x3F Letter_Mask:0x03 QId:0 FlowId:0 Single-segment msg*check sourceID*check destID C66xx_0: GEL Output: MapReg56:SrcId:0x0000 DestId:0x0000 Mbox:0 Letter:0 MBox_Mask:0x3F Letter_Mask:0x03 QId:0 FlowId:0 Single-segment msg*check sourceID*check destID C66xx_0: GEL Output: MapReg57:SrcId:0x0000 DestId:0x0000 Mbox:0 Letter:0 MBox_Mask:0x3F Letter_Mask:0x03 QId:0 FlowId:0 Single-segment msg*check sourceID*check destID C66xx_0: GEL Output: MapReg58:SrcId:0x0000 DestId:0x0000 Mbox:0 Letter:0 MBox_Mask:0x3F Letter_Mask:0x03 QId:0 FlowId:0 Single-segment msg*check sourceID*check destID C66xx_0: GEL Output: MapReg59:SrcId:0x0000 DestId:0x0000 Mbox:0 Letter:0 MBox_Mask:0x3F Letter_Mask:0x03 QId:0 FlowId:0 Single-segment msg*check sourceID*check destID C66xx_0: GEL Output: MapReg60:SrcId:0x0000 DestId:0x0000 Mbox:0 Letter:0 MBox_Mask:0x3F Letter_Mask:0x03 QId:0 FlowId:0 Single-segment msg*check sourceID*check destID C66xx_0: GEL Output: MapReg61:SrcId:0x0000 DestId:0x0000 Mbox:0 Letter:0 MBox_Mask:0x3F Letter_Mask:0x03 QId:0 FlowId:0 Single-segment msg*check sourceID*check destID C66xx_0: GEL Output: MapReg62:SrcId:0x0000 DestId:0x0000 Mbox:0 Letter:0 MBox_Mask:0x3F Letter_Mask:0x03 QId:0 FlowId:0 Single-segment msg*check sourceID*check destID C66xx_0: GEL Output: MapReg63:SrcId:0x0000 DestId:0x0000 Mbox:0 Letter:0 MBox_Mask:0x3F Letter_Mask:0x03 QId:0 FlowId:0 Single-segment msg*check sourceID*check destID C66xx_0: GEL Output: ********************************** RXU Type 9 Mapping Registers (RXU_TYPE9_MAPn_0, RXU_TYPE9_MAPn_1, RXU_TYPE9_MAPn_2 and RXU_MAP_QID) ****************************************************** C66xx_0: GEL Output: RXU_T9Map0 :SrcId:0x0000 DestId:0x0000 COS:0x00 COS_mask:0x00 STRM_id:0x0000 STRM__Mask:0xFFFF QId:0 FlowId:0 check sourceID*check destID C66xx_0: GEL Output: RXU_T9Map1 :SrcId:0x0000 DestId:0x0000 COS:0x00 COS_mask:0x00 STRM_id:0x0000 STRM__Mask:0xFFFF QId:0 FlowId:0 check sourceID*check destID C66xx_0: GEL Output: RXU_T9Map2 :SrcId:0x0000 DestId:0x0000 COS:0x00 COS_mask:0x00 STRM_id:0x0000 STRM__Mask:0xFFFF QId:0 FlowId:0 check sourceID*check destID C66xx_0: GEL Output: RXU_T9Map3 :SrcId:0x0000 DestId:0x0000 COS:0x00 COS_mask:0x00 STRM_id:0x0000 STRM__Mask:0xFFFF QId:0 FlowId:0 check sourceID*check destID C66xx_0: GEL Output: RXU_T9Map4 :SrcId:0x0000 DestId:0x0000 COS:0x00 COS_mask:0x00 STRM_id:0x0000 STRM__Mask:0xFFFF QId:0 FlowId:0 check sourceID*check destID C66xx_0: GEL Output: RXU_T9Map5 :SrcId:0x0000 DestId:0x0000 COS:0x00 COS_mask:0x00 STRM_id:0x0000 STRM__Mask:0xFFFF QId:0 FlowId:0 check sourceID*check destID C66xx_0: GEL Output: RXU_T9Map6 :SrcId:0x0000 DestId:0x0000 COS:0x00 COS_mask:0x00 STRM_id:0x0000 STRM__Mask:0xFFFF QId:0 FlowId:0 check sourceID*check destID C66xx_0: GEL Output: RXU_T9Map7 :SrcId:0x0000 DestId:0x0000 COS:0x00 COS_mask:0x00 STRM_id:0x0000 STRM__Mask:0xFFFF QId:0 FlowId:0 check sourceID*check destID C66xx_0: GEL Output: RXU_T9Map8 :SrcId:0x0000 DestId:0x0000 COS:0x00 COS_mask:0x00 STRM_id:0x0000 STRM__Mask:0xFFFF QId:0 FlowId:0 check sourceID*check destID C66xx_0: GEL Output: RXU_T9Map9 :SrcId:0x0000 DestId:0x0000 COS:0x00 COS_mask:0x00 STRM_id:0x0000 STRM__Mask:0xFFFF QId:0 FlowId:0 check sourceID*check destID C66xx_0: GEL Output: RXU_T9Map10:SrcId:0x0000 DestId:0x0000 COS:0x00 COS_mask:0x00 STRM_id:0x0000 STRM__Mask:0xFFFF QId:0 FlowId:0 check sourceID*check destID C66xx_0: GEL Output: RXU_T9Map11:SrcId:0x0000 DestId:0x0000 COS:0x00 COS_mask:0x00 STRM_id:0x0000 STRM__Mask:0xFFFF QId:0 FlowId:0 check sourceID*check destID C66xx_0: GEL Output: RXU_T9Map12:SrcId:0x0000 DestId:0x0000 COS:0x00 COS_mask:0x00 STRM_id:0x0000 STRM__Mask:0xFFFF QId:0 FlowId:0 check sourceID*check destID C66xx_0: GEL Output: RXU_T9Map13:SrcId:0x0000 DestId:0x0000 COS:0x00 COS_mask:0x00 STRM_id:0x0000 STRM__Mask:0xFFFF QId:0 FlowId:0 check sourceID*check destID C66xx_0: GEL Output: RXU_T9Map14:SrcId:0x0000 DestId:0x0000 COS:0x00 COS_mask:0x00 STRM_id:0x0000 STRM__Mask:0xFFFF QId:0 FlowId:0 check sourceID*check destID C66xx_0: GEL Output: RXU_T9Map15:SrcId:0x0000 DestId:0x0000 COS:0x00 COS_mask:0x00 STRM_id:0x0000 STRM__Mask:0xFFFF QId:0 FlowId:0 check sourceID*check destID C66xx_0: GEL Output: RXU_T9Map16:SrcId:0x0000 DestId:0x0000 COS:0x00 COS_mask:0x00 STRM_id:0x0000 STRM__Mask:0xFFFF QId:0 FlowId:0 check sourceID*check destID C66xx_0: GEL Output: RXU_T9Map17:SrcId:0x0000 DestId:0x0000 COS:0x00 COS_mask:0x00 STRM_id:0x0000 STRM__Mask:0xFFFF QId:0 FlowId:0 check sourceID*check destID C66xx_0: GEL Output: RXU_T9Map18:SrcId:0x0000 DestId:0x0000 COS:0x00 COS_mask:0x00 STRM_id:0x0000 STRM__Mask:0xFFFF QId:0 FlowId:0 check sourceID*check destID C66xx_0: GEL Output: RXU_T9Map19:SrcId:0x0000 DestId:0x0000 COS:0x00 COS_mask:0x00 STRM_id:0x0000 STRM__Mask:0xFFFF QId:0 FlowId:0 check sourceID*check destID C66xx_0: GEL Output: RXU_T9Map20:SrcId:0x0000 DestId:0x0000 COS:0x00 COS_mask:0x00 STRM_id:0x0000 STRM__Mask:0xFFFF QId:0 FlowId:0 check sourceID*check destID C66xx_0: GEL Output: RXU_T9Map21:SrcId:0x0000 DestId:0x0000 COS:0x00 COS_mask:0x00 STRM_id:0x0000 STRM__Mask:0xFFFF QId:0 FlowId:0 check sourceID*check destID C66xx_0: GEL Output: RXU_T9Map22:SrcId:0x0000 DestId:0x0000 COS:0x00 COS_mask:0x00 STRM_id:0x0000 STRM__Mask:0xFFFF QId:0 FlowId:0 check sourceID*check destID C66xx_0: GEL Output: RXU_T9Map23:SrcId:0x0000 DestId:0x0000 COS:0x00 COS_mask:0x00 STRM_id:0x0000 STRM__Mask:0xFFFF QId:0 FlowId:0 check sourceID*check destID C66xx_0: GEL Output: RXU_T9Map24:SrcId:0x0000 DestId:0x0000 COS:0x00 COS_mask:0x00 STRM_id:0x0000 STRM__Mask:0xFFFF QId:0 FlowId:0 check sourceID*check destID C66xx_0: GEL Output: RXU_T9Map25:SrcId:0x0000 DestId:0x0000 COS:0x00 COS_mask:0x00 STRM_id:0x0000 STRM__Mask:0xFFFF QId:0 FlowId:0 check sourceID*check destID C66xx_0: GEL Output: RXU_T9Map26:SrcId:0x0000 DestId:0x0000 COS:0x00 COS_mask:0x00 STRM_id:0x0000 STRM__Mask:0xFFFF QId:0 FlowId:0 check sourceID*check destID C66xx_0: GEL Output: RXU_T9Map27:SrcId:0x0000 DestId:0x0000 COS:0x00 COS_mask:0x00 STRM_id:0x0000 STRM__Mask:0xFFFF QId:0 FlowId:0 check sourceID*check destID C66xx_0: GEL Output: RXU_T9Map28:SrcId:0x0000 DestId:0x0000 COS:0x00 COS_mask:0x00 STRM_id:0x0000 STRM__Mask:0xFFFF QId:0 FlowId:0 check sourceID*check destID C66xx_0: GEL Output: RXU_T9Map29:SrcId:0x0000 DestId:0x0000 COS:0x00 COS_mask:0x00 STRM_id:0x0000 STRM__Mask:0xFFFF QId:0 FlowId:0 check sourceID*check destID C66xx_0: GEL Output: RXU_T9Map30:SrcId:0x0000 DestId:0x0000 COS:0x00 COS_mask:0x00 STRM_id:0x0000 STRM__Mask:0xFFFF QId:0 FlowId:0 check sourceID*check destID C66xx_0: GEL Output: RXU_T9Map31:SrcId:0x0000 DestId:0x0000 COS:0x00 COS_mask:0x00 STRM_id:0x0000 STRM__Mask:0xFFFF QId:0 FlowId:0 check sourceID*check destID C66xx_0: GEL Output: RXU_T9Map32:SrcId:0x0000 DestId:0x0000 COS:0x00 COS_mask:0x00 STRM_id:0x0000 STRM__Mask:0xFFFF QId:0 FlowId:0 check sourceID*check destID C66xx_0: GEL Output: RXU_T9Map33:SrcId:0x0000 DestId:0x0000 COS:0x00 COS_mask:0x00 STRM_id:0x0000 STRM__Mask:0xFFFF QId:0 FlowId:0 check sourceID*check destID C66xx_0: GEL Output: RXU_T9Map34:SrcId:0x0000 DestId:0x0000 COS:0x00 COS_mask:0x00 STRM_id:0x0000 STRM__Mask:0xFFFF QId:0 FlowId:0 check sourceID*check destID C66xx_0: GEL Output: RXU_T9Map35:SrcId:0x0000 DestId:0x0000 COS:0x00 COS_mask:0x00 STRM_id:0x0000 STRM__Mask:0xFFFF QId:0 FlowId:0 check sourceID*check destID C66xx_0: GEL Output: RXU_T9Map36:SrcId:0x0000 DestId:0x0000 COS:0x00 COS_mask:0x00 STRM_id:0x0000 STRM__Mask:0xFFFF QId:0 FlowId:0 check sourceID*check destID C66xx_0: GEL Output: RXU_T9Map37:SrcId:0x0000 DestId:0x0000 COS:0x00 COS_mask:0x00 STRM_id:0x0000 STRM__Mask:0xFFFF QId:0 FlowId:0 check sourceID*check destID C66xx_0: GEL Output: RXU_T9Map38:SrcId:0x0000 DestId:0x0000 COS:0x00 COS_mask:0x00 STRM_id:0x0000 STRM__Mask:0xFFFF QId:0 FlowId:0 check sourceID*check destID C66xx_0: GEL Output: RXU_T9Map39:SrcId:0x0000 DestId:0x0000 COS:0x00 COS_mask:0x00 STRM_id:0x0000 STRM__Mask:0xFFFF QId:0 FlowId:0 check sourceID*check destID C66xx_0: GEL Output: RXU_T9Map40:SrcId:0x0000 DestId:0x0000 COS:0x00 COS_mask:0x00 STRM_id:0x0000 STRM__Mask:0xFFFF QId:0 FlowId:0 check sourceID*check destID C66xx_0: GEL Output: RXU_T9Map41:SrcId:0x0000 DestId:0x0000 COS:0x00 COS_mask:0x00 STRM_id:0x0000 STRM__Mask:0xFFFF QId:0 FlowId:0 check sourceID*check destID C66xx_0: GEL Output: RXU_T9Map42:SrcId:0x0000 DestId:0x0000 COS:0x00 COS_mask:0x00 STRM_id:0x0000 STRM__Mask:0xFFFF QId:0 FlowId:0 check sourceID*check destID C66xx_0: GEL Output: RXU_T9Map43:SrcId:0x0000 DestId:0x0000 COS:0x00 COS_mask:0x00 STRM_id:0x0000 STRM__Mask:0xFFFF QId:0 FlowId:0 check sourceID*check destID C66xx_0: GEL Output: RXU_T9Map44:SrcId:0x0000 DestId:0x0000 COS:0x00 COS_mask:0x00 STRM_id:0x0000 STRM__Mask:0xFFFF QId:0 FlowId:0 check sourceID*check destID C66xx_0: GEL Output: RXU_T9Map45:SrcId:0x0000 DestId:0x0000 COS:0x00 COS_mask:0x00 STRM_id:0x0000 STRM__Mask:0xFFFF QId:0 FlowId:0 check sourceID*check destID C66xx_0: GEL Output: RXU_T9Map46:SrcId:0x0000 DestId:0x0000 COS:0x00 COS_mask:0x00 STRM_id:0x0000 STRM__Mask:0xFFFF QId:0 FlowId:0 check sourceID*check destID C66xx_0: GEL Output: RXU_T9Map47:SrcId:0x0000 DestId:0x0000 COS:0x00 COS_mask:0x00 STRM_id:0x0000 STRM__Mask:0xFFFF QId:0 FlowId:0 check sourceID*check destID C66xx_0: GEL Output: RXU_T9Map48:SrcId:0x0000 DestId:0x0000 COS:0x00 COS_mask:0x00 STRM_id:0x0000 STRM__Mask:0xFFFF QId:0 FlowId:0 check sourceID*check destID C66xx_0: GEL Output: RXU_T9Map49:SrcId:0x0000 DestId:0x0000 COS:0x00 COS_mask:0x00 STRM_id:0x0000 STRM__Mask:0xFFFF QId:0 FlowId:0 check sourceID*check destID C66xx_0: GEL Output: RXU_T9Map50:SrcId:0x0000 DestId:0x0000 COS:0x00 COS_mask:0x00 STRM_id:0x0000 STRM__Mask:0xFFFF QId:0 FlowId:0 check sourceID*check destID C66xx_0: GEL Output: RXU_T9Map51:SrcId:0x0000 DestId:0x0000 COS:0x00 COS_mask:0x00 STRM_id:0x0000 STRM__Mask:0xFFFF QId:0 FlowId:0 check sourceID*check destID C66xx_0: GEL Output: RXU_T9Map52:SrcId:0x0000 DestId:0x0000 COS:0x00 COS_mask:0x00 STRM_id:0x0000 STRM__Mask:0xFFFF QId:0 FlowId:0 check sourceID*check destID C66xx_0: GEL Output: RXU_T9Map53:SrcId:0x0000 DestId:0x0000 COS:0x00 COS_mask:0x00 STRM_id:0x0000 STRM__Mask:0xFFFF QId:0 FlowId:0 check sourceID*check destID C66xx_0: GEL Output: RXU_T9Map54:SrcId:0x0000 DestId:0x0000 COS:0x00 COS_mask:0x00 STRM_id:0x0000 STRM__Mask:0xFFFF QId:0 FlowId:0 check sourceID*check destID C66xx_0: GEL Output: RXU_T9Map55:SrcId:0x0000 DestId:0x0000 COS:0x00 COS_mask:0x00 STRM_id:0x0000 STRM__Mask:0xFFFF QId:0 FlowId:0 check sourceID*check destID C66xx_0: GEL Output: RXU_T9Map56:SrcId:0x0000 DestId:0x0000 COS:0x00 COS_mask:0x00 STRM_id:0x0000 STRM__Mask:0xFFFF QId:0 FlowId:0 check sourceID*check destID C66xx_0: GEL Output: RXU_T9Map57:SrcId:0x0000 DestId:0x0000 COS:0x00 COS_mask:0x00 STRM_id:0x0000 STRM__Mask:0xFFFF QId:0 FlowId:0 check sourceID*check destID C66xx_0: GEL Output: RXU_T9Map58:SrcId:0x0000 DestId:0x0000 COS:0x00 COS_mask:0x00 STRM_id:0x0000 STRM__Mask:0xFFFF QId:0 FlowId:0 check sourceID*check destID C66xx_0: GEL Output: RXU_T9Map59:SrcId:0x0000 DestId:0x0000 COS:0x00 COS_mask:0x00 STRM_id:0x0000 STRM__Mask:0xFFFF QId:0 FlowId:0 check sourceID*check destID C66xx_0: GEL Output: RXU_T9Map60:SrcId:0x0000 DestId:0x0000 COS:0x00 COS_mask:0x00 STRM_id:0x0000 STRM__Mask:0xFFFF QId:0 FlowId:0 check sourceID*check destID C66xx_0: GEL Output: RXU_T9Map61:SrcId:0x0000 DestId:0x0000 COS:0x00 COS_mask:0x00 STRM_id:0x0000 STRM__Mask:0xFFFF QId:0 FlowId:0 check sourceID*check destID C66xx_0: GEL Output: RXU_T9Map62:SrcId:0x0000 DestId:0x0000 COS:0x00 COS_mask:0x00 STRM_id:0x0000 STRM__Mask:0xFFFF QId:0 FlowId:0 check sourceID*check destID C66xx_0: GEL Output: RXU_T9Map63:SrcId:0x0000 DestId:0x0000 COS:0x00 COS_mask:0x00 STRM_id:0x0000 STRM__Mask:0xFFFF QId:0 FlowId:0 check sourceID*check destID C66xx_0: GEL Output: ******************************************************************************************************* C66xx_0: GEL Output: ********************************* SRIO GARBAGE QUEUES ****************************************************** C66xx_0: GEL Output: ******************************************************************************************************* C66xx_0: GEL Output: Queue900 stores descriptors of message whose length mismatch between size in the UDI packet and recieved payload. C66xx_0: GEL Output: Queue 900 Status --> Entry Count 0 Byte Count 0 Packet Size 0 Queue Threshold In terms of Packets 1 C66xx_0: GEL Output: Queue901 stores descriptors of message which timeOut on receiving one of the segments. C66xx_0: GEL Output: Queue 901 Status --> Entry Count 0 Byte Count 0 Packet Size 0 Queue Threshold In terms of Packets 1 C66xx_0: GEL Output: Queue902 stores descriptors of message which received more than retry_count 'retry' responses C66xx_0: GEL Output: Queue 902 Status --> Entry Count 0 Byte Count 0 Packet Size 0 Queue Threshold In terms of Packets 1 C66xx_0: GEL Output: Queue903 stores descriptors of message which received an 'error' response. C66xx_0: GEL Output: Queue 903 Status --> Entry Count 0 Byte Count 0 Packet Size 0 Queue Threshold In terms of Packets 1 C66xx_0: GEL Output: Queue905 stores descriptors of type11 message which fails the requirement (Msg_len/16) <= Ssize C66xx_0: GEL Output: Queue 905 Status --> Entry Count 0 Byte Count 0 Packet Size 0 Queue Threshold In terms of Packets 1 C66xx_0: GEL Output: ******************************************************************************************************* C66xx_0: GEL Output: ********************************** PORT PLM CONFIGURATION ****************************************************** C66xx_0: GEL Output: ******************************************************************************************************* C66xx_0: GEL Output: ******************* PORT0 PLM CONFIGURATION ******************* C66xx_0: GEL Output: ******************* PLM Port Implementation Specific Control Register (PLM_SP0_IMP_SPEC_CTL) ******************* C66xx_0: GEL Output: DLT_THRESH => Dead link timer threshold set to 0 C66xx_0: GEL Output: SWAP_RX => Port0 RX is ##NOT SWAPPED## C66xx_0: GEL Output: SWAP_TX => Port0 TX is ##NOT SWAPPED## C66xx_0: GEL Output: PORT_SELF_RST => Port is ##NOT RESET## on receiving port reset request C66xx_0: GEL Output: LLB_EN => Line loopback mode is ##DISABLED## C66xx_0: GEL Output: TX_BYPASS => Transmitter clock crossing FIFO ##NOT BYPASSED## C66xx_0: GEL Output: SOFT_RST_PORT => Normal mode of operation C66xx_0: GEL Output: DLB_EN => Digital equipment loopback mode ##DISABLED## C66xx_0: GEL Output: USE_IDLE1 => IDLE1 sequences (above 5.5 GBaud) are **NOT ALLOWED** C66xx_0: GEL Output: USE_IDLE2 => IDLE2 sequences (below 5.5 GBaud) are **NOT ALLOWED** C66xx_0: GEL Output: PAYL_CAP => Payload capture (packet/control symbol error capture) settings are ##NOT CHANGED## C66xx_0: GEL Output: ******************* PLM Port Interrupt Enable Register (PLM_SP0_INT_ENABLE) ******************* C66xx_0: GEL Output: OUTPUT_DEGR => Interrupt notification for Output Degraded event ##DISABLED## C66xx_0: GEL Output: OUTPUT_FAIL => Interrupt notification for Output Failed event ##DISABLED## C66xx_0: GEL Output: PORT_ERR => Interrupt notification for Port Error event ##DISABLED## C66xx_0: GEL Output: DLT => Interrupt notification for Dead Link Timer events ##DISABLED## C66xx_0: GEL Output: LINK_INIT => Interrupt notification for Link Initialization event ##DISABLED## C66xx_0: GEL Output: MAX_DENIAL => Interrupt notification for Max Denial event ##DISABLED## C66xx_0: GEL Output: ******************* PLM Port0 Port-Write Enable Register (PLM_SP0_PW_ENABLE) ******************* C66xx_0: GEL Output: OUTPUT_DEGR => Contribution to port-write request for Output Degraded event ##DISABLED## C66xx_0: GEL Output: OUTPUT_FAIL => Contribution to port-write request for Output Failed event ##DISABLED## C66xx_0: GEL Output: PORT_ERR => Contribution to port-write request for Port Error event ##DISABLED## C66xx_0: GEL Output: DLT => Contribution to port-write request for Dead Link Timer events ##DISABLED## C66xx_0: GEL Output: LINK_INIT => Contribution to port-write request for Link Initialization event ##DISABLED## C66xx_0: GEL Output: MAX_DENIAL => Contribution to port-write request for Max Denial event ##DISABLED## C66xx_0: GEL Output: ******************* PLM Port Event Generate Register (PLM_SP0_EVENT_GEN) ******************* C66xx_0: GEL Output: OUTPUT_DEGR => Event Generation for Output Degraded event ##DISABLED## C66xx_0: GEL Output: OUTPUT_FAIL => Event Generation for Output Failed event ##DISABLED## C66xx_0: GEL Output: PORT_ERR => Event Generation for Port Error event ##DISABLED## C66xx_0: GEL Output: DLT => Event Generation for Dead Link Timer events ##DISABLED## C66xx_0: GEL Output: LINK_INIT => Event Generation for Link Initialization event ##DISABLED## C66xx_0: GEL Output: MAX_DENIAL => Event Generation for Max Denial event ##DISABLED## C66xx_0: GEL Output: ******************* PLM Port All Interrupts Enable Register (PLM_SP0_ALL_INT_EN) ******************* C66xx_0: GEL Output: IRQ_EN => Interrupt Error reporting ##DISABLED## C66xx_0: GEL Output: ******************* PLM Port All Port-Writes Enable Register (PLM_SP0_ALL_PW_EN) ******************* C66xx_0: GEL Output: PW_EN => Port-write request generation **ENABLED** C66xx_0: GEL Output: ******************* PLM Port Path Control Register (PLM_SP0_PATH_CTL) ******************* C66xx_0: GEL Output: PATH_MODE => MODE4( 4x ) C66xx_0: GEL Output: PATH_CONFIG => 4 Lanes, a maximum of 4 ports C66xx_0: GEL Output: PATH_ID => 0 C66xx_0: GEL Output: ******************* PLM Port Discovery Timer Register(PLM_SP0_DISCOVERY_TIMER) ******************* C66xx_0: GEL Output: DISCOVERY_TIMER => 0.0 us (default value = 0.0)) C66xx_0: GEL Output: ******************* Port Silence Timer(PLM_SP0_SILENCE_TIMER) ******************* C66xx_0: GEL Output: SILENCE_TIMER => 0.0 us C66xx_0: GEL Output: ******************* PLM Port Vmin Exponent Register (PLM_SP0_VMIN_EXP) ******************* C66xx_0: GEL Output: MMAX => 0x03 is the max threshold for Mcounter (as per RapidIO 2.1 specs) C66xx_0: GEL Output: IMAX => 0x03 is the max threshold for Icounter (as per RapidIO 2.1 specs) C66xx_0: GEL Output: VMIN_EXP => 0x00 is the No of /VALID/ code groups required for synchronization C66xx_0: GEL Output: ******************* PLM Port Lane Polarity Control Register(PLM_SP0_POL_CTL) ******************* C66xx_0: GEL Output: RX0_POL => RX0 differential pair is ##NOT SWAPPED## C66xx_0: GEL Output: RX1_POL => RX1 differential pair is ##NOT SWAPPED## C66xx_0: GEL Output: RX2_POL => RX2 differential pair is ##NOT SWAPPED## C66xx_0: GEL Output: RX3_POL => RX3 differential pair is ##NOT SWAPPED## C66xx_0: GEL Output: TX0_POL => TX0 differential pair is ##NOT SWAPPED## C66xx_0: GEL Output: TX1_POL => TX1 differential pair is ##NOT SWAPPED## C66xx_0: GEL Output: TX2_POL => TX2 differential pair is ##NOT SWAPPED## C66xx_0: GEL Output: TX3_POL => TX3 differential pair is ##NOT SWAPPED## C66xx_0: GEL Output: ******************* PLM Port Packet Denial Control Register(PLM_SP0_DENIAL_CTL) ******************* C66xx_0: GEL Output: DENIAL_THRESH => 0x00000000 is the threshold of too many consecutive retries C66xx_0: GEL Output: CNT_RTY => Retry Control Symbols ##DO COUNT## towards the packet denial threshold C66xx_0: GEL Output: CNT_PNA => Packet-Not-Accepted Control Symbols ##DO COUNT## towards the packet denial threshold C66xx_0: GEL Output: ******************* PLM Port MECS Forwarding Register(PLM_SP0_MECS_FWD) ******************* C66xx_0: GEL Output: Port0 ##DOES NOT FORWARD## MECS with cmd=0 C66xx_0: GEL Output: Port0 ##DOES NOT FORWARD## MECS with cmd=1 C66xx_0: GEL Output: Port0 ##DOES NOT FORWARD## MECS with cmd=2 C66xx_0: GEL Output: Port0 ##DOES NOT FORWARD## MECS with cmd=3 C66xx_0: GEL Output: Port0 ##DOES NOT FORWARD## MECS with cmd=4 C66xx_0: GEL Output: Port0 ##DOES NOT FORWARD## MECS with cmd=5 C66xx_0: GEL Output: Port0 ##DOES NOT FORWARD## MECS with cmd=6 C66xx_0: GEL Output: Port0 ##DOES NOT FORWARD## MECS with cmd=7 C66xx_0: GEL Output: ******************* PORT1 PLM CONFIGURATION ******************* C66xx_0: GEL Output: ******************* PLM Port Implementation Specific Control Register (PLM_SP1_IMP_SPEC_CTL) ******************* C66xx_0: GEL Output: DLT_THRESH => Dead link timer threshold set to 0 C66xx_0: GEL Output: SWAP_RX => Port1 RX is **SWAPPED** with that of Port0 C66xx_0: GEL Output: SWAP_TX => Port1 TX is **SWAPPED** with that of Port0 C66xx_0: GEL Output: PORT_SELF_RST => Port is ##NOT RESET## on receiving port reset request C66xx_0: GEL Output: LLB_EN => Line loopback mode is ##DISABLED## C66xx_0: GEL Output: TX_BYPASS => Transmitter clock crossing FIFO ##NOT BYPASSED## C66xx_0: GEL Output: SOFT_RST_PORT => Normal mode of operation C66xx_0: GEL Output: DLB_EN => Digital equipment loopback mode ##DISABLED## C66xx_0: GEL Output: USE_IDLE1 => IDLE1 sequences (above 5.5 GBaud) are **NOT ALLOWED** C66xx_0: GEL Output: USE_IDLE2 => IDLE2 sequences (below 5.5 GBaud) are **NOT ALLOWED** C66xx_0: GEL Output: PAYL_CAP => Payload capture (packet/control symbol error capture) settings are ##NOT CHANGED## C66xx_0: GEL Output: ******************* PLM Port Interrupt Enable Register (PLM_SP1_INT_ENABLE) ******************* C66xx_0: GEL Output: OUTPUT_DEGR => Interrupt notification for Output Degraded event ##DISABLED## C66xx_0: GEL Output: OUTPUT_FAIL => Interrupt notification for Output Failed event ##DISABLED## C66xx_0: GEL Output: PORT_ERR => Interrupt notification for Port Error event ##DISABLED## C66xx_0: GEL Output: DLT => Interrupt notification for Dead Link Timer events ##DISABLED## C66xx_0: GEL Output: LINK_INIT => Interrupt notification for Link Initialization event ##DISABLED## C66xx_0: GEL Output: MAX_DENIAL => Interrupt notification for Max Denial event ##DISABLED## C66xx_0: GEL Output: ******************* PLM Port1 Port-Write Enable Register (PLM_SP1_PW_ENABLE) ******************* C66xx_0: GEL Output: OUTPUT_DEGR => Contribution to port-write request for Output Degraded event ##DISABLED## C66xx_0: GEL Output: OUTPUT_FAIL => Contribution to port-write request for Output Failed event ##DISABLED## C66xx_0: GEL Output: PORT_ERR => Contribution to port-write request for Port Error event ##DISABLED## C66xx_0: GEL Output: DLT => Contribution to port-write request for Dead Link Timer events ##DISABLED## C66xx_0: GEL Output: LINK_INIT => Contribution to port-write request for Link Initialization event ##DISABLED## C66xx_0: GEL Output: MAX_DENIAL => Contribution to port-write request for Max Denial event ##DISABLED## C66xx_0: GEL Output: ******************* PLM Port Event Generate Register (PLM_SP1_EVENT_GEN) ******************* C66xx_0: GEL Output: OUTPUT_DEGR => Event Generation for Output Degraded event ##DISABLED## C66xx_0: GEL Output: OUTPUT_FAIL => Event Generation for Output Failed event ##DISABLED## C66xx_0: GEL Output: PORT_ERR => Event Generation for Port Error event ##DISABLED## C66xx_0: GEL Output: DLT => Event Generation for Dead Link Timer events ##DISABLED## C66xx_0: GEL Output: LINK_INIT => Event Generation for Link Initialization event ##DISABLED## C66xx_0: GEL Output: MAX_DENIAL => Event Generation for Max Denial event ##DISABLED## C66xx_0: GEL Output: ******************* PLM Port All Interrupts Enable Register (PLM_SP1_ALL_INT_EN) ******************* C66xx_0: GEL Output: IRQ_EN => Interrupt Error reporting ##DISABLED## C66xx_0: GEL Output: ******************* PLM Port All Port-Writes Enable Register (PLM_SP1_ALL_PW_EN) ******************* C66xx_0: GEL Output: PW_EN => Port-write request generation **ENABLED** C66xx_0: GEL Output: ******************* PLM Port Path Control Register (PLM_SP1_PATH_CTL) ******************* C66xx_0: GEL Output: PATH_MODE => MODE4( 4x ) C66xx_0: GEL Output: PATH_CONFIG => 4 Lanes, a maximum of 4 ports C66xx_0: GEL Output: PATH_ID => 0 C66xx_0: GEL Output: ******************* PLM Port Discovery Timer Register(PLM_SP1_DISCOVERY_TIMER) ******************* C66xx_0: GEL Output: DISCOVERY_TIMER => 0.0 us (default value = 0.0)) C66xx_0: GEL Output: ******************* Port Silence Timer(PLM_SP1_SILENCE_TIMER) ******************* C66xx_0: GEL Output: SILENCE_TIMER => 0.0 us C66xx_0: GEL Output: ******************* PLM Port Vmin Exponent Register (PLM_SP1_VMIN_EXP) ******************* C66xx_0: GEL Output: MMAX => 0x03 is the max threshold for Mcounter (as per RapidIO 2.1 specs) C66xx_0: GEL Output: IMAX => 0x03 is the max threshold for Icounter (as per RapidIO 2.1 specs) C66xx_0: GEL Output: VMIN_EXP => 0x00 is the No of /VALID/ code groups required for synchronization C66xx_0: GEL Output: ******************* PLM Port Lane Polarity Control Register(PLM_SP1_POL_CTL) ******************* C66xx_0: GEL Output: RX0_POL => RX0 differential pair is ##NOT SWAPPED## C66xx_0: GEL Output: RX1_POL => RX1 differential pair is ##NOT SWAPPED## C66xx_0: GEL Output: RX2_POL => RX2 differential pair is ##NOT SWAPPED## C66xx_0: GEL Output: RX3_POL => RX3 differential pair is ##NOT SWAPPED## C66xx_0: GEL Output: TX0_POL => TX0 differential pair is ##NOT SWAPPED## C66xx_0: GEL Output: TX1_POL => TX1 differential pair is ##NOT SWAPPED## C66xx_0: GEL Output: TX2_POL => TX2 differential pair is ##NOT SWAPPED## C66xx_0: GEL Output: TX3_POL => TX3 differential pair is ##NOT SWAPPED## C66xx_0: GEL Output: ******************* PLM Port Packet Denial Control Register(PLM_SP1_DENIAL_CTL) ******************* C66xx_0: GEL Output: DENIAL_THRESH => 0x00000000 is the threshold of too many consecutive retries C66xx_0: GEL Output: CNT_RTY => Retry Control Symbols ##DO COUNT## towards the packet denial threshold C66xx_0: GEL Output: CNT_PNA => Packet-Not-Accepted Control Symbols ##DO COUNT## towards the packet denial threshold C66xx_0: GEL Output: ******************* PLM Port MECS Forwarding Register(PLM_SP1_MECS_FWD) ******************* C66xx_0: GEL Output: Port1 ##DOES NOT FORWARD## MECS with cmd=0 C66xx_0: GEL Output: Port1 ##DOES NOT FORWARD## MECS with cmd=1 C66xx_0: GEL Output: Port1 ##DOES NOT FORWARD## MECS with cmd=2 C66xx_0: GEL Output: Port1 ##DOES NOT FORWARD## MECS with cmd=3 C66xx_0: GEL Output: Port1 ##DOES NOT FORWARD## MECS with cmd=4 C66xx_0: GEL Output: Port1 ##DOES NOT FORWARD## MECS with cmd=5 C66xx_0: GEL Output: Port1 ##DOES NOT FORWARD## MECS with cmd=6 C66xx_0: GEL Output: Port1 ##DOES NOT FORWARD## MECS with cmd=7 C66xx_0: GEL Output: ******************* PORT2 PLM CONFIGURATION ******************* C66xx_0: GEL Output: ******************* PLM Port Implementation Specific Control Register (PLM_SP2_IMP_SPEC_CTL) ******************* C66xx_0: GEL Output: DLT_THRESH => Dead link timer threshold set to 0 C66xx_0: GEL Output: SWAP_RX => Port2 RX is **SWAPPED** with that of Port0 C66xx_0: GEL Output: SWAP_TX => Port2 TX is **SWAPPED** with that of Port0 C66xx_0: GEL Output: PORT_SELF_RST => Port is ##NOT RESET## on receiving port reset request C66xx_0: GEL Output: LLB_EN => Line loopback mode is ##DISABLED## C66xx_0: GEL Output: TX_BYPASS => Transmitter clock crossing FIFO ##NOT BYPASSED## C66xx_0: GEL Output: SOFT_RST_PORT => Normal mode of operation C66xx_0: GEL Output: DLB_EN => Digital equipment loopback mode ##DISABLED## C66xx_0: GEL Output: USE_IDLE1 => IDLE1 sequences (above 5.5 GBaud) are **NOT ALLOWED** C66xx_0: GEL Output: USE_IDLE2 => IDLE2 sequences (below 5.5 GBaud) are **NOT ALLOWED** C66xx_0: GEL Output: PAYL_CAP => Payload capture (packet/control symbol error capture) settings are ##NOT CHANGED## C66xx_0: GEL Output: ******************* PLM Port Interrupt Enable Register (PLM_SP2_INT_ENABLE) ******************* C66xx_0: GEL Output: OUTPUT_DEGR => Interrupt notification for Output Degraded event ##DISABLED## C66xx_0: GEL Output: OUTPUT_FAIL => Interrupt notification for Output Failed event ##DISABLED## C66xx_0: GEL Output: PORT_ERR => Interrupt notification for Port Error event ##DISABLED## C66xx_0: GEL Output: DLT => Interrupt notification for Dead Link Timer events ##DISABLED## C66xx_0: GEL Output: LINK_INIT => Interrupt notification for Link Initialization event ##DISABLED## C66xx_0: GEL Output: MAX_DENIAL => Interrupt notification for Max Denial event ##DISABLED## C66xx_0: GEL Output: ******************* PLM Port2 Port-Write Enable Register (PLM_SP2_PW_ENABLE) ******************* C66xx_0: GEL Output: OUTPUT_DEGR => Contribution to port-write request for Output Degraded event ##DISABLED## C66xx_0: GEL Output: OUTPUT_FAIL => Contribution to port-write request for Output Failed event ##DISABLED## C66xx_0: GEL Output: PORT_ERR => Contribution to port-write request for Port Error event ##DISABLED## C66xx_0: GEL Output: DLT => Contribution to port-write request for Dead Link Timer events ##DISABLED## C66xx_0: GEL Output: LINK_INIT => Contribution to port-write request for Link Initialization event ##DISABLED## C66xx_0: GEL Output: MAX_DENIAL => Contribution to port-write request for Max Denial event ##DISABLED## C66xx_0: GEL Output: ******************* PLM Port Event Generate Register (PLM_SP2_EVENT_GEN) ******************* C66xx_0: GEL Output: OUTPUT_DEGR => Event Generation for Output Degraded event ##DISABLED## C66xx_0: GEL Output: OUTPUT_FAIL => Event Generation for Output Failed event ##DISABLED## C66xx_0: GEL Output: PORT_ERR => Event Generation for Port Error event ##DISABLED## C66xx_0: GEL Output: DLT => Event Generation for Dead Link Timer events ##DISABLED## C66xx_0: GEL Output: LINK_INIT => Event Generation for Link Initialization event ##DISABLED## C66xx_0: GEL Output: MAX_DENIAL => Event Generation for Max Denial event ##DISABLED## C66xx_0: GEL Output: ******************* PLM Port All Interrupts Enable Register (PLM_SP2_ALL_INT_EN) ******************* C66xx_0: GEL Output: IRQ_EN => Interrupt Error reporting ##DISABLED## C66xx_0: GEL Output: ******************* PLM Port All Port-Writes Enable Register (PLM_SP2_ALL_PW_EN) ******************* C66xx_0: GEL Output: PW_EN => Port-write request generation **ENABLED** C66xx_0: GEL Output: ******************* PLM Port Path Control Register (PLM_SP2_PATH_CTL) ******************* C66xx_0: GEL Output: PATH_MODE => MODE4( 4x ) C66xx_0: GEL Output: PATH_CONFIG => 4 Lanes, a maximum of 4 ports C66xx_0: GEL Output: PATH_ID => 0 C66xx_0: GEL Output: ******************* PLM Port Discovery Timer Register(PLM_SP2_DISCOVERY_TIMER) ******************* C66xx_0: GEL Output: DISCOVERY_TIMER => 0.0 us (default value = 0.0)) C66xx_0: GEL Output: ******************* Port Silence Timer(PLM_SP2_SILENCE_TIMER) ******************* C66xx_0: GEL Output: SILENCE_TIMER => 0.0 us C66xx_0: GEL Output: ******************* PLM Port Vmin Exponent Register (PLM_SP2_VMIN_EXP) ******************* C66xx_0: GEL Output: MMAX => 0x03 is the max threshold for Mcounter (as per RapidIO 2.1 specs) C66xx_0: GEL Output: IMAX => 0x03 is the max threshold for Icounter (as per RapidIO 2.1 specs) C66xx_0: GEL Output: VMIN_EXP => 0x00 is the No of /VALID/ code groups required for synchronization C66xx_0: GEL Output: ******************* PLM Port Lane Polarity Control Register(PLM_SP2_POL_CTL) ******************* C66xx_0: GEL Output: RX0_POL => RX0 differential pair is ##NOT SWAPPED## C66xx_0: GEL Output: RX1_POL => RX1 differential pair is ##NOT SWAPPED## C66xx_0: GEL Output: RX2_POL => RX2 differential pair is ##NOT SWAPPED## C66xx_0: GEL Output: RX3_POL => RX3 differential pair is ##NOT SWAPPED## C66xx_0: GEL Output: TX0_POL => TX0 differential pair is ##NOT SWAPPED## C66xx_0: GEL Output: TX1_POL => TX1 differential pair is ##NOT SWAPPED## C66xx_0: GEL Output: TX2_POL => TX2 differential pair is ##NOT SWAPPED## C66xx_0: GEL Output: TX3_POL => TX3 differential pair is ##NOT SWAPPED## C66xx_0: GEL Output: ******************* PLM Port Packet Denial Control Register(PLM_SP2_DENIAL_CTL) ******************* C66xx_0: GEL Output: DENIAL_THRESH => 0x00000000 is the threshold of too many consecutive retries C66xx_0: GEL Output: CNT_RTY => Retry Control Symbols ##DO COUNT## towards the packet denial threshold C66xx_0: GEL Output: CNT_PNA => Packet-Not-Accepted Control Symbols ##DO COUNT## towards the packet denial threshold C66xx_0: GEL Output: ******************* PLM Port MECS Forwarding Register(PLM_SP2_MECS_FWD) ******************* C66xx_0: GEL Output: Port2 ##DOES NOT FORWARD## MECS with cmd=0 C66xx_0: GEL Output: Port2 ##DOES NOT FORWARD## MECS with cmd=1 C66xx_0: GEL Output: Port2 ##DOES NOT FORWARD## MECS with cmd=2 C66xx_0: GEL Output: Port2 ##DOES NOT FORWARD## MECS with cmd=3 C66xx_0: GEL Output: Port2 ##DOES NOT FORWARD## MECS with cmd=4 C66xx_0: GEL Output: Port2 ##DOES NOT FORWARD## MECS with cmd=5 C66xx_0: GEL Output: Port2 ##DOES NOT FORWARD## MECS with cmd=6 C66xx_0: GEL Output: Port2 ##DOES NOT FORWARD## MECS with cmd=7 C66xx_0: GEL Output: ******************* PORT3 PLM CONFIGURATION ******************* C66xx_0: GEL Output: ******************* PLM Port Implementation Specific Control Register (PLM_SP3_IMP_SPEC_CTL) ******************* C66xx_0: GEL Output: DLT_THRESH => Dead link timer threshold set to 0 C66xx_0: GEL Output: SWAP_RX => Port3 RX is **SWAPPED** with that of Port0 C66xx_0: GEL Output: SWAP_TX => Port3 TX is **SWAPPED** with that of Port0 C66xx_0: GEL Output: PORT_SELF_RST => Port is ##NOT RESET## on receiving port reset request C66xx_0: GEL Output: LLB_EN => Line loopback mode is ##DISABLED## C66xx_0: GEL Output: TX_BYPASS => Transmitter clock crossing FIFO ##NOT BYPASSED## C66xx_0: GEL Output: SOFT_RST_PORT => Normal mode of operation C66xx_0: GEL Output: DLB_EN => Digital equipment loopback mode ##DISABLED## C66xx_0: GEL Output: USE_IDLE1 => IDLE1 sequences (above 5.5 GBaud) are **NOT ALLOWED** C66xx_0: GEL Output: USE_IDLE2 => IDLE2 sequences (below 5.5 GBaud) are **NOT ALLOWED** C66xx_0: GEL Output: PAYL_CAP => Payload capture (packet/control symbol error capture) settings are ##NOT CHANGED## C66xx_0: GEL Output: ******************* PLM Port Interrupt Enable Register (PLM_SP3_INT_ENABLE) ******************* C66xx_0: GEL Output: OUTPUT_DEGR => Interrupt notification for Output Degraded event ##DISABLED## C66xx_0: GEL Output: OUTPUT_FAIL => Interrupt notification for Output Failed event ##DISABLED## C66xx_0: GEL Output: PORT_ERR => Interrupt notification for Port Error event ##DISABLED## C66xx_0: GEL Output: DLT => Interrupt notification for Dead Link Timer events ##DISABLED## C66xx_0: GEL Output: LINK_INIT => Interrupt notification for Link Initialization event ##DISABLED## C66xx_0: GEL Output: MAX_DENIAL => Interrupt notification for Max Denial event ##DISABLED## C66xx_0: GEL Output: ******************* PLM Port3 Port-Write Enable Register (PLM_SP3_PW_ENABLE) ******************* C66xx_0: GEL Output: OUTPUT_DEGR => Contribution to port-write request for Output Degraded event ##DISABLED## C66xx_0: GEL Output: OUTPUT_FAIL => Contribution to port-write request for Output Failed event ##DISABLED## C66xx_0: GEL Output: PORT_ERR => Contribution to port-write request for Port Error event ##DISABLED## C66xx_0: GEL Output: DLT => Contribution to port-write request for Dead Link Timer events ##DISABLED## C66xx_0: GEL Output: LINK_INIT => Contribution to port-write request for Link Initialization event ##DISABLED## C66xx_0: GEL Output: MAX_DENIAL => Contribution to port-write request for Max Denial event ##DISABLED## C66xx_0: GEL Output: ******************* PLM Port Event Generate Register (PLM_SP3_EVENT_GEN) ******************* C66xx_0: GEL Output: OUTPUT_DEGR => Event Generation for Output Degraded event ##DISABLED## C66xx_0: GEL Output: OUTPUT_FAIL => Event Generation for Output Failed event ##DISABLED## C66xx_0: GEL Output: PORT_ERR => Event Generation for Port Error event ##DISABLED## C66xx_0: GEL Output: DLT => Event Generation for Dead Link Timer events ##DISABLED## C66xx_0: GEL Output: LINK_INIT => Event Generation for Link Initialization event ##DISABLED## C66xx_0: GEL Output: MAX_DENIAL => Event Generation for Max Denial event ##DISABLED## C66xx_0: GEL Output: ******************* PLM Port All Interrupts Enable Register (PLM_SP3_ALL_INT_EN) ******************* C66xx_0: GEL Output: IRQ_EN => Interrupt Error reporting ##DISABLED## C66xx_0: GEL Output: ******************* PLM Port All Port-Writes Enable Register (PLM_SP3_ALL_PW_EN) ******************* C66xx_0: GEL Output: PW_EN => Port-write request generation **ENABLED** C66xx_0: GEL Output: ******************* PLM Port Path Control Register (PLM_SP3_PATH_CTL) ******************* C66xx_0: GEL Output: PATH_MODE => MODE4( 4x ) C66xx_0: GEL Output: PATH_CONFIG => 4 Lanes, a maximum of 4 ports C66xx_0: GEL Output: PATH_ID => 0 C66xx_0: GEL Output: ******************* PLM Port Discovery Timer Register(PLM_SP3_DISCOVERY_TIMER) ******************* C66xx_0: GEL Output: DISCOVERY_TIMER => 0.0 us (default value = 0.0)) C66xx_0: GEL Output: ******************* Port Silence Timer(PLM_SP3_SILENCE_TIMER) ******************* C66xx_0: GEL Output: SILENCE_TIMER => 0.0 us C66xx_0: GEL Output: ******************* PLM Port Vmin Exponent Register (PLM_SP3_VMIN_EXP) ******************* C66xx_0: GEL Output: MMAX => 0x03 is the max threshold for Mcounter (as per RapidIO 2.1 specs) C66xx_0: GEL Output: IMAX => 0x03 is the max threshold for Icounter (as per RapidIO 2.1 specs) C66xx_0: GEL Output: VMIN_EXP => 0x00 is the No of /VALID/ code groups required for synchronization C66xx_0: GEL Output: ******************* PLM Port Lane Polarity Control Register(PLM_SP3_POL_CTL) ******************* C66xx_0: GEL Output: RX0_POL => RX0 differential pair is ##NOT SWAPPED## C66xx_0: GEL Output: RX1_POL => RX1 differential pair is ##NOT SWAPPED## C66xx_0: GEL Output: RX2_POL => RX2 differential pair is ##NOT SWAPPED## C66xx_0: GEL Output: RX3_POL => RX3 differential pair is ##NOT SWAPPED## C66xx_0: GEL Output: TX0_POL => TX0 differential pair is ##NOT SWAPPED## C66xx_0: GEL Output: TX1_POL => TX1 differential pair is ##NOT SWAPPED## C66xx_0: GEL Output: TX2_POL => TX2 differential pair is ##NOT SWAPPED## C66xx_0: GEL Output: TX3_POL => TX3 differential pair is ##NOT SWAPPED## C66xx_0: GEL Output: ******************* PLM Port Packet Denial Control Register(PLM_SP3_DENIAL_CTL) ******************* C66xx_0: GEL Output: DENIAL_THRESH => 0x00000000 is the threshold of too many consecutive retries C66xx_0: GEL Output: CNT_RTY => Retry Control Symbols ##DO COUNT## towards the packet denial threshold C66xx_0: GEL Output: CNT_PNA => Packet-Not-Accepted Control Symbols ##DO COUNT## towards the packet denial threshold C66xx_0: GEL Output: ******************* PLM Port MECS Forwarding Register(PLM_SP3_MECS_FWD) ******************* C66xx_0: GEL Output: Port3 ##DOES NOT FORWARD## MECS with cmd=0 C66xx_0: GEL Output: Port3 ##DOES NOT FORWARD## MECS with cmd=1 C66xx_0: GEL Output: Port3 ##DOES NOT FORWARD## MECS with cmd=2 C66xx_0: GEL Output: Port3 ##DOES NOT FORWARD## MECS with cmd=3 C66xx_0: GEL Output: Port3 ##DOES NOT FORWARD## MECS with cmd=4 C66xx_0: GEL Output: Port3 ##DOES NOT FORWARD## MECS with cmd=5 C66xx_0: GEL Output: Port3 ##DOES NOT FORWARD## MECS with cmd=6 C66xx_0: GEL Output: Port3 ##DOES NOT FORWARD## MECS with cmd=7 C66xx_0: GEL Output: ******************************************************************************************************* C66xx_0: GEL Output: ********************************** PORT PLM STATUS ****************************************************** C66xx_0: GEL Output: ******************************************************************************************************* C66xx_0: GEL Output: ******************* PORT0 PLM STATUS ******************* C66xx_0: GEL Output: ******************* PLM Port Power Down Control Register (PLM_SP0_PWDN_CTL) ******************* C66xx_0: GEL Output: Port0 is in ##NORMAL## mode C66xx_0: GEL Output: ******************* PLM Port Event Status Register(PLM_SP0_Status) ******************* C66xx_0: GEL Output: TLM_INT => Port0 TLM has ##NOT DETECTED## an event, which requires interrupt notification. C66xx_0: GEL Output: PBM_INT => Port0 PBM has ##NOT DETECTED## an event, which requires interrupt notification. C66xx_0: GEL Output: MECS => Port0 has ##NOT RECEIVED## a Multi-cast Event Control Symbol C66xx_0: GEL Output: TLM_PW => Port0 TLM has ##NOT DETECTED## an event, which requires Port-Write notification C66xx_0: GEL Output: PBM_PW => Port0 PBM has ##NOT DETECTED## an event, which requires Port-Write notification C66xx_0: GEL Output: RST_REQ => Port0 has ##NOT RECEIVED## a reset request command C66xx_0: GEL Output: OUTPUT_DEGR => Port0 is ##NOT## in output degraded condition C66xx_0: GEL Output: OUTPUT_FAIL => Port0 is ##NOT## in output failed condition C66xx_0: GEL Output: PORT_ERR => Port0 has ##NOT ENCOUNTERED## a unrecoverable HW error C66xx_0: GEL Output: DLT => Port0 has ##NOT DETECTED## that its link partner has been removed C66xx_0: GEL Output: LINK_INIT => Port0 Link Initialization **UNSUCCESSFUL** C66xx_0: GEL Output: MAX_DENIAL => Port0 has ##NOT EXCEEDED## the denial threshold C66xx_0: GEL Output: ******************* PLM Port Received MECS Status Register(PLM_SP0_RCVD_MECS) ******************* C66xx_0: GEL Output: Port0 ##DID NOT RECEIVE## MECS with cmd=0 C66xx_0: GEL Output: Port0 ##DID NOT RECEIVE## MECS with cmd=1 C66xx_0: GEL Output: Port0 ##DID NOT RECEIVE## MECS with cmd=2 C66xx_0: GEL Output: Port0 ##DID NOT RECEIVE## MECS with cmd=3 C66xx_0: GEL Output: Port0 ##DID NOT RECEIVE## MECS with cmd=4 C66xx_0: GEL Output: Port0 ##DID NOT RECEIVE## MECS with cmd=5 C66xx_0: GEL Output: Port0 ##DID NOT RECEIVE## MECS with cmd=6 C66xx_0: GEL Output: Port0 ##DID NOT RECEIVE## MECS with cmd=7 C66xx_0: GEL Output: ******************* PORT1 PLM STATUS ******************* C66xx_0: GEL Output: ******************* PLM Port Power Down Control Register (PLM_SP1_PWDN_CTL) ******************* C66xx_0: GEL Output: Port1 is in ##NORMAL## mode C66xx_0: GEL Output: ******************* PLM Port Event Status Register(PLM_SP1_Status) ******************* C66xx_0: GEL Output: TLM_INT => Port1 TLM has ##NOT DETECTED## an event, which requires interrupt notification. C66xx_0: GEL Output: PBM_INT => Port1 PBM has ##NOT DETECTED## an event, which requires interrupt notification. C66xx_0: GEL Output: MECS => Port1 has ##NOT RECEIVED## a Multi-cast Event Control Symbol C66xx_0: GEL Output: TLM_PW => Port1 TLM has ##NOT DETECTED## an event, which requires Port-Write notification C66xx_0: GEL Output: PBM_PW => Port1 PBM has ##NOT DETECTED## an event, which requires Port-Write notification C66xx_0: GEL Output: RST_REQ => Port1 has ##NOT RECEIVED## a reset request command C66xx_0: GEL Output: OUTPUT_DEGR => Port1 is ##NOT## in output degraded condition C66xx_0: GEL Output: OUTPUT_FAIL => Port1 is ##NOT## in output failed condition C66xx_0: GEL Output: PORT_ERR => Port1 has ##NOT ENCOUNTERED## a unrecoverable HW error C66xx_0: GEL Output: DLT => Port1 has ##NOT DETECTED## that its link partner has been removed C66xx_0: GEL Output: LINK_INIT => Port1 Link Initialization **UNSUCCESSFUL** C66xx_0: GEL Output: MAX_DENIAL => Port1 has ##NOT EXCEEDED## the denial threshold C66xx_0: GEL Output: ******************* PLM Port Received MECS Status Register(PLM_SP1_RCVD_MECS) ******************* C66xx_0: GEL Output: Port1 ##DID NOT RECEIVE## MECS with cmd=0 C66xx_0: GEL Output: Port1 ##DID NOT RECEIVE## MECS with cmd=1 C66xx_0: GEL Output: Port1 ##DID NOT RECEIVE## MECS with cmd=2 C66xx_0: GEL Output: Port1 ##DID NOT RECEIVE## MECS with cmd=3 C66xx_0: GEL Output: Port1 ##DID NOT RECEIVE## MECS with cmd=4 C66xx_0: GEL Output: Port1 ##DID NOT RECEIVE## MECS with cmd=5 C66xx_0: GEL Output: Port1 ##DID NOT RECEIVE## MECS with cmd=6 C66xx_0: GEL Output: Port1 ##DID NOT RECEIVE## MECS with cmd=7 C66xx_0: GEL Output: ******************* PORT2 PLM STATUS ******************* C66xx_0: GEL Output: ******************* PLM Port Power Down Control Register (PLM_SP2_PWDN_CTL) ******************* C66xx_0: GEL Output: Port2 is in ##NORMAL## mode C66xx_0: GEL Output: ******************* PLM Port Event Status Register(PLM_SP2_Status) ******************* C66xx_0: GEL Output: TLM_INT => Port2 TLM has ##NOT DETECTED## an event, which requires interrupt notification. C66xx_0: GEL Output: PBM_INT => Port2 PBM has ##NOT DETECTED## an event, which requires interrupt notification. C66xx_0: GEL Output: MECS => Port2 has ##NOT RECEIVED## a Multi-cast Event Control Symbol C66xx_0: GEL Output: TLM_PW => Port2 TLM has ##NOT DETECTED## an event, which requires Port-Write notification C66xx_0: GEL Output: PBM_PW => Port2 PBM has ##NOT DETECTED## an event, which requires Port-Write notification C66xx_0: GEL Output: RST_REQ => Port2 has ##NOT RECEIVED## a reset request command C66xx_0: GEL Output: OUTPUT_DEGR => Port2 is ##NOT## in output degraded condition C66xx_0: GEL Output: OUTPUT_FAIL => Port2 is ##NOT## in output failed condition C66xx_0: GEL Output: PORT_ERR => Port2 has ##NOT ENCOUNTERED## a unrecoverable HW error C66xx_0: GEL Output: DLT => Port2 has ##NOT DETECTED## that its link partner has been removed C66xx_0: GEL Output: LINK_INIT => Port2 Link Initialization **UNSUCCESSFUL** C66xx_0: GEL Output: MAX_DENIAL => Port2 has ##NOT EXCEEDED## the denial threshold C66xx_0: GEL Output: ******************* PLM Port Received MECS Status Register(PLM_SP2_RCVD_MECS) ******************* C66xx_0: GEL Output: Port2 ##DID NOT RECEIVE## MECS with cmd=0 C66xx_0: GEL Output: Port2 ##DID NOT RECEIVE## MECS with cmd=1 C66xx_0: GEL Output: Port2 ##DID NOT RECEIVE## MECS with cmd=2 C66xx_0: GEL Output: Port2 ##DID NOT RECEIVE## MECS with cmd=3 C66xx_0: GEL Output: Port2 ##DID NOT RECEIVE## MECS with cmd=4 C66xx_0: GEL Output: Port2 ##DID NOT RECEIVE## MECS with cmd=5 C66xx_0: GEL Output: Port2 ##DID NOT RECEIVE## MECS with cmd=6 C66xx_0: GEL Output: Port2 ##DID NOT RECEIVE## MECS with cmd=7 C66xx_0: GEL Output: ******************* PORT3 PLM STATUS ******************* C66xx_0: GEL Output: ******************* PLM Port Power Down Control Register (PLM_SP3_PWDN_CTL) ******************* C66xx_0: GEL Output: Port3 is in ##NORMAL## mode C66xx_0: GEL Output: ******************* PLM Port Event Status Register(PLM_SP3_Status) ******************* C66xx_0: GEL Output: TLM_INT => Port3 TLM has ##NOT DETECTED## an event, which requires interrupt notification. C66xx_0: GEL Output: PBM_INT => Port3 PBM has ##NOT DETECTED## an event, which requires interrupt notification. C66xx_0: GEL Output: MECS => Port3 has ##NOT RECEIVED## a Multi-cast Event Control Symbol C66xx_0: GEL Output: TLM_PW => Port3 TLM has ##NOT DETECTED## an event, which requires Port-Write notification C66xx_0: GEL Output: PBM_PW => Port3 PBM has ##NOT DETECTED## an event, which requires Port-Write notification C66xx_0: GEL Output: RST_REQ => Port3 has ##NOT RECEIVED## a reset request command C66xx_0: GEL Output: OUTPUT_DEGR => Port3 is ##NOT## in output degraded condition C66xx_0: GEL Output: OUTPUT_FAIL => Port3 is ##NOT## in output failed condition C66xx_0: GEL Output: PORT_ERR => Port3 has ##NOT ENCOUNTERED## a unrecoverable HW error C66xx_0: GEL Output: DLT => Port3 has ##NOT DETECTED## that its link partner has been removed C66xx_0: GEL Output: LINK_INIT => Port3 Link Initialization **UNSUCCESSFUL** C66xx_0: GEL Output: MAX_DENIAL => Port3 has ##NOT EXCEEDED## the denial threshold C66xx_0: GEL Output: ******************* PLM Port Received MECS Status Register(PLM_SP3_RCVD_MECS) ******************* C66xx_0: GEL Output: Port3 ##DID NOT RECEIVE## MECS with cmd=0 C66xx_0: GEL Output: Port3 ##DID NOT RECEIVE## MECS with cmd=1 C66xx_0: GEL Output: Port3 ##DID NOT RECEIVE## MECS with cmd=2 C66xx_0: GEL Output: Port3 ##DID NOT RECEIVE## MECS with cmd=3 C66xx_0: GEL Output: Port3 ##DID NOT RECEIVE## MECS with cmd=4 C66xx_0: GEL Output: Port3 ##DID NOT RECEIVE## MECS with cmd=5 C66xx_0: GEL Output: Port3 ##DID NOT RECEIVE## MECS with cmd=6 C66xx_0: GEL Output: Port3 ##DID NOT RECEIVE## MECS with cmd=7 C66xx_0: GEL Output: ******************************************************************************************************* C66xx_0: GEL Output: ********************************** PORT TLM CONFIGURATION ****************************************************** C66xx_0: GEL Output: ******************************************************************************************************* C66xx_0: GEL Output: ******************* PORT0 TLM CONFIGURATION ******************* C66xx_0: GEL Output: ******************* TLM Port Control Register (TLM_SP0_CONTROL) ******************* C66xx_0: GEL Output: LENGTH => 9 => The no of data nodes to be stored, before the PBMi notifies to schedule a pkt(default value=9) C66xx_0: GEL Output: Promiscuous Mode Settings: C66xx_0: GEL Output: For Maintainence type pkts : C66xx_0: GEL Output: If destID matches base destID => route pkt to LLM C66xx_0: GEL Output: If destID matches BRR => route by BRR C66xx_0: GEL Output: No match of destID => Discard this pkt C66xx_0: GEL Output: For Non-Maintainence type pkts : C66xx_0: GEL Output: If destID matches base destID => route pkt to User-Core C66xx_0: GEL Output: If destID matches BRR => route pkt to User-Core C66xx_0: GEL Output: No match of destID => Discard this pkt C66xx_0: GEL Output: VOQ_SELECT => VOQ within a Port Group is determined by the packet's FLOWID (PRIO,CRF) C66xx_0: GEL Output: PORTGROUP_SELECT => There is only one port group to which TLMi directs non-LLM traffic C66xx_0: GEL Output: ******************* TLM Port Interrupt Enable Register(TLM_SP0_INT_ENABLE) ******************* C66xx_0: GEL Output: IG_BRR_FILTER => IG_BRR_FILTER ##DOES NOT## contribute to the port's interrupt request C66xx_0: GEL Output: IG_BAD_VC => IG_BAD_VC ##DOES NOT## contribute to the port's interrupt request C66xx_0: GEL Output: ******************* TLM Port0 Port-Write Enable Register(TLM_SP0_PW_ENABLE) ******************* C66xx_0: GEL Output: IG_BRR_FILTER => IG_BRR_FILTER ##DOES NOT## contribute to the port's Port_write request C66xx_0: GEL Output: IG_BAD_VC => IG_BAD_VC ##DOES NOT## contribute to the port's Port_write request C66xx_0: GEL Output: ******************* TLM Port Base Routing Register 0 Control Register(TLM_SP0_BRR_0_CTL) ******************* C66xx_0: GEL Output: PRIVATE => used only by one port (PRIVATE) C66xx_0: GEL Output: ROUTE_MR_TO_LLM => maintenance request/reserved packets with DestID matching BRR are routed to the LLM C66xx_0: GEL Output: ENABLE => BRR's ##NOT USED## for accepting and routing inbound pkts C66xx_0: GEL Output: ******************* TLM Port Base Routing Register 0 Pattern & Match Register(TLM_SP0_BRR_0_PATTERN_MATCH) ******************* C66xx_0: GEL Output: MATCH => 0x00000000 => Indicates which of the 16 bits are compared against the DestID C66xx_0: GEL Output: PATTERN => 0x00000000 => These are the 16 bits which are compared one-to-one with the DestID C66xx_0: GEL Output: ******************* TLM Port Base Routing Register 1 Control Register(TLM_SP0_BRR_1_CTL) ******************* C66xx_0: GEL Output: PRIVATE => used only by one port (PRIVATE) C66xx_0: GEL Output: ROUTE_MR_TO_LLM => maintenance request/reserved packets with DestID matching BRR are routed to the LLM C66xx_0: GEL Output: ENABLE => BRR's **USED** for accepting and routing inbound pkts C66xx_0: GEL Output: ******************* TLM Port Base Routing Register 1 Pattern & Match Register(TLM_SP0_BRR_1_PATTERN_MATCH) ******************* C66xx_0: GEL Output: MATCH => 0x0000FFFF => Indicates which of the 16 bits are compared against the DestID C66xx_0: GEL Output: PATTERN => 0x00004560 => These are the 16 bits which are compared one-to-one with the DestID C66xx_0: GEL Output: ******************* TLM Port Base Routing Register 2 Control Register(TLM_SP0_BRR_2_CTL) ******************* C66xx_0: GEL Output: PRIVATE => used by all ports in the path (PUBLIC) C66xx_0: GEL Output: ROUTE_MR_TO_LLM => maintenance request/reserved packets with DestID matching BRR are routed to the LLM C66xx_0: GEL Output: ENABLE => BRR's ##NOT USED## for accepting and routing inbound pkts C66xx_0: GEL Output: ******************* TLM Port Base Routing Register 2 Pattern & Match Register(TLM_SP0_BRR_2_PATTERN_MATCH) ******************* C66xx_0: GEL Output: MATCH => 0x0000FFFF => Indicates which of the 16 bits are compared against the DestID C66xx_0: GEL Output: PATTERN => 0x00001234 => These are the 16 bits which are compared one-to-one with the DestID C66xx_0: GEL Output: ******************* TLM Port Base Routing Register 3 Control Register(TLM_SP0_BRR_3_CTL) ******************* C66xx_0: GEL Output: PRIVATE => used by all ports in the path (PUBLIC) C66xx_0: GEL Output: ROUTE_MR_TO_LLM => maintenance request/reserved packets with DestID matching BRR are routed to the LLM C66xx_0: GEL Output: ENABLE => BRR's ##NOT USED## for accepting and routing inbound pkts C66xx_0: GEL Output: ******************* TLM Port Base Routing Register 3 Pattern & Match Register(TLM_SP0_BRR_3_PATTERN_MATCH) ******************* C66xx_0: GEL Output: MATCH => 0x0000FFFF => Indicates which of the 16 bits are compared against the DestID C66xx_0: GEL Output: PATTERN => 0x00005678 => These are the 16 bits which are compared one-to-one with the DestID C66xx_0: GEL Output: ******************* PORT1 TLM CONFIGURATION ******************* C66xx_0: GEL Output: ******************* TLM Port Control Register (TLM_SP1_CONTROL) ******************* C66xx_0: GEL Output: LENGTH => 9 => The no of data nodes to be stored, before the PBMi notifies to schedule a pkt(default value=9) C66xx_0: GEL Output: Promiscuous Mode Settings: C66xx_0: GEL Output: For Maintainence type pkts : C66xx_0: GEL Output: If destID matches base destID => route pkt to LLM C66xx_0: GEL Output: If destID matches BRR => route by BRR C66xx_0: GEL Output: No match of destID => Discard this pkt C66xx_0: GEL Output: For Non-Maintainence type pkts : C66xx_0: GEL Output: If destID matches base destID => route pkt to User-Core C66xx_0: GEL Output: If destID matches BRR => route pkt to User-Core C66xx_0: GEL Output: No match of destID => Discard this pkt C66xx_0: GEL Output: VOQ_SELECT => VOQ within a Port Group is determined by the packet's FLOWID (PRIO,CRF) C66xx_0: GEL Output: PORTGROUP_SELECT => There is only one port group to which TLMi directs non-LLM traffic C66xx_0: GEL Output: ******************* TLM Port Interrupt Enable Register(TLM_SP1_INT_ENABLE) ******************* C66xx_0: GEL Output: IG_BRR_FILTER => IG_BRR_FILTER ##DOES NOT## contribute to the port's interrupt request C66xx_0: GEL Output: IG_BAD_VC => IG_BAD_VC ##DOES NOT## contribute to the port's interrupt request C66xx_0: GEL Output: ******************* TLM Port1 Port-Write Enable Register(TLM_SP1_PW_ENABLE) ******************* C66xx_0: GEL Output: IG_BRR_FILTER => IG_BRR_FILTER ##DOES NOT## contribute to the port's Port_write request C66xx_0: GEL Output: IG_BAD_VC => IG_BAD_VC ##DOES NOT## contribute to the port's Port_write request C66xx_0: GEL Output: ******************* TLM Port Base Routing Register 0 Control Register(TLM_SP1_BRR_0_CTL) ******************* C66xx_0: GEL Output: PRIVATE => used by all ports in the path (PUBLIC) C66xx_0: GEL Output: ROUTE_MR_TO_LLM => maintenance request/reserved packets with DestID matching BRR are routed to the LLM C66xx_0: GEL Output: ENABLE => BRR's **USED** for accepting and routing inbound pkts C66xx_0: GEL Output: ******************* TLM Port Base Routing Register 0 Pattern & Match Register(TLM_SP1_BRR_0_PATTERN_MATCH) ******************* C66xx_0: GEL Output: MATCH => 0x00000000 => Indicates which of the 16 bits are compared against the DestID C66xx_0: GEL Output: PATTERN => 0x00000000 => These are the 16 bits which are compared one-to-one with the DestID C66xx_0: GEL Output: ******************* TLM Port Base Routing Register 1 Control Register(TLM_SP1_BRR_1_CTL) ******************* C66xx_0: GEL Output: PRIVATE => used by all ports in the path (PUBLIC) C66xx_0: GEL Output: ROUTE_MR_TO_LLM => maintenance request/reserved packets with DestID matching BRR are routed to the LLM C66xx_0: GEL Output: ENABLE => BRR's ##NOT USED## for accepting and routing inbound pkts C66xx_0: GEL Output: ******************* TLM Port Base Routing Register 1 Pattern & Match Register(TLM_SP1_BRR_1_PATTERN_MATCH) ******************* C66xx_0: GEL Output: MATCH => 0x0000FFFF => Indicates which of the 16 bits are compared against the DestID C66xx_0: GEL Output: PATTERN => 0x00000000 => These are the 16 bits which are compared one-to-one with the DestID C66xx_0: GEL Output: ******************* TLM Port Base Routing Register 2 Control Register(TLM_SP1_BRR_2_CTL) ******************* C66xx_0: GEL Output: PRIVATE => used only by one port (PRIVATE) C66xx_0: GEL Output: ROUTE_MR_TO_LLM => maintenance request/reserved packets with DestID matching BRR are routed to the LLM C66xx_0: GEL Output: ENABLE => BRR's **USED** for accepting and routing inbound pkts C66xx_0: GEL Output: ******************* TLM Port Base Routing Register 2 Pattern & Match Register(TLM_SP1_BRR_2_PATTERN_MATCH) ******************* C66xx_0: GEL Output: MATCH => 0x0000FFFF => Indicates which of the 16 bits are compared against the DestID C66xx_0: GEL Output: PATTERN => 0x00000000 => These are the 16 bits which are compared one-to-one with the DestID C66xx_0: GEL Output: ******************* TLM Port Base Routing Register 3 Control Register(TLM_SP1_BRR_3_CTL) ******************* C66xx_0: GEL Output: PRIVATE => used only by one port (PRIVATE) C66xx_0: GEL Output: ROUTE_MR_TO_LLM => maintenance request/reserved packets with DestID matching BRR are routed to the LLM C66xx_0: GEL Output: ENABLE => BRR's **USED** for accepting and routing inbound pkts C66xx_0: GEL Output: ******************* TLM Port Base Routing Register 3 Pattern & Match Register(TLM_SP1_BRR_3_PATTERN_MATCH) ******************* C66xx_0: GEL Output: MATCH => 0x0000FFFF => Indicates which of the 16 bits are compared against the DestID C66xx_0: GEL Output: PATTERN => 0x00000000 => These are the 16 bits which are compared one-to-one with the DestID C66xx_0: GEL Output: ******************* PORT2 TLM CONFIGURATION ******************* C66xx_0: GEL Output: ******************* TLM Port Control Register (TLM_SP2_CONTROL) ******************* C66xx_0: GEL Output: LENGTH => 9 => The no of data nodes to be stored, before the PBMi notifies to schedule a pkt(default value=9) C66xx_0: GEL Output: Promiscuous Mode Settings: C66xx_0: GEL Output: For Maintainence type pkts : C66xx_0: GEL Output: If destID matches base destID => route pkt to LLM C66xx_0: GEL Output: If destID matches BRR => route by BRR C66xx_0: GEL Output: No match of destID => Discard this pkt C66xx_0: GEL Output: For Non-Maintainence type pkts : C66xx_0: GEL Output: If destID matches base destID => route pkt to User-Core C66xx_0: GEL Output: If destID matches BRR => route pkt to User-Core C66xx_0: GEL Output: No match of destID => Discard this pkt C66xx_0: GEL Output: VOQ_SELECT => VOQ within a Port Group is determined by the packet's FLOWID (PRIO,CRF) C66xx_0: GEL Output: PORTGROUP_SELECT => There is only one port group to which TLMi directs non-LLM traffic C66xx_0: GEL Output: ******************* TLM Port Interrupt Enable Register(TLM_SP2_INT_ENABLE) ******************* C66xx_0: GEL Output: IG_BRR_FILTER => IG_BRR_FILTER ##DOES NOT## contribute to the port's interrupt request C66xx_0: GEL Output: IG_BAD_VC => IG_BAD_VC ##DOES NOT## contribute to the port's interrupt request C66xx_0: GEL Output: ******************* TLM Port2 Port-Write Enable Register(TLM_SP2_PW_ENABLE) ******************* C66xx_0: GEL Output: IG_BRR_FILTER => IG_BRR_FILTER ##DOES NOT## contribute to the port's Port_write request C66xx_0: GEL Output: IG_BAD_VC => IG_BAD_VC ##DOES NOT## contribute to the port's Port_write request C66xx_0: GEL Output: ******************* TLM Port Base Routing Register 0 Control Register(TLM_SP2_BRR_0_CTL) ******************* C66xx_0: GEL Output: PRIVATE => used only by one port (PRIVATE) C66xx_0: GEL Output: ROUTE_MR_TO_LLM => maintenance request/reserved packets with DestID matching BRR are routed to the LLM C66xx_0: GEL Output: ENABLE => BRR's ##NOT USED## for accepting and routing inbound pkts C66xx_0: GEL Output: ******************* TLM Port Base Routing Register 0 Pattern & Match Register(TLM_SP2_BRR_0_PATTERN_MATCH) ******************* C66xx_0: GEL Output: MATCH => 0x00000000 => Indicates which of the 16 bits are compared against the DestID C66xx_0: GEL Output: PATTERN => 0x00000000 => These are the 16 bits which are compared one-to-one with the DestID C66xx_0: GEL Output: ******************* TLM Port Base Routing Register 1 Control Register(TLM_SP2_BRR_1_CTL) ******************* C66xx_0: GEL Output: PRIVATE => used only by one port (PRIVATE) C66xx_0: GEL Output: ROUTE_MR_TO_LLM => maintenance request/reserved packets with DestID matching BRR are routed to the LLM C66xx_0: GEL Output: ENABLE => BRR's ##NOT USED## for accepting and routing inbound pkts C66xx_0: GEL Output: ******************* TLM Port Base Routing Register 1 Pattern & Match Register(TLM_SP2_BRR_1_PATTERN_MATCH) ******************* C66xx_0: GEL Output: MATCH => 0x0000FFFF => Indicates which of the 16 bits are compared against the DestID C66xx_0: GEL Output: PATTERN => 0x00000000 => These are the 16 bits which are compared one-to-one with the DestID C66xx_0: GEL Output: ******************* TLM Port Base Routing Register 2 Control Register(TLM_SP2_BRR_2_CTL) ******************* C66xx_0: GEL Output: PRIVATE => used only by one port (PRIVATE) C66xx_0: GEL Output: ROUTE_MR_TO_LLM => maintenance request/reserved packets with DestID matching BRR are routed to the LLM C66xx_0: GEL Output: ENABLE => BRR's ##NOT USED## for accepting and routing inbound pkts C66xx_0: GEL Output: ******************* TLM Port Base Routing Register 2 Pattern & Match Register(TLM_SP2_BRR_2_PATTERN_MATCH) ******************* C66xx_0: GEL Output: MATCH => 0x0000FFFF => Indicates which of the 16 bits are compared against the DestID C66xx_0: GEL Output: PATTERN => 0x00000000 => These are the 16 bits which are compared one-to-one with the DestID C66xx_0: GEL Output: ******************* TLM Port Base Routing Register 3 Control Register(TLM_SP2_BRR_3_CTL) ******************* C66xx_0: GEL Output: PRIVATE => used only by one port (PRIVATE) C66xx_0: GEL Output: ROUTE_MR_TO_LLM => maintenance request/reserved packets with DestID matching BRR are routed to the LLM C66xx_0: GEL Output: ENABLE => BRR's ##NOT USED## for accepting and routing inbound pkts C66xx_0: GEL Output: ******************* TLM Port Base Routing Register 3 Pattern & Match Register(TLM_SP2_BRR_3_PATTERN_MATCH) ******************* C66xx_0: GEL Output: MATCH => 0x0000FFFF => Indicates which of the 16 bits are compared against the DestID C66xx_0: GEL Output: PATTERN => 0x00000000 => These are the 16 bits which are compared one-to-one with the DestID C66xx_0: GEL Output: ******************* PORT3 TLM CONFIGURATION ******************* C66xx_0: GEL Output: ******************* TLM Port Control Register (TLM_SP3_CONTROL) ******************* C66xx_0: GEL Output: LENGTH => 9 => The no of data nodes to be stored, before the PBMi notifies to schedule a pkt(default value=9) C66xx_0: GEL Output: Promiscuous Mode Settings: C66xx_0: GEL Output: For Maintainence type pkts : C66xx_0: GEL Output: If destID matches base destID => route pkt to LLM C66xx_0: GEL Output: If destID matches BRR => route by BRR C66xx_0: GEL Output: No match of destID => Discard this pkt C66xx_0: GEL Output: For Non-Maintainence type pkts : C66xx_0: GEL Output: If destID matches base destID => route pkt to User-Core C66xx_0: GEL Output: If destID matches BRR => route pkt to User-Core C66xx_0: GEL Output: No match of destID => Discard this pkt C66xx_0: GEL Output: VOQ_SELECT => VOQ within a Port Group is determined by the packet's FLOWID (PRIO,CRF) C66xx_0: GEL Output: PORTGROUP_SELECT => There is only one port group to which TLMi directs non-LLM traffic C66xx_0: GEL Output: ******************* TLM Port Interrupt Enable Register(TLM_SP3_INT_ENABLE) ******************* C66xx_0: GEL Output: IG_BRR_FILTER => IG_BRR_FILTER ##DOES NOT## contribute to the port's interrupt request C66xx_0: GEL Output: IG_BAD_VC => IG_BAD_VC ##DOES NOT## contribute to the port's interrupt request C66xx_0: GEL Output: ******************* TLM Port3 Port-Write Enable Register(TLM_SP3_PW_ENABLE) ******************* C66xx_0: GEL Output: IG_BRR_FILTER => IG_BRR_FILTER ##DOES NOT## contribute to the port's Port_write request C66xx_0: GEL Output: IG_BAD_VC => IG_BAD_VC ##DOES NOT## contribute to the port's Port_write request C66xx_0: GEL Output: ******************* TLM Port Base Routing Register 0 Control Register(TLM_SP3_BRR_0_CTL) ******************* C66xx_0: GEL Output: PRIVATE => used only by one port (PRIVATE) C66xx_0: GEL Output: ROUTE_MR_TO_LLM => maintenance request/reserved packets with DestID matching BRR are routed to the LLM C66xx_0: GEL Output: ENABLE => BRR's ##NOT USED## for accepting and routing inbound pkts C66xx_0: GEL Output: ******************* TLM Port Base Routing Register 0 Pattern & Match Register(TLM_SP3_BRR_0_PATTERN_MATCH) ******************* C66xx_0: GEL Output: MATCH => 0x00000000 => Indicates which of the 16 bits are compared against the DestID C66xx_0: GEL Output: PATTERN => 0x00000000 => These are the 16 bits which are compared one-to-one with the DestID C66xx_0: GEL Output: ******************* TLM Port Base Routing Register 1 Control Register(TLM_SP3_BRR_1_CTL) ******************* C66xx_0: GEL Output: PRIVATE => used only by one port (PRIVATE) C66xx_0: GEL Output: ROUTE_MR_TO_LLM => maintenance request/reserved packets with DestID matching BRR are routed to the LLM C66xx_0: GEL Output: ENABLE => BRR's ##NOT USED## for accepting and routing inbound pkts C66xx_0: GEL Output: ******************* TLM Port Base Routing Register 1 Pattern & Match Register(TLM_SP3_BRR_1_PATTERN_MATCH) ******************* C66xx_0: GEL Output: MATCH => 0x0000FFFF => Indicates which of the 16 bits are compared against the DestID C66xx_0: GEL Output: PATTERN => 0x00000000 => These are the 16 bits which are compared one-to-one with the DestID C66xx_0: GEL Output: ******************* TLM Port Base Routing Register 2 Control Register(TLM_SP3_BRR_2_CTL) ******************* C66xx_0: GEL Output: PRIVATE => used only by one port (PRIVATE) C66xx_0: GEL Output: ROUTE_MR_TO_LLM => maintenance request/reserved packets with DestID matching BRR are routed to the LLM C66xx_0: GEL Output: ENABLE => BRR's ##NOT USED## for accepting and routing inbound pkts C66xx_0: GEL Output: ******************* TLM Port Base Routing Register 2 Pattern & Match Register(TLM_SP3_BRR_2_PATTERN_MATCH) ******************* C66xx_0: GEL Output: MATCH => 0x0000FFFF => Indicates which of the 16 bits are compared against the DestID C66xx_0: GEL Output: PATTERN => 0x00000000 => These are the 16 bits which are compared one-to-one with the DestID C66xx_0: GEL Output: ******************* TLM Port Base Routing Register 3 Control Register(TLM_SP3_BRR_3_CTL) ******************* C66xx_0: GEL Output: PRIVATE => used only by one port (PRIVATE) C66xx_0: GEL Output: ROUTE_MR_TO_LLM => maintenance request/reserved packets with DestID matching BRR are routed to the LLM C66xx_0: GEL Output: ENABLE => BRR's ##NOT USED## for accepting and routing inbound pkts C66xx_0: GEL Output: ******************* TLM Port Base Routing Register 3 Pattern & Match Register(TLM_SP3_BRR_3_PATTERN_MATCH) ******************* C66xx_0: GEL Output: MATCH => 0x0000FFFF => Indicates which of the 16 bits are compared against the DestID C66xx_0: GEL Output: PATTERN => 0x00000000 => These are the 16 bits which are compared one-to-one with the DestID C66xx_0: GEL Output: ******************************************************************************************************* C66xx_0: GEL Output: ********************************** PORT TLM STATUS ****************************************************** C66xx_0: GEL Output: ******************************************************************************************************* C66xx_0: GEL Output: ******************* PORT0 TLM STATUS ******************* C66xx_0: GEL Output: ******************* TLM Port Status Register (TLM_SP0_STATUS) ******************* C66xx_0: GEL Output: IG_BRR_FILTER => Port0 has ##NOT DISCARDED## an inbound transaction based on BRR programming C66xx_0: GEL Output: IG_BAD_VC => Port0 has ##NOT DETECTED## an inbound packet with VC bit set C66xx_0: GEL Output: ******************* PORT1 TLM STATUS ******************* C66xx_0: GEL Output: ******************* TLM Port Status Register (TLM_SP1_STATUS) ******************* C66xx_0: GEL Output: IG_BRR_FILTER => Port1 has ##NOT DISCARDED## an inbound transaction based on BRR programming C66xx_0: GEL Output: IG_BAD_VC => Port1 has ##NOT DETECTED## an inbound packet with VC bit set C66xx_0: GEL Output: ******************* PORT2 TLM STATUS ******************* C66xx_0: GEL Output: ******************* TLM Port Status Register (TLM_SP2_STATUS) ******************* C66xx_0: GEL Output: IG_BRR_FILTER => Port2 has ##NOT DISCARDED## an inbound transaction based on BRR programming C66xx_0: GEL Output: IG_BAD_VC => Port2 has ##NOT DETECTED## an inbound packet with VC bit set C66xx_0: GEL Output: ******************* PORT3 TLM STATUS ******************* C66xx_0: GEL Output: ******************* TLM Port Status Register (TLM_SP3_STATUS) ******************* C66xx_0: GEL Output: IG_BRR_FILTER => Port3 has ##NOT DISCARDED## an inbound transaction based on BRR programming C66xx_0: GEL Output: IG_BAD_VC => Port3 has ##NOT DETECTED## an inbound packet with VC bit set C66xx_0: GEL Output: ******************************************************************************************************* C66xx_0: GEL Output: ********************************** PORT PBM CONFIGURATION ****************************************************** C66xx_0: GEL Output: ******************************************************************************************************* C66xx_0: GEL Output: ******************* PORT0 PBM CONFIGURATION ******************* C66xx_0: GEL Output: ******************* PBM Port Control Register (PBM_SP0_CONTROL) ******************* C66xx_0: GEL Output: EG_REORDER_STICK => The CRQ is reordered after each reorder event for 1 repeat times C66xx_0: GEL Output: EG_REORDER_MODE => Reorder on reorder trigger, bring the oldest higher preference flowID to front of CRQ C66xx_0: GEL Output: ******************* PBM Port Interrupt Enable Register(PBM_SP0_INT_ENABLE) ******************* C66xx_0: GEL Output: EG_BABBLE_PACKET => Babble pkt event ##DOESNT CONTRIBUTE## to the port interrupt request C66xx_0: GEL Output: EG_BAD_CHANNEL => Bad channel event ##DOESNT CONTRIBUTE## to the port interrupt request C66xx_0: GEL Output: EG_CRQ_OVERFLOW => CRQ overflow event ##DOESNT CONTRIBUTE## to the port interrupt request C66xx_0: GEL Output: EG_DATA_OVERFLOW => Data overflow event ##DOESNT CONTRIBUTE## to the port interrupt request C66xx_0: GEL Output: ******************* PBM Port0 Port-Write Enable Register (PBM_SP0_Port-Write_ENABLE) ******************* C66xx_0: GEL Output: EG_BABBLE_PACKET => Babble pkt event ##DOESNT CONTRIBUTE## to the port Port-Write request C66xx_0: GEL Output: EG_BAD_CHANNEL => Bad channel event ##DOESNT CONTRIBUTE## to the port Port-Write request C66xx_0: GEL Output: EG_CRQ_OVERFLOW => CRQ overflow event ##DOESNT CONTRIBUTE## to the port Port-Write request C66xx_0: GEL Output: EG_DATA_OVERFLOW => Data overflow event ##DOESNT CONTRIBUTE## to the port Port-Write request C66xx_0: GEL Output: ******************* PBM Port Event Generate Register (PBM_SP0_EVENT_GEN) ******************* C66xx_0: GEL Output: EG_BABBLE_PACKET => Babble pkt event generation ##DISABLED## C66xx_0: GEL Output: EG_BAD_CHANNEL => Bad channel event generation ##DISABLED## C66xx_0: GEL Output: EG_CRQ_OVERFLOW => CRQ overflow event generation ##DISABLED## C66xx_0: GEL Output: EG_DATA_OVERFLOW => Data overflow event generation ##DISABLED## C66xx_0: GEL Output: ******************* PBM Port Ingress Resources Register(PBM_SP0_IG_RESOURCES) ******************* C66xx_0: GEL Output: TAGS => Number of Tags implemented in the PBMi for packet storage for this port is 288 C66xx_0: GEL Output: DATANODES => Number of Data-nodes implemented in the PBMi for packet storage for this port is 288 C66xx_0: GEL Output: ******************* PBM Port Egress Resources Register (PBM_SP0_EG_RESOURCES) ******************* C66xx_0: GEL Output: CRQ_ENTRIES => Number of CRQ entries implemented in the PBMe for packet storage for this port is 33 C66xx_0: GEL Output: DATANODES => Number of Data-nodes implemented in the PBMe for packet storage for this port is 292 C66xx_0: GEL Output: ******************* PBM Port Ingress Watermarks 0 Register(PBM_SP0_IG_WATERMARK0) ******************* C66xx_0: GEL Output: PRIO0_WM => Prio 0 packets are accepted if the number of free Data Nodes is > 72 C66xx_0: GEL Output: PRIO0CRF_WM => Prio 0+CRF packets are accepted if the number of free Data Nodes is > 63 C66xx_0: GEL Output: ******************* PBM Port Ingress Watermarks 1 Register(PBM_SP0_IG_WATERMARK1) ******************* C66xx_0: GEL Output: PRIO1_WM => Prio 1 packets are accepted if the number of free Data Nodes is > 54 C66xx_0: GEL Output: PRIO1CRF_WM => Prio 1+CRF packets are accepted if the number of free Data Nodes is > 63 C66xx_0: GEL Output: ******************* PBM Port Ingress Watermarks 2 Register(PBM_SP0_IG_WATERMARK2) ******************* C66xx_0: GEL Output: PRIO2_WM => Prio 2 packets are accepted if the number of free Data Nodes is > 36 C66xx_0: GEL Output: PRIO2CRF_WM => Prio 2+CRF packets are accepted if the number of free Data Nodes is > 27 C66xx_0: GEL Output: ******************* PBM Port Ingress Watermarks 3 Register(PBM_SP0_IG_WATERMARK3) ******************* C66xx_0: GEL Output: PRIO3_WM => Prio 3 packets are accepted if the number of free Data Nodes is > 18 C66xx_0: GEL Output: PRIO3CRF_WM => Prio 3+CRF packets are accepted if the number of free Data Nodes is > 9 C66xx_0: GEL Output: ******************* PORT1 PBM CONFIGURATION ******************* C66xx_0: GEL Output: ******************* PBM Port Control Register (PBM_SP1_CONTROL) ******************* C66xx_0: GEL Output: EG_REORDER_STICK => The CRQ is reordered after each reorder event for 1 repeat times C66xx_0: GEL Output: EG_REORDER_MODE => Reorder on reorder trigger, bring the oldest higher preference flowID to front of CRQ C66xx_0: GEL Output: ******************* PBM Port Interrupt Enable Register(PBM_SP1_INT_ENABLE) ******************* C66xx_0: GEL Output: EG_BABBLE_PACKET => Babble pkt event ##DOESNT CONTRIBUTE## to the port interrupt request C66xx_0: GEL Output: EG_BAD_CHANNEL => Bad channel event ##DOESNT CONTRIBUTE## to the port interrupt request C66xx_0: GEL Output: EG_CRQ_OVERFLOW => CRQ overflow event ##DOESNT CONTRIBUTE## to the port interrupt request C66xx_0: GEL Output: EG_DATA_OVERFLOW => Data overflow event ##DOESNT CONTRIBUTE## to the port interrupt request C66xx_0: GEL Output: ******************* PBM Port1 Port-Write Enable Register (PBM_SP1_Port-Write_ENABLE) ******************* C66xx_0: GEL Output: EG_BABBLE_PACKET => Babble pkt event ##DOESNT CONTRIBUTE## to the port Port-Write request C66xx_0: GEL Output: EG_BAD_CHANNEL => Bad channel event ##DOESNT CONTRIBUTE## to the port Port-Write request C66xx_0: GEL Output: EG_CRQ_OVERFLOW => CRQ overflow event ##DOESNT CONTRIBUTE## to the port Port-Write request C66xx_0: GEL Output: EG_DATA_OVERFLOW => Data overflow event ##DOESNT CONTRIBUTE## to the port Port-Write request C66xx_0: GEL Output: ******************* PBM Port Event Generate Register (PBM_SP1_EVENT_GEN) ******************* C66xx_0: GEL Output: EG_BABBLE_PACKET => Babble pkt event generation ##DISABLED## C66xx_0: GEL Output: EG_BAD_CHANNEL => Bad channel event generation ##DISABLED## C66xx_0: GEL Output: EG_CRQ_OVERFLOW => CRQ overflow event generation ##DISABLED## C66xx_0: GEL Output: EG_DATA_OVERFLOW => Data overflow event generation ##DISABLED## C66xx_0: GEL Output: ******************* PBM Port Ingress Resources Register(PBM_SP1_IG_RESOURCES) ******************* C66xx_0: GEL Output: TAGS => Number of Tags implemented in the PBMi for packet storage for this port is 0 C66xx_0: GEL Output: DATANODES => Number of Data-nodes implemented in the PBMi for packet storage for this port is 0 C66xx_0: GEL Output: ******************* PBM Port Egress Resources Register (PBM_SP1_EG_RESOURCES) ******************* C66xx_0: GEL Output: CRQ_ENTRIES => Number of CRQ entries implemented in the PBMe for packet storage for this port is 9 C66xx_0: GEL Output: DATANODES => Number of Data-nodes implemented in the PBMe for packet storage for this port is 0 C66xx_0: GEL Output: ******************* PBM Port Ingress Watermarks 0 Register(PBM_SP1_IG_WATERMARK0) ******************* C66xx_0: GEL Output: PRIO0_WM => Prio 0 packets are accepted if the number of free Data Nodes is > 72 C66xx_0: GEL Output: PRIO0CRF_WM => Prio 0+CRF packets are accepted if the number of free Data Nodes is > 63 C66xx_0: GEL Output: ******************* PBM Port Ingress Watermarks 1 Register(PBM_SP1_IG_WATERMARK1) ******************* C66xx_0: GEL Output: PRIO1_WM => Prio 1 packets are accepted if the number of free Data Nodes is > 54 C66xx_0: GEL Output: PRIO1CRF_WM => Prio 1+CRF packets are accepted if the number of free Data Nodes is > 63 C66xx_0: GEL Output: ******************* PBM Port Ingress Watermarks 2 Register(PBM_SP1_IG_WATERMARK2) ******************* C66xx_0: GEL Output: PRIO2_WM => Prio 2 packets are accepted if the number of free Data Nodes is > 36 C66xx_0: GEL Output: PRIO2CRF_WM => Prio 2+CRF packets are accepted if the number of free Data Nodes is > 27 C66xx_0: GEL Output: ******************* PBM Port Ingress Watermarks 3 Register(PBM_SP1_IG_WATERMARK3) ******************* C66xx_0: GEL Output: PRIO3_WM => Prio 3 packets are accepted if the number of free Data Nodes is > 18 C66xx_0: GEL Output: PRIO3CRF_WM => Prio 3+CRF packets are accepted if the number of free Data Nodes is > 9 C66xx_0: GEL Output: ******************* PORT2 PBM CONFIGURATION ******************* C66xx_0: GEL Output: ******************* PBM Port Control Register (PBM_SP2_CONTROL) ******************* C66xx_0: GEL Output: EG_REORDER_STICK => The CRQ is reordered after each reorder event for 1 repeat times C66xx_0: GEL Output: EG_REORDER_MODE => Reorder on reorder trigger, bring the oldest higher preference flowID to front of CRQ C66xx_0: GEL Output: ******************* PBM Port Interrupt Enable Register(PBM_SP2_INT_ENABLE) ******************* C66xx_0: GEL Output: EG_BABBLE_PACKET => Babble pkt event ##DOESNT CONTRIBUTE## to the port interrupt request C66xx_0: GEL Output: EG_BAD_CHANNEL => Bad channel event ##DOESNT CONTRIBUTE## to the port interrupt request C66xx_0: GEL Output: EG_CRQ_OVERFLOW => CRQ overflow event ##DOESNT CONTRIBUTE## to the port interrupt request C66xx_0: GEL Output: EG_DATA_OVERFLOW => Data overflow event ##DOESNT CONTRIBUTE## to the port interrupt request C66xx_0: GEL Output: ******************* PBM Port2 Port-Write Enable Register (PBM_SP2_Port-Write_ENABLE) ******************* C66xx_0: GEL Output: EG_BABBLE_PACKET => Babble pkt event ##DOESNT CONTRIBUTE## to the port Port-Write request C66xx_0: GEL Output: EG_BAD_CHANNEL => Bad channel event ##DOESNT CONTRIBUTE## to the port Port-Write request C66xx_0: GEL Output: EG_CRQ_OVERFLOW => CRQ overflow event ##DOESNT CONTRIBUTE## to the port Port-Write request C66xx_0: GEL Output: EG_DATA_OVERFLOW => Data overflow event ##DOESNT CONTRIBUTE## to the port Port-Write request C66xx_0: GEL Output: ******************* PBM Port Event Generate Register (PBM_SP2_EVENT_GEN) ******************* C66xx_0: GEL Output: EG_BABBLE_PACKET => Babble pkt event generation ##DISABLED## C66xx_0: GEL Output: EG_BAD_CHANNEL => Bad channel event generation ##DISABLED## C66xx_0: GEL Output: EG_CRQ_OVERFLOW => CRQ overflow event generation ##DISABLED## C66xx_0: GEL Output: EG_DATA_OVERFLOW => Data overflow event generation ##DISABLED## C66xx_0: GEL Output: ******************* PBM Port Ingress Resources Register(PBM_SP2_IG_RESOURCES) ******************* C66xx_0: GEL Output: TAGS => Number of Tags implemented in the PBMi for packet storage for this port is 0 C66xx_0: GEL Output: DATANODES => Number of Data-nodes implemented in the PBMi for packet storage for this port is 0 C66xx_0: GEL Output: ******************* PBM Port Egress Resources Register (PBM_SP2_EG_RESOURCES) ******************* C66xx_0: GEL Output: CRQ_ENTRIES => Number of CRQ entries implemented in the PBMe for packet storage for this port is 17 C66xx_0: GEL Output: DATANODES => Number of Data-nodes implemented in the PBMe for packet storage for this port is 0 C66xx_0: GEL Output: ******************* PBM Port Ingress Watermarks 0 Register(PBM_SP2_IG_WATERMARK0) ******************* C66xx_0: GEL Output: PRIO0_WM => Prio 0 packets are accepted if the number of free Data Nodes is > 72 C66xx_0: GEL Output: PRIO0CRF_WM => Prio 0+CRF packets are accepted if the number of free Data Nodes is > 63 C66xx_0: GEL Output: ******************* PBM Port Ingress Watermarks 1 Register(PBM_SP2_IG_WATERMARK1) ******************* C66xx_0: GEL Output: PRIO1_WM => Prio 1 packets are accepted if the number of free Data Nodes is > 54 C66xx_0: GEL Output: PRIO1CRF_WM => Prio 1+CRF packets are accepted if the number of free Data Nodes is > 63 C66xx_0: GEL Output: ******************* PBM Port Ingress Watermarks 2 Register(PBM_SP2_IG_WATERMARK2) ******************* C66xx_0: GEL Output: PRIO2_WM => Prio 2 packets are accepted if the number of free Data Nodes is > 36 C66xx_0: GEL Output: PRIO2CRF_WM => Prio 2+CRF packets are accepted if the number of free Data Nodes is > 27 C66xx_0: GEL Output: ******************* PBM Port Ingress Watermarks 3 Register(PBM_SP2_IG_WATERMARK3) ******************* C66xx_0: GEL Output: PRIO3_WM => Prio 3 packets are accepted if the number of free Data Nodes is > 18 C66xx_0: GEL Output: PRIO3CRF_WM => Prio 3+CRF packets are accepted if the number of free Data Nodes is > 9 C66xx_0: GEL Output: ******************* PORT3 PBM CONFIGURATION ******************* C66xx_0: GEL Output: ******************* PBM Port Control Register (PBM_SP3_CONTROL) ******************* C66xx_0: GEL Output: EG_REORDER_STICK => The CRQ is reordered after each reorder event for 1 repeat times C66xx_0: GEL Output: EG_REORDER_MODE => Reorder on reorder trigger, bring the oldest higher preference flowID to front of CRQ C66xx_0: GEL Output: ******************* PBM Port Interrupt Enable Register(PBM_SP3_INT_ENABLE) ******************* C66xx_0: GEL Output: EG_BABBLE_PACKET => Babble pkt event ##DOESNT CONTRIBUTE## to the port interrupt request C66xx_0: GEL Output: EG_BAD_CHANNEL => Bad channel event ##DOESNT CONTRIBUTE## to the port interrupt request C66xx_0: GEL Output: EG_CRQ_OVERFLOW => CRQ overflow event ##DOESNT CONTRIBUTE## to the port interrupt request C66xx_0: GEL Output: EG_DATA_OVERFLOW => Data overflow event ##DOESNT CONTRIBUTE## to the port interrupt request C66xx_0: GEL Output: ******************* PBM Port3 Port-Write Enable Register (PBM_SP3_Port-Write_ENABLE) ******************* C66xx_0: GEL Output: EG_BABBLE_PACKET => Babble pkt event ##DOESNT CONTRIBUTE## to the port Port-Write request C66xx_0: GEL Output: EG_BAD_CHANNEL => Bad channel event ##DOESNT CONTRIBUTE## to the port Port-Write request C66xx_0: GEL Output: EG_CRQ_OVERFLOW => CRQ overflow event ##DOESNT CONTRIBUTE## to the port Port-Write request C66xx_0: GEL Output: EG_DATA_OVERFLOW => Data overflow event ##DOESNT CONTRIBUTE## to the port Port-Write request C66xx_0: GEL Output: ******************* PBM Port Event Generate Register (PBM_SP3_EVENT_GEN) ******************* C66xx_0: GEL Output: EG_BABBLE_PACKET => Babble pkt event generation ##DISABLED## C66xx_0: GEL Output: EG_BAD_CHANNEL => Bad channel event generation ##DISABLED## C66xx_0: GEL Output: EG_CRQ_OVERFLOW => CRQ overflow event generation ##DISABLED## C66xx_0: GEL Output: EG_DATA_OVERFLOW => Data overflow event generation ##DISABLED## C66xx_0: GEL Output: ******************* PBM Port Ingress Resources Register(PBM_SP3_IG_RESOURCES) ******************* C66xx_0: GEL Output: TAGS => Number of Tags implemented in the PBMi for packet storage for this port is 0 C66xx_0: GEL Output: DATANODES => Number of Data-nodes implemented in the PBMi for packet storage for this port is 0 C66xx_0: GEL Output: ******************* PBM Port Egress Resources Register (PBM_SP3_EG_RESOURCES) ******************* C66xx_0: GEL Output: CRQ_ENTRIES => Number of CRQ entries implemented in the PBMe for packet storage for this port is 9 C66xx_0: GEL Output: DATANODES => Number of Data-nodes implemented in the PBMe for packet storage for this port is 0 C66xx_0: GEL Output: ******************* PBM Port Ingress Watermarks 0 Register(PBM_SP3_IG_WATERMARK0) ******************* C66xx_0: GEL Output: PRIO0_WM => Prio 0 packets are accepted if the number of free Data Nodes is > 72 C66xx_0: GEL Output: PRIO0CRF_WM => Prio 0+CRF packets are accepted if the number of free Data Nodes is > 63 C66xx_0: GEL Output: ******************* PBM Port Ingress Watermarks 1 Register(PBM_SP3_IG_WATERMARK1) ******************* C66xx_0: GEL Output: PRIO1_WM => Prio 1 packets are accepted if the number of free Data Nodes is > 54 C66xx_0: GEL Output: PRIO1CRF_WM => Prio 1+CRF packets are accepted if the number of free Data Nodes is > 63 C66xx_0: GEL Output: ******************* PBM Port Ingress Watermarks 2 Register(PBM_SP3_IG_WATERMARK2) ******************* C66xx_0: GEL Output: PRIO2_WM => Prio 2 packets are accepted if the number of free Data Nodes is > 36 C66xx_0: GEL Output: PRIO2CRF_WM => Prio 2+CRF packets are accepted if the number of free Data Nodes is > 27 C66xx_0: GEL Output: ******************* PBM Port Ingress Watermarks 3 Register(PBM_SP3_IG_WATERMARK3) ******************* C66xx_0: GEL Output: PRIO3_WM => Prio 3 packets are accepted if the number of free Data Nodes is > 18 C66xx_0: GEL Output: PRIO3CRF_WM => Prio 3+CRF packets are accepted if the number of free Data Nodes is > 9 C66xx_0: GEL Output: ******************************************************************************************************* C66xx_0: GEL Output: ********************************** PORT PBM STATUS ****************************************************** C66xx_0: GEL Output: ******************************************************************************************************* C66xx_0: GEL Output: ******************* PORT0 PBM STATUS ******************* C66xx_0: GEL Output: ******************* PBM Port Status Register (PBM_SP0_STATUS) ******************* C66xx_0: GEL Output: EG_BABBLE_PACKET => Babble pkt event is ##NOT DETECTED## C66xx_0: GEL Output: EG_BAD_CHANNEL => Bad channel event is ##NOT DETECTED## C66xx_0: GEL Output: EG_CRQ_OVERFLOW => CRQ overflow event is ##NOT DETECTED## C66xx_0: GEL Output: EG_DATA_OVERFLOW => Data overflow event is ##NOT DETECTED## C66xx_0: GEL Output: EG_EMPTY => The PBMe **HAS NO** pkts enqueued C66xx_0: GEL Output: IG_EMPTY => The PBMi **HAS NO** pkts enqueued C66xx_0: GEL Output: ******************* PORT1 PBM STATUS ******************* C66xx_0: GEL Output: ******************* PBM Port Status Register (PBM_SP1_STATUS) ******************* C66xx_0: GEL Output: EG_BABBLE_PACKET => Babble pkt event is ##NOT DETECTED## C66xx_0: GEL Output: EG_BAD_CHANNEL => Bad channel event is ##NOT DETECTED## C66xx_0: GEL Output: EG_CRQ_OVERFLOW => CRQ overflow event is ##NOT DETECTED## C66xx_0: GEL Output: EG_DATA_OVERFLOW => Data overflow event is ##NOT DETECTED## C66xx_0: GEL Output: EG_EMPTY => The PBMe **HAS NO** pkts enqueued C66xx_0: GEL Output: IG_EMPTY => The PBMi **HAS NO** pkts enqueued C66xx_0: GEL Output: ******************* PORT2 PBM STATUS ******************* C66xx_0: GEL Output: ******************* PBM Port Status Register (PBM_SP2_STATUS) ******************* C66xx_0: GEL Output: EG_BABBLE_PACKET => Babble pkt event is ##NOT DETECTED## C66xx_0: GEL Output: EG_BAD_CHANNEL => Bad channel event is ##NOT DETECTED## C66xx_0: GEL Output: EG_CRQ_OVERFLOW => CRQ overflow event is ##NOT DETECTED## C66xx_0: GEL Output: EG_DATA_OVERFLOW => Data overflow event is ##NOT DETECTED## C66xx_0: GEL Output: EG_EMPTY => The PBMe **HAS NO** pkts enqueued C66xx_0: GEL Output: IG_EMPTY => The PBMi **HAS NO** pkts enqueued C66xx_0: GEL Output: ******************* PORT3 PBM STATUS ******************* C66xx_0: GEL Output: ******************* PBM Port Status Register (PBM_SP3_STATUS) ******************* C66xx_0: GEL Output: EG_BABBLE_PACKET => Babble pkt event is ##NOT DETECTED## C66xx_0: GEL Output: EG_BAD_CHANNEL => Bad channel event is ##NOT DETECTED## C66xx_0: GEL Output: EG_CRQ_OVERFLOW => CRQ overflow event is ##NOT DETECTED## C66xx_0: GEL Output: EG_DATA_OVERFLOW => Data overflow event is ##NOT DETECTED## C66xx_0: GEL Output: EG_EMPTY => The PBMe **HAS NO** pkts enqueued C66xx_0: GEL Output: IG_EMPTY => The PBMi **HAS NO** pkts enqueued C66xx_0: GEL Output: ******************************************************************************************************* C66xx_0: GEL Output: ********************************** EVENT MGT CONFIGURATION ****************************************************** C66xx_0: GEL Output: ******************************************************************************************************* C66xx_0: GEL Output: ******************* Event Management Interrupts Enable Register(EM_INT_ENABLE) ******************* C66xx_0: GEL Output: LOCALOG => ##DISABLES## a logical layer event detected in the User Core to cause an interrupt. C66xx_0: GEL Output: PW_RX => ##DISABLES## the reception of a Port-Write to cause an interrupt C66xx_0: GEL Output: MECS => ##ENABLES## an interrupt to be raised upon reception of an MECS C66xx_0: GEL Output: LOG => ##DISABLES## a logical layer event detected in the User Core to cause an interrupt C66xx_0: GEL Output: ******************* Event Management Device Interrupt Enable Register(EM_DEV_INT_EN) ******************* C66xx_0: GEL Output: INT_EN => Interrupt line is ##DEASSERTED## C66xx_0: GEL Output: ******************* Event Management Port-Write Enable Register(EM_PW_ENABLE) ******************* C66xx_0: GEL Output: LOCALOG => ##DISABLES## an implementation-specific Logical/Transport Layer Error to cause a Port-Write to be sent C66xx_0: GEL Output: LOG => **ENABLES** a logical layer event to cause a Port-Write to be sent C66xx_0: GEL Output: ******************* Event Management Device Port-Write Enable Register(EM_DEV_PW_EN) ******************* C66xx_0: GEL Output: PW_EN => Port-Writes are ##NOT SENT## C66xx_0: GEL Output: ******************* Event Management MECS Interrupt Enable Register(EM_MECS_INT_EN) ******************* C66xx_0: GEL Output: MECS received with cmd=0 **RAISE** an interrupt request C66xx_0: GEL Output: MECS received with cmd=1 **DOESNT RAISE** an interrupt request C66xx_0: GEL Output: MECS received with cmd=2 **DOESNT RAISE** an interrupt request C66xx_0: GEL Output: MECS received with cmd=3 **DOESNT RAISE** an interrupt request C66xx_0: GEL Output: MECS received with cmd=4 **DOESNT RAISE** an interrupt request C66xx_0: GEL Output: MECS received with cmd=5 **DOESNT RAISE** an interrupt request C66xx_0: GEL Output: MECS received with cmd=6 **DOESNT RAISE** an interrupt request C66xx_0: GEL Output: MECS received with cmd=7 **DOESNT RAISE** an interrupt request C66xx_0: GEL Output: ******************* Event Management MECS Capture Out Register(EM_MECS_CAP_EN) ******************* C66xx_0: GEL Output: MECS with cmd=0 ##DOESNT TOGGLE## mecs_captured_out[0] C66xx_0: GEL Output: MECS with cmd=1 ##DOESNT TOGGLE## mecs_captured_out[1] C66xx_0: GEL Output: MECS with cmd=2 ##DOESNT TOGGLE## mecs_captured_out[2] C66xx_0: GEL Output: MECS with cmd=3 ##DOESNT TOGGLE## mecs_captured_out[3] C66xx_0: GEL Output: MECS with cmd=4 ##DOESNT TOGGLE## mecs_captured_out[4] C66xx_0: GEL Output: MECS with cmd=5 ##DOESNT TOGGLE## mecs_captured_out[5] C66xx_0: GEL Output: MECS with cmd=6 ##DOESNT TOGGLE## mecs_captured_out[6] C66xx_0: GEL Output: MECS with cmd=7 ##DOESNT TOGGLE## mecs_captured_out[7] C66xx_0: GEL Output: ******************* Event Management MECS Trigger In Register(EM_MECS_TRIG_EN) ******************* C66xx_0: GEL Output: mecs_trigger_in[0] is ##DISABLED## to trigger a MECS request with cmd=0 to all RapidIO ports C66xx_0: GEL Output: mecs_trigger_in[1] is ##DISABLED## to trigger a MECS request with cmd=1 to all RapidIO ports C66xx_0: GEL Output: mecs_trigger_in[2] is ##DISABLED## to trigger a MECS request with cmd=2 to all RapidIO ports C66xx_0: GEL Output: mecs_trigger_in[3] is ##DISABLED## to trigger a MECS request with cmd=3 to all RapidIO ports C66xx_0: GEL Output: mecs_trigger_in[4] is ##DISABLED## to trigger a MECS request with cmd=4 to all RapidIO ports C66xx_0: GEL Output: mecs_trigger_in[5] is ##DISABLED## to trigger a MECS request with cmd=5 to all RapidIO ports C66xx_0: GEL Output: mecs_trigger_in[6] is ##DISABLED## to trigger a MECS request with cmd=6 to all RapidIO ports C66xx_0: GEL Output: mecs_trigger_in[7] is ##DISABLED## to trigger a MECS request with cmd=7 to all RapidIO ports C66xx_0: GEL Output: Edge ##NOT DETECTED## on mecs_trigger_in[0] C66xx_0: GEL Output: Edge ##NOT DETECTED## on mecs_trigger_in[1] C66xx_0: GEL Output: Edge ##NOT DETECTED## on mecs_trigger_in[2] C66xx_0: GEL Output: Edge ##NOT DETECTED## on mecs_trigger_in[3] C66xx_0: GEL Output: Edge ##NOT DETECTED## on mecs_trigger_in[4] C66xx_0: GEL Output: Edge ##NOT DETECTED## on mecs_trigger_in[5] C66xx_0: GEL Output: Edge ##NOT DETECTED## on mecs_trigger_in[6] C66xx_0: GEL Output: Edge ##NOT DETECTED## on mecs_trigger_in[7] C66xx_0: GEL Output: ******************* Event Management Reset Request Interrupt Enable Register(EM_RST_INT_EN) ******************* C66xx_0: GEL Output: ##DEASSERT## interrupt for reset requests received on port #0 C66xx_0: GEL Output: ##DEASSERT## interrupt for reset requests received on port #1 C66xx_0: GEL Output: ##DEASSERT## interrupt for reset requests received on port #2 C66xx_0: GEL Output: ##DEASSERT## interrupt for reset requests received on port #3 C66xx_0: GEL Output: ******************* Event Management Reset Request Port-Write Enable Register(EM_RST_PW_EN) ******************* C66xx_0: GEL Output: ##DO NOT SEND## Port-Write for reset requests received on port #0 C66xx_0: GEL Output: ##DO NOT SEND## Port-Write for reset requests received on port #1 C66xx_0: GEL Output: ##DO NOT SEND## Port-Write for reset requests received on port #2 C66xx_0: GEL Output: ##DO NOT SEND## Port-Write for reset requests received on port #3 C66xx_0: GEL Output: ******************************************************************************************************* C66xx_0: GEL Output: ********************************** EVENT MGT STATUS ****************************************************** C66xx_0: GEL Output: ******************************************************************************************************* C66xx_0: GEL Output: ******************* Event Management Interrupt Status Register (EM_INT_STAT) ******************* C66xx_0: GEL Output: LOCALOG => one or more of the enabled errors in ERR_DET CSR is ##NOT SET## C66xx_0: GEL Output: PW_RX => A Port-Write ##HAS NOT## been received C66xx_0: GEL Output: MECS => A MECS with an enabled CMD field is ##NOT RECEIVED## by one of the RIO ports C66xx_0: GEL Output: RCS => A reset request ##HAS NOT## been detected by a port. C66xx_0: GEL Output: LOG => An enabled Log/Trans error has ##NOT BEEN DETECTED## and reported by User Core LOGERR Signals C66xx_0: GEL Output: PORT => A port-specific event ##HAS NOT BEEN## detected. C66xx_0: GEL Output: ******************* Event Management Interrupt Port Status Register(EM_INT_PORT_STAT) ******************* C66xx_0: GEL Output: IRQ_PENDING[31] => Interrupt ##NOT PENDING## for port #0 C66xx_0: GEL Output: IRQ_PENDING[30] => Interrupt ##NOT PENDING## for port #1 C66xx_0: GEL Output: IRQ_PENDING[29] => Interrupt ##NOT PENDING## for port #2 C66xx_0: GEL Output: IRQ_PENDING[28] => Interrupt ##NOT PENDING## for port #3 C66xx_0: GEL Output: ******************* Event Management Port-Write Status Register (EM_PW_STAT) ******************* C66xx_0: GEL Output: LOCALOG => one or more of the enabled errors in ERR_DET CSR is ##NOT SET## (Port_write is not sent) C66xx_0: GEL Output: MULTIPORT_ERR => Multiple ports ##HAVE NOT DETECTED## errors which use port-write notification (Port_write is not sent) C66xx_0: GEL Output: RCS => A reset request ##HAS NOT## been detected by a port. (Port_write is not sent) C66xx_0: GEL Output: LOG => An enabled Log/Trans error has ##NOT BEEN DETECTED## and reported by User Core LOGERR Signals (Port_write is not sent) C66xx_0: GEL Output: PORT => A port-specific event ##HAS NOT BEEN## detected. (Port_write is not sent) C66xx_0: GEL Output: ******************* Event Management Port-Write Port Status Register (EM_PW_PORT_STAT) ******************* C66xx_0: GEL Output: PW_PENDING[31] => Port-Write ##NOT PENDING## for port #0 C66xx_0: GEL Output: PW_PENDING[30] => Port-Write ##NOT PENDING## for port #1 C66xx_0: GEL Output: PW_PENDING[29] => Port-Write ##NOT PENDING## for port #2 C66xx_0: GEL Output: PW_PENDING[28] => Port-Write ##NOT PENDING## for port #3 C66xx_0: GEL Output: ******************* Event Management MECS Status Register (EM_MECS_STAT) ******************* C66xx_0: GEL Output: MECS **RECEIVED** with cmd=0 by any of the RIO ports C66xx_0: GEL Output: MECS **RECEIVED** with cmd=1 by any of the RIO ports C66xx_0: GEL Output: MECS **RECEIVED** with cmd=2 by any of the RIO ports C66xx_0: GEL Output: MECS **RECEIVED** with cmd=3 by any of the RIO ports C66xx_0: GEL Output: MECS **RECEIVED** with cmd=4 by any of the RIO ports C66xx_0: GEL Output: MECS **RECEIVED** with cmd=5 by any of the RIO ports C66xx_0: GEL Output: MECS **RECEIVED** with cmd=6 by any of the RIO ports C66xx_0: GEL Output: MECS **RECEIVED** with cmd=7 by any of the RIO ports C66xx_0: GEL Output: ******************* Event Management MECS Port Status Register(EM_MECS_PORT_STAT) ******************* C66xx_0: GEL Output: PORT[31] => MECS ##NOT RECEIVED## by port #0 C66xx_0: GEL Output: PORT[30] => MECS ##NOT RECEIVED## by port #1 C66xx_0: GEL Output: PORT[29] => MECS ##NOT RECEIVED## by port #2 C66xx_0: GEL Output: PORT[28] => MECS ##NOT RECEIVED## by port #3 C66xx_0: GEL Output: ******************* Event Management Reset Request Port Status Register(EM_RST_PORT_STAT) ******************* C66xx_0: GEL Output: RST_REQ[31] => Reset Request ##NOT RECEIVED## by port #0 C66xx_0: GEL Output: RST_REQ[30] => Reset Request ##NOT RECEIVED## by port #1 C66xx_0: GEL Output: RST_REQ[29] => Reset Request ##NOT RECEIVED## by port #2 C66xx_0: GEL Output: RST_REQ[28] => Reset Request ##NOT RECEIVED## by port #3 C66xx_0: GEL Output: ******************************************************************************************************* C66xx_0: GEL Output: ********************************** PORT-WRITE CONFIGURATION ****************************************************** C66xx_0: GEL Output: ******************************************************************************************************* C66xx_0: GEL Output: ******************* Port-Write Control Register (PW_CTL) ******************* C66xx_0: GEL Output: PWC_MODE => Continuous Port-Write capture mode C66xx_0: GEL Output: PW_TIMER => Disabled. Port-Write is sent once only C66xx_0: GEL Output: ******************* Port-Write Routing Register (PW_ROUTE) ******************* C66xx_0: GEL Output: Set to send Port-Writes to port0 (default) C66xx_0: GEL Output: ******************* Port-Write Reception Event Generate Register (PW_RX_EVENT_GEN) ******************* C66xx_0: GEL Output: PW_VAL => An Event is **NOT GENERATED** when valid Port-Write data is received C66xx_0: GEL Output: PW_DISC => An Event is **NOT GENERATED** when a Port-Write is discarded C66xx_0: GEL Output: ******************************************************************************************************* C66xx_0: GEL Output: ********************************** PORT-WRITE STATUS ****************************************************** C66xx_0: GEL Output: ******************************************************************************************************* C66xx_0: GEL Output: ******************* Port-Write Reception Status CSR (PW_RX_STAT) ******************* C66xx_0: GEL Output: PW_VAL => The Port-Write data registers ##DO NOT CONTAIN## valid data C66xx_0: GEL Output: PW_DISC => A Port-Write was ##NOT DISCARDED## C66xx_0: GEL Output: WDPTR => 0 (determines the size of the Port-Write payload received) C66xx_0: GEL Output: RW_SIZE => 0x00 (determines the size of the Port-Write payload received) C66xx_0: GEL Output: ******************* Port-Write Reception Capture(n) CSR (PW_RX_CAPT(n)) ******************* C66xx_0: GEL Output: PW_CAPT[0] => 0x00000000 C66xx_0: GEL Output: PW_CAPT[1] => 0x00000000 C66xx_0: GEL Output: PW_CAPT[2] => 0x00000000 C66xx_0: GEL Output: PW_CAPT[3] => 0x00000000 C66xx_0: GEL Output: ******************************************************************************************************* C66xx_0: GEL Output: ********************************** LLM CONFIGURATION ****************************************************** C66xx_0: GEL Output: ******************************************************************************************************* C66xx_0: GEL Output: ******************* Port Number CSR (PORT_NUMBER) ******************* C66xx_0: GEL Output: PORT_NUM => Maintenance read operation accessed this register through Port0 C66xx_0: GEL Output: PORT_TOTAL => Total number of Ports are 4 C66xx_0: GEL Output: ******************* Port IP Prescalar for SRV_CLK Register(PRESCALAR_SRV_CLK) ******************* C66xx_0: GEL Output: PRESCALAR_SRV_CLK => 33 (srio_ip_clk of 312.5 MHz) C66xx_0: GEL Output: SRV_CLK_PERIOD => 0.1056 us C66xx_0: GEL Output: ******************* Register Reset Control CSR (REG_RST_CTL) ******************* C66xx_0: GEL Output: CLEAR_STICKY => Sticky bits are **CLEARED** by SELF_RST and PWDN_PORT C66xx_0: GEL Output: ******************* Local Logical/Transport Layer Error Enable CSR (LOCAL_ERR_EN)******************* C66xx_0: GEL Output: ILL_TYPE_EN => Unsupported Transaction error reporting ##DISABLED## C66xx_0: GEL Output: ILL_ID_EN => Illegal transaction target error reporting ##DISABLED## C66xx_0: GEL Output: ******************************************************************************************************* C66xx_0: GEL Output: ********************************** LLM STATUS ****************************************************** C66xx_0: GEL Output: ******************************************************************************************************* C66xx_0: GEL Output: ******************* Local Logical/Transport Layer Error Detect CSR(LOCAL_ERR_DET) ******************* C66xx_0: GEL Output: ILL_TYPE => Unsupported Transaction is ##NOT RECEIVED## C66xx_0: GEL Output: ILL_ID => Illegal transaction target error has ##NOT OCCURED## C66xx_0: GEL Output: ******************* Local Logical/Transport Layer High Address Capture CSR (LOCAL_H_ADDR_CAPT) ******************* C66xx_0: GEL Output: MSB of address associated with the error (ADDR[31:0]) => 0x00000000 C66xx_0: GEL Output: ******************* Local Logical/Transport Layer Address Capture CSR(LOCAL_ADDR_CAPT) ******************* C66xx_0: GEL Output: LSB of address associated with the error (ADDR[60:32]) => 0x00000000 C66xx_0: GEL Output: Extended address bits associated with the error (XAMBS[1:0]) => 0x00 C66xx_0: GEL Output: ********************************** Local Logical/Transport Layer deviceID Capture CSR(LOCAL_ID_CAPT) ****************************************************** C66xx_0: GEL Output: No occurence of logical layer errors or logical layer error capture disabled C66xx_0: GEL Output: ********************************** Local Logical/Transport Layer Control Capture CSR(LOCAL_CTRL_CAPT) ****************************************************** C66xx_0: GEL Output: IMP_SPECIFIC- ---> 0x0000 C66xx_0: GEL Output: MSGINFO ---> 0x00 C66xx_0: GEL Output: PKT_TYPE ---> Not a valid packet type C66xx_0: GEL Output: ******************************************************************************************************* C66xx_0: GEL Output: ********************************** FABRIC STATUS ****************************************************** C66xx_0: GEL Output: ******************************************************************************************************* C66xx_0: GEL Output: ******************* Fabric Control and Status Register (FABRIC_CSR) ******************* C66xx_0: GEL Output: IG_UC_BACKPRESSURE => Ingress User Core backpressure indication ##NOT ASSERTED## C66xx_0: GEL Output: IG_LLM_BACKPRESSURE => Ingress LLM backpressure indication ##NOT ASSERTED## C66xx_0: GEL Output: ******************* Port0 Fabric Status Register (SP0_FABRIC_STATUS) ******************* C66xx_0: GEL Output: IG_UC_BACKPRESSURE => 0x00 C66xx_0: GEL Output: IG_LLM_BACKPRESSURE => 0x00 C66xx_0: GEL Output: ******************* Port1 Fabric Status Register (SP1_FABRIC_STATUS) ******************* C66xx_0: GEL Output: IG_UC_BACKPRESSURE => 0x00 C66xx_0: GEL Output: IG_LLM_BACKPRESSURE => 0x00 C66xx_0: GEL Output: ******************* Port2 Fabric Status Register (SP2_FABRIC_STATUS) ******************* C66xx_0: GEL Output: IG_UC_BACKPRESSURE => 0x00 C66xx_0: GEL Output: IG_LLM_BACKPRESSURE => 0x00 C66xx_0: GEL Output: ******************* Port3 Fabric Status Register (SP3_FABRIC_STATUS) ******************* C66xx_0: GEL Output: IG_UC_BACKPRESSURE => 0x00 C66xx_0: GEL Output: IG_LLM_BACKPRESSURE => 0x00