/*
 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
/dts-v1/;

#include "am33xx.dtsi"
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	model = "TI AM3359 ICE-V2";
	compatible = "ti,am3359-icev2", "ti,am33xx";

	cpus {
		cpu@0 {
			cpu0-supply = <&vdd1_reg>;
		};
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x10000000>; /* 256 MB */
	};

	chosen {
		stdout-path = &uart0;
	};

	vbat: fixedregulator0 {
		compatible = "regulator-fixed";
		regulator-name = "vbat";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		regulator-boot-on;
	};

	lis3_reg: fixedregulator1 {
		compatible = "regulator-fixed";
		regulator-name = "lis3_reg";
		regulator-boot-on;
	};
	
	/* Dual mac ethernet application node on icss */
	pruss_eth {
		compatible = "ti,am3359-prueth";
		pruss = <&pruss>;
		sram = <&ocmcram>;
		interrupt-parent = <&pruss_intc>;
		status = "disabled";

		pinctrl-0 = <&pruss_eth_default>;
		pinctrl-names = "default";

		pruss_emac0: ethernet-mii0 {
			phy-handle = <&pruss_eth0_phy>;
			phy-mode = "mii";
			interrupts = <20>, <22>;
			interrupt-names = "rx", "tx";
			/* Filled in by bootloader */
			local-mac-address = [00 00 00 00 00 00];
		};

		pruss_emac1: ethernet-mii1 {
			phy-handle = <&pruss_eth1_phy>;
			phy-mode = "mii";
			interrupts = <21>, <23>;
			interrupt-names = "rx", "tx";
			/* Filled in by bootloader */
			local-mac-address = [00 00 00 00 00 00];
		};
	};
};

&am33xx_pinmux {
	pinctrl-names = "default";

	i2c0_pins: pinmux_i2c0_pins {
		pinctrl-single,pins = <
			AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c0_sda.i2c0_sda */
			AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c0_scl.i2c0_scl */
		>;
	};

	i2c1_pins: pinmux_i2c1_pins {
		pinctrl-single,pins = <
			AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE2)	/* spi0_d1.i2c1_sda */
			AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE2)	/* spi0_cs0.i2c1_scl */
		>;
	};

	uart0_pins: pinmux_uart0_pins {
		pinctrl-single,pins = <
			AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0)	/* uart0_rxd.uart0_rxd */
			AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* uart0_txd.uart0_txd */
		>;
	};

	uart1_pins: pinmux_uart1_pins {
		pinctrl-single,pins = <
			AM33XX_IOPAD(0x978, PIN_INPUT | MUX_MODE0)		/* uart1_ctsn.uart1_ctsn */
			AM33XX_IOPAD(0x97C, PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* uart1_rtsn.uart1_rtsn */
			AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0)	/* uart1_rxd.uart1_rxd */
			AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* uart1_txd.uart1_txd */
		>;
	};

	nandflash_pins_s0: nandflash_pins_s0 {
		pinctrl-single,pins = <
			AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad0.gpmc_ad0 */
			AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad1.gpmc_ad1 */
			AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad2.gpmc_ad2 */
			AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad3.gpmc_ad3 */
			AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad4.gpmc_ad4 */
			AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad5.gpmc_ad5 */
			AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad6.gpmc_ad6 */
			AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad7.gpmc_ad7 */
			//AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_wait0.gpmc_wait0 */
			//AM33XX_IOPAD(0x874, PIN_INPUT_PULLUP | MUX_MODE7)	/* gpmc_wpn.gpio0_30 */
			AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0)		/* gpmc_csn0.gpmc_csn0  */
			AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0)		/* gpmc_advn_ale.gpmc_advn_ale */
			AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0)		/* gpmc_oen_ren.gpmc_oen_ren */
			AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0)		/* gpmc_wen.gpmc_wen */
			AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0)		/* gpmc_be0n_cle.gpmc_be0n_cle */
		>;
	};

	cpsw_default: cpsw_default {
		pinctrl-single,pins = <
			/* Slave 1 */
			0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE1)	/* mii1_txen.rgmii1_tctl */
			0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE1)	/* mii1_txd1.rgmii1_td1 */
			0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE1)	/* mii1_txd0.rgmii1_td0 */
			0x13c (PIN_INPUT_PULLDOWN | MUX_MODE1)	/* mii1_rxd1.rgmii1_rd1 */
			0x140 (PIN_INPUT_PULLDOWN | MUX_MODE1)	/* mii1_rxd0.rgmii1_rd0 */
			0x10C (PIN_INPUT_PULLDOWN | MUX_MODE1)	/* mii1_crs */
			0x110 (PIN_INPUT_PULLDOWN | MUX_MODE1)	/* mii1_rx_er */
			0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* mii1_ref_clk */
		>;
	};

	cpsw_sleep: cpsw_sleep {
		pinctrl-single,pins = <
			/* Slave 1 reset value */
			0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)	/* mii1_txen.rgmii1_tctl */
			0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)	/* mii1_txd1.rgmii1_td1 */
			0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)	/* mii1_txd0.rgmii1_td0 */
			0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)	/* mii1_rxd1.rgmii1_rd1 */
			0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)	/* mii1_rxd0.rgmii1_rd0 */
			0x10C (PIN_INPUT_PULLDOWN | MUX_MODE7)	/* mii1_crs */
			0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)	/* mii1_rx_er */
			0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7)	/* mii1_ref_clk */
		>;
	};

	davinci_mdio_default: davinci_mdio_default {
		pinctrl-single,pins = <
			/* MDIO */
			AM33XX_IOPAD(0x948, (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0))	/* mdio_data.mdio_data */
			AM33XX_IOPAD(0x94c, (PIN_OUTPUT_PULLUP | MUX_MODE0))			/* mdio_clk.mdio_clk */
			AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE7)		/* PHY-SELECT */
			AM33XX_IOPAD(0x9a4, PIN_OUTPUT | MUX_MODE7)		/* PHY-RESET */
		>;
	};

	davinci_mdio_sleep: davinci_mdio_sleep {
		pinctrl-single,pins = <
			/* MDIO reset value */
			AM33XX_IOPAD(0x948, (PIN_INPUT_PULLDOWN | MUX_MODE7))
			AM33XX_IOPAD(0x94c, (PIN_INPUT_PULLDOWN | MUX_MODE7))
		>;
	};
	
	pruss_mdio_default: pruss_mdio_default {
		pinctrl-single,pins = <
			AM33XX_IOPAD(0x88c, (PIN_OUTPUT | MUX_MODE5))		/* gpmc_clk.pr1_mdio_mdclk */
			AM33XX_IOPAD(0x888, (PIN_INPUT  | MUX_MODE5))		/* gpmc_csn3.pr1_mdio_data */
			//AM33XX_IOPAD(0x89c, (PIN_INPUT_PULLUP | MUX_MODE7))	/* gpmc_ben0_cle.gpio2_5 */
		>;
	};
	
	pruss_eth_default: pruss_eth_default {
		pinctrl-single,pins = <
			0x20 ( PIN_INPUT | MUX_MODE5 ) /* (U10) gpmc_ad8.pr1_mii_mt0_clk */
			0x38 ( PIN_OUTPUT | MUX_MODE5 ) /* (V13) gpmc_ad14.pr1_mii0_txd0 */
			0x34 ( PIN_OUTPUT | MUX_MODE5 ) /* (R12) gpmc_ad13.pr1_mii0_txd1 */
			0x30 ( PIN_OUTPUT | MUX_MODE5 ) /* (T12) gpmc_ad12.pr1_mii0_txd2 */
			0x2c ( PIN_OUTPUT | MUX_MODE5 ) /* (U12) gpmc_ad11.pr1_mii0_txd3 */
			0xcc ( PIN_INPUT | MUX_MODE5 ) /* (U4) lcd_data11.pr1_mii0_rxd0 */
			0xc8 ( PIN_INPUT | MUX_MODE5 ) /* (U3) lcd_data10.pr1_mii0_rxd1 */
			0xc4 ( PIN_INPUT | MUX_MODE5 ) /* (U2) lcd_data9.pr1_mii0_rxd2 */
			0xc0 ( PIN_INPUT | MUX_MODE5 ) /* (U1) lcd_data8.pr1_mii0_rxd3 */
			0x28 ( PIN_OUTPUT | MUX_MODE5 ) /* (T11) gpmc_ad10.pr1_mii0_txen */
			0xd8 ( PIN_INPUT | MUX_MODE5 ) /* (V4) lcd_data14.pr1_mii_mr0_clk */
			0xdc ( PIN_INPUT | MUX_MODE5 ) /* (T5) lcd_data15.pr1_mii0_rxdv */
			0xd4 ( PIN_INPUT | MUX_MODE5 ) /* (V3) lcd_data13.pr1_mii0_rxer */
			0xd0 ( PIN_INPUT | MUX_MODE5 ) /* (V2) lcd_data12.pr1_mii0_rxlink */
			0xe8 ( PIN_INPUT | MUX_MODE2 ) /* (V5) lcd_pclk.pr1_mii0_crs */
			//0x24 ( PIN_INPUT | MUX_MODE5 ) /* (T10) gpmc_ad9.pr1_mii0_col */

			AM33XX_IOPAD(0x840, (PIN_INPUT  | MUX_MODE5))	/* gpmc_a0.pr1_mii_mt1_clk */
			AM33XX_IOPAD(0x850, (PIN_OUTPUT | MUX_MODE5))	/* gpmc_a4.pr1_mii1_txd0 */
			AM33XX_IOPAD(0x84c, (PIN_OUTPUT | MUX_MODE5))	/* gpmc_a3.pr1_mii1_txd1 */
			AM33XX_IOPAD(0x848, (PIN_OUTPUT | MUX_MODE5))	/* gpmc_a2.pr1_mii1_txd2 */
			AM33XX_IOPAD(0x844, (PIN_OUTPUT | MUX_MODE5))	/* gpmc_a1.pr1_mii1_txd3 */
			AM33XX_IOPAD(0x860, (PIN_INPUT  | MUX_MODE5))	/* gpmc_a8.pr1_mii1_rxd0 */
			AM33XX_IOPAD(0x85c, (PIN_INPUT  | MUX_MODE5))	/* gpmc_a7.pr1_mii1_rxd1 */
			AM33XX_IOPAD(0x858, (PIN_INPUT  | MUX_MODE5))	/* gpmc_a6.pr1_mii1_rxd2 */
			AM33XX_IOPAD(0x854, (PIN_INPUT  | MUX_MODE5))	/* gpmc_a5.pr1_mii1_rxd3 */
			AM33XX_IOPAD(0x874, (PIN_OUTPUT | MUX_MODE5))	/* gpmc_wpn.pr1_mii1_txen */
			AM33XX_IOPAD(0x864, (PIN_INPUT  | MUX_MODE5))	/* gpmc_a9.pr1_mii_mr1_clk */
			AM33XX_IOPAD(0x868, (PIN_INPUT  | MUX_MODE5))	/* gpmc_a10.pr1_mii1_rxdv */
			AM33XX_IOPAD(0x86c, (PIN_INPUT  | MUX_MODE5))	/* gpmc_a11.pr1_mii1_rxer */
			AM33XX_IOPAD(0x878, (PIN_INPUT  | MUX_MODE5))	/* gpmc_ben1.pr1_mii1_rxlink */
			AM33XX_IOPAD(0x8ec, (PIN_INPUT  | MUX_MODE2))	/* lcd_ac_bias_en.pr1_mii1_crs */
			//AM33XX_IOPAD(0x870, (PIN_INPUT  | MUX_MODE5))	/* gpmc_wait0.pr1_mii1_col */
		>;
	};	
};

&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_pins>;

	status = "okay";
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart1_pins>;

	status = "okay";
};

&i2c0 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c0_pins>;

	status = "okay";
	clock-frequency = <400000>;

	tps: tps@2d {
		reg = <0x2d>;
	};
};

&cppi41dma  {
	status = "okay";
};

&i2c1 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c1_pins>;

	status = "disable";
	clock-frequency = <100000>;
};

&elm {
	status = "okay";
};

&gpmc {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&nandflash_pins_s0>;
	ranges = <0 0 0x08000000 0x1000000>;	/* CS0: 16MB for NAND */
	nand@0,0 {
		compatible = "ti,omap2-nand";
		reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
		interrupt-parent = <&gpmc>;
		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
			     <1 IRQ_TYPE_NONE>;	/* termcount */
		rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
		ti,nand-xfer-type = "prefetch-dma";
		ti,nand-ecc-opt = "bch8";
		ti,elm-id = <&elm>;
		nand-bus-width = <8>;
		gpmc,device-width = <1>;
		gpmc,sync-clk-ps = <0>;
		gpmc,cs-on-ns = <0>;
		gpmc,cs-rd-off-ns = <44>;
		gpmc,cs-wr-off-ns = <44>;
		gpmc,adv-on-ns = <6>;
		gpmc,adv-rd-off-ns = <34>;
		gpmc,adv-wr-off-ns = <44>;
		gpmc,we-on-ns = <0>;
		gpmc,we-off-ns = <40>;
		gpmc,oe-on-ns = <0>;
		gpmc,oe-off-ns = <54>;
		gpmc,access-ns = <64>;
		gpmc,rd-cycle-ns = <82>;
		gpmc,wr-cycle-ns = <82>;
		gpmc,bus-turnaround-ns = <0>;
		gpmc,cycle2cycle-delay-ns = <0>;
		gpmc,clk-activation-ns = <0>;
		gpmc,wr-access-ns = <40>;
		gpmc,wr-data-mux-bus-ns = <0>;
		/* MTD partition table */
		/* All SPL-* partitions are sized to minimal length
		 * which can be independently programmable. For
		 * NAND flash this is equal to size of erase-block */
		#address-cells = <1>;
		#size-cells = <1>;
		/* MTD partition table */
		partition@0 {
			label = "SPL1";
			reg = <0x00000000 0x000020000>;
		};

		partition@1 {
			label = "SPL2";
			reg = <0x00020000 0x00020000>;
		};

		partition@2 {
			label = "SPL3";
			reg = <0x00040000 0x00020000>;
		};

		partition@3 {
			label = "SPL4";
			reg = <0x00060000 0x00020000>;
		};

		partition@4 {
			label = "U-boot";
			reg = <0x00080000 0x001e0000>;
		};

		partition@5 {
			label = "environment";
			reg = <0x00260000 0x00020000>;
		};

		partition@6 {
			label = "Kernel";
			reg = <0x00280000 0x00500000>;
		};

		partition@7 {
			label = "File-System";
			reg = <0x00780000 0x0f880000>;
		};
	};
};

#include "tps65910.dtsi"

&tps {
	vcc1-supply = <&vbat>;
	vcc2-supply = <&vbat>;
	vcc3-supply = <&vbat>;
	vcc4-supply = <&vbat>;
	vcc5-supply = <&vbat>;
	vcc6-supply = <&vbat>;
	vcc7-supply = <&vbat>;
	vccio-supply = <&vbat>;

	regulators {
		vrtc_reg: regulator@0 {
			regulator-always-on;
		};

		vio_reg: regulator@1 {
			regulator-always-on;
		};

		vdd1_reg: regulator@2 {
			/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
			regulator-name = "vdd_mpu";
			regulator-min-microvolt = <912500>;
			regulator-max-microvolt = <1351500>;
			regulator-boot-on;
			regulator-always-on;
		};

		vdd2_reg: regulator@3 {
			/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
			regulator-name = "vdd_core";
			regulator-min-microvolt = <912500>;
			regulator-max-microvolt = <1150000>;
			regulator-boot-on;
			regulator-always-on;
		};

		vdd3_reg: regulator@4 {
			regulator-always-on;
		};

		vdig1_reg: regulator@5 {
			regulator-always-on;
		};

		vdig2_reg: regulator@6 {
			regulator-always-on;
		};

		vpll_reg: regulator@7 {
			regulator-always-on;
		};

		vdac_reg: regulator@8 {
			regulator-always-on;
		};

		vaux1_reg: regulator@9 {
			regulator-always-on;
		};

		vaux2_reg: regulator@10 {
			regulator-always-on;
		};

		vaux33_reg: regulator@11 {
			regulator-always-on;
		};

		vmmc_reg: regulator@12 {
			regulator-min-microvolt = <1800000>;
			regulator-max-microvolt = <3300000>;
			regulator-always-on;
		};
	};
};

&mac {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&cpsw_default>;
	pinctrl-1 = <&cpsw_sleep>;
	slaves = <1>;
	status = "okay";
};

&davinci_mdio {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&davinci_mdio_default>;
	pinctrl-1 = <&davinci_mdio_sleep>;
	status = "okay";
	reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
	reset-delay-us = <2>;   /* PHY datasheet states 1uS min */
};

&cpsw_emac0 {
	phy_id = <&davinci_mdio>, <1>;
	phy-mode = "rmii";
};

&phy_sel {
        rmii-clock-ext = <1>;
};

&pruss_soc_bus {
	status = "okay";

	pruss: pruss@4a300000 {
		status = "okay";

		pru0: pru@4a334000 {
			status = "okay";
		};

		pru1: pru@4a338000 {
			status = "okay";
		};
	};
};

&pruss_mdio {
	pinctrl-0 = <&pruss_mdio_default>;
	pinctrl-names = "default";
	reset-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
	reset-delay-us = <2>; /* PHY datasheet states 1uS min */
	status = "disabled";

	pruss_eth0_phy: ethernet-phy@1 {
		 reg = <1>;
	 };

	pruss_eth1_phy: ethernet-phy@0 {
		 reg = <0>;
	 };
};


&pruss_soc_bus {
		uio_pruss_mdio: uio_pruss_mdio@4a332400 {
			compatible = "ti,davinci_mdio";
			reg = <0x4a332400 0x90>;
			clocks = <&dpll_core_m4_ck>;
			clock-names = "fck";
			bus_freq = <1000000>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		uio_pruss_mem: uio_pruss_mem {
			compatible = "ti,uio-module-drv";
			mem = <0x4a300000 0x2000>,
			      <0x4a302000 0x2000>,
			      <0x4a310000 0x3000>,
			      <0x4a320000 0x2000>,
			      <0x4a326000 0x2000>,
			      <0x4a32e000 0x31c>,
			      <0x4a332000 0x58>;
			mem-names = "dram0", "dram1", "shrdram2", "intc", "cfg",
				    "iep", "mii_rt";

			status = "okay";
		};
		uio_pruss_mem2: uio_pruss_mem2 {
			compatible = "ti,uio-module-drv";
			mem = <0x4a328000 0xd4>,
			      <0x4a330000 0x174>,
			      <0x4a332400 0x90>,
			      <0x40302000 0x0e000>;
			mem-names = "uart", "ecap", "mdio", "ocmc";
			status = "okay";
		};

		uio_pruss_evt0: uio_pruss_evt0 {
			compatible = "ti,uio-module-drv";
                        interrupts = <20>;
			interrupt-mode = <1>;
			status = "okay";
		};
		uio_pruss_evt1: uio_pruss_evt1 {
			compatible = "ti,uio-module-drv";
                        interrupts = <21>;
			interrupt-mode = <1>;
			status = "okay";
		};
		uio_pruss_evt2: uio_pruss_evt2 {
			compatible = "ti,uio-module-drv";
                        interrupts = <22>;
			interrupt-mode = <1>;
			status = "okay";
		};
		uio_pruss_evt3: uio_pruss_evt3 {
			compatible = "ti,uio-module-drv";
                        interrupts = <23>;
			interrupt-mode = <1>;
			status = "okay";
		};
		uio_pruss_evt4: uio_pruss_evt4 {
			compatible = "ti,uio-module-drv";
                        interrupts = <24>;
			interrupt-mode = <1>;
			status = "okay";
		};
		uio_pruss_evt5: uio_pruss_evt5 {
			compatible = "ti,uio-module-drv";
                        interrupts = <25>;
			interrupt-mode = <1>;
			status = "okay";
		};
		uio_pruss_evt6: uio_pruss_evt6 {
			compatible = "ti,uio-module-drv";
                        interrupts = <26>;
			interrupt-mode = <1>;
			status = "okay";
		};
		uio_pruss_evt7: uio_pruss_evt7 {
			compatible = "ti,uio-module-drv";
                        interrupts = <27>;
			interrupt-mode = <1>;
			status = "okay";
		};

		uio_pruss_0_mem: uio_pruss_0_mem {
			compatible = "ti,uio-module-drv";
			mem = <0x4a334000 0x2000>,
			      <0x4a322000 0x400>,
			      <0x4a322400 0x100>;
			mem-names = "iram", "control", "debug";
			status = "okay";
		};

		uio_pruss_1_mem: uio_pruss_1_mem {
			compatible = "ti,uio-module-drv";
			mem = <0x4a338000 0x2000>,
			      <0x4a324000 0x400>,
			      <0x4a324400 0x100>;
			mem-names = "iram", "control", "debug";
			status = "okay";
		};
};

&am33xx_pinmux {
	uio_pruss_mdio_eth_default: uio_pruss_mdio_eht_default {
		pinctrl-single,pins = <
			AM33XX_IOPAD(0x88c, (PIN_OUTPUT | MUX_MODE5))           /* gpmc_clk.pr1_mdio_mdclk */
			AM33XX_IOPAD(0x888, (PIN_INPUT  | MUX_MODE5))           /* gpmc_csn3.pr1_mdio_data */
			0x20 ( PIN_INPUT | MUX_MODE5 ) /* (U10) gpmc_ad8.pr1_mii_mt0_clk */
			0x38 ( PIN_OUTPUT | MUX_MODE5 ) /* (V13) gpmc_ad14.pr1_mii0_txd0 */
			0x34 ( PIN_OUTPUT | MUX_MODE5 ) /* (R12) gpmc_ad13.pr1_mii0_txd1 */
			0x30 ( PIN_OUTPUT | MUX_MODE5 ) /* (T12) gpmc_ad12.pr1_mii0_txd2 */
			0x2c ( PIN_OUTPUT | MUX_MODE5 ) /* (U12) gpmc_ad11.pr1_mii0_txd3 */
			0xcc ( PIN_INPUT | MUX_MODE5 ) /* (U4) lcd_data11.pr1_mii0_rxd0 */
			0xc8 ( PIN_INPUT | MUX_MODE5 ) /* (U3) lcd_data10.pr1_mii0_rxd1 */
			0xc4 ( PIN_INPUT | MUX_MODE5 ) /* (U2) lcd_data9.pr1_mii0_rxd2 */
			0xc0 ( PIN_INPUT | MUX_MODE5 ) /* (U1) lcd_data8.pr1_mii0_rxd3 */
			0x28 ( PIN_OUTPUT | MUX_MODE5 ) /* (T11) gpmc_ad10.pr1_mii0_txen */
			0xd8 ( PIN_INPUT | MUX_MODE5 ) /* (V4) lcd_data14.pr1_mii_mr0_clk */
			0xdc ( PIN_INPUT | MUX_MODE5 ) /* (T5) lcd_data15.pr1_mii0_rxdv */
			0xd4 ( PIN_INPUT | MUX_MODE5 ) /* (V3) lcd_data13.pr1_mii0_rxer */
			0xd0 ( PIN_INPUT | MUX_MODE5 ) /* (V2) lcd_data12.pr1_mii0_rxlink */
			0xe8 ( PIN_INPUT | MUX_MODE2 ) /* (V5) lcd_pclk.pr1_mii0_crs */
			//0x24 ( PIN_INPUT | MUX_MODE5 ) /* (T10) gpmc_ad9.pr1_mii0_col */

			AM33XX_IOPAD(0x840, (PIN_INPUT  | MUX_MODE5))	/* gpmc_a0.pr1_mii_mt1_clk */
			AM33XX_IOPAD(0x850, (PIN_OUTPUT | MUX_MODE5))	/* gpmc_a4.pr1_mii1_txd0 */
			AM33XX_IOPAD(0x84c, (PIN_OUTPUT | MUX_MODE5))	/* gpmc_a3.pr1_mii1_txd1 */
			AM33XX_IOPAD(0x848, (PIN_OUTPUT | MUX_MODE5))	/* gpmc_a2.pr1_mii1_txd2 */
			AM33XX_IOPAD(0x844, (PIN_OUTPUT | MUX_MODE5))	/* gpmc_a1.pr1_mii1_txd3 */
			AM33XX_IOPAD(0x860, (PIN_INPUT  | MUX_MODE5))	/* gpmc_a8.pr1_mii1_rxd0 */
			AM33XX_IOPAD(0x85c, (PIN_INPUT  | MUX_MODE5))	/* gpmc_a7.pr1_mii1_rxd1 */
			AM33XX_IOPAD(0x858, (PIN_INPUT  | MUX_MODE5))	/* gpmc_a6.pr1_mii1_rxd2 */
			AM33XX_IOPAD(0x854, (PIN_INPUT  | MUX_MODE5))	/* gpmc_a5.pr1_mii1_rxd3 */
			AM33XX_IOPAD(0x874, (PIN_OUTPUT | MUX_MODE5))	/* gpmc_wpn.pr1_mii1_txen */
			AM33XX_IOPAD(0x864, (PIN_INPUT  | MUX_MODE5))	/* gpmc_a9.pr1_mii_mr1_clk */
			AM33XX_IOPAD(0x868, (PIN_INPUT  | MUX_MODE5))	/* gpmc_a10.pr1_mii1_rxdv */
			AM33XX_IOPAD(0x86c, (PIN_INPUT  | MUX_MODE5))	/* gpmc_a11.pr1_mii1_rxer */
			AM33XX_IOPAD(0x878, (PIN_INPUT  | MUX_MODE5))	/* gpmc_ben1.pr1_mii1_rxlink */
			AM33XX_IOPAD(0x8ec, (PIN_INPUT  | MUX_MODE2))	/* lcd_ac_bias_en.pr1_mii1_crs */
			//AM33XX_IOPAD(0x870, (PIN_INPUT  | MUX_MODE5))	/* gpmc_wait0.pr1_mii1_col */
		>;
	};
};

&uio_pruss_mdio {
	pinctrl-0 = <&uio_pruss_mdio_eth_default>;
	pinctrl-names = "default";
	reset-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
	reset-delay-us = <2>; /* PHY datasheet states 1uS min */
	status = "okay";

	uio_pruss_eth0_phy: ethernet-phy@1 {
		reg = <1>;
	};

	uio_pruss_eth1_phy: ethernet-phy@0 {
		reg = <0>;
	};
};

&pruss {
	status = "disabled";
};

&pru0 {
	status = "disabled";
};

&pru1 {
	status = "disabled";
};

&pruss_intc {
	status = "disabled";
};

&pruss_mdio {
	status = "disabled";
};

&pruss_emac0 {
	status = "disabled";
};

&pruss_emac1 {
	status = "disabled";
};