/* This file was auto-generated by TI PinMux on 6/8/2020 at 1:21:22 PM. */ /* This file should only be used as a reference. Some pins/peripherals, */ /* depending on your use case, may need additional configuration. */ /* Some or all the pins from the following groups are not used by device tree myemif1 myglue1 myosc1 myusb1 myusb2 */ /dts-v1/; #include "am33xx.dtsi" #include / { model = "TI AM335x EVM"; compatible = "ti,am335x-evm", "ti,am33xx"; memory@80000000 { device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256MB*/ }; cpus { cpu@0{ }; }; chosen { stdout-path = &uart0; }; }; &am33xx_pinmux { mydebugss1_pins_default: mydebugss1_pins_default { pinctrl-single,pins = < AM33XX_IOPAD(0x9d0, PIN_INPUT | MUX_MODE0) /* (C11) TMS.TMS */ AM33XX_IOPAD(0x9d4, PIN_INPUT | MUX_MODE0) /* (B11) TDI.TDI */ AM33XX_IOPAD(0x9d8, PIN_OUTPUT | MUX_MODE0) /* (A11) TDO.TDO */ AM33XX_IOPAD(0x9dc, PIN_INPUT | MUX_MODE0) /* (A12) TCK.TCK */ AM33XX_IOPAD(0x9e0, PIN_INPUT | MUX_MODE0) /* (B10) nTRST.nTRST */ AM33XX_IOPAD(0x9e4, PIN_INPUT | MUX_MODE0) /* (C14) EMU0.EMU0 */ AM33XX_IOPAD(0x9e8, PIN_INPUT | MUX_MODE0) /* (B14) EMU1.EMU1 */ AM33XX_IOPAD(0x9a4, PIN_INPUT | MUX_MODE4) /* (C13) mcasp0_fsr.EMU2 */ AM33XX_IOPAD(0x9a8, PIN_INPUT | MUX_MODE4) /* (D13) mcasp0_axr1.EMU3 */ AM33XX_IOPAD(0x9ac, PIN_INPUT | MUX_MODE4) /* (A14) mcasp0_ahclkx.EMU4 */ >; }; myglue1_pins_default: myglue1_pins_default { pinctrl-single,pins = < AM33XX_IOPAD(0x9b8, PIN_INPUT | MUX_MODE0) /* (A10) nRESETIN_OUT.nRESETIN_OUT */ AM33XX_IOPAD(0x9c0, PIN_INPUT | MUX_MODE0) /* (B18) nNMI.nNMI */ AM33XX_IOPAD(0x9b4, PIN_INPUT | MUX_MODE0) /* (D14) xdma_event_intr1.xdma_event_intr1 */ AM33XX_IOPAD(0x964, PIN_INPUT | MUX_MODE6) /* (C18) eCAP0_in_PWM0_out.xdma_event_intr2 */ AM33XX_IOPAD(0x9b0, PIN_OUTPUT | MUX_MODE3) /* (A15) xdma_event_intr0.clkout1 */ >; }; mygpio1_pins_default: mygpio1_pins_default { pinctrl-single,pins = < AM33XX_IOPAD(0x908, PIN_INPUT | MUX_MODE7) /* (H16) gmii1_col.gpio3[0] */ AM33XX_IOPAD(0x90c, PIN_INPUT | MUX_MODE7) /* (H17) gmii1_crs.gpio3[1] */ AM33XX_IOPAD(0x910, PIN_INPUT | MUX_MODE7) /* (J15) gmii1_rxer.gpio3[2] */ AM33XX_IOPAD(0x990, PIN_INPUT | MUX_MODE7) /* (A13) mcasp0_aclkx.gpio3[14] */ AM33XX_IOPAD(0x994, PIN_INPUT | MUX_MODE7) /* (B13) mcasp0_fsx.gpio3[15] */ AM33XX_IOPAD(0x998, PIN_INPUT | MUX_MODE7) /* (D12) mcasp0_axr0.gpio3[16] */ AM33XX_IOPAD(0x99c, PIN_INPUT | MUX_MODE7) /* (C12) mcasp0_ahclkr.gpio3[17] */ AM33XX_IOPAD(0x9a0, PIN_INPUT | MUX_MODE7) /* (B12) mcasp0_aclkr.gpio3[18] */ >; }; mygpio2_pins_default: mygpio2_pins_default { pinctrl-single,pins = < AM33XX_IOPAD(0x8f0, PIN_INPUT | MUX_MODE7) /* (F17) mmc0_dat3.gpio2[26] */ AM33XX_IOPAD(0x8f4, PIN_INPUT | MUX_MODE7) /* (F18) mmc0_dat2.gpio2[27] */ AM33XX_IOPAD(0x8f8, PIN_INPUT | MUX_MODE7) /* (G15) mmc0_dat1.gpio2[28] */ AM33XX_IOPAD(0x8fc, PIN_INPUT | MUX_MODE7) /* (G16) mmc0_dat0.gpio2[29] */ AM33XX_IOPAD(0x900, PIN_INPUT | MUX_MODE7) /* (G17) mmc0_clk.gpio2[30] */ AM33XX_IOPAD(0x904, PIN_INPUT | MUX_MODE7) /* (G18) mmc0_cmd.gpio2[31] */ >; }; mygpmc1_pins_default: mygpmc1_pins_default { pinctrl-single,pins = < AM33XX_IOPAD(0x83c, PIN_INPUT | MUX_MODE0) /* (U13) gpmc_ad15.gpmc_ad15 */ AM33XX_IOPAD(0x838, PIN_INPUT | MUX_MODE0) /* (V13) gpmc_ad14.gpmc_ad14 */ AM33XX_IOPAD(0x834, PIN_INPUT | MUX_MODE0) /* (R12) gpmc_ad13.gpmc_ad13 */ AM33XX_IOPAD(0x830, PIN_INPUT | MUX_MODE0) /* (T12) gpmc_ad12.gpmc_ad12 */ AM33XX_IOPAD(0x82c, PIN_INPUT | MUX_MODE0) /* (U12) gpmc_ad11.gpmc_ad11 */ AM33XX_IOPAD(0x828, PIN_INPUT | MUX_MODE0) /* (T11) gpmc_ad10.gpmc_ad10 */ AM33XX_IOPAD(0x824, PIN_INPUT | MUX_MODE0) /* (T10) gpmc_ad9.gpmc_ad9 */ AM33XX_IOPAD(0x820, PIN_INPUT | MUX_MODE0) /* (U10) gpmc_ad8.gpmc_ad8 */ AM33XX_IOPAD(0x81c, PIN_INPUT | MUX_MODE0) /* (T9) gpmc_ad7.gpmc_ad7 */ AM33XX_IOPAD(0x818, PIN_INPUT | MUX_MODE0) /* (R9) gpmc_ad6.gpmc_ad6 */ AM33XX_IOPAD(0x814, PIN_INPUT | MUX_MODE0) /* (V8) gpmc_ad5.gpmc_ad5 */ AM33XX_IOPAD(0x810, PIN_INPUT | MUX_MODE0) /* (U8) gpmc_ad4.gpmc_ad4 */ AM33XX_IOPAD(0x80c, PIN_INPUT | MUX_MODE0) /* (T8) gpmc_ad3.gpmc_ad3 */ AM33XX_IOPAD(0x808, PIN_INPUT | MUX_MODE0) /* (R8) gpmc_ad2.gpmc_ad2 */ AM33XX_IOPAD(0x804, PIN_INPUT | MUX_MODE0) /* (V7) gpmc_ad1.gpmc_ad1 */ AM33XX_IOPAD(0x800, PIN_INPUT | MUX_MODE0) /* (U7) gpmc_ad0.gpmc_ad0 */ AM33XX_IOPAD(0x870, PIN_INPUT | MUX_MODE0) /* (T17) gpmc_wait0.gpmc_wait0 */ /*AM33XX_IOPAD(0x88c, PIN_INPUT | MUX_MODE2)*/ /* (V12) gpmc_clk.gpmc_wait1 */ AM33XX_IOPAD(0x884, PIN_OUTPUT | MUX_MODE1) /* (V9) gpmc_csn2.gpmc_be1n */ AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* (V6) gpmc_csn0.gpmc_csn0 */ /*AM33XX_IOPAD(0x888, PIN_OUTPUT | MUX_MODE0)*/ /* (T13) gpmc_csn3.gpmc_csn3 */ AM33XX_IOPAD(0x874, PIN_OUTPUT | MUX_MODE2) /* (U17) gpmc_wpn.gpmc_csn5 */ AM33XX_IOPAD(0x880, PIN_INPUT | MUX_MODE1) /* (U9) gpmc_csn1.gpmc_clk */ AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* (R7) gpmc_advn_ale.gpmc_advn_ale */ AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* (T7) gpmc_oen_ren.gpmc_oen_ren */ AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* (U6) gpmc_wen.gpmc_wen */ AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* (T6) gpmc_be0n_cle.gpmc_be0n_cle */ AM33XX_IOPAD(0x878, PIN_OUTPUT | MUX_MODE4) /* (U18) gpmc_be1n.gpmc_dir */ >; }; myi2c1_pins_default: myi2c1_pins_default { pinctrl-single,pins = < AM33XX_IOPAD(0x96c, PIN_INPUT | MUX_MODE3) /* (E17) uart0_rtsn.I2C1_SCL */ AM33XX_IOPAD(0x968, PIN_INPUT | MUX_MODE3) /* (E18) uart0_ctsn.I2C1_SDA */ >; }; myi2c2_pins_default: myi2c2_pins_default { pinctrl-single,pins = < AM33XX_IOPAD(0x98c, PIN_INPUT | MUX_MODE0) /* (C16) I2C0_SCL.I2C0_SCL */ AM33XX_IOPAD(0x988, PIN_INPUT | MUX_MODE0) /* (C17) I2C0_SDA.I2C0_SDA */ >; }; myi2c3_pins_default: myi2c3_pins_default { pinctrl-single,pins = < AM33XX_IOPAD(0x97c, PIN_INPUT | MUX_MODE3) /* (D17) uart1_rtsn.I2C2_SCL */ AM33XX_IOPAD(0x978, PIN_INPUT | MUX_MODE3) /* (D18) uart1_ctsn.I2C2_SDA */ >; }; mylcdc4_pins_default: mylcdc4_pins_default { pinctrl-single,pins = < AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE0) /* (U5) lcd_vsync.lcd_vsync */ AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0) /* (R5) lcd_hsync.lcd_hsync */ AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0) /* (V5) lcd_pclk.lcd_pclk */ AM33XX_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0) /* (R6) lcd_ac_bias_en.lcd_ac_bias_en */ AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0) /* (R1) lcd_data0.lcd_data0 */ AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0) /* (R2) lcd_data1.lcd_data1 */ AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0) /* (R3) lcd_data2.lcd_data2 */ AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0) /* (R4) lcd_data3.lcd_data3 */ AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0) /* (T1) lcd_data4.lcd_data4 */ AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0) /* (T2) lcd_data5.lcd_data5 */ AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0) /* (T3) lcd_data6.lcd_data6 */ AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0) /* (T4) lcd_data7.lcd_data7 */ AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0) /* (U1) lcd_data8.lcd_data8 */ AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0) /* (U2) lcd_data9.lcd_data9 */ AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0) /* (U3) lcd_data10.lcd_data10 */ AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0) /* (U4) lcd_data11.lcd_data11 */ AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0) /* (V2) lcd_data12.lcd_data12 */ AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0) /* (V3) lcd_data13.lcd_data13 */ AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0) /* (V4) lcd_data14.lcd_data14 */ AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0) /* (T5) lcd_data15.lcd_data15 */ >; }; mymdio1_pins_default: mymdio1_pins_default { pinctrl-single,pins = < AM33XX_IOPAD(0x94c, PIN_OUTPUT | MUX_MODE0) /* (M18) mdio_clk.mdio_clk */ AM33XX_IOPAD(0x948, PIN_INPUT | MUX_MODE0) /* (M17) mdio_data.mdio_data */ >; }; myrgmii2_pins_default: myrgmii2_pins_default { pinctrl-single,pins = < AM33XX_IOPAD(0x840, PIN_OUTPUT | MUX_MODE2) /* (R13) gpmc_a0.rgmii2_tctl */ AM33XX_IOPAD(0x844, PIN_INPUT | MUX_MODE2) /* (V14) gpmc_a1.rgmii2_rctl */ AM33XX_IOPAD(0x858, PIN_OUTPUT | MUX_MODE2) /* (U15) gpmc_a6.rgmii2_tclk */ AM33XX_IOPAD(0x85c, PIN_INPUT | MUX_MODE2) /* (T15) gpmc_a7.rgmii2_rclk */ AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE2) /* (V15) gpmc_a5.rgmii2_td0 */ AM33XX_IOPAD(0x850, PIN_OUTPUT | MUX_MODE2) /* (R14) gpmc_a4.rgmii2_td1 */ AM33XX_IOPAD(0x84c, PIN_OUTPUT | MUX_MODE2) /* (T14) gpmc_a3.rgmii2_td2 */ AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE2) /* (U14) gpmc_a2.rgmii2_td3 */ AM33XX_IOPAD(0x86c, PIN_INPUT | MUX_MODE2) /* (V17) gpmc_a11.rgmii2_rd0 */ AM33XX_IOPAD(0x868, PIN_INPUT | MUX_MODE2) /* (T16) gpmc_a10.rgmii2_rd1 */ AM33XX_IOPAD(0x864, PIN_INPUT | MUX_MODE2) /* (U16) gpmc_a9.rgmii2_rd2 */ AM33XX_IOPAD(0x860, PIN_INPUT | MUX_MODE2) /* (V16) gpmc_a8.rgmii2_rd3 */ >; }; myrgmii3_pins_default: myrgmii3_pins_default { pinctrl-single,pins = < AM33XX_IOPAD(0x914, PIN_OUTPUT | MUX_MODE2) /* (J16) gmii1_txen.rgmii1_tctl */ AM33XX_IOPAD(0x918, PIN_INPUT | MUX_MODE2) /* (J17) gmii1_rxdv.rgmii1_rctl */ AM33XX_IOPAD(0x92c, PIN_OUTPUT | MUX_MODE2) /* (K18) gmii1_txclk.rgmii1_tclk */ AM33XX_IOPAD(0x930, PIN_INPUT | MUX_MODE2) /* (L18) gmii1_rxclk.rgmii1_rclk */ AM33XX_IOPAD(0x928, PIN_OUTPUT | MUX_MODE2) /* (K17) gmii1_txd0.rgmii1_td0 */ AM33XX_IOPAD(0x924, PIN_OUTPUT | MUX_MODE2) /* (K16) gmii1_txd1.rgmii1_td1 */ AM33XX_IOPAD(0x920, PIN_OUTPUT | MUX_MODE2) /* (K15) gmii1_txd2.rgmii1_td2 */ AM33XX_IOPAD(0x91c, PIN_OUTPUT | MUX_MODE2) /* (J18) gmii1_txd3.rgmii1_td3 */ AM33XX_IOPAD(0x940, PIN_INPUT | MUX_MODE2) /* (M16) gmii1_rxd0.rgmii1_rd0 */ AM33XX_IOPAD(0x93c, PIN_INPUT | MUX_MODE2) /* (L15) gmii1_rxd1.rgmii1_rd1 */ AM33XX_IOPAD(0x938, PIN_INPUT | MUX_MODE2) /* (L16) gmii1_rxd2.rgmii1_rd2 */ AM33XX_IOPAD(0x934, PIN_INPUT | MUX_MODE2) /* (L17) gmii1_rxd3.rgmii1_rd3 */ >; }; myspi1_pins_default: myspi1_pins_default { pinctrl-single,pins = < AM33XX_IOPAD(0x950, PIN_INPUT | MUX_MODE0) /* (A17) spi0_sclk.spi0_sclk */ AM33XX_IOPAD(0x954, PIN_INPUT | MUX_MODE0) /* (B17) spi0_d0.spi0_d0 */ AM33XX_IOPAD(0x958, PIN_INPUT | MUX_MODE0) /* (B16) spi0_d1.spi0_d1 */ AM33XX_IOPAD(0x95c, PIN_INPUT | MUX_MODE0) /* (A16) spi0_cs0.spi0_cs0 */ AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE0) /* (C15) spi0_cs1.spi0_cs1 */ >; }; myuart1_pins_default: myuart1_pins_default { pinctrl-single,pins = < AM33XX_IOPAD(0x970, PIN_INPUT | MUX_MODE0) /* (E15) uart0_rxd.uart0_rxd */ AM33XX_IOPAD(0x974, PIN_OUTPUT | MUX_MODE0) /* (E16) uart0_txd.uart0_txd */ >; }; myuart2_pins_default: myuart2_pins_default { pinctrl-single,pins = < AM33XX_IOPAD(0x980, PIN_INPUT | MUX_MODE0) /* (D16) uart1_rxd.uart1_rxd */ AM33XX_IOPAD(0x984, PIN_OUTPUT | MUX_MODE0) /* (D15) uart1_txd.uart1_txd */ >; }; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&myuart1_pins_default>; status = "okay"; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&myuart2_pins_default>; status = "okay"; }; &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&myi2c2_pins_default>; status = "okay"; clock-frequency = <100000>; }; &i2c1 { pinctrl-names = "default"; pinctrl-0 = <&myi2c1_pins_default>; status = "okay"; clock-frequency = <100000>; }; &i2c2 { pinctrl-names = "default"; pinctrl-0 = <&myi2c3_pins_default>; status = "okay"; clock-frequency = <100000>; }; &elm { status = "okay"; }; &gpmc { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mygpmc1_pins_default>; /* When present, the module should not be reset at init */ /*ti,no-reset-on-init;*/ /* When present, the module should not be idled at init */ /*ti,no-idle-on-init;*/ /* When present, the module is never allowed to idle */ /*ti,no-idle;*/ /* ranges: Must be set up to reflect the memory layout with four integer values for each chip-select line in use: 0 */ ranges = <0 0 0x08000000 0x01000000>, /* CS0: 256MB for NAND */ <3 0 0x10000000 0x02000000>; /*CSn3 for FPGA*/ nand@0,0 { compatible = "ti,omap2-nand"; reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ interrupt-parent = <&gpmc>; interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ <1 IRQ_TYPE_NONE>; /* termcount */ ti,nand-xfer-type = "prefetch-dma"; ti,nand-ecc-opt = "bch16"; ti,elm-id = <&elm>; nand-bus-width = <16>; gpmc,device-width = <2>; gpmc,sync-clk-ps = <0>; gpmc,cs-on-ns = <0>; gpmc,cs-rd-off-ns = <44>; gpmc,cs-wr-off-ns = <44>; gpmc,adv-on-ns = <6>; gpmc,adv-rd-off-ns = <34>; gpmc,adv-wr-off-ns = <44>; gpmc,we-on-ns = <0>; gpmc,we-off-ns = <40>; gpmc,oe-on-ns = <0>; gpmc,oe-off-ns = <54>; gpmc,access-ns = <64>; gpmc,rd-cycle-ns = <82>; gpmc,wr-cycle-ns = <82>; gpmc,bus-turnaround-ns = <0>; gpmc,cycle2cycle-delay-ns = <0>; gpmc,clk-activation-ns = <0>; gpmc,wr-access-ns = <40>; /* MTD partition table */ /* All SPL-* partitions are sized to minimal length * which can be independently programmable. For * NAND flash this is equal to size of erase-block */ #address-cells = <1>; #size-cells = <1>; partition@0 { label = "NAND.SPL"; reg = <0x00000000 0x00020000>; }; partition@1 { label = "NAND.u-boot-spl-os"; reg = <0x00020000 0x00040000>; }; partition@2 { label = "NAND.u-boot"; reg = <0x00060000 0x00100000>; }; partition@3 { label = "NAND.u-boot-env"; reg = <0x00160000 0x00020000>; }; partition@4 { label = "NAND.u-boot-env.backup1"; reg = <0x00180000 0x00020000>; }; partition@5 { label = "NAND.kernel"; reg = <0x001a0000 0x00800000>; }; partition@6 { label = "NAND.rootfs"; reg = <0x009a0000 0x0f660000>; }; /* partition@7 { label = "NAND.fdtfile.Working"; reg = <0x06ea0000 0x00020000>; }; partition@8 { label = "NAND.kernel_fs.Working"; reg = <0x06ec0000 0x06c00000>; }; partition@9 { label = "NAND.Database"; reg = <0x0dac0000 0x00800000>; }; partition@10 { label = "NAND.Image_Type"; reg = <0x0e2c0000 0x00020000>; }; partition@11 { label = "NAND.Database.Golden"; reg = <0x0e2e0000 0x00800000>; }; partition@12 { label = "NAND.User.defined"; reg = <0xEAE0000 0x1520000>; }; */ }; fpga@1,0{ reg = <3 0 0x10000000>; /*CSn3*/ compatible = "xillybus,xillybus-1.00.a"; #address-cells = <1>; #size-cells = <0>; bank-width = <2>; /* GPMC_CONFIG1_DEVICESIZE(1) *//*16 bit wide*/ /*fpga timings deprecated*/ }; }; /* refer: https://www.kernel.org/doc/Documentation/devicetree/bindings/net/cpsw.txt */ &mac { pinctrl-names = "default"; pinctrl-0 = <&myrgmii3_pins_default>; pinctrl-1 = <&myrgmii2_pins_default>; /* Specifies RGMII2 as teh default port */ active_slave = <1>; status = "okay"; }; &davinci_mdio { pinctrl-names = "default"; pinctrl-0 = <&mymdio1_pins_default>; pinctrl-1 = <&mymdio1_pins_default>; status = "okay"; }; &cpsw_emac1 { /* debug port */ phy_id = <&davinci_mdio>, <2>; phy-mode = "rgmii"; }; &spi0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&myspi1_pins_default>; r4_fpga@1 { compatible = "r4_fpga"; gpio-controller; #gpio-cells = <2>; reg = <1>; spi-max-frequency = <1000000>; spi-cpol; }; spi_nor: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "winbond,w25q64", "jedec,spi-nor"; spi-max-frequency = <80000000>; m25p,fast-read; reg = <0>; partition@0 { label = "u-boot-spl"; reg = <0x0 0x20000>; read-only; }; partition@1 { label = "u-boot"; reg = <0x20000 0x100000>; read-only; }; partition@2 { label = "u-boot-env"; reg = <0x180000 0x20000>; read-only; }; partition@3 { label = "misc"; reg = <0x1A0000 0x660000>; }; }; };