CONTROL: device_id = 0x2b98c02f * AM43xx family * Silicon Revision 1.2 CONTROL: control_status = 0x00400301 * Bit 26 (SYSBOOT18=0): Do not route EXTCLK to CLKOUT2 * Bits 23:22 (SYSBOOT15:14=1): 24 MHz CM_CLKSEL_DPLL_DDR = 0x00003202 * DPLL_MULT = 50 (x50) * DPLL_DIV = 2 (/3) CM_DIV_M2_DPLL_DDR = 0x00000221 * CLKST = 1: M2 output clock enabled * DIVHS = 1 (/1) CM_DIV_M4_DPLL_DDR = 0x00000222 * CLKST = 1: M4 output clock enabled * DIVHS = 2 (/2) DPLL_DDR Summary -> F_input = 24 MHz -> CLKOUT_M2 = DDR_PLL_CLKOUT = 400 MHz -> CLKOUT_M4 = DLL_CLKOUT = 400 MHz EMIF: SDRAM_CONFIG = 0x61a05332 * SDRAM_TYPE = DDR3 * Bits 26:24 (reg_ddr_term) set for RZQ/4 (001b) * Bits 19:18 (reg_sdram_drive) set for RZQ/6 (00b) * Bits 17:16 (cwl) set for 5 (00b) * NARROW_MODE=1 (16-bit wide) * Bits 13:10 (CL) set for 6 * Bits 9:7 (ROWSIZE) set for 15 row bits * Bits 6:4 (IBANK) set for 8 banks * Bit 3 (EBANK) set for 1 chip select (CS0) * Bits 3:0 (PAGESIZE) set for 10 column bits EMIF: PWR_MGMT_CTRL = 0x000000a0 DDR PHY: DDR_PHY_CTRL_1 = 0x00048009 * PHY_INVERT_CLKOUT=1. * READ_LAT=9, (corresponds correctly with CL and PHY_INVERT_CLKOUT) DDR PHY: EXT_PHY_CTRL_1 = 0x00040100 DDR PHY: EXT_PHY_CTRL_36 = 0x00000177 * Configured as recommended. CTRL_DDR_ADDRCTRL_IOCTRL = 0x00000084 * Bits 9:5 control ddr_ck and ddr_ckn - Slew fastest - Drive Strength 9 mA * Bits 4:0 control all other address/control pins - Slew fastest - Drive Strength 9 mA CTRL_DDR_ADDRCTRL_WD0_IOCTRL = 0x00000000 CTRL_DDR_ADDRCTRL_WD1_IOCTRL = 0x00000000 * [ddr_a0 ] Pullup/Pulldown disabled * [ddr_a1 ] Pullup/Pulldown disabled * [ddr_a2 ] Pullup/Pulldown disabled * [ddr_a3 ] Pullup/Pulldown disabled * [ddr_a4 ] Pullup/Pulldown disabled * [ddr_a5 ] Pullup/Pulldown disabled * [ddr_a6 ] Pullup/Pulldown disabled * [ddr_a7 ] Pullup/Pulldown disabled * [ddr_a8 ] Pullup/Pulldown disabled * [ddr_a9 ] Pullup/Pulldown disabled * [ddr_a10 ] Pullup/Pulldown disabled * [ddr_a11 ] Pullup/Pulldown disabled * [ddr_a12 ] Pullup/Pulldown disabled * [ddr_a13 ] Pullup/Pulldown disabled * [ddr_a14 ] Pullup/Pulldown disabled * [ddr_a15 ] Pullup/Pulldown disabled * [ddr_ba2 ] Pullup/Pulldown disabled * [ddr_ba1 ] Pullup/Pulldown disabled * [ddr_ba0 ] Pullup/Pulldown disabled * [ddr_wen ] Pullup/Pulldown disabled * [ddr_rasn ] Pullup/Pulldown disabled * [ddr_casn ] Pullup/Pulldown disabled * [ddr_nck ] Pullup/Pulldown disabled * [ddr_ck ] Pullup/Pulldown disabled * [ddr_cke ] Pullup/Pulldown disabled * [ddr_csn1 ] Pullup/Pulldown disabled * [ddr_csn0 ] Pullup/Pulldown disabled * [ddr_resetn] Pullup/Pulldown disabled * [ddr_odt1 ] Pullup/Pulldown disabled * [ddr_odt0 ] Pullup/Pulldown disabled CTRL_DDR_DATA0_IOCTRL = 0x00000084 * ddr_d0 Pullup/Pulldown disabled * ddr_d1 Pullup/Pulldown disabled * ddr_d2 Pullup/Pulldown disabled * ddr_d3 Pullup/Pulldown disabled * ddr_d4 Pullup/Pulldown disabled * ddr_d5 Pullup/Pulldown disabled * ddr_d6 Pullup/Pulldown disabled * ddr_d7 Pullup/Pulldown disabled * ddr_dqm0 Pullup/Pulldown disabled * ddr_dqs0 and ddr_dqsn0 Pullup/Pulldown disabled * Bits 9:5 control ddr_dqs0, ddr_dqsn0 - Slew fastest - Drive Strength 9 mA * Bits 4:0 control ddr_d[7:0], dqm0 - Slew fastest - Drive Strength 9 mA CTRL_DDR_DATA1_IOCTRL = 0x00000084 * ddr_d8 Pullup/Pulldown disabled * ddr_d9 Pullup/Pulldown disabled * ddr_d10 Pullup/Pulldown disabled * ddr_d11 Pullup/Pulldown disabled * ddr_d12 Pullup/Pulldown disabled * ddr_d13 Pullup/Pulldown disabled * ddr_d14 Pullup/Pulldown disabled * ddr_d15 Pullup/Pulldown disabled * ddr_dqm1 Pullup/Pulldown disabled * ddr_dqs1 and ddr_dqsn1 Pullup/Pulldown disabled * Bits 9:5 control ddr_dqs1, ddr_dqsn1 - Slew fastest - Drive Strength 9 mA * Bits 4:0 control ddr_d[15:8], ddr_dqm1 - Slew fastest - Drive Strength 9 mA CTRL_DDR_DATA2_IOCTRL = 0x00000084 * ddr_d16 Pullup/Pulldown disabled * ddr_d17 Pullup/Pulldown disabled * ddr_d18 Pullup/Pulldown disabled * ddr_d19 Pullup/Pulldown disabled * ddr_d20 Pullup/Pulldown disabled * ddr_d21 Pullup/Pulldown disabled * ddr_d22 Pullup/Pulldown disabled * ddr_d23 Pullup/Pulldown disabled * ddr_dqm2 Pullup/Pulldown disabled * ddr_dqs2 and ddr_dqsn2 Pullup/Pulldown disabled * Bits 9:5 control ddr_dqs2, ddr_dqsn2 - Slew fastest - Drive Strength 9 mA * Bits 4:0 control ddr_d[23:16], ddr_dqm2 - Slew fastest - Drive Strength 9 mA CTRL_DDR_DATA3_IOCTRL = 0x00000084 * ddr_d24 Pullup/Pulldown disabled * ddr_d25 Pullup/Pulldown disabled * ddr_d26 Pullup/Pulldown disabled * ddr_d27 Pullup/Pulldown disabled * ddr_d28 Pullup/Pulldown disabled * ddr_d29 Pullup/Pulldown disabled * ddr_d30 Pullup/Pulldown disabled * ddr_d31 Pullup/Pulldown disabled * ddr_dqm3 Pullup/Pulldown disabled * ddr_dqs3 and ddr_dqsn3 Pullup/Pulldown disabled * Bits 9:5 control ddr_dqs3, ddr_dqsn3 - Slew fastest - Drive Strength 9 mA * Bits 4:0 control ddr_d[31:24], ddr_dqm3 - Slew fastest - Drive Strength 9 mA CONTROL: CTRL_DDR_IO = 0x00000000 * Bit 31: DDR_RESETn controlled by EMIF. CONTROL: CTRL_VTP = 0x00010167 * VTP not disabled (expected in normal operation, but not DS0). CONTROL: CTRL_VREF = 0x00000000 * VREF supplied externally (typical). CONTROL: CTRL_DDR_CKE = 0x0000000f * CKE0 controlled by EMIF (normal/ungated operation). * CKE1 controlled by EMIF (normal/ungated operation). CONTROL: CTRL_EMIF_SDRAM_CONFIG_EXT = 0x0002c163 * Bit 17: NARROW_ONLY = 1 * Bits 15:14: phy_num_of_samples = 3 -> 128 samples, full leveling * Bit 13: phy_sel_logic = 0 (Recommended) * Bit 12: phy_all_dq_mpr_rd_resp = 0 * Bits 11:09: phy_output_sts_select = 0 * Bit 8: dynamic_pwrdn_en = 1 * Bits 06:05: phy_rd_local_odt = 3, Half Thevenin load * Bit 3: dfi_clock_phase_ctrl = 0 * Bit 1: en_slice_1 = 1 (CMD PHY1) * Bit 0: en_slice_0 = 1 (CMD PHY0)