# 1 "arch/arm/boot/dts/am571x-art57xx.dts"
# 1 "<built-in>"
# 1 "<command-line>"
# 1 "arch/arm/boot/dts/am571x-art57xx.dts"
# 11 "arch/arm/boot/dts/am571x-art57xx.dts"
/dts-v1/;

# 1 "arch/arm/boot/dts/am571x-tqma57xx.dtsi" 1
# 11 "arch/arm/boot/dts/am571x-tqma57xx.dtsi"
# 1 "arch/arm/boot/dts/dra72x.dtsi" 1
# 10 "arch/arm/boot/dts/dra72x.dtsi"
# 1 "arch/arm/boot/dts/dra7.dtsi" 1
# 10 "arch/arm/boot/dts/dra7.dtsi"
# 1 "./scripts/dtc/include-prefixes/dt-bindings/bus/ti-sysc.h" 1
# 11 "arch/arm/boot/dts/dra7.dtsi" 2
# 1 "./scripts/dtc/include-prefixes/dt-bindings/clock/dra7.h" 1
# 12 "arch/arm/boot/dts/dra7.dtsi" 2
# 1 "./scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/arm-gic.h" 1
# 9 "./scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/arm-gic.h"
# 1 "./scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/irq.h" 1
# 10 "./scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/arm-gic.h" 2
# 13 "arch/arm/boot/dts/dra7.dtsi" 2
# 1 "./scripts/dtc/include-prefixes/dt-bindings/pinctrl/dra.h" 1
# 14 "arch/arm/boot/dts/dra7.dtsi" 2




/ {
 #address-cells = <2>;
 #size-cells = <2>;

 compatible = "ti,dra7xx";
 interrupt-parent = <&crossbar_mpu>;
 chosen { };

 aliases {
  i2c0 = &i2c1;
  i2c1 = &i2c2;
  i2c2 = &i2c3;
  i2c3 = &i2c4;
  i2c4 = &i2c5;
  serial0 = &uart1;
  serial1 = &uart2;
  serial2 = &uart3;
  serial3 = &uart4;
  serial4 = &uart5;
  serial5 = &uart6;
  serial6 = &uart7;
  serial7 = &uart8;
  serial8 = &uart9;
  serial9 = &uart10;
  ethernet0 = &cpsw_emac0;
  ethernet1 = &cpsw_emac1;
  d_can0 = &dcan1;
  d_can1 = &dcan2;
  spi0 = &qspi;
 };

 timer {
  compatible = "arm,armv7-timer";
  interrupts = <1 13 ((((1 << (2)) - 1) << 8) | 8)>,
        <1 14 ((((1 << (2)) - 1) << 8) | 8)>,
        <1 11 ((((1 << (2)) - 1) << 8) | 8)>,
        <1 10 ((((1 << (2)) - 1) << 8) | 8)>;
  interrupt-parent = <&gic>;
 };

 gic: interrupt-controller@48211000 {
  compatible = "arm,cortex-a15-gic";
  interrupt-controller;
  #interrupt-cells = <3>;
  reg = <0x0 0x48211000 0x0 0x1000>,
        <0x0 0x48212000 0x0 0x2000>,
        <0x0 0x48214000 0x0 0x2000>,
        <0x0 0x48216000 0x0 0x2000>;
  interrupts = <1 9 ((((1 << (2)) - 1) << 8) | 4)>;
  interrupt-parent = <&gic>;
 };

 wakeupgen: interrupt-controller@48281000 {
  compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
  interrupt-controller;
  #interrupt-cells = <3>;
  reg = <0x0 0x48281000 0x0 0x1000>;
  interrupt-parent = <&gic>;
 };

 cpus {
  #address-cells = <1>;
  #size-cells = <0>;

  cpu0: cpu@0 {
   device_type = "cpu";
   compatible = "arm,cortex-a15";
   reg = <0>;

   operating-points-v2 = <&cpu0_opp_table>;

   clocks = <&dpll_mpu_ck>;
   clock-names = "cpu";

   clock-latency = <300000>;


   #cooling-cells = <2>;

   vbb-supply = <&abb_mpu>;
  };
 };

 cpu0_opp_table: opp-table {
  compatible = "operating-points-v2-ti-cpu";
  syscon = <&scm_wkup>;

  opp_nom-1000000000 {
   opp-hz = /bits/ 64 <1000000000>;
   opp-microvolt = <1060000 850000 1150000>,
     <1060000 850000 1150000>;
   opp-supported-hw = <0xFF 0x01>;
   opp-suspend;
  };

  opp_od-1176000000 {
   opp-hz = /bits/ 64 <1176000000>;
   opp-microvolt = <1160000 885000 1160000>,
     <1160000 885000 1160000>;

   opp-supported-hw = <0xFF 0x02>;
  };

  opp_high@1500000000 {
   opp-hz = /bits/ 64 <1500000000>;
   opp-microvolt = <1210000 950000 1250000>,
     <1210000 950000 1250000>;
   opp-supported-hw = <0xFF 0x04>;
  };
 };





 soc {
  compatible = "ti,omap-infra";
  mpu {
   compatible = "ti,omap5-mpu";
   ti,hwmods = "mpu";
  };
 };
# 148 "arch/arm/boot/dts/dra7.dtsi"
 ocp {
  compatible = "ti,dra7-l3-noc", "simple-bus";
  #address-cells = <1>;
  #size-cells = <1>;
  ranges = <0x0 0x0 0x0 0xc0000000>;
  ti,hwmods = "l3_main_1", "l3_main_2";
  reg = <0x0 0x44000000 0x0 0x1000000>,
        <0x0 0x45000000 0x0 0x1000>;
  interrupts-extended = <&crossbar_mpu 0 4 4>,
          <&wakeupgen 0 10 4>;

  l4_cfg: l4@4a000000 {
   compatible = "ti,dra7-l4-cfg", "simple-bus";
   #address-cells = <1>;
   #size-cells = <1>;
   ranges = <0 0x4a000000 0x22c000>;

   scm: scm@2000 {
    compatible = "ti,dra7-scm-core", "simple-bus";
    reg = <0x2000 0x2000>;
    #address-cells = <1>;
    #size-cells = <1>;
    ranges = <0 0x2000 0x2000>;

    scm_conf: scm_conf@0 {
     compatible = "syscon", "simple-bus";
     reg = <0x0 0x1400>;
     #address-cells = <1>;
     #size-cells = <1>;
     ranges = <0 0x0 0x1400>;

     pbias_regulator: pbias_regulator@e00 {
      compatible = "ti,pbias-dra7", "ti,pbias-omap";
      reg = <0xe00 0x4>;
      syscon = <&scm_conf>;
      pbias_mmc_reg: pbias_mmc_omap5 {
       regulator-name = "pbias_mmc_omap5";
       regulator-min-microvolt = <1800000>;
       regulator-max-microvolt = <3300000>;
      };
     };

     scm_conf_clocks: clocks {
      #address-cells = <1>;
      #size-cells = <0>;
     };
    };

    dra7_pmx_core: pinmux@1400 {
     compatible = "ti,dra7-padconf",
           "pinctrl-single";
     reg = <0x1400 0x0468>;
     #address-cells = <1>;
     #size-cells = <0>;
     #pinctrl-cells = <1>;
     #interrupt-cells = <1>;
     interrupt-controller;
     pinctrl-single,register-width = <32>;
     pinctrl-single,function-mask = <0x3fffffff>;
    };

    scm_conf1: scm_conf@1c04 {
     compatible = "syscon";
     reg = <0x1c04 0x0020>;
     #syscon-cells = <2>;
    };

    scm_conf_pcie: scm_conf@1c24 {
     compatible = "syscon";
     reg = <0x1c24 0x0024>;
    };

    sdma_xbar: dma-router@b78 {
     compatible = "ti,dra7-dma-crossbar";
     reg = <0xb78 0xfc>;
     #dma-cells = <1>;
     dma-requests = <205>;
     ti,dma-safe-map = <0>;
     dma-masters = <&sdma>;
    };

    edma_xbar: dma-router@c78 {
     compatible = "ti,dra7-dma-crossbar";
     reg = <0xc78 0x7c>;
     #dma-cells = <2>;
     dma-requests = <204>;
     ti,dma-safe-map = <0>;
     dma-masters = <&edma>;
    };
   };

   cm_core_aon: cm_core_aon@5000 {
    compatible = "ti,dra7-cm-core-aon",
           "simple-bus";
    #address-cells = <1>;
    #size-cells = <1>;
    reg = <0x5000 0x2000>;
    ranges = <0 0x5000 0x2000>;

    cm_core_aon_clocks: clocks {
     #address-cells = <1>;
     #size-cells = <0>;
    };

    cm_core_aon_clockdomains: clockdomains {
    };
   };

   cm_core: cm_core@8000 {
    compatible = "ti,dra7-cm-core", "simple-bus";
    #address-cells = <1>;
    #size-cells = <1>;
    reg = <0x8000 0x3000>;
    ranges = <0 0x8000 0x3000>;

    cm_core_clocks: clocks {
     #address-cells = <1>;
     #size-cells = <0>;
    };

    cm_core_clockdomains: clockdomains {
    };
   };
  };

  l4_wkup: l4@4ae00000 {
   compatible = "ti,dra7-l4-wkup", "simple-bus";
   #address-cells = <1>;
   #size-cells = <1>;
   ranges = <0 0x4ae00000 0x3f000>;

   counter32k: counter@4000 {
    compatible = "ti,omap-counter32k";
    reg = <0x4000 0x40>;
    ti,hwmods = "counter_32k";
   };

   prm: prm@6000 {
    compatible = "ti,dra7-prm", "simple-bus";
    reg = <0x6000 0x3000>;
    interrupts = <0 6 4>;
    #address-cells = <1>;
    #size-cells = <1>;
    ranges = <0 0x6000 0x3000>;

    prm_clocks: clocks {
     #address-cells = <1>;
     #size-cells = <0>;
    };

    prm_clockdomains: clockdomains {
    };
   };

   scm_wkup: scm_conf@c000 {
    compatible = "syscon";
    reg = <0xc000 0x1000>;
   };
  };

  axi@0 {
   compatible = "simple-bus";
   #size-cells = <1>;
   #address-cells = <1>;
   ranges = <0x51000000 0x51000000 0x3000
      0x0 0x20000000 0x10000000>;




   pcie1_rc: pcie@51000000 {
    reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
    reg-names = "rc_dbics", "ti_conf", "config";
    interrupts = <0 232 0x4>, <0 233 0x4>;
    #address-cells = <3>;
    #size-cells = <2>;
    device_type = "pci";
    ranges = <0x81000000 0 0 0x03000 0 0x00010000
       0x82000000 0 0x20013000 0x13000 0 0xffed000>;
    bus-range = <0x00 0xff>;
    #interrupt-cells = <1>;
    num-lanes = <1>;
    linux,pci-domain = <0>;
    ti,hwmods = "pcie1";
    phys = <&pcie1_phy>;
    phy-names = "pcie-phy0";
    ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
    interrupt-map-mask = <0 0 0 7>;
    interrupt-map = <0 0 0 1 &pcie1_intc 1>,
      <0 0 0 2 &pcie1_intc 2>,
      <0 0 0 3 &pcie1_intc 3>,
      <0 0 0 4 &pcie1_intc 4>;
    ti,syscon-unaligned-access = <&scm_conf1 0x14 1>;
    status = "disabled";
    pcie1_intc: interrupt-controller {
     interrupt-controller;
     #address-cells = <0>;
     #interrupt-cells = <1>;
    };
   };

   pcie1_ep: pcie_ep@51000000 {
    reg = <0x51000000 0x28>, <0x51002000 0x14c>, <0x51001000 0x28>, <0x1000 0x10000000>;
    reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space";
    interrupts = <0 232 0x4>;
    num-lanes = <1>;
    num-ib-windows = <4>;
    num-ob-windows = <16>;
    ti,hwmods = "pcie1";
    phys = <&pcie1_phy>;
    phy-names = "pcie-phy0";
    ti,syscon-unaligned-access = <&scm_conf1 0x14 1>;
    ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
    status = "disabled";
   };
  };

  axi@1 {
   compatible = "simple-bus";
   #size-cells = <1>;
   #address-cells = <1>;
   ranges = <0x51800000 0x51800000 0x3000
      0x0 0x30000000 0x10000000>;
   status = "disabled";
   pcie2_rc: pcie@51800000 {
    reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
    reg-names = "rc_dbics", "ti_conf", "config";
    interrupts = <0 355 0x4>, <0 356 0x4>;
    #address-cells = <3>;
    #size-cells = <2>;
    device_type = "pci";
    ranges = <0x81000000 0 0 0x03000 0 0x00010000
       0x82000000 0 0x30013000 0x13000 0 0xffed000>;
    bus-range = <0x00 0xff>;
    #interrupt-cells = <1>;
    num-lanes = <1>;
    linux,pci-domain = <1>;
    ti,hwmods = "pcie2";
    phys = <&pcie2_phy>;
    phy-names = "pcie-phy0";
    interrupt-map-mask = <0 0 0 7>;
    interrupt-map = <0 0 0 1 &pcie2_intc 1>,
      <0 0 0 2 &pcie2_intc 2>,
      <0 0 0 3 &pcie2_intc 3>,
      <0 0 0 4 &pcie2_intc 4>;
    ti,syscon-unaligned-access = <&scm_conf1 0x14 2>;
    pcie2_intc: interrupt-controller {
     interrupt-controller;
     #address-cells = <0>;
     #interrupt-cells = <1>;
    };
   };
  };

  ocmcram1: ocmcram@40300000 {
   compatible = "mmio-sram";
   reg = <0x40300000 0x80000>;
   ranges = <0x0 0x40300000 0x80000>;
   #address-cells = <1>;
   #size-cells = <1>;
# 419 "arch/arm/boot/dts/dra7.dtsi"
   sram-hs@0 {
    compatible = "ti,secure-ram";
    reg = <0x0 0x0>;
   };
  };







  ocmcram2: ocmcram@40400000 {
   status = "disabled";
   compatible = "mmio-sram";
   reg = <0x40400000 0x100000>;
   ranges = <0x0 0x40400000 0x100000>;
   #address-cells = <1>;
   #size-cells = <1>;
  };

  ocmcram3: ocmcram@40500000 {
   status = "disabled";
   compatible = "mmio-sram";
   reg = <0x40500000 0x100000>;
   ranges = <0x0 0x40500000 0x100000>;
   #address-cells = <1>;
   #size-cells = <1>;
  };

  bandgap: bandgap@4a0021e0 {
   reg = <0x4a0021e0 0xc
    0x4a00232c 0xc
    0x4a002380 0x2c
    0x4a0023C0 0x3c
    0x4a002564 0x8
    0x4a002574 0x50>;
    compatible = "ti,dra752-bandgap";
    interrupts = <0 121 4>;
    #thermal-sensor-cells = <1>;
  };

  dsp1_system: dsp_system@40d00000 {
   compatible = "syscon";
   reg = <0x40d00000 0x100>;
  };

  dra7_iodelay_core: padconf@4844a000 {
   compatible = "ti,dra7-iodelay";
   reg = <0x4844a000 0x0d1c>;
   #address-cells = <1>;
   #size-cells = <0>;
   #pinctrl-cells = <2>;
  };

  sdma: dma-controller@4a056000 {
   compatible = "ti,omap4430-sdma";
   reg = <0x4a056000 0x1000>;
   interrupts = <0 7 4>,
         <0 8 4>,
         <0 9 4>,
         <0 10 4>;
   #dma-cells = <1>;
   dma-channels = <32>;
   dma-requests = <127>;
   ti,hwmods = "dma_system";
  };

  edma: edma@43300000 {
   compatible = "ti,edma3-tpcc";
   ti,hwmods = "tpcc";
   reg = <0x43300000 0x100000>;
   reg-names = "edma3_cc";
   interrupts = <0 361 4>,
         <0 360 4>,
         <0 359 4>;
   interrupt-names = "edma3_ccint", "edma3_mperr",
       "edma3_ccerrint";
   dma-requests = <64>;
   #dma-cells = <2>;

   ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>;







  };

  edma_tptc0: tptc@43400000 {
   compatible = "ti,edma3-tptc";
   ti,hwmods = "tptc0";
   reg = <0x43400000 0x100000>;
   interrupts = <0 370 4>;
   interrupt-names = "edma3_tcerrint";
  };

  edma_tptc1: tptc@43500000 {
   compatible = "ti,edma3-tptc";
   ti,hwmods = "tptc1";
   reg = <0x43500000 0x100000>;
   interrupts = <0 371 4>;
   interrupt-names = "edma3_tcerrint";
  };

  gpio1: gpio@4ae10000 {
   compatible = "ti,omap4-gpio";
   reg = <0x4ae10000 0x200>;
   interrupts = <0 24 4>;
   ti,hwmods = "gpio1";
   gpio-controller;
   #gpio-cells = <2>;
   interrupt-controller;
   #interrupt-cells = <2>;
  };

  gpio2: gpio@48055000 {
   compatible = "ti,omap4-gpio";
   reg = <0x48055000 0x200>;
   interrupts = <0 25 4>;
   ti,hwmods = "gpio2";
   gpio-controller;
   #gpio-cells = <2>;
   interrupt-controller;
   #interrupt-cells = <2>;
  };

  gpio3: gpio@48057000 {
   compatible = "ti,omap4-gpio";
   reg = <0x48057000 0x200>;
   interrupts = <0 26 4>;
   ti,hwmods = "gpio3";
   gpio-controller;
   #gpio-cells = <2>;
   interrupt-controller;
   #interrupt-cells = <2>;
  };

  gpio4: gpio@48059000 {
   compatible = "ti,omap4-gpio";
   reg = <0x48059000 0x200>;
   interrupts = <0 27 4>;
   ti,hwmods = "gpio4";
   gpio-controller;
   #gpio-cells = <2>;
   interrupt-controller;
   #interrupt-cells = <2>;
  };

  gpio5: gpio@4805b000 {
   compatible = "ti,omap4-gpio";
   reg = <0x4805b000 0x200>;
   interrupts = <0 28 4>;
   ti,hwmods = "gpio5";
   gpio-controller;
   #gpio-cells = <2>;
   interrupt-controller;
   #interrupt-cells = <2>;
  };

  gpio6: gpio@4805d000 {
   compatible = "ti,omap4-gpio";
   reg = <0x4805d000 0x200>;
   interrupts = <0 29 4>;
   ti,hwmods = "gpio6";
   gpio-controller;
   #gpio-cells = <2>;
   interrupt-controller;
   #interrupt-cells = <2>;
  };

  gpio7: gpio@48051000 {
   compatible = "ti,omap4-gpio";
   reg = <0x48051000 0x200>;
   interrupts = <0 30 4>;
   ti,hwmods = "gpio7";
   gpio-controller;
   #gpio-cells = <2>;
   interrupt-controller;
   #interrupt-cells = <2>;
  };

  gpio8: gpio@48053000 {
   compatible = "ti,omap4-gpio";
   reg = <0x48053000 0x200>;
   interrupts = <0 116 4>;
   ti,hwmods = "gpio8";
   gpio-controller;
   #gpio-cells = <2>;
   interrupt-controller;
   #interrupt-cells = <2>;
  };

  uart1: serial@4806a000 {
   compatible = "ti,dra742-uart", "ti,omap4-uart";
   reg = <0x4806a000 0x100>;
   interrupts-extended = <&crossbar_mpu 0 67 4>;
   ti,hwmods = "uart1";
   clock-frequency = <48000000>;
   status = "disabled";
   dmas = <&sdma_xbar 49>, <&sdma_xbar 50>;
   dma-names = "tx", "rx";
  };

  uart2: serial@4806c000 {
   compatible = "ti,dra742-uart", "ti,omap4-uart";
   reg = <0x4806c000 0x100>;
   interrupts = <0 68 4>;
   ti,hwmods = "uart2";
   clock-frequency = <48000000>;
   status = "disabled";
   dmas = <&sdma_xbar 51>, <&sdma_xbar 52>;
   dma-names = "tx", "rx";
  };

  uart3: serial@48020000 {
   compatible = "ti,dra742-uart", "ti,omap4-uart";
   reg = <0x48020000 0x100>;
   interrupts = <0 69 4>;
   ti,hwmods = "uart3";
   clock-frequency = <48000000>;
   status = "disabled";
   dmas = <&sdma_xbar 53>, <&sdma_xbar 54>;
   dma-names = "tx", "rx";
  };

  uart4: serial@4806e000 {
   compatible = "ti,dra742-uart", "ti,omap4-uart";
   reg = <0x4806e000 0x100>;
   interrupts = <0 65 4>;
   ti,hwmods = "uart4";
   clock-frequency = <48000000>;
                        status = "disabled";
   dmas = <&sdma_xbar 55>, <&sdma_xbar 56>;
   dma-names = "tx", "rx";
  };

  uart5: serial@48066000 {
   compatible = "ti,dra742-uart", "ti,omap4-uart";
   reg = <0x48066000 0x100>;
   interrupts = <0 100 4>;
   ti,hwmods = "uart5";
   clock-frequency = <48000000>;
   status = "disabled";
   dmas = <&sdma_xbar 63>, <&sdma_xbar 64>;
   dma-names = "tx", "rx";
  };

  uart6: serial@48068000 {
   compatible = "ti,dra742-uart", "ti,omap4-uart";
   reg = <0x48068000 0x100>;
   interrupts = <0 101 4>;
   ti,hwmods = "uart6";
   clock-frequency = <48000000>;
   status = "disabled";
   dmas = <&sdma_xbar 79>, <&sdma_xbar 80>;
   dma-names = "tx", "rx";
  };

  uart7: serial@48420000 {
   compatible = "ti,dra742-uart", "ti,omap4-uart";
   reg = <0x48420000 0x100>;
   interrupts = <0 218 4>;
   ti,hwmods = "uart7";
   clock-frequency = <48000000>;
   status = "disabled";
  };

  uart8: serial@48422000 {
   compatible = "ti,dra742-uart", "ti,omap4-uart";
   reg = <0x48422000 0x100>;
   interrupts = <0 219 4>;
   ti,hwmods = "uart8";
   clock-frequency = <48000000>;
   status = "disabled";
  };

  uart9: serial@48424000 {
   compatible = "ti,dra742-uart", "ti,omap4-uart";
   reg = <0x48424000 0x100>;
   interrupts = <0 220 4>;
   ti,hwmods = "uart9";
   clock-frequency = <48000000>;
   status = "disabled";
  };

  uart10: serial@4ae2b000 {
   compatible = "ti,dra742-uart", "ti,omap4-uart";
   reg = <0x4ae2b000 0x100>;
   interrupts = <0 221 4>;
   ti,hwmods = "uart10";
   clock-frequency = <48000000>;
   status = "disabled";
  };

  mailbox1: mailbox@4a0f4000 {
   compatible = "ti,omap4-mailbox";
   reg = <0x4a0f4000 0x200>;
   interrupts = <0 21 4>,
         <0 135 4>,
         <0 134 4>;
   ti,hwmods = "mailbox1";
   #mbox-cells = <1>;
   ti,mbox-num-users = <3>;
   ti,mbox-num-fifos = <8>;
   status = "disabled";
  };

  mailbox2: mailbox@4883a000 {
   compatible = "ti,omap4-mailbox";
   reg = <0x4883a000 0x200>;
   interrupts = <0 237 4>,
         <0 238 4>,
         <0 239 4>,
         <0 240 4>;
   ti,hwmods = "mailbox2";
   #mbox-cells = <1>;
   ti,mbox-num-users = <4>;
   ti,mbox-num-fifos = <12>;
   status = "disabled";
  };

  mailbox3: mailbox@4883c000 {
   compatible = "ti,omap4-mailbox";
   reg = <0x4883c000 0x200>;
   interrupts = <0 241 4>,
         <0 242 4>,
         <0 243 4>,
         <0 244 4>;
   ti,hwmods = "mailbox3";
   #mbox-cells = <1>;
   ti,mbox-num-users = <4>;
   ti,mbox-num-fifos = <12>;
   status = "disabled";
  };

  mailbox4: mailbox@4883e000 {
   compatible = "ti,omap4-mailbox";
   reg = <0x4883e000 0x200>;
   interrupts = <0 245 4>,
         <0 246 4>,
         <0 247 4>,
         <0 248 4>;
   ti,hwmods = "mailbox4";
   #mbox-cells = <1>;
   ti,mbox-num-users = <4>;
   ti,mbox-num-fifos = <12>;
   status = "disabled";
  };

  mailbox5: mailbox@48840000 {
   compatible = "ti,omap4-mailbox";
   reg = <0x48840000 0x200>;
   interrupts = <0 249 4>,
         <0 250 4>,
         <0 251 4>,
         <0 252 4>;
   ti,hwmods = "mailbox5";
   #mbox-cells = <1>;
   ti,mbox-num-users = <4>;
   ti,mbox-num-fifos = <12>;
   status = "disabled";
  };

  mailbox6: mailbox@48842000 {
   compatible = "ti,omap4-mailbox";
   reg = <0x48842000 0x200>;
   interrupts = <0 253 4>,
         <0 254 4>,
         <0 255 4>,
         <0 256 4>;
   ti,hwmods = "mailbox6";
   #mbox-cells = <1>;
   ti,mbox-num-users = <4>;
   ti,mbox-num-fifos = <12>;
   status = "disabled";
  };

  mailbox7: mailbox@48844000 {
   compatible = "ti,omap4-mailbox";
   reg = <0x48844000 0x200>;
   interrupts = <0 257 4>,
         <0 258 4>,
         <0 259 4>,
         <0 260 4>;
   ti,hwmods = "mailbox7";
   #mbox-cells = <1>;
   ti,mbox-num-users = <4>;
   ti,mbox-num-fifos = <12>;
   status = "disabled";
  };

  mailbox8: mailbox@48846000 {
   compatible = "ti,omap4-mailbox";
   reg = <0x48846000 0x200>;
   interrupts = <0 261 4>,
         <0 262 4>,
         <0 263 4>,
         <0 264 4>;
   ti,hwmods = "mailbox8";
   #mbox-cells = <1>;
   ti,mbox-num-users = <4>;
   ti,mbox-num-fifos = <12>;
   status = "disabled";
  };

  mailbox9: mailbox@4885e000 {
   compatible = "ti,omap4-mailbox";
   reg = <0x4885e000 0x200>;
   interrupts = <0 265 4>,
         <0 266 4>,
         <0 267 4>,
         <0 268 4>;
   ti,hwmods = "mailbox9";
   #mbox-cells = <1>;
   ti,mbox-num-users = <4>;
   ti,mbox-num-fifos = <12>;
   status = "disabled";
  };

  mailbox10: mailbox@48860000 {
   compatible = "ti,omap4-mailbox";
   reg = <0x48860000 0x200>;
   interrupts = <0 269 4>,
         <0 270 4>,
         <0 271 4>,
         <0 272 4>;
   ti,hwmods = "mailbox10";
   #mbox-cells = <1>;
   ti,mbox-num-users = <4>;
   ti,mbox-num-fifos = <12>;
   status = "disabled";
  };

  mailbox11: mailbox@48862000 {
   compatible = "ti,omap4-mailbox";
   reg = <0x48862000 0x200>;
   interrupts = <0 273 4>,
         <0 274 4>,
         <0 275 4>,
         <0 276 4>;
   ti,hwmods = "mailbox11";
   #mbox-cells = <1>;
   ti,mbox-num-users = <4>;
   ti,mbox-num-fifos = <12>;
   status = "disabled";
  };

  mailbox12: mailbox@48864000 {
   compatible = "ti,omap4-mailbox";
   reg = <0x48864000 0x200>;
   interrupts = <0 277 4>,
         <0 278 4>,
         <0 279 4>,
         <0 280 4>;
   ti,hwmods = "mailbox12";
   #mbox-cells = <1>;
   ti,mbox-num-users = <4>;
   ti,mbox-num-fifos = <12>;
   status = "disabled";
  };

  mailbox13: mailbox@48802000 {
   compatible = "ti,omap4-mailbox";
   reg = <0x48802000 0x200>;
   interrupts = <0 379 4>,
         <0 380 4>,
         <0 381 4>,
         <0 382 4>;
   ti,hwmods = "mailbox13";
   #mbox-cells = <1>;
   ti,mbox-num-users = <4>;
   ti,mbox-num-fifos = <12>;
   status = "disabled";
  };

  timer1: timer@4ae18000 {
   compatible = "ti,omap5430-timer";
   reg = <0x4ae18000 0x80>;
   interrupts = <0 32 4>;
   ti,hwmods = "timer1";
   ti,timer-alwon;
   clock-names = "fck";
   clocks = <&wkupaon_clkctrl ((0x40) - 0x20) 24>;
  };

  timer2: timer@48032000 {
   compatible = "ti,omap5430-timer";
   reg = <0x48032000 0x80>;
   interrupts = <0 33 4>;
   ti,hwmods = "timer2";
   clocks = <&l4per_clkctrl ((0x38) - 0x0) 24>;
   clock-names = "fck";
  };

  timer3: timer@48034000 {
   compatible = "ti,omap5430-timer";
   reg = <0x48034000 0x80>;
   interrupts = <0 34 4>;
   ti,hwmods = "timer3";
   clocks = <&l4per_clkctrl ((0x40) - 0x0) 24>;
   clock-names = "fck";
  };

  timer4: timer@48036000 {
   compatible = "ti,omap5430-timer";
   reg = <0x48036000 0x80>;
   interrupts = <0 35 4>;
   ti,hwmods = "timer4";
   clocks = <&l4per_clkctrl ((0x48) - 0x0) 24>;
   clock-names = "fck";
  };

  timer5: timer@48820000 {
   compatible = "ti,omap5430-timer";
   reg = <0x48820000 0x80>;
   interrupts = <0 36 4>;
   ti,hwmods = "timer5";
   clocks = <&ipu_clkctrl ((0x58) - 0x40) 24>;
   clock-names = "fck";
  };

  timer6: timer@48822000 {
   compatible = "ti,omap5430-timer";
   reg = <0x48822000 0x80>;
   interrupts = <0 37 4>;
   ti,hwmods = "timer6";
   clocks = <&ipu_clkctrl ((0x60) - 0x40) 24>;
   clock-names = "fck";
  };

  timer7: timer@48824000 {
   compatible = "ti,omap5430-timer";
   reg = <0x48824000 0x80>;
   interrupts = <0 38 4>;
   ti,hwmods = "timer7";
   clocks = <&ipu_clkctrl ((0x68) - 0x40) 24>;
   clock-names = "fck";
  };

  timer8: timer@48826000 {
   compatible = "ti,omap5430-timer";
   reg = <0x48826000 0x80>;
   interrupts = <0 39 4>;
   ti,hwmods = "timer8";
   clocks = <&ipu_clkctrl ((0x70) - 0x40) 24>;
   clock-names = "fck";
  };

  timer9: timer@4803e000 {
   compatible = "ti,omap5430-timer";
   reg = <0x4803e000 0x80>;
   interrupts = <0 40 4>;
   ti,hwmods = "timer9";
   clocks = <&l4per_clkctrl ((0x50) - 0x0) 24>;
   clock-names = "fck";
  };

  timer10: timer@48086000 {
   compatible = "ti,omap5430-timer";
   reg = <0x48086000 0x80>;
   interrupts = <0 41 4>;
   ti,hwmods = "timer10";
   clocks = <&l4per_clkctrl ((0x28) - 0x0) 24>;
   clock-names = "fck";
  };

  timer11: timer@48088000 {
   compatible = "ti,omap5430-timer";
   reg = <0x48088000 0x80>;
   interrupts = <0 42 4>;
   ti,hwmods = "timer11";
   clocks = <&l4per_clkctrl ((0x30) - 0x0) 24>;
   clock-names = "fck";
  };

  timer12: timer@4ae20000 {
   compatible = "ti,omap5430-timer";
   reg = <0x4ae20000 0x80>;
   interrupts = <0 90 4>;
   ti,hwmods = "timer12";
   ti,timer-alwon;
   ti,timer-secure;
   clocks = <&wkupaon_clkctrl ((0x48) - 0x20) 24>;
   clock-names = "fck";
  };

  timer13: timer@48828000 {
   compatible = "ti,omap5430-timer";
   reg = <0x48828000 0x80>;
   interrupts = <0 339 4>;
   ti,hwmods = "timer13";
   clocks = <&l4per_clkctrl ((0xc8) - 0x0) 24>;
   clock-names = "fck";
  };

  timer14: timer@4882a000 {
   compatible = "ti,omap5430-timer";
   reg = <0x4882a000 0x80>;
   interrupts = <0 340 4>;
   ti,hwmods = "timer14";
   clocks = <&l4per_clkctrl ((0xd0) - 0x0) 24>;
   clock-names = "fck";
  };

  timer15: timer@4882c000 {
   compatible = "ti,omap5430-timer";
   reg = <0x4882c000 0x80>;
   interrupts = <0 341 4>;
   ti,hwmods = "timer15";
   clocks = <&l4per_clkctrl ((0xd8) - 0x0) 24>;
   clock-names = "fck";
  };

  timer16: timer@4882e000 {
   compatible = "ti,omap5430-timer";
   reg = <0x4882e000 0x80>;
   interrupts = <0 342 4>;
   ti,hwmods = "timer16";
   clocks = <&l4per_clkctrl ((0x130) - 0x0) 24>;
   clock-names = "fck";
   assigned-clocks = <&l4per_clkctrl ((0x130) - 0x0) 24>;
   assigned-clock-parents = <&abe_giclk_div>;
  };

  wdt2: wdt@4ae14000 {
   compatible = "ti,omap3-wdt";
   reg = <0x4ae14000 0x80>;
   interrupts = <0 75 4>;
   ti,hwmods = "wd_timer2";
  };

  hwspinlock: spinlock@4a0f6000 {
   compatible = "ti,omap4-hwspinlock";
   reg = <0x4a0f6000 0x1000>;
   ti,hwmods = "spinlock";
   #hwlock-cells = <1>;
  };

  dmm@4e000000 {
   compatible = "ti,omap5-dmm";
   reg = <0x4e000000 0x800>;
   interrupts = <0 108 4>;
   ti,hwmods = "dmm";
  };

  ipu1: ipu@58820000 {
   compatible = "ti,dra7-ipu";
   reg = <0x58820000 0x10000>;
   reg-names = "l2ram";
   ti,hwmods = "ipu1";
   iommus = <&mmu_ipu1>;
   ti,rproc-standby-info = <0x4a005520>;
   status = "disabled";
  };

  ipu2: ipu@55020000 {
   compatible = "ti,dra7-ipu";
   reg = <0x55020000 0x10000>;
   reg-names = "l2ram";
   ti,hwmods = "ipu2";
   iommus = <&mmu_ipu2>;
   ti,rproc-standby-info = <0x4a008920>;
   status = "disabled";
  };

  dsp1: dsp@40800000 {
   compatible = "ti,dra7-dsp";
   reg = <0x40800000 0x48000>,
         <0x40e00000 0x8000>,
         <0x40f00000 0x8000>;
   reg-names = "l2ram", "l1pram", "l1dram";
   ti,hwmods = "dsp1";
   syscon-bootreg = <&scm_conf 0x55c>;
   iommus = <&mmu0_dsp1>, <&mmu1_dsp1>;
   ti,rproc-standby-info = <0x4a005420>;
   status = "disabled";
  };

  i2c1: i2c@48070000 {
   compatible = "ti,omap4-i2c";
   reg = <0x48070000 0x100>;
   interrupts = <0 51 4>;
   #address-cells = <1>;
   #size-cells = <0>;
   ti,hwmods = "i2c1";
   status = "disabled";
  };

  i2c2: i2c@48072000 {
   compatible = "ti,omap4-i2c";
   reg = <0x48072000 0x100>;
   interrupts = <0 52 4>;
   #address-cells = <1>;
   #size-cells = <0>;
   ti,hwmods = "i2c2";
   status = "disabled";
  };

  i2c3: i2c@48060000 {
   compatible = "ti,omap4-i2c";
   reg = <0x48060000 0x100>;
   interrupts = <0 56 4>;
   #address-cells = <1>;
   #size-cells = <0>;
   ti,hwmods = "i2c3";
   status = "disabled";
  };

  i2c4: i2c@4807a000 {
   compatible = "ti,omap4-i2c";
   reg = <0x4807a000 0x100>;
   interrupts = <0 57 4>;
   #address-cells = <1>;
   #size-cells = <0>;
   ti,hwmods = "i2c4";
   status = "disabled";
  };

  i2c5: i2c@4807c000 {
   compatible = "ti,omap4-i2c";
   reg = <0x4807c000 0x100>;
   interrupts = <0 55 4>;
   #address-cells = <1>;
   #size-cells = <0>;
   ti,hwmods = "i2c5";
   status = "disabled";
  };

  mmc1: mmc@4809c000 {
   compatible = "ti,dra7-sdhci";
   reg = <0x4809c000 0x400>;
   interrupts = <0 78 4>;
   ti,hwmods = "mmc1";
   status = "disabled";
   pbias-supply = <&pbias_mmc_reg>;
   max-frequency = <192000000>;
   mmc-ddr-1_8v;
   mmc-ddr-3_3v;
  };

  hdqw1w: 1w@480b2000 {
   compatible = "ti,omap3-1w";
   reg = <0x480b2000 0x1000>;
   interrupts = <0 53 4>;
   ti,hwmods = "hdq1w";
  };

  mmc2: mmc@480b4000 {
   compatible = "ti,dra7-sdhci";
   reg = <0x480b4000 0x400>;
   interrupts = <0 81 4>;
   ti,hwmods = "mmc2";
   status = "disabled";
   max-frequency = <192000000>;

   sdhci-caps-mask = <0x7 0x0>;
   mmc-hs200-1_8v;
   mmc-ddr-1_8v;
   mmc-ddr-3_3v;
  };

  mmc3: mmc@480ad000 {
   compatible = "ti,dra7-sdhci";
   reg = <0x480ad000 0x400>;
   interrupts = <0 89 4>;
   ti,hwmods = "mmc3";
   status = "disabled";

   max-frequency = <64000000>;

   sdhci-caps-mask = <0x0 0x400000>;
  };

  mmc4: mmc@480d1000 {
   compatible = "ti,dra7-sdhci";
   reg = <0x480d1000 0x400>;
   interrupts = <0 91 4>;
   ti,hwmods = "mmc4";
   status = "disabled";
   max-frequency = <192000000>;

   sdhci-caps-mask = <0x0 0x400000>;
  };

  mmu0_dsp1: mmu@40d01000 {
   compatible = "ti,dra7-dsp-iommu";
   reg = <0x40d01000 0x100>;
   interrupts = <0 23 4>;
   ti,hwmods = "mmu0_dsp1";
   #iommu-cells = <0>;
   ti,syscon-mmuconfig = <&dsp1_system 0x0>;
  };

  mmu1_dsp1: mmu@40d02000 {
   compatible = "ti,dra7-dsp-iommu";
   reg = <0x40d02000 0x100>;
   interrupts = <0 145 4>;
   ti,hwmods = "mmu1_dsp1";
   #iommu-cells = <0>;
   ti,syscon-mmuconfig = <&dsp1_system 0x1>;
  };

  mmu_ipu1: mmu@58882000 {
   compatible = "ti,dra7-iommu";
   reg = <0x58882000 0x100>;
   interrupts = <0 395 4>;
   ti,hwmods = "mmu_ipu1";
   #iommu-cells = <0>;
   ti,iommu-bus-err-back;
  };

  mmu_ipu2: mmu@55082000 {
   compatible = "ti,dra7-iommu";
   reg = <0x55082000 0x100>;
   interrupts = <0 396 4>;
   ti,hwmods = "mmu_ipu2";
   #iommu-cells = <0>;
   ti,iommu-bus-err-back;
  };

  pruss_soc_bus1: pruss-soc-bus@4b226004 {
   compatible = "ti,am5728-pruss-soc-bus";
   reg = <0x4b226004 0x4>;
   ti,hwmods = "pruss1";
   #address-cells = <1>;
   #size-cells = <1>;
   ranges;
   status = "disabled";

   pruss1: pruss@4b200000 {
    compatible = "ti,am5728-pruss";
    reg = <0x4b200000 0x80000>;
    interrupts = <0 186 4>,
          <0 187 4>,
          <0 188 4>,
          <0 189 4>,
          <0 190 4>,
          <0 191 4>,
          <0 192 4>,
          <0 193 4>;
    interrupt-names = "host2", "host3", "host4",
        "host5", "host6", "host7",
        "host8", "host9";
    #address-cells = <1>;
    #size-cells = <1>;
    ranges;
    status = "disabled";

    pruss1_mem: memories@4b200000 {
     reg = <0x4b200000 0x2000>,
           <0x4b202000 0x2000>,
           <0x4b210000 0x8000>,
           <0x4b22e000 0x31c>,
           <0x4b230000 0x60>;
     reg-names = "dram0", "dram1",
          "shrdram2", "iep", "ecap";
    };

    pruss1_cfg: cfg@4b226000 {
     compatible = "syscon";
     reg = <0x4b226000 0x2000>;
    };

    pruss1_mii_rt: mii-rt@4b232000 {
     compatible = "syscon";
     reg = <0x4b232000 0x58>;
    };

    pruss1_intc: interrupt-controller@4b220000 {
     compatible = "ti,am5728-pruss-intc";
     reg = <0x4b220000 0x2000>;
     interrupt-controller;
     #interrupt-cells = <1>;
    };

    pru1_0: pru@4b234000 {
     compatible = "ti,am5728-pru";
     reg = <0x4b234000 0x3000>,
           <0x4b222000 0x400>,
           <0x4b222400 0x100>;
     reg-names = "iram", "control", "debug";
     firmware-name = "am57xx-pru1_0-fw";
     interrupt-parent = <&pruss1_intc>;
     interrupts = <16>, <17>;
     interrupt-names = "vring", "kick";
    };

    pru1_1: pru@4b238000 {
     compatible = "ti,am5728-pru";
     reg = <0x4b238000 0x3000>,
           <0x4b224000 0x400>,
           <0x4b224400 0x100>;
     reg-names = "iram", "control", "debug";
     firmware-name = "am57xx-pru1_1-fw";
     interrupt-parent = <&pruss1_intc>;
     interrupts = <18>, <19>;
     interrupt-names = "vring", "kick";
    };

    pruss1_mdio: mdio@4b232400 {
     compatible = "ti,davinci_mdio";
     reg = <0x4b232400 0x90>;
     #address-cells = <1>;
     #size-cells = <0>;
     clocks = <&dpll_gmac_h13x2_ck>;
     clock-names = "fck";
     bus_freq = <1000000>;
     status = "disabled";
    };
   };
  };

  pruss_soc_bus2: pruss-soc-bus@4b2a6004 {
   compatible = "ti,am5728-pruss-soc-bus";
   reg = <0x4b2a6004 0x4>;
   ti,hwmods = "pruss2";
   #address-cells = <1>;
   #size-cells = <1>;
   ranges;
   status = "disabled";

   pruss2: pruss@4b280000 {
    compatible = "ti,am5728-pruss";
    reg = <0x4b280000 0x80000>;
    interrupts = <0 196 4>,
          <0 197 4>,
          <0 198 4>,
          <0 199 4>,
          <0 200 4>,
          <0 201 4>,
          <0 202 4>,
          <0 203 4>;
    interrupt-names = "host2", "host3", "host4",
        "host5", "host6", "host7",
        "host8", "host9";
    #address-cells = <1>;
    #size-cells = <1>;
    ranges;
    status = "disabled";

    pruss2_mem: memories@4b280000 {
     reg = <0x4b280000 0x2000>,
           <0x4b282000 0x2000>,
           <0x4b290000 0x8000>,
           <0x4b2ae000 0x31c>,
           <0x4b2b0000 0x60>;
     reg-names = "dram0", "dram1",
          "shrdram2", "iep", "ecap";
    };

    pruss2_cfg: cfg@4b2a6000 {
     compatible = "syscon";
     reg = <0x4b2a6000 0x2000>;
    };

    pruss2_mii_rt: mii-rt@4b2b2000 {
     compatible = "syscon";
     reg = <0x4b2b2000 0x58>;
    };

    pruss2_intc: interrupt-controller@4b2a0000 {
     compatible = "ti,am5728-pruss-intc";
     reg = <0x4b2a0000 0x2000>;
     interrupt-controller;
     #interrupt-cells = <1>;
    };

    pru2_0: pru@4b2b4000 {
     compatible = "ti,am5728-pru";
     reg = <0x4b2b4000 0x3000>,
           <0x4b2a2000 0x400>,
           <0x4b2a2400 0x100>;
     reg-names = "iram", "control", "debug";
     firmware-name = "am57xx-pru2_0-fw";
     interrupt-parent = <&pruss2_intc>;
     interrupts = <16>, <17>;
     interrupt-names = "vring", "kick";
    };

    pru2_1: pru@4b2b8000 {
     compatible = "ti,am5728-pru";
     reg = <0x4b2b8000 0x3000>,
           <0x4b2a4000 0x400>,
           <0x4b2a4400 0x100>;
     reg-names = "iram", "control", "debug";
     firmware-name = "am57xx-pru2_1-fw";
     interrupt-parent = <&pruss2_intc>;
     interrupts = <18>, <19>;
     interrupt-names = "vring", "kick";
    };

    pruss2_mdio: mdio@4b2b2400 {
     compatible = "ti,davinci_mdio";
     reg = <0x4b2b2400 0x90>;
     #address-cells = <1>;
     #size-cells = <0>;
     clocks = <&dpll_gmac_h13x2_ck>;
     clock-names = "fck";
     bus_freq = <1000000>;
     status = "disabled";
    };
   };
  };

  abb_mpu: regulator-abb-mpu {
   compatible = "ti,abb-v3";
   regulator-name = "abb_mpu";
   #address-cells = <0>;
   #size-cells = <0>;
   clocks = <&sys_clkin1>;
   ti,settling-time = <50>;
   ti,clock-cycles = <16>;

   reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
         <0x4ae06014 0x4>, <0x4a003b20 0xc>,
         <0x4ae0c158 0x4>;
   reg-names = "setup-address", "control-address",
        "int-address", "efuse-address",
        "ldo-address";
   ti,tranxdone-status-mask = <0x80>;

   ti,ldovbb-override-mask = <0x400>;

   ti,ldovbb-vset-mask = <0x1F>;





   ti,abb_info = <

   1060000 0 0x0 0 0x02000000 0x01F00000
   1160000 0 0x4 0 0x02000000 0x01F00000
   1210000 0 0x8 0 0x02000000 0x01F00000
   >;
  };

  abb_ivahd: regulator-abb-ivahd {
   compatible = "ti,abb-v3";
   regulator-name = "abb_ivahd";
   #address-cells = <0>;
   #size-cells = <0>;
   clocks = <&sys_clkin1>;
   ti,settling-time = <50>;
   ti,clock-cycles = <16>;

   reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
         <0x4ae06010 0x4>, <0x4a0025cc 0xc>,
         <0x4a002470 0x4>;
   reg-names = "setup-address", "control-address",
        "int-address", "efuse-address",
        "ldo-address";
   ti,tranxdone-status-mask = <0x40000000>;

   ti,ldovbb-override-mask = <0x400>;

   ti,ldovbb-vset-mask = <0x1F>;





   ti,abb_info = <

   1055000 0 0x0 0 0x02000000 0x01F00000
   1150000 0 0x4 0 0x02000000 0x01F00000
   1250000 0 0x8 0 0x02000000 0x01F00000
   >;
  };

  abb_dspeve: regulator-abb-dspeve {
   compatible = "ti,abb-v3";
   regulator-name = "abb_dspeve";
   #address-cells = <0>;
   #size-cells = <0>;
   clocks = <&sys_clkin1>;
   ti,settling-time = <50>;
   ti,clock-cycles = <16>;

   reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
         <0x4ae06010 0x4>, <0x4a0025e0 0xc>,
         <0x4a00246c 0x4>;
   reg-names = "setup-address", "control-address",
        "int-address", "efuse-address",
        "ldo-address";
   ti,tranxdone-status-mask = <0x20000000>;

   ti,ldovbb-override-mask = <0x400>;

   ti,ldovbb-vset-mask = <0x1F>;





   ti,abb_info = <

   1055000 0 0x0 0 0x02000000 0x01F00000
   1150000 0 0x4 0 0x02000000 0x01F00000
   1250000 0 0x8 0 0x02000000 0x01F00000
   >;
  };

  abb_gpu: regulator-abb-gpu {
   compatible = "ti,abb-v3";
   regulator-name = "abb_gpu";
   #address-cells = <0>;
   #size-cells = <0>;
   clocks = <&sys_clkin1>;
   ti,settling-time = <50>;
   ti,clock-cycles = <16>;

   reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
         <0x4ae06010 0x4>, <0x4a003b08 0xc>,
         <0x4ae0c154 0x4>;
   reg-names = "setup-address", "control-address",
        "int-address", "efuse-address",
        "ldo-address";
   ti,tranxdone-status-mask = <0x10000000>;

   ti,ldovbb-override-mask = <0x400>;

   ti,ldovbb-vset-mask = <0x1F>;





   ti,abb_info = <

   1090000 0 0x0 0 0x02000000 0x01F00000
   1210000 0 0x4 0 0x02000000 0x01F00000
   1280000 0 0x8 0 0x02000000 0x01F00000
   >;
  };

  mcspi1: spi@48098000 {
   compatible = "ti,omap4-mcspi";
   reg = <0x48098000 0x200>;
   interrupts = <0 60 4>;
   #address-cells = <1>;
   #size-cells = <0>;
   ti,hwmods = "mcspi1";
   ti,spi-num-cs = <4>;
   dmas = <&sdma_xbar 35>,
          <&sdma_xbar 36>,
          <&sdma_xbar 37>,
          <&sdma_xbar 38>,
          <&sdma_xbar 39>,
          <&sdma_xbar 40>,
          <&sdma_xbar 41>,
          <&sdma_xbar 42>;
   dma-names = "tx0", "rx0", "tx1", "rx1",
        "tx2", "rx2", "tx3", "rx3";
   status = "disabled";
  };

  mcspi2: spi@4809a000 {
   compatible = "ti,omap4-mcspi";
   reg = <0x4809a000 0x200>;
   interrupts = <0 61 4>;
   #address-cells = <1>;
   #size-cells = <0>;
   ti,hwmods = "mcspi2";
   ti,spi-num-cs = <2>;
   dmas = <&sdma_xbar 43>,
          <&sdma_xbar 44>,
          <&sdma_xbar 45>,
          <&sdma_xbar 46>;
   dma-names = "tx0", "rx0", "tx1", "rx1";
   status = "disabled";
  };

  mcspi3: spi@480b8000 {
   compatible = "ti,omap4-mcspi";
   reg = <0x480b8000 0x200>;
   interrupts = <0 86 4>;
   #address-cells = <1>;
   #size-cells = <0>;
   ti,hwmods = "mcspi3";
   ti,spi-num-cs = <2>;
   dmas = <&sdma_xbar 15>, <&sdma_xbar 16>;
   dma-names = "tx0", "rx0";
   status = "disabled";
  };

  mcspi4: spi@480ba000 {
   compatible = "ti,omap4-mcspi";
   reg = <0x480ba000 0x200>;
   interrupts = <0 43 4>;
   #address-cells = <1>;
   #size-cells = <0>;
   ti,hwmods = "mcspi4";
   ti,spi-num-cs = <1>;
   dmas = <&sdma_xbar 70>, <&sdma_xbar 71>;
   dma-names = "tx0", "rx0";
   status = "disabled";
  };

  qspi: spi@4b300000 {
   compatible = "ti,dra7xxx-qspi";
   reg = <0x4b300000 0x100>,
         <0x5c000000 0x4000000>;
   reg-names = "qspi_base", "qspi_mmap";
   syscon-chipselects = <&scm_conf 0x558>;
   #address-cells = <1>;
   #size-cells = <0>;
   ti,hwmods = "qspi";
   clocks = <&l4per_clkctrl ((0x138) - 0x0) 25>;
   clock-names = "fck";
   num-cs = <4>;
   interrupts = <0 343 4>;
   status = "disabled";
  };


  ocp2scp@4a090000 {
   compatible = "ti,omap-ocp2scp";
   #address-cells = <1>;
   #size-cells = <1>;
   ranges;
   reg = <0x4a090000 0x20>;
   ti,hwmods = "ocp2scp3";
   sata_phy: phy@4a096000 {
    compatible = "ti,phy-pipe3-sata";
    reg = <0x4A096000 0x80>,
          <0x4A096400 0x64>,
          <0x4A096800 0x40>;
    reg-names = "phy_rx", "phy_tx", "pll_ctrl";
    syscon-phy-power = <&scm_conf 0x374>;
    clocks = <&sys_clkin1>,
      <&l3init_clkctrl ((0x88) - 0x20) 8>;
    clock-names = "sysclk", "refclk";
    syscon-pllreset = <&scm_conf 0x3fc>;
    #phy-cells = <0>;
   };

   pcie1_phy: pciephy@4a094000 {
    compatible = "ti,phy-pipe3-pcie";
    reg = <0x4a094000 0x80>,
          <0x4a094400 0x64>;
    reg-names = "phy_rx", "phy_tx";
    syscon-phy-power = <&scm_conf_pcie 0x1c>;
    syscon-pcs = <&scm_conf_pcie 0x10>;
    clocks = <&dpll_pcie_ref_ck>,
      <&dpll_pcie_ref_m2ldo_ck>,
      <&l3init_clkctrl ((0xb0) - 0x20) 8>,
      <&l3init_clkctrl ((0xb0) - 0x20) 9>,
      <&l3init_clkctrl ((0xb0) - 0x20) 10>,
      <&optfclk_pciephy_div>,
      <&sys_clkin1>;
    clock-names = "dpll_ref", "dpll_ref_m2",
           "wkupclk", "refclk",
           "div-clk", "phy-div", "sysclk";
    #phy-cells = <0>;
   };

   pcie2_phy: pciephy@4a095000 {
    compatible = "ti,phy-pipe3-pcie";
    reg = <0x4a095000 0x80>,
          <0x4a095400 0x64>;
    reg-names = "phy_rx", "phy_tx";
    syscon-phy-power = <&scm_conf_pcie 0x20>;
    syscon-pcs = <&scm_conf_pcie 0x10>;
    clocks = <&dpll_pcie_ref_ck>,
      <&dpll_pcie_ref_m2ldo_ck>,
      <&l3init_clkctrl ((0xb8) - 0x20) 8>,
      <&l3init_clkctrl ((0xb8) - 0x20) 9>,
      <&l3init_clkctrl ((0xb8) - 0x20) 10>,
      <&optfclk_pciephy_div>,
      <&sys_clkin1>;
    clock-names = "dpll_ref", "dpll_ref_m2",
           "wkupclk", "refclk",
           "div-clk", "phy-div", "sysclk";
    #phy-cells = <0>;
    status = "disabled";
   };
  };

  sata: sata@4a141100 {
   compatible = "snps,dwc-ahci";
   reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
   interrupts = <0 49 4>;
   phys = <&sata_phy>;
   phy-names = "sata-phy";
   clocks = <&l3init_clkctrl ((0x88) - 0x20) 8>;
   ti,hwmods = "sata";
   ports-implemented = <0x1>;
  };

  rtc: rtc@48838000 {
   compatible = "ti,am3352-rtc";
   reg = <0x48838000 0x100>;
   interrupts = <0 217 4>,
         <0 217 4>;
   ti,hwmods = "rtcss";
   clocks = <&sys_32k_ck>;
  };


  ocp2scp@4a080000 {
   compatible = "ti,omap-ocp2scp";
   #address-cells = <1>;
   #size-cells = <1>;
   ranges;
   reg = <0x4a080000 0x20>;
   ti,hwmods = "ocp2scp1";

   usb2_phy1: phy@4a084000 {
    compatible = "ti,dra7x-usb2", "ti,omap-usb2";
    reg = <0x4a084000 0x400>;
    syscon-phy-power = <&scm_conf 0x300>;
    clocks = <&usb_phy1_always_on_clk32k>,
      <&l3init_clkctrl ((0xf0) - 0x20) 8>;
    clock-names = "wkupclk",
      "refclk";
    #phy-cells = <0>;
   };

   usb2_phy2: phy@4a085000 {
    compatible = "ti,dra7x-usb2-phy2",
          "ti,omap-usb2";
    reg = <0x4a085000 0x400>;
    syscon-phy-power = <&scm_conf 0xe74>;
    clocks = <&usb_phy2_always_on_clk32k>,
      <&l3init_clkctrl ((0x40) - 0x20) 8>;
    clock-names = "wkupclk",
      "refclk";
    #phy-cells = <0>;
   };

   usb3_phy1: phy@4a084400 {
    compatible = "ti,omap-usb3";
    reg = <0x4a084400 0x80>,
          <0x4a084800 0x64>,
          <0x4a084c00 0x40>;
    reg-names = "phy_rx", "phy_tx", "pll_ctrl";
    syscon-phy-power = <&scm_conf 0x370>;
    clocks = <&usb_phy3_always_on_clk32k>,
      <&sys_clkin1>,
      <&l3init_clkctrl ((0xf0) - 0x20) 8>;
    clock-names = "wkupclk",
      "sysclk",
      "refclk";
    #phy-cells = <0>;
   };
  };

  target-module@4a0dd000 {
   compatible = "ti,sysc-omap4-sr", "ti,sysc";
   ti,hwmods = "smartreflex_core";
   reg = <0x4a0dd038 0x4>;
   reg-names = "sysc";
   ti,sysc-mask = <(1 << 26)>;
   ti,sysc-sidle = <0>,
     <1>,
     <2>,
     <3>;
   clocks = <&coreaon_clkctrl ((0x38) - 0x20) 0>;
   clock-names = "fck";
   #address-cells = <1>;
   #size-cells = <1>;
   ranges = <0 0x4a0dd000 0x001000>;


  };

  target-module@4a0d9000 {
   compatible = "ti,sysc-omap4-sr", "ti,sysc";
   ti,hwmods = "smartreflex_mpu";
   reg = <0x4a0d9038 0x4>;
   reg-names = "sysc";
   ti,sysc-mask = <(1 << 26)>;
   ti,sysc-sidle = <0>,
     <1>,
     <2>,
     <3>;
   clocks = <&coreaon_clkctrl ((0x28) - 0x20) 0>;
   clock-names = "fck";
   #address-cells = <1>;
   #size-cells = <1>;
   ranges = <0 0x4a0d9000 0x001000>;


  };

  omap_dwc3_1: omap_dwc3_1@48880000 {
   compatible = "ti,dwc3";
   ti,hwmods = "usb_otg_ss1";
   reg = <0x48880000 0x10000>;
   interrupts = <0 72 4>;
   #address-cells = <1>;
   #size-cells = <1>;
   utmi-mode = <2>;
   ranges;
   usb1: usb@48890000 {
    compatible = "snps,dwc3";
    reg = <0x48890000 0x17000>;
    interrupts = <0 71 4>,
          <0 71 4>,
          <0 72 4>;
    interrupt-names = "peripheral",
        "host",
        "otg";
    phys = <&usb2_phy1>, <&usb3_phy1>;
    phy-names = "usb2-phy", "usb3-phy";
    maximum-speed = "super-speed";
    dr_mode = "otg";
    snps,dis_u3_susphy_quirk;
    snps,dis_u2_susphy_quirk;
   };
  };

  omap_dwc3_2: omap_dwc3_2@488c0000 {
   compatible = "ti,dwc3";
   ti,hwmods = "usb_otg_ss2";
   reg = <0x488c0000 0x10000>;
   interrupts = <0 87 4>;
   #address-cells = <1>;
   #size-cells = <1>;
   utmi-mode = <2>;
   ranges;
   usb2: usb@488d0000 {
    compatible = "snps,dwc3";
    reg = <0x488d0000 0x17000>;
    interrupts = <0 73 4>,
          <0 73 4>,
          <0 87 4>;
    interrupt-names = "peripheral",
        "host",
        "otg";
    phys = <&usb2_phy2>;
    phy-names = "usb2-phy";
    maximum-speed = "high-speed";
    dr_mode = "otg";
    snps,dis_u3_susphy_quirk;
    snps,dis_u2_susphy_quirk;
    snps,dis_metastability_quirk;
   };
  };


  omap_dwc3_3: omap_dwc3_3@48900000 {
   compatible = "ti,dwc3";
   ti,hwmods = "usb_otg_ss3";
   reg = <0x48900000 0x10000>;
   interrupts = <0 344 4>;
   #address-cells = <1>;
   #size-cells = <1>;
   utmi-mode = <2>;
   ranges;
   status = "disabled";
   usb3: usb@48910000 {
    compatible = "snps,dwc3";
    reg = <0x48910000 0x17000>;
    interrupts = <0 88 4>,
          <0 88 4>,
          <0 344 4>;
    interrupt-names = "peripheral",
        "host",
        "otg";
    maximum-speed = "high-speed";
    dr_mode = "otg";
    snps,dis_u3_susphy_quirk;
    snps,dis_u2_susphy_quirk;
   };
  };

  elm: elm@48078000 {
   compatible = "ti,am3352-elm";
   reg = <0x48078000 0xfc0>;
   interrupts = <0 1 4>;
   ti,hwmods = "elm";
   status = "disabled";
  };

  gpmc: gpmc@50000000 {
   compatible = "ti,am3352-gpmc";
   ti,hwmods = "gpmc";
   reg = <0x50000000 0x37c>;
   interrupts = <0 15 4>;
   dmas = <&edma_xbar 4 0>;
   dma-names = "rxtx";
   gpmc,num-cs = <8>;
   gpmc,num-waitpins = <2>;
   #address-cells = <2>;
   #size-cells = <1>;
   interrupt-controller;
   #interrupt-cells = <2>;
   gpio-controller;
   #gpio-cells = <2>;
   status = "disabled";
  };

  atl: atl@4843c000 {
   compatible = "ti,dra7-atl";
   reg = <0x4843c000 0x3ff>;
   ti,hwmods = "atl";
   ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
          <&atl_clkin2_ck>, <&atl_clkin3_ck>;
   clocks = <&atl_clkctrl ((0x0) - 0x0) 26>;
   clock-names = "fck";
   status = "disabled";
  };

  mcasp1: mcasp@48460000 {
   compatible = "ti,dra7-mcasp-audio";
   ti,hwmods = "mcasp1";
   reg = <0x48460000 0x2000>,
         <0x45800000 0x1000>;
   reg-names = "mpu","dat";
   interrupts = <0 104 4>,
         <0 103 4>;
   interrupt-names = "tx", "rx";
   dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>;
   dma-names = "tx", "rx";
   clocks = <&ipu_clkctrl ((0x50) - 0x40) 22>, <&ipu_clkctrl ((0x50) - 0x40) 24>,
     <&ipu_clkctrl ((0x50) - 0x40) 28>;
   clock-names = "fck", "ahclkx", "ahclkr";
   status = "disabled";
  };

  mcasp2: mcasp@48464000 {
   compatible = "ti,dra7-mcasp-audio";
   ti,hwmods = "mcasp2";
   reg = <0x48464000 0x2000>,
         <0x45c00000 0x1000>;
   reg-names = "mpu","dat";
   interrupts = <0 149 4>,
         <0 148 4>;
   interrupt-names = "tx", "rx";
   dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>;
   dma-names = "tx", "rx";
   clocks = <&l4per_clkctrl ((0x160) - 0x0) 22>,
     <&l4per_clkctrl ((0x160) - 0x0) 24>,
     <&l4per_clkctrl ((0x160) - 0x0) 28>;
   clock-names = "fck", "ahclkx", "ahclkr";
   status = "disabled";
  };

  mcasp3: mcasp@48468000 {
   compatible = "ti,dra7-mcasp-audio";
   ti,hwmods = "mcasp3";
   reg = <0x48468000 0x2000>,
         <0x46000000 0x1000>;
   reg-names = "mpu","dat";
   interrupts = <0 151 4>,
         <0 150 4>;
   interrupt-names = "tx", "rx";
   dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>;
   dma-names = "tx", "rx";
   clocks = <&l4per_clkctrl ((0x168) - 0x0) 22>,
     <&l4per_clkctrl ((0x168) - 0x0) 24>;
   clock-names = "fck", "ahclkx";
   status = "disabled";
  };

  mcasp4: mcasp@4846c000 {
   compatible = "ti,dra7-mcasp-audio";
   ti,hwmods = "mcasp4";
   reg = <0x4846c000 0x2000>,
         <0x48436000 0x1000>;
   reg-names = "mpu","dat";
   interrupts = <0 153 4>,
         <0 152 4>;
   interrupt-names = "tx", "rx";
   dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>;
   dma-names = "tx", "rx";
   clocks = <&l4per_clkctrl ((0x198) - 0x0) 22>,
     <&l4per_clkctrl ((0x198) - 0x0) 24>;
   clock-names = "fck", "ahclkx";
   status = "disabled";
  };

  mcasp5: mcasp@48470000 {
   compatible = "ti,dra7-mcasp-audio";
   ti,hwmods = "mcasp5";
   reg = <0x48470000 0x2000>,
         <0x4843a000 0x1000>;
   reg-names = "mpu","dat";
   interrupts = <0 155 4>,
         <0 154 4>;
   interrupt-names = "tx", "rx";
   dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>;
   dma-names = "tx", "rx";
   clocks = <&l4per_clkctrl ((0x178) - 0x0) 22>,
     <&l4per_clkctrl ((0x178) - 0x0) 24>;
   clock-names = "fck", "ahclkx";
   status = "disabled";
  };

  mcasp6: mcasp@48474000 {
   compatible = "ti,dra7-mcasp-audio";
   ti,hwmods = "mcasp6";
   reg = <0x48474000 0x2000>,
         <0x4844c000 0x1000>;
   reg-names = "mpu","dat";
   interrupts = <0 157 4>,
         <0 156 4>;
   interrupt-names = "tx", "rx";
   dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>;
   dma-names = "tx", "rx";
   clocks = <&l4per_clkctrl ((0x204) - 0x0) 22>,
     <&l4per_clkctrl ((0x204) - 0x0) 24>;
   clock-names = "fck", "ahclkx";
   status = "disabled";
  };

  mcasp7: mcasp@48478000 {
   compatible = "ti,dra7-mcasp-audio";
   ti,hwmods = "mcasp7";
   reg = <0x48478000 0x2000>,
         <0x48450000 0x1000>;
   reg-names = "mpu","dat";
   interrupts = <0 159 4>,
         <0 158 4>;
   interrupt-names = "tx", "rx";
   dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>;
   dma-names = "tx", "rx";
   clocks = <&l4per_clkctrl ((0x208) - 0x0) 22>,
     <&l4per_clkctrl ((0x208) - 0x0) 24>;
   clock-names = "fck", "ahclkx";
   status = "disabled";
  };

  mcasp8: mcasp@4847c000 {
   compatible = "ti,dra7-mcasp-audio";
   ti,hwmods = "mcasp8";
   reg = <0x4847c000 0x2000>,
         <0x48454000 0x1000>;
   reg-names = "mpu","dat";
   interrupts = <0 161 4>,
         <0 160 4>;
   interrupt-names = "tx", "rx";
   dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>;
   dma-names = "tx", "rx";
   clocks = <&l4per_clkctrl ((0x190) - 0x0) 22>,
     <&l4per_clkctrl ((0x190) - 0x0) 24>;
   clock-names = "fck", "ahclkx";
   status = "disabled";
  };

  crossbar_mpu: crossbar@4a002a48 {
   compatible = "ti,irq-crossbar";
   reg = <0x4a002a48 0x130>;
   interrupt-controller;
   interrupt-parent = <&wakeupgen>;
   #interrupt-cells = <3>;
   ti,max-irqs = <160>;
   ti,max-crossbar-sources = <400>;
   ti,reg-size = <2>;
   ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
   ti,irqs-skip = <10 133 139 140>;
   ti,irqs-safe-map = <0>;
  };

  mac: ethernet@48484000 {
   compatible = "ti,dra7-cpsw","ti,cpsw";
   ti,hwmods = "gmac";
   clocks = <&gmac_main_clk>, <&l3init_clkctrl ((0xd0) - 0x20) 25>;
   clock-names = "fck", "cpts";
   cpdma_channels = <8>;
   ale_entries = <1024>;
   bd_ram_size = <0x2000>;
   mac_control = <0x20>;
   slaves = <2>;
   active_slave = <0>;
   cpts_clock_mult = <0x784CFE14>;
   cpts_clock_shift = <29>;
   reg = <0x48484000 0x1000
          0x48485200 0x2E00>;
   #address-cells = <1>;
   #size-cells = <1>;
# 2103 "arch/arm/boot/dts/dra7.dtsi"
   ti,no-idle;







   interrupts = <0 334 4>,
         <0 335 4>,
         <0 336 4>,
         <0 337 4>;
   ranges;
   syscon = <&scm_conf>;
   status = "disabled";

   davinci_mdio: mdio@48485000 {
    compatible = "ti,cpsw-mdio","ti,davinci_mdio";
    #address-cells = <1>;
    #size-cells = <0>;
    ti,hwmods = "davinci_mdio";
    bus_freq = <1000000>;
    reg = <0x48485000 0x100>;
   };

   cpsw_emac0: slave@48480200 {

    mac-address = [ 00 00 00 00 00 00 ];
   };

   cpsw_emac1: slave@48480300 {

    mac-address = [ 00 00 00 00 00 00 ];
   };

   phy_sel: cpsw-phy-sel@4a002554 {
    compatible = "ti,dra7xx-cpsw-phy-sel";
    reg= <0x4a002554 0x4>;
    reg-names = "gmii-sel";
   };
  };

  dcan1: can@4ae3c000 {
   compatible = "ti,dra7-d_can";
   ti,hwmods = "dcan1";
   reg = <0x4ae3c000 0x2000>;
   syscon-raminit = <&scm_conf 0x558 0>;
   interrupts = <0 222 4>;
   clocks = <&wkupaon_clkctrl ((0x88) - 0x20) 24>;
   status = "disabled";
  };

  dcan2: can@48480000 {
   compatible = "ti,dra7-d_can";
   ti,hwmods = "dcan2";
   reg = <0x48480000 0x2000>;
   syscon-raminit = <&scm_conf 0x558 1>;
   interrupts = <0 225 4>;
   clocks = <&sys_clkin1>;
   status = "disabled";
  };

  gpu: gpu@56000000 {
   compatible = "ti,dra7-sgx544", "img,sgx544";
   reg = <0x56000000 0x10000>;
   reg-names = "gpu_ocp_base";
   interrupts = <0 16 4>;
   ti,hwmods = "gpu";
   clocks = <&l3_iclk_div>, <&gpu_core_gclk_mux>,
    <&gpu_hyd_gclk_mux>;
   clock-names = "iclk", "fclk1", "fclk2";
   status = "disabled";
  };

  bb2d: bb2d@59000000 {
   compatible = "ti,dra7-bb2d";
   reg = <0x59000000 0x0700>;
   interrupts = <0 120 4>;
   ti,hwmods = "bb2d";
   clocks = <&dss_clkctrl ((0x30) - 0x20) 0>;
   clock-names = "fck";
   status = "disabled";
  };

  dss: dss@58000000 {
   compatible = "ti,dra7-dss";


   status = "disabled";
   ti,hwmods = "dss_core";

   syscon-pll-ctrl = <&scm_conf 0x538>;
   #address-cells = <1>;
   #size-cells = <1>;
   ranges;

   dispc@58001000 {
    compatible = "ti,dra7-dispc";
    reg = <0x58001000 0x1000>;
    interrupts = <0 20 4>;
    ti,hwmods = "dss_dispc";
    clocks = <&dss_clkctrl ((0x20) - 0x20) 8>;
    clock-names = "fck";

    syscon-pol = <&scm_conf 0x534>;
   };

   hdmi: encoder@58060000 {
    compatible = "ti,dra7-hdmi";
    reg = <0x58040000 0x200>,
          <0x58040200 0x80>,
          <0x58040300 0x80>,
          <0x58060000 0x19000>;
    reg-names = "wp", "pll", "phy", "core";
    interrupts = <0 96 4>;
    status = "disabled";
    ti,hwmods = "dss_hdmi";
    clocks = <&dss_clkctrl ((0x20) - 0x20) 9>,
      <&dss_clkctrl ((0x20) - 0x20) 10>;
    clock-names = "fck", "sys_clk";
    dmas = <&sdma_xbar 76>;
    dma-names = "audio_tx";
   };
  };

  epwmss0: epwmss@4843e000 {
   compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
   reg = <0x4843e000 0x30>;
   ti,hwmods = "epwmss0";
   #address-cells = <1>;
   #size-cells = <1>;
   status = "disabled";
   ranges;

   ehrpwm0: pwm@4843e200 {
    compatible = "ti,dra746-ehrpwm",
          "ti,am3352-ehrpwm";
    #pwm-cells = <3>;
    reg = <0x4843e200 0x80>;
    clocks = <&ehrpwm0_tbclk>, <&l4_root_clk_div>;
    clock-names = "tbclk", "fck";
    status = "disabled";
   };

   ecap0: ecap@4843e100 {
    compatible = "ti,dra746-ecap",
          "ti,am3352-ecap";
    #pwm-cells = <3>;
    reg = <0x4843e100 0x80>;
    clocks = <&l4_root_clk_div>;
    clock-names = "fck";
    status = "disabled";
   };
  };

  epwmss1: epwmss@48440000 {
   compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
   reg = <0x48440000 0x30>;
   ti,hwmods = "epwmss1";
   #address-cells = <1>;
   #size-cells = <1>;
   status = "disabled";
   ranges;

   ehrpwm1: pwm@48440200 {
    compatible = "ti,dra746-ehrpwm",
          "ti,am3352-ehrpwm";
    #pwm-cells = <3>;
    reg = <0x48440200 0x80>;
    clocks = <&ehrpwm1_tbclk>, <&l4_root_clk_div>;
    clock-names = "tbclk", "fck";
    status = "disabled";
   };

   ecap1: ecap@48440100 {
    compatible = "ti,dra746-ecap",
          "ti,am3352-ecap";
    #pwm-cells = <3>;
    reg = <0x48440100 0x80>;
    clocks = <&l4_root_clk_div>;
    clock-names = "fck";
    status = "disabled";
   };
  };

  epwmss2: epwmss@48442000 {
   compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
   reg = <0x48442000 0x30>;
   ti,hwmods = "epwmss2";
   #address-cells = <1>;
   #size-cells = <1>;
   status = "disabled";
   ranges;

   ehrpwm2: pwm@48442200 {
    compatible = "ti,dra746-ehrpwm",
          "ti,am3352-ehrpwm";
    #pwm-cells = <3>;
    reg = <0x48442200 0x80>;
    clocks = <&ehrpwm2_tbclk>, <&l4_root_clk_div>;
    clock-names = "tbclk", "fck";
    status = "disabled";
   };

   ecap2: ecap@48442100 {
    compatible = "ti,dra746-ecap",
          "ti,am3352-ecap";
    #pwm-cells = <3>;
    reg = <0x48442100 0x80>;
    clocks = <&l4_root_clk_div>;
    clock-names = "fck";
    status = "disabled";
   };
  };

  aes1: aes@4b500000 {
   compatible = "ti,omap4-aes";
   ti,hwmods = "aes1";
   reg = <0x4b500000 0xa0>;
   interrupts = <0 80 4>;
   dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>;
   dma-names = "tx", "rx";
   clocks = <&l3_iclk_div>;
   clock-names = "fck";
  };

  aes2: aes@4b700000 {
   compatible = "ti,omap4-aes";
   ti,hwmods = "aes2";
   reg = <0x4b700000 0xa0>;
   interrupts = <0 59 4>;
   dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>;
   dma-names = "tx", "rx";
   clocks = <&l3_iclk_div>;
   clock-names = "fck";
  };

  des: des@480a5000 {
   compatible = "ti,omap4-des";
   ti,hwmods = "des";
   reg = <0x480a5000 0xa0>;
   interrupts = <0 77 4>;
   dmas = <&sdma_xbar 117>, <&sdma_xbar 116>;
   dma-names = "tx", "rx";
   clocks = <&l3_iclk_div>;
   clock-names = "fck";
  };

  sham: sham@53100000 {
   compatible = "ti,omap5-sham";
   ti,hwmods = "sham";
   reg = <0x4b101000 0x300>;
   interrupts = <0 46 4>;
   dmas = <&edma_xbar 119 0>;
   dma-names = "rx";
   clocks = <&l3_iclk_div>;
   clock-names = "fck";
  };

  rng: rng@48090000 {
   compatible = "ti,omap4-rng";
   ti,hwmods = "rng";
   reg = <0x48090000 0x2000>;
   interrupts = <0 47 4>;
   clocks = <&l3_iclk_div>;
   clock-names = "fck";
  };

  opp_supply_mpu: opp-supply@4a003b20 {
   compatible = "ti,omap5-opp-supply";
   reg = <0x4a003b20 0xc>;
   ti,efuse-settings = <

   1060000 0x0
   1160000 0x4
   1210000 0x8
   >;
   ti,absolute-max-voltage-uv = <1500000>;
  };

  vpe {
   compatible = "ti,vpe";
   ti,hwmods = "vpe";
   clocks = <&dpll_core_h23x2_ck>;
   clock-names = "fck";
   reg = <0x489d0000 0x120>,
         <0x489d0700 0x80>,
         <0x489d5700 0x18>,
         <0x489dd000 0x400>;
   reg-names = "vpe_top",
        "sc",
        "csc",
        "vpdma";
   interrupts = <0 354 4>;
   #address-cells = <1>;
   #size-cells = <0>;
  };

  vip1: vip@0x48970000 {
   compatible = "ti,vip1";
   reg = <0x48970000 0x114>,
         <0x48975500 0xD8>,
         <0x48975700 0x18>,
         <0x48975800 0x80>,
         <0x48975a00 0xD8>,
         <0x48975c00 0x18>,
         <0x48975d00 0x80>,
         <0x4897d000 0x400>;
   reg-names = "vip",
        "parser0",
        "csc0",
        "sc0",
        "parser1",
        "csc1",
        "sc1",
        "vpdma";
   ti,hwmods = "vip1";
   interrupts = <0 351 4>,
         <0 392 4>;

   syscon-pol = <&scm_conf 0x534>;
   #address-cells = <1>;
   #size-cells = <0>;
   status = "disabled";
   ports {
    #address-cells = <1>;
    #size-cells = <0>;

    vin1a: port@0 {
     reg = <0>;
    };
    vin2a: port@1 {
     reg = <1>;
    };
    vin1b: port@2 {
     reg = <2>;
    };
    vin2b: port@3 {
     reg = <3>;
    };
   };
  };
 };

 thermal_zones: thermal-zones {
# 1 "arch/arm/boot/dts/omap4-cpu-thermal.dtsi" 1
# 12 "arch/arm/boot/dts/omap4-cpu-thermal.dtsi"
# 1 "./scripts/dtc/include-prefixes/dt-bindings/thermal/thermal.h" 1
# 13 "arch/arm/boot/dts/omap4-cpu-thermal.dtsi" 2

cpu_thermal: cpu_thermal {
 polling-delay-passive = <250>;
 polling-delay = <1000>;


        thermal-sensors = <&bandgap 0>;

 cpu_trips: trips {
                cpu_alert0: cpu_alert {
                        temperature = <100000>;
                        hysteresis = <2000>;
                        type = "passive";
                };
                cpu_crit: cpu_crit {
                        temperature = <125000>;
                        hysteresis = <2000>;
                        type = "critical";
                };
        };

 cpu_cooling_maps: cooling-maps {
  map0 {
   trip = <&cpu_alert0>;
   cooling-device =
    <&cpu0 (~0) (~0)>;
  };
 };
};
# 2449 "arch/arm/boot/dts/dra7.dtsi" 2
# 1 "arch/arm/boot/dts/omap5-gpu-thermal.dtsi" 1
# 14 "arch/arm/boot/dts/omap5-gpu-thermal.dtsi"
gpu_thermal: gpu_thermal {
 polling-delay-passive = <250>;
 polling-delay = <500>;


 thermal-sensors = <&bandgap 1>;

 trips {
  gpu_crit: gpu_crit {
   temperature = <125000>;
   hysteresis = <2000>;
   type = "critical";
  };
 };
};
# 2450 "arch/arm/boot/dts/dra7.dtsi" 2
# 1 "arch/arm/boot/dts/omap5-core-thermal.dtsi" 1
# 14 "arch/arm/boot/dts/omap5-core-thermal.dtsi"
core_thermal: core_thermal {
 polling-delay-passive = <250>;
 polling-delay = <500>;


 thermal-sensors = <&bandgap 2>;

 trips {
  core_crit: core_crit {
   temperature = <125000>;
   hysteresis = <2000>;
   type = "critical";
  };
 };
};
# 2451 "arch/arm/boot/dts/dra7.dtsi" 2
# 1 "arch/arm/boot/dts/dra7-dspeve-thermal.dtsi" 1
# 13 "arch/arm/boot/dts/dra7-dspeve-thermal.dtsi"
dspeve_thermal: dspeve_thermal {
 polling-delay-passive = <250>;
 polling-delay = <500>;


 thermal-sensors = <&bandgap 3>;

 trips {
  dspeve_crit: dspeve_crit {
   temperature = <125000>;
   hysteresis = <2000>;
   type = "critical";
  };
 };
};
# 2452 "arch/arm/boot/dts/dra7.dtsi" 2
# 1 "arch/arm/boot/dts/dra7-iva-thermal.dtsi" 1
# 13 "arch/arm/boot/dts/dra7-iva-thermal.dtsi"
iva_thermal: iva_thermal {
 polling-delay-passive = <250>;
 polling-delay = <500>;


 thermal-sensors = <&bandgap 4>;

 trips {
  iva_crit: iva_crit {
   temperature = <125000>;
   hysteresis = <2000>;
   type = "critical";
  };
 };
};
# 2453 "arch/arm/boot/dts/dra7.dtsi" 2
 };

};

&cpu_thermal {
 polling-delay = <500>;
 coefficients = <0 2000>;
};

&gpu_thermal {
 coefficients = <0 2000>;
};

&core_thermal {
 coefficients = <0 2000>;
};

&dspeve_thermal {
 coefficients = <0 2000>;
};

&iva_thermal {
 coefficients = <0 2000>;
};

&cpu_crit {
 temperature = <120000>;
};

# 1 "arch/arm/boot/dts/dra7xx-clocks.dtsi" 1
# 10 "arch/arm/boot/dts/dra7xx-clocks.dtsi"
&cm_core_aon_clocks {
 atl_clkin0_ck: atl_clkin0_ck {
  #clock-cells = <0>;
  compatible = "ti,dra7-atl-clock";
  clocks = <&atl_clkctrl ((0x0) - 0x0) 26>;
 };

 atl_clkin1_ck: atl_clkin1_ck {
  #clock-cells = <0>;
  compatible = "ti,dra7-atl-clock";
  clocks = <&atl_clkctrl ((0x0) - 0x0) 26>;
 };

 atl_clkin2_ck: atl_clkin2_ck {
  #clock-cells = <0>;
  compatible = "ti,dra7-atl-clock";
  clocks = <&atl_clkctrl ((0x0) - 0x0) 26>;
 };

 atl_clkin3_ck: atl_clkin3_ck {
  #clock-cells = <0>;
  compatible = "ti,dra7-atl-clock";
  clocks = <&atl_clkctrl ((0x0) - 0x0) 26>;
 };

 hdmi_clkin_ck: hdmi_clkin_ck {
  #clock-cells = <0>;
  compatible = "fixed-clock";
  clock-frequency = <0>;
 };

 mlb_clkin_ck: mlb_clkin_ck {
  #clock-cells = <0>;
  compatible = "fixed-clock";
  clock-frequency = <0>;
 };

 mlbp_clkin_ck: mlbp_clkin_ck {
  #clock-cells = <0>;
  compatible = "fixed-clock";
  clock-frequency = <0>;
 };

 pciesref_acs_clk_ck: pciesref_acs_clk_ck {
  #clock-cells = <0>;
  compatible = "fixed-clock";
  clock-frequency = <100000000>;
 };

 ref_clkin0_ck: ref_clkin0_ck {
  #clock-cells = <0>;
  compatible = "fixed-clock";
  clock-frequency = <0>;
 };

 ref_clkin1_ck: ref_clkin1_ck {
  #clock-cells = <0>;
  compatible = "fixed-clock";
  clock-frequency = <0>;
 };

 ref_clkin2_ck: ref_clkin2_ck {
  #clock-cells = <0>;
  compatible = "fixed-clock";
  clock-frequency = <0>;
 };

 ref_clkin3_ck: ref_clkin3_ck {
  #clock-cells = <0>;
  compatible = "fixed-clock";
  clock-frequency = <0>;
 };

 rmii_clk_ck: rmii_clk_ck {
  #clock-cells = <0>;
  compatible = "fixed-clock";
  clock-frequency = <0>;
 };

 sdvenc_clkin_ck: sdvenc_clkin_ck {
  #clock-cells = <0>;
  compatible = "fixed-clock";
  clock-frequency = <0>;
 };

 secure_32k_clk_src_ck: secure_32k_clk_src_ck {
  #clock-cells = <0>;
  compatible = "fixed-clock";
  clock-frequency = <32768>;
 };

 sys_clk32_crystal_ck: sys_clk32_crystal_ck {
  #clock-cells = <0>;
  compatible = "fixed-clock";
  clock-frequency = <32768>;
 };

 sys_clk32_pseudo_ck: sys_clk32_pseudo_ck {
  #clock-cells = <0>;
  compatible = "fixed-factor-clock";
  clocks = <&sys_clkin1>;
  clock-mult = <1>;
  clock-div = <610>;
 };

 virt_12000000_ck: virt_12000000_ck {
  #clock-cells = <0>;
  compatible = "fixed-clock";
  clock-frequency = <12000000>;
 };

 virt_13000000_ck: virt_13000000_ck {
  #clock-cells = <0>;
  compatible = "fixed-clock";
  clock-frequency = <13000000>;
 };

 virt_16800000_ck: virt_16800000_ck {
  #clock-cells = <0>;
  compatible = "fixed-clock";
  clock-frequency = <16800000>;
 };

 virt_19200000_ck: virt_19200000_ck {
  #clock-cells = <0>;
  compatible = "fixed-clock";
  clock-frequency = <19200000>;
 };

 virt_20000000_ck: virt_20000000_ck {
  #clock-cells = <0>;
  compatible = "fixed-clock";
  clock-frequency = <20000000>;
 };

 virt_26000000_ck: virt_26000000_ck {
  #clock-cells = <0>;
  compatible = "fixed-clock";
  clock-frequency = <26000000>;
 };

 virt_27000000_ck: virt_27000000_ck {
  #clock-cells = <0>;
  compatible = "fixed-clock";
  clock-frequency = <27000000>;
 };

 virt_38400000_ck: virt_38400000_ck {
  #clock-cells = <0>;
  compatible = "fixed-clock";
  clock-frequency = <38400000>;
 };

 sys_clkin2: sys_clkin2 {
  #clock-cells = <0>;
  compatible = "fixed-clock";
  clock-frequency = <22579200>;
 };

 usb_otg_clkin_ck: usb_otg_clkin_ck {
  #clock-cells = <0>;
  compatible = "fixed-clock";
  clock-frequency = <0>;
 };

 video1_clkin_ck: video1_clkin_ck {
  #clock-cells = <0>;
  compatible = "fixed-clock";
  clock-frequency = <0>;
 };

 video1_m2_clkin_ck: video1_m2_clkin_ck {
  #clock-cells = <0>;
  compatible = "fixed-clock";
  clock-frequency = <0>;
 };

 video2_clkin_ck: video2_clkin_ck {
  #clock-cells = <0>;
  compatible = "fixed-clock";
  clock-frequency = <0>;
 };

 video2_m2_clkin_ck: video2_m2_clkin_ck {
  #clock-cells = <0>;
  compatible = "fixed-clock";
  clock-frequency = <0>;
 };

 dpll_abe_ck: dpll_abe_ck@1e0 {
  #clock-cells = <0>;
  compatible = "ti,omap4-dpll-m4xen-clock";
  clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
  reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
  assigned-clocks = <&dpll_abe_ck>;
  assigned-clock-rates = <50000000>;
 };

 dpll_abe_x2_ck: dpll_abe_x2_ck {
  #clock-cells = <0>;
  compatible = "ti,omap4-dpll-x2-clock";
  clocks = <&dpll_abe_ck>;
 };

 dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 {
  #clock-cells = <0>;
  compatible = "ti,divider-clock";
  clocks = <&dpll_abe_x2_ck>;
  ti,max-div = <31>;
  ti,autoidle-shift = <8>;
  reg = <0x01f0>;
  ti,index-starts-at-one;
  ti,invert-autoidle-bit;
 };

 abe_clk: abe_clk@108 {
  #clock-cells = <0>;
  compatible = "ti,divider-clock";
  clocks = <&dpll_abe_m2x2_ck>;
  ti,max-div = <4>;
  reg = <0x0108>;
  ti,index-power-of-two;
 };

 dpll_abe_m2_ck: dpll_abe_m2_ck@1f0 {
  #clock-cells = <0>;
  compatible = "ti,divider-clock";
  clocks = <&dpll_abe_ck>;
  ti,max-div = <31>;
  ti,autoidle-shift = <8>;
  reg = <0x01f0>;
  ti,index-starts-at-one;
  ti,invert-autoidle-bit;
 };

 dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 {
  #clock-cells = <0>;
  compatible = "ti,divider-clock";
  clocks = <&dpll_abe_x2_ck>;
  ti,max-div = <31>;
  ti,autoidle-shift = <8>;
  reg = <0x01f4>;
  ti,index-starts-at-one;
  ti,invert-autoidle-bit;
 };

 dpll_core_byp_mux: dpll_core_byp_mux@12c {
  #clock-cells = <0>;
  compatible = "ti,mux-clock";
  clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
  ti,bit-shift = <23>;
  reg = <0x012c>;
 };

 dpll_core_ck: dpll_core_ck@120 {
  #clock-cells = <0>;
  compatible = "ti,omap4-dpll-core-clock";
  clocks = <&sys_clkin1>, <&dpll_core_byp_mux>;
  reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
 };

 dpll_core_x2_ck: dpll_core_x2_ck {
  #clock-cells = <0>;
  compatible = "ti,omap4-dpll-x2-clock";
  clocks = <&dpll_core_ck>;
 };

 dpll_core_h12x2_ck: dpll_core_h12x2_ck@13c {
  #clock-cells = <0>;
  compatible = "ti,divider-clock";
  clocks = <&dpll_core_x2_ck>;
  ti,max-div = <63>;
  ti,autoidle-shift = <8>;
  reg = <0x013c>;
  ti,index-starts-at-one;
  ti,invert-autoidle-bit;
 };

 mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
  #clock-cells = <0>;
  compatible = "fixed-factor-clock";
  clocks = <&dpll_core_h12x2_ck>;
  clock-mult = <1>;
  clock-div = <1>;
 };

 dpll_mpu_ck: dpll_mpu_ck@160 {
  #clock-cells = <0>;
  compatible = "ti,omap5-mpu-dpll-clock";
  clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>;
  reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
 };

 dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 {
  #clock-cells = <0>;
  compatible = "ti,divider-clock";
  clocks = <&dpll_mpu_ck>;
  ti,max-div = <31>;
  ti,autoidle-shift = <8>;
  reg = <0x0170>;
  ti,index-starts-at-one;
  ti,invert-autoidle-bit;
 };

 mpu_dclk_div: mpu_dclk_div {
  #clock-cells = <0>;
  compatible = "fixed-factor-clock";
  clocks = <&dpll_mpu_m2_ck>;
  clock-mult = <1>;
  clock-div = <1>;
 };

 dsp_dpll_hs_clk_div: dsp_dpll_hs_clk_div {
  #clock-cells = <0>;
  compatible = "fixed-factor-clock";
  clocks = <&dpll_core_h12x2_ck>;
  clock-mult = <1>;
  clock-div = <1>;
 };

 dpll_dsp_byp_mux: dpll_dsp_byp_mux@240 {
  #clock-cells = <0>;
  compatible = "ti,mux-clock";
  clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;
  ti,bit-shift = <23>;
  reg = <0x0240>;
 };

 dpll_dsp_ck: dpll_dsp_ck@234 {
  #clock-cells = <0>;
  compatible = "ti,omap4-dpll-clock";
  clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>;
  reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>;
  assigned-clocks = <&dpll_dsp_ck>;
  assigned-clock-rates = <600000000>;
 };

 dpll_dsp_m2_ck: dpll_dsp_m2_ck@244 {
  #clock-cells = <0>;
  compatible = "ti,divider-clock";
  clocks = <&dpll_dsp_ck>;
  ti,max-div = <31>;
  ti,autoidle-shift = <8>;
  reg = <0x0244>;
  ti,index-starts-at-one;
  ti,invert-autoidle-bit;
  assigned-clocks = <&dpll_dsp_m2_ck>;
  assigned-clock-rates = <600000000>;
 };

 iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
  #clock-cells = <0>;
  compatible = "fixed-factor-clock";
  clocks = <&dpll_core_h12x2_ck>;
  clock-mult = <1>;
  clock-div = <1>;
 };

 dpll_iva_byp_mux: dpll_iva_byp_mux@1ac {
  #clock-cells = <0>;
  compatible = "ti,mux-clock";
  clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;
  ti,bit-shift = <23>;
  reg = <0x01ac>;
 };

 dpll_iva_ck: dpll_iva_ck@1a0 {
  #clock-cells = <0>;
  compatible = "ti,omap4-dpll-clock";
  clocks = <&sys_clkin1>, <&dpll_iva_byp_mux>;
  reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
  assigned-clocks = <&dpll_iva_ck>;
  assigned-clock-rates = <1165000000>;
 };

 dpll_iva_m2_ck: dpll_iva_m2_ck@1b0 {
  #clock-cells = <0>;
  compatible = "ti,divider-clock";
  clocks = <&dpll_iva_ck>;
  ti,max-div = <31>;
  ti,autoidle-shift = <8>;
  reg = <0x01b0>;
  ti,index-starts-at-one;
  ti,invert-autoidle-bit;
  assigned-clocks = <&dpll_iva_m2_ck>;
  assigned-clock-rates = <388333334>;
 };

 iva_dclk: iva_dclk {
  #clock-cells = <0>;
  compatible = "fixed-factor-clock";
  clocks = <&dpll_iva_m2_ck>;
  clock-mult = <1>;
  clock-div = <1>;
 };

 dpll_gpu_byp_mux: dpll_gpu_byp_mux@2e4 {
  #clock-cells = <0>;
  compatible = "ti,mux-clock";
  clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
  ti,bit-shift = <23>;
  reg = <0x02e4>;
 };

 dpll_gpu_ck: dpll_gpu_ck@2d8 {
  #clock-cells = <0>;
  compatible = "ti,omap4-dpll-clock";
  clocks = <&sys_clkin1>, <&dpll_gpu_byp_mux>;
  reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>;
  assigned-clocks = <&dpll_gpu_ck>;
  assigned-clock-rates = <1277000000>;
 };

 dpll_gpu_m2_ck: dpll_gpu_m2_ck@2e8 {
  #clock-cells = <0>;
  compatible = "ti,divider-clock";
  clocks = <&dpll_gpu_ck>;
  ti,max-div = <31>;
  ti,autoidle-shift = <8>;
  reg = <0x02e8>;
  ti,index-starts-at-one;
  ti,invert-autoidle-bit;
  assigned-clocks = <&dpll_gpu_m2_ck>;
  assigned-clock-rates = <425666667>;
 };

 dpll_core_m2_ck: dpll_core_m2_ck@130 {
  #clock-cells = <0>;
  compatible = "ti,divider-clock";
  clocks = <&dpll_core_ck>;
  ti,max-div = <31>;
  ti,autoidle-shift = <8>;
  reg = <0x0130>;
  ti,index-starts-at-one;
  ti,invert-autoidle-bit;
 };

 core_dpll_out_dclk_div: core_dpll_out_dclk_div {
  #clock-cells = <0>;
  compatible = "fixed-factor-clock";
  clocks = <&dpll_core_m2_ck>;
  clock-mult = <1>;
  clock-div = <1>;
 };

 dpll_ddr_byp_mux: dpll_ddr_byp_mux@21c {
  #clock-cells = <0>;
  compatible = "ti,mux-clock";
  clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
  ti,bit-shift = <23>;
  reg = <0x021c>;
 };

 dpll_ddr_ck: dpll_ddr_ck@210 {
  #clock-cells = <0>;
  compatible = "ti,omap4-dpll-clock";
  clocks = <&sys_clkin1>, <&dpll_ddr_byp_mux>;
  reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>;
 };

 dpll_ddr_m2_ck: dpll_ddr_m2_ck@220 {
  #clock-cells = <0>;
  compatible = "ti,divider-clock";
  clocks = <&dpll_ddr_ck>;
  ti,max-div = <31>;
  ti,autoidle-shift = <8>;
  reg = <0x0220>;
  ti,index-starts-at-one;
  ti,invert-autoidle-bit;
 };

 dpll_gmac_byp_mux: dpll_gmac_byp_mux@2b4 {
  #clock-cells = <0>;
  compatible = "ti,mux-clock";
  clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
  ti,bit-shift = <23>;
  reg = <0x02b4>;
 };

 dpll_gmac_ck: dpll_gmac_ck@2a8 {
  #clock-cells = <0>;
  compatible = "ti,omap4-dpll-clock";
  clocks = <&sys_clkin1>, <&dpll_gmac_byp_mux>;
  reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>;
 };

 dpll_gmac_m2_ck: dpll_gmac_m2_ck@2b8 {
  #clock-cells = <0>;
  compatible = "ti,divider-clock";
  clocks = <&dpll_gmac_ck>;
  ti,max-div = <31>;
  ti,autoidle-shift = <8>;
  reg = <0x02b8>;
  ti,index-starts-at-one;
  ti,invert-autoidle-bit;
 };

 video2_dclk_div: video2_dclk_div {
  #clock-cells = <0>;
  compatible = "fixed-factor-clock";
  clocks = <&video2_m2_clkin_ck>;
  clock-mult = <1>;
  clock-div = <1>;
 };

 video1_dclk_div: video1_dclk_div {
  #clock-cells = <0>;
  compatible = "fixed-factor-clock";
  clocks = <&video1_m2_clkin_ck>;
  clock-mult = <1>;
  clock-div = <1>;
 };

 hdmi_dclk_div: hdmi_dclk_div {
  #clock-cells = <0>;
  compatible = "fixed-factor-clock";
  clocks = <&hdmi_clkin_ck>;
  clock-mult = <1>;
  clock-div = <1>;
 };

 per_dpll_hs_clk_div: per_dpll_hs_clk_div {
  #clock-cells = <0>;
  compatible = "fixed-factor-clock";
  clocks = <&dpll_abe_m3x2_ck>;
  clock-mult = <1>;
  clock-div = <2>;
 };

 usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
  #clock-cells = <0>;
  compatible = "fixed-factor-clock";
  clocks = <&dpll_abe_m3x2_ck>;
  clock-mult = <1>;
  clock-div = <3>;
 };

 eve_dpll_hs_clk_div: eve_dpll_hs_clk_div {
  #clock-cells = <0>;
  compatible = "fixed-factor-clock";
  clocks = <&dpll_core_h12x2_ck>;
  clock-mult = <1>;
  clock-div = <1>;
 };

 dpll_eve_byp_mux: dpll_eve_byp_mux@290 {
  #clock-cells = <0>;
  compatible = "ti,mux-clock";
  clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;
  ti,bit-shift = <23>;
  reg = <0x0290>;
 };

 dpll_eve_ck: dpll_eve_ck@284 {
  #clock-cells = <0>;
  compatible = "ti,omap4-dpll-clock";
  clocks = <&sys_clkin1>, <&dpll_eve_byp_mux>;
  reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>;
 };

 dpll_eve_m2_ck: dpll_eve_m2_ck@294 {
  #clock-cells = <0>;
  compatible = "ti,divider-clock";
  clocks = <&dpll_eve_ck>;
  ti,max-div = <31>;
  ti,autoidle-shift = <8>;
  reg = <0x0294>;
  ti,index-starts-at-one;
  ti,invert-autoidle-bit;
 };

 eve_dclk_div: eve_dclk_div {
  #clock-cells = <0>;
  compatible = "fixed-factor-clock";
  clocks = <&dpll_eve_m2_ck>;
  clock-mult = <1>;
  clock-div = <1>;
 };

 dpll_core_h13x2_ck: dpll_core_h13x2_ck@140 {
  #clock-cells = <0>;
  compatible = "ti,divider-clock";
  clocks = <&dpll_core_x2_ck>;
  ti,max-div = <63>;
  ti,autoidle-shift = <8>;
  reg = <0x0140>;
  ti,index-starts-at-one;
  ti,invert-autoidle-bit;
 };

 dpll_core_h14x2_ck: dpll_core_h14x2_ck@144 {
  #clock-cells = <0>;
  compatible = "ti,divider-clock";
  clocks = <&dpll_core_x2_ck>;
  ti,max-div = <63>;
  ti,autoidle-shift = <8>;
  reg = <0x0144>;
  ti,index-starts-at-one;
  ti,invert-autoidle-bit;
 };

 dpll_core_h22x2_ck: dpll_core_h22x2_ck@154 {
  #clock-cells = <0>;
  compatible = "ti,divider-clock";
  clocks = <&dpll_core_x2_ck>;
  ti,max-div = <63>;
  ti,autoidle-shift = <8>;
  reg = <0x0154>;
  ti,index-starts-at-one;
  ti,invert-autoidle-bit;
 };

 dpll_core_h23x2_ck: dpll_core_h23x2_ck@158 {
  #clock-cells = <0>;
  compatible = "ti,divider-clock";
  clocks = <&dpll_core_x2_ck>;
  ti,max-div = <63>;
  ti,autoidle-shift = <8>;
  reg = <0x0158>;
  ti,index-starts-at-one;
  ti,invert-autoidle-bit;
 };

 dpll_core_h24x2_ck: dpll_core_h24x2_ck@15c {
  #clock-cells = <0>;
  compatible = "ti,divider-clock";
  clocks = <&dpll_core_x2_ck>;
  ti,max-div = <63>;
  ti,autoidle-shift = <8>;
  reg = <0x015c>;
  ti,index-starts-at-one;
  ti,invert-autoidle-bit;
 };

 dpll_ddr_x2_ck: dpll_ddr_x2_ck {
  #clock-cells = <0>;
  compatible = "ti,omap4-dpll-x2-clock";
  clocks = <&dpll_ddr_ck>;
 };

 dpll_ddr_h11x2_ck: dpll_ddr_h11x2_ck@228 {
  #clock-cells = <0>;
  compatible = "ti,divider-clock";
  clocks = <&dpll_ddr_x2_ck>;
  ti,max-div = <63>;
  ti,autoidle-shift = <8>;
  reg = <0x0228>;
  ti,index-starts-at-one;
  ti,invert-autoidle-bit;
 };

 dpll_dsp_x2_ck: dpll_dsp_x2_ck {
  #clock-cells = <0>;
  compatible = "ti,omap4-dpll-x2-clock";
  clocks = <&dpll_dsp_ck>;
 };

 dpll_dsp_m3x2_ck: dpll_dsp_m3x2_ck@248 {
  #clock-cells = <0>;
  compatible = "ti,divider-clock";
  clocks = <&dpll_dsp_x2_ck>;
  ti,max-div = <31>;
  ti,autoidle-shift = <8>;
  reg = <0x0248>;
  ti,index-starts-at-one;
  ti,invert-autoidle-bit;
  assigned-clocks = <&dpll_dsp_m3x2_ck>;
  assigned-clock-rates = <400000000>;
 };

 dpll_gmac_x2_ck: dpll_gmac_x2_ck {
  #clock-cells = <0>;
  compatible = "ti,omap4-dpll-x2-clock";
  clocks = <&dpll_gmac_ck>;
 };

 dpll_gmac_h11x2_ck: dpll_gmac_h11x2_ck@2c0 {
  #clock-cells = <0>;
  compatible = "ti,divider-clock";
  clocks = <&dpll_gmac_x2_ck>;
  ti,max-div = <63>;
  ti,autoidle-shift = <8>;
  reg = <0x02c0>;
  ti,index-starts-at-one;
  ti,invert-autoidle-bit;
 };

 dpll_gmac_h12x2_ck: dpll_gmac_h12x2_ck@2c4 {
  #clock-cells = <0>;
  compatible = "ti,divider-clock";
  clocks = <&dpll_gmac_x2_ck>;
  ti,max-div = <63>;
  ti,autoidle-shift = <8>;
  reg = <0x02c4>;
  ti,index-starts-at-one;
  ti,invert-autoidle-bit;
 };

 dpll_gmac_h13x2_ck: dpll_gmac_h13x2_ck@2c8 {
  #clock-cells = <0>;
  compatible = "ti,divider-clock";
  clocks = <&dpll_gmac_x2_ck>;
  ti,max-div = <63>;
  ti,autoidle-shift = <8>;
  reg = <0x02c8>;
  ti,index-starts-at-one;
  ti,invert-autoidle-bit;
 };

 dpll_gmac_m3x2_ck: dpll_gmac_m3x2_ck@2bc {
  #clock-cells = <0>;
  compatible = "ti,divider-clock";
  clocks = <&dpll_gmac_x2_ck>;
  ti,max-div = <31>;
  ti,autoidle-shift = <8>;
  reg = <0x02bc>;
  ti,index-starts-at-one;
  ti,invert-autoidle-bit;
 };

 gmii_m_clk_div: gmii_m_clk_div {
  #clock-cells = <0>;
  compatible = "fixed-factor-clock";
  clocks = <&dpll_gmac_h11x2_ck>;
  clock-mult = <1>;
  clock-div = <2>;
 };

 hdmi_clk2_div: hdmi_clk2_div {
  #clock-cells = <0>;
  compatible = "fixed-factor-clock";
  clocks = <&hdmi_clkin_ck>;
  clock-mult = <1>;
  clock-div = <1>;
 };

 hdmi_div_clk: hdmi_div_clk {
  #clock-cells = <0>;
  compatible = "fixed-factor-clock";
  clocks = <&hdmi_clkin_ck>;
  clock-mult = <1>;
  clock-div = <1>;
 };

 l3_iclk_div: l3_iclk_div@100 {
  #clock-cells = <0>;
  compatible = "ti,divider-clock";
  ti,max-div = <2>;
  ti,bit-shift = <4>;
  reg = <0x0100>;
  clocks = <&dpll_core_h12x2_ck>;
  ti,index-power-of-two;
 };

 l4_root_clk_div: l4_root_clk_div {
  #clock-cells = <0>;
  compatible = "fixed-factor-clock";
  clocks = <&l3_iclk_div>;
  clock-mult = <1>;
  clock-div = <2>;
 };

 video1_clk2_div: video1_clk2_div {
  #clock-cells = <0>;
  compatible = "fixed-factor-clock";
  clocks = <&video1_clkin_ck>;
  clock-mult = <1>;
  clock-div = <1>;
 };

 video1_div_clk: video1_div_clk {
  #clock-cells = <0>;
  compatible = "fixed-factor-clock";
  clocks = <&video1_clkin_ck>;
  clock-mult = <1>;
  clock-div = <1>;
 };

 video2_clk2_div: video2_clk2_div {
  #clock-cells = <0>;
  compatible = "fixed-factor-clock";
  clocks = <&video2_clkin_ck>;
  clock-mult = <1>;
  clock-div = <1>;
 };

 video2_div_clk: video2_div_clk {
  #clock-cells = <0>;
  compatible = "fixed-factor-clock";
  clocks = <&video2_clkin_ck>;
  clock-mult = <1>;
  clock-div = <1>;
 };

 dummy_ck: dummy_ck {
  #clock-cells = <0>;
  compatible = "fixed-clock";
  clock-frequency = <0>;
 };
};
&prm_clocks {
 sys_clkin1: sys_clkin1@110 {
  #clock-cells = <0>;
  compatible = "ti,mux-clock";
  clocks = <&virt_12000000_ck>, <&virt_20000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
  reg = <0x0110>;
  ti,index-starts-at-one;
 };

 abe_dpll_sys_clk_mux: abe_dpll_sys_clk_mux@118 {
  #clock-cells = <0>;
  compatible = "ti,mux-clock";
  clocks = <&sys_clkin1>, <&sys_clkin2>;
  reg = <0x0118>;
 };

 abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@114 {
  #clock-cells = <0>;
  compatible = "ti,mux-clock";
  clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
  reg = <0x0114>;
 };

 abe_dpll_clk_mux: abe_dpll_clk_mux@10c {
  #clock-cells = <0>;
  compatible = "ti,mux-clock";
  clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
  reg = <0x010c>;
 };

 abe_24m_fclk: abe_24m_fclk@11c {
  #clock-cells = <0>;
  compatible = "ti,divider-clock";
  clocks = <&dpll_abe_m2x2_ck>;
  reg = <0x011c>;
  ti,dividers = <8>, <16>;
 };

 aess_fclk: aess_fclk@178 {
  #clock-cells = <0>;
  compatible = "ti,divider-clock";
  clocks = <&abe_clk>;
  reg = <0x0178>;
  ti,max-div = <2>;
 };

 abe_giclk_div: abe_giclk_div@174 {
  #clock-cells = <0>;
  compatible = "ti,divider-clock";
  clocks = <&aess_fclk>;
  reg = <0x0174>;
  ti,max-div = <2>;
 };

 abe_lp_clk_div: abe_lp_clk_div@1d8 {
  #clock-cells = <0>;
  compatible = "ti,divider-clock";
  clocks = <&dpll_abe_m2x2_ck>;
  reg = <0x01d8>;
  ti,dividers = <16>, <32>;
 };

 abe_sys_clk_div: abe_sys_clk_div@120 {
  #clock-cells = <0>;
  compatible = "ti,divider-clock";
  clocks = <&sys_clkin1>;
  reg = <0x0120>;
  ti,max-div = <2>;
 };

 adc_gfclk_mux: adc_gfclk_mux@1dc {
  #clock-cells = <0>;
  compatible = "ti,mux-clock";
  clocks = <&sys_clkin1>, <&sys_clkin2>, <&sys_32k_ck>;
  reg = <0x01dc>;
 };

 sys_clk1_dclk_div: sys_clk1_dclk_div@1c8 {
  #clock-cells = <0>;
  compatible = "ti,divider-clock";
  clocks = <&sys_clkin1>;
  ti,max-div = <64>;
  reg = <0x01c8>;
  ti,index-power-of-two;
 };

 sys_clk2_dclk_div: sys_clk2_dclk_div@1cc {
  #clock-cells = <0>;
  compatible = "ti,divider-clock";
  clocks = <&sys_clkin2>;
  ti,max-div = <64>;
  reg = <0x01cc>;
  ti,index-power-of-two;
 };

 per_abe_x1_dclk_div: per_abe_x1_dclk_div@1bc {
  #clock-cells = <0>;
  compatible = "ti,divider-clock";
  clocks = <&dpll_abe_m2_ck>;
  ti,max-div = <64>;
  reg = <0x01bc>;
  ti,index-power-of-two;
 };

 dsp_gclk_div: dsp_gclk_div@18c {
  #clock-cells = <0>;
  compatible = "ti,divider-clock";
  clocks = <&dpll_dsp_m2_ck>;
  ti,max-div = <64>;
  reg = <0x018c>;
  ti,index-power-of-two;
 };

 gpu_dclk: gpu_dclk@1a0 {
  #clock-cells = <0>;
  compatible = "ti,divider-clock";
  clocks = <&dpll_gpu_m2_ck>;
  ti,max-div = <64>;
  reg = <0x01a0>;
  ti,index-power-of-two;
 };

 emif_phy_dclk_div: emif_phy_dclk_div@190 {
  #clock-cells = <0>;
  compatible = "ti,divider-clock";
  clocks = <&dpll_ddr_m2_ck>;
  ti,max-div = <64>;
  reg = <0x0190>;
  ti,index-power-of-two;
 };

 gmac_250m_dclk_div: gmac_250m_dclk_div@19c {
  #clock-cells = <0>;
  compatible = "ti,divider-clock";
  clocks = <&dpll_gmac_m2_ck>;
  ti,max-div = <64>;
  reg = <0x019c>;
  ti,index-power-of-two;
 };

 gmac_main_clk: gmac_main_clk {
  #clock-cells = <0>;
  compatible = "fixed-factor-clock";
  clocks = <&gmac_250m_dclk_div>;
  clock-mult = <1>;
  clock-div = <2>;
 };

 l3init_480m_dclk_div: l3init_480m_dclk_div@1ac {
  #clock-cells = <0>;
  compatible = "ti,divider-clock";
  clocks = <&dpll_usb_m2_ck>;
  ti,max-div = <64>;
  reg = <0x01ac>;
  ti,index-power-of-two;
 };

 usb_otg_dclk_div: usb_otg_dclk_div@184 {
  #clock-cells = <0>;
  compatible = "ti,divider-clock";
  clocks = <&usb_otg_clkin_ck>;
  ti,max-div = <64>;
  reg = <0x0184>;
  ti,index-power-of-two;
 };

 sata_dclk_div: sata_dclk_div@1c0 {
  #clock-cells = <0>;
  compatible = "ti,divider-clock";
  clocks = <&sys_clkin1>;
  ti,max-div = <64>;
  reg = <0x01c0>;
  ti,index-power-of-two;
 };

 pcie2_dclk_div: pcie2_dclk_div@1b8 {
  #clock-cells = <0>;
  compatible = "ti,divider-clock";
  clocks = <&dpll_pcie_ref_m2_ck>;
  ti,max-div = <64>;
  reg = <0x01b8>;
  ti,index-power-of-two;
 };

 pcie_dclk_div: pcie_dclk_div@1b4 {
  #clock-cells = <0>;
  compatible = "ti,divider-clock";
  clocks = <&apll_pcie_m2_ck>;
  ti,max-div = <64>;
  reg = <0x01b4>;
  ti,index-power-of-two;
 };

 emu_dclk_div: emu_dclk_div@194 {
  #clock-cells = <0>;
  compatible = "ti,divider-clock";
  clocks = <&sys_clkin1>;
  ti,max-div = <64>;
  reg = <0x0194>;
  ti,index-power-of-two;
 };

 secure_32k_dclk_div: secure_32k_dclk_div@1c4 {
  #clock-cells = <0>;
  compatible = "ti,divider-clock";
  clocks = <&secure_32k_clk_src_ck>;
  ti,max-div = <64>;
  reg = <0x01c4>;
  ti,index-power-of-two;
 };

 clkoutmux0_clk_mux: clkoutmux0_clk_mux@158 {
  #clock-cells = <0>;
  compatible = "ti,mux-clock";
  clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
  reg = <0x0158>;
 };

 clkoutmux1_clk_mux: clkoutmux1_clk_mux@15c {
  #clock-cells = <0>;
  compatible = "ti,mux-clock";
  clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
  reg = <0x015c>;
 };

 clkoutmux2_clk_mux: clkoutmux2_clk_mux@160 {
  #clock-cells = <0>;
  compatible = "ti,mux-clock";
  clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
  reg = <0x0160>;
 };

 custefuse_sys_gfclk_div: custefuse_sys_gfclk_div {
  #clock-cells = <0>;
  compatible = "fixed-factor-clock";
  clocks = <&sys_clkin1>;
  clock-mult = <1>;
  clock-div = <2>;
 };

 eve_clk: eve_clk@180 {
  #clock-cells = <0>;
  compatible = "ti,mux-clock";
  clocks = <&dpll_eve_m2_ck>, <&dpll_dsp_m3x2_ck>;
  reg = <0x0180>;
 };

 hdmi_dpll_clk_mux: hdmi_dpll_clk_mux@164 {
  #clock-cells = <0>;
  compatible = "ti,mux-clock";
  clocks = <&sys_clkin1>, <&sys_clkin2>;
  reg = <0x0164>;
 };

 mlb_clk: mlb_clk@134 {
  #clock-cells = <0>;
  compatible = "ti,divider-clock";
  clocks = <&mlb_clkin_ck>;
  ti,max-div = <64>;
  reg = <0x0134>;
  ti,index-power-of-two;
 };

 mlbp_clk: mlbp_clk@130 {
  #clock-cells = <0>;
  compatible = "ti,divider-clock";
  clocks = <&mlbp_clkin_ck>;
  ti,max-div = <64>;
  reg = <0x0130>;
  ti,index-power-of-two;
 };

 per_abe_x1_gfclk2_div: per_abe_x1_gfclk2_div@138 {
  #clock-cells = <0>;
  compatible = "ti,divider-clock";
  clocks = <&dpll_abe_m2_ck>;
  ti,max-div = <64>;
  reg = <0x0138>;
  ti,index-power-of-two;
 };

 timer_sys_clk_div: timer_sys_clk_div@144 {
  #clock-cells = <0>;
  compatible = "ti,divider-clock";
  clocks = <&sys_clkin1>;
  reg = <0x0144>;
  ti,max-div = <2>;
 };

 video1_dpll_clk_mux: video1_dpll_clk_mux@168 {
  #clock-cells = <0>;
  compatible = "ti,mux-clock";
  clocks = <&sys_clkin1>, <&sys_clkin2>;
  reg = <0x0168>;
 };

 video2_dpll_clk_mux: video2_dpll_clk_mux@16c {
  #clock-cells = <0>;
  compatible = "ti,mux-clock";
  clocks = <&sys_clkin1>, <&sys_clkin2>;
  reg = <0x016c>;
 };

 wkupaon_iclk_mux: wkupaon_iclk_mux@108 {
  #clock-cells = <0>;
  compatible = "ti,mux-clock";
  clocks = <&sys_clkin1>, <&abe_lp_clk_div>;
  reg = <0x0108>;
 };
};

&cm_core_clocks {
 dpll_pcie_ref_ck: dpll_pcie_ref_ck@200 {
  #clock-cells = <0>;
  compatible = "ti,omap4-dpll-clock";
  clocks = <&sys_clkin1>, <&sys_clkin1>;
  reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>;
 };

 dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck@210 {
  #clock-cells = <0>;
  compatible = "ti,divider-clock";
  clocks = <&dpll_pcie_ref_ck>;
  ti,max-div = <31>;
  ti,autoidle-shift = <8>;
  reg = <0x0210>;
  ti,index-starts-at-one;
  ti,invert-autoidle-bit;
 };

 apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 {
  compatible = "ti,mux-clock";
  clocks = <&dpll_pcie_ref_m2ldo_ck>, <&pciesref_acs_clk_ck>;
  #clock-cells = <0>;
  reg = <0x021c 0x4>;
  ti,bit-shift = <7>;
 };

 apll_pcie_ck: apll_pcie_ck@21c {
  #clock-cells = <0>;
  compatible = "ti,dra7-apll-clock";
  clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
  reg = <0x021c>, <0x0220>;
 };

 optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {
  compatible = "ti,divider-clock";
  clocks = <&apll_pcie_ck>;
  #clock-cells = <0>;
  reg = <0x021c>;
  ti,dividers = <2>, <1>;
  ti,bit-shift = <8>;
  ti,max-div = <2>;
 };

 apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {
  #clock-cells = <0>;
  compatible = "fixed-factor-clock";
  clocks = <&apll_pcie_ck>;
  clock-mult = <1>;
  clock-div = <1>;
 };

 apll_pcie_clkvcoldo_div: apll_pcie_clkvcoldo_div {
  #clock-cells = <0>;
  compatible = "fixed-factor-clock";
  clocks = <&apll_pcie_ck>;
  clock-mult = <1>;
  clock-div = <1>;
 };

 apll_pcie_m2_ck: apll_pcie_m2_ck {
  #clock-cells = <0>;
  compatible = "fixed-factor-clock";
  clocks = <&apll_pcie_ck>;
  clock-mult = <1>;
  clock-div = <1>;
 };

 dpll_per_byp_mux: dpll_per_byp_mux@14c {
  #clock-cells = <0>;
  compatible = "ti,mux-clock";
  clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;
  ti,bit-shift = <23>;
  reg = <0x014c>;
 };

 dpll_per_ck: dpll_per_ck@140 {
  #clock-cells = <0>;
  compatible = "ti,omap4-dpll-clock";
  clocks = <&sys_clkin1>, <&dpll_per_byp_mux>;
  reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
 };

 dpll_per_m2_ck: dpll_per_m2_ck@150 {
  #clock-cells = <0>;
  compatible = "ti,divider-clock";
  clocks = <&dpll_per_ck>;
  ti,max-div = <31>;
  ti,autoidle-shift = <8>;
  reg = <0x0150>;
  ti,index-starts-at-one;
  ti,invert-autoidle-bit;
 };

 func_96m_aon_dclk_div: func_96m_aon_dclk_div {
  #clock-cells = <0>;
  compatible = "fixed-factor-clock";
  clocks = <&dpll_per_m2_ck>;
  clock-mult = <1>;
  clock-div = <1>;
 };

 dpll_usb_byp_mux: dpll_usb_byp_mux@18c {
  #clock-cells = <0>;
  compatible = "ti,mux-clock";
  clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;
  ti,bit-shift = <23>;
  reg = <0x018c>;
 };

 dpll_usb_ck: dpll_usb_ck@180 {
  #clock-cells = <0>;
  compatible = "ti,omap4-dpll-j-type-clock";
  clocks = <&sys_clkin1>, <&dpll_usb_byp_mux>;
  reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
 };

 dpll_usb_m2_ck: dpll_usb_m2_ck@190 {
  #clock-cells = <0>;
  compatible = "ti,divider-clock";
  clocks = <&dpll_usb_ck>;
  ti,max-div = <127>;
  ti,autoidle-shift = <8>;
  reg = <0x0190>;
  ti,index-starts-at-one;
  ti,invert-autoidle-bit;
 };

 dpll_pcie_ref_m2_ck: dpll_pcie_ref_m2_ck@210 {
  #clock-cells = <0>;
  compatible = "ti,divider-clock";
  clocks = <&dpll_pcie_ref_ck>;
  ti,max-div = <127>;
  ti,autoidle-shift = <8>;
  reg = <0x0210>;
  ti,index-starts-at-one;
  ti,invert-autoidle-bit;
 };

 dpll_per_x2_ck: dpll_per_x2_ck {
  #clock-cells = <0>;
  compatible = "ti,omap4-dpll-x2-clock";
  clocks = <&dpll_per_ck>;
 };

 dpll_per_h11x2_ck: dpll_per_h11x2_ck@158 {
  #clock-cells = <0>;
  compatible = "ti,divider-clock";
  clocks = <&dpll_per_x2_ck>;
  ti,max-div = <63>;
  ti,autoidle-shift = <8>;
  reg = <0x0158>;
  ti,index-starts-at-one;
  ti,invert-autoidle-bit;
 };

 dpll_per_h12x2_ck: dpll_per_h12x2_ck@15c {
  #clock-cells = <0>;
  compatible = "ti,divider-clock";
  clocks = <&dpll_per_x2_ck>;
  ti,max-div = <63>;
  ti,autoidle-shift = <8>;
  reg = <0x015c>;
  ti,index-starts-at-one;
  ti,invert-autoidle-bit;
 };

 dpll_per_h13x2_ck: dpll_per_h13x2_ck@160 {
  #clock-cells = <0>;
  compatible = "ti,divider-clock";
  clocks = <&dpll_per_x2_ck>;
  ti,max-div = <63>;
  ti,autoidle-shift = <8>;
  reg = <0x0160>;
  ti,index-starts-at-one;
  ti,invert-autoidle-bit;
 };

 dpll_per_h14x2_ck: dpll_per_h14x2_ck@164 {
  #clock-cells = <0>;
  compatible = "ti,divider-clock";
  clocks = <&dpll_per_x2_ck>;
  ti,max-div = <63>;
  ti,autoidle-shift = <8>;
  reg = <0x0164>;
  ti,index-starts-at-one;
  ti,invert-autoidle-bit;
 };

 dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 {
  #clock-cells = <0>;
  compatible = "ti,divider-clock";
  clocks = <&dpll_per_x2_ck>;
  ti,max-div = <31>;
  ti,autoidle-shift = <8>;
  reg = <0x0150>;
  ti,index-starts-at-one;
  ti,invert-autoidle-bit;
 };

 dpll_usb_clkdcoldo: dpll_usb_clkdcoldo {
  #clock-cells = <0>;
  compatible = "fixed-factor-clock";
  clocks = <&dpll_usb_ck>;
  clock-mult = <1>;
  clock-div = <1>;
 };

 func_128m_clk: func_128m_clk {
  #clock-cells = <0>;
  compatible = "fixed-factor-clock";
  clocks = <&dpll_per_h11x2_ck>;
  clock-mult = <1>;
  clock-div = <2>;
 };

 func_12m_fclk: func_12m_fclk {
  #clock-cells = <0>;
  compatible = "fixed-factor-clock";
  clocks = <&dpll_per_m2x2_ck>;
  clock-mult = <1>;
  clock-div = <16>;
 };

 func_24m_clk: func_24m_clk {
  #clock-cells = <0>;
  compatible = "fixed-factor-clock";
  clocks = <&dpll_per_m2_ck>;
  clock-mult = <1>;
  clock-div = <4>;
 };

 func_48m_fclk: func_48m_fclk {
  #clock-cells = <0>;
  compatible = "fixed-factor-clock";
  clocks = <&dpll_per_m2x2_ck>;
  clock-mult = <1>;
  clock-div = <4>;
 };

 func_96m_fclk: func_96m_fclk {
  #clock-cells = <0>;
  compatible = "fixed-factor-clock";
  clocks = <&dpll_per_m2x2_ck>;
  clock-mult = <1>;
  clock-div = <2>;
 };

 l3init_60m_fclk: l3init_60m_fclk@104 {
  #clock-cells = <0>;
  compatible = "ti,divider-clock";
  clocks = <&dpll_usb_m2_ck>;
  reg = <0x0104>;
  ti,dividers = <1>, <8>;
 };

 clkout2_clk: clkout2_clk@6b0 {
  #clock-cells = <0>;
  compatible = "ti,gate-clock";
  clocks = <&clkoutmux2_clk_mux>;
  ti,bit-shift = <8>;
  reg = <0x06b0>;
 };

 l3init_960m_gfclk: l3init_960m_gfclk@6c0 {
  #clock-cells = <0>;
  compatible = "ti,gate-clock";
  clocks = <&dpll_usb_clkdcoldo>;
  ti,bit-shift = <8>;
  reg = <0x06c0>;
 };

 usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k@640 {
  #clock-cells = <0>;
  compatible = "ti,gate-clock";
  clocks = <&sys_32k_ck>;
  ti,bit-shift = <8>;
  reg = <0x0640>;
 };

 usb_phy2_always_on_clk32k: usb_phy2_always_on_clk32k@688 {
  #clock-cells = <0>;
  compatible = "ti,gate-clock";
  clocks = <&sys_32k_ck>;
  ti,bit-shift = <8>;
  reg = <0x0688>;
 };

 usb_phy3_always_on_clk32k: usb_phy3_always_on_clk32k@698 {
  #clock-cells = <0>;
  compatible = "ti,gate-clock";
  clocks = <&sys_32k_ck>;
  ti,bit-shift = <8>;
  reg = <0x0698>;
 };

 gpu_core_gclk_mux: gpu_core_gclk_mux@1220 {
  #clock-cells = <0>;
  compatible = "ti,mux-clock";
  clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
  ti,bit-shift = <24>;
  reg = <0x1220>;
  assigned-clocks = <&gpu_core_gclk_mux>;
  assigned-clock-parents = <&dpll_gpu_m2_ck>;
 };

 gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1220 {
  #clock-cells = <0>;
  compatible = "ti,mux-clock";
  clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
  ti,bit-shift = <26>;
  reg = <0x1220>;
  assigned-clocks = <&gpu_hyd_gclk_mux>;
  assigned-clock-parents = <&dpll_gpu_m2_ck>;
 };

 l3instr_ts_gclk_div: l3instr_ts_gclk_div@e50 {
  #clock-cells = <0>;
  compatible = "ti,divider-clock";
  clocks = <&wkupaon_iclk_mux>;
  ti,bit-shift = <24>;
  reg = <0x0e50>;
  ti,dividers = <8>, <16>, <32>;
 };

 vip1_gclk_mux: vip1_gclk_mux@1020 {
  #clock-cells = <0>;
  compatible = "ti,mux-clock";
  clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
  ti,bit-shift = <24>;
  reg = <0x1020>;
 };

 vip2_gclk_mux: vip2_gclk_mux@1028 {
  #clock-cells = <0>;
  compatible = "ti,mux-clock";
  clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
  ti,bit-shift = <24>;
  reg = <0x1028>;
 };

 vip3_gclk_mux: vip3_gclk_mux@1030 {
  #clock-cells = <0>;
  compatible = "ti,mux-clock";
  clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
  ti,bit-shift = <24>;
  reg = <0x1030>;
 };
};

&cm_core_clockdomains {
 coreaon_clkdm: coreaon_clkdm {
  compatible = "ti,clockdomain";
  clocks = <&dpll_usb_ck>;
 };
};

&scm_conf_clocks {
 dss_deshdcp_clk: dss_deshdcp_clk@558 {
  #clock-cells = <0>;
  compatible = "ti,gate-clock";
  clocks = <&l3_iclk_div>;
  ti,bit-shift = <0>;
  reg = <0x558>;
 };

       ehrpwm0_tbclk: ehrpwm0_tbclk@558 {
  #clock-cells = <0>;
  compatible = "ti,gate-clock";
  clocks = <&l4_root_clk_div>;
  ti,bit-shift = <20>;
  reg = <0x0558>;
 };

 ehrpwm1_tbclk: ehrpwm1_tbclk@558 {
  #clock-cells = <0>;
  compatible = "ti,gate-clock";
  clocks = <&l4_root_clk_div>;
  ti,bit-shift = <21>;
  reg = <0x0558>;
 };

 ehrpwm2_tbclk: ehrpwm2_tbclk@558 {
  #clock-cells = <0>;
  compatible = "ti,gate-clock";
  clocks = <&l4_root_clk_div>;
  ti,bit-shift = <22>;
  reg = <0x0558>;
 };

 sys_32k_ck: sys_32k_ck {
  #clock-cells = <0>;
  compatible = "ti,mux-clock";
  clocks = <&sys_clk32_crystal_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>;
  ti,bit-shift = <8>;
  reg = <0x6c4>;
 };
};

&cm_core_aon {
 mpu_cm: mpu_cm@300 {
  compatible = "ti,omap4-cm";
  reg = <0x300 0x100>;
  #address-cells = <1>;
  #size-cells = <1>;
  ranges = <0 0x300 0x100>;

  mpu_clkctrl: clk@20 {
   compatible = "ti,clkctrl";
   reg = <0x20 0x4>;
   #clock-cells = <2>;
  };
 };

 dsp1_cm: dsp1_cm@400 {
  compatible = "ti,omap4-cm";
  reg = <0x400 0x100>;
  #address-cells = <1>;
  #size-cells = <1>;
  ranges = <0 0x400 0x100>;

  dsp1_clkctrl: clk@20 {
   compatible = "ti,clkctrl";
   reg = <0x20 0x4>;
   #clock-cells = <2>;
  };
 };

 ipu1_cm: ipu1_cm@500 {
  compatible = "ti,omap4-cm";
  reg = <0x500 0x40>;
  #address-cells = <1>;
  #size-cells = <1>;
  ranges = <0 0x500 0x100>;

  ipu1_clkctrl: clk@20 {
   compatible = "ti,clkctrl";
   reg = <0x20 0x20>;
   #clock-cells = <2>;

   assigned-clocks = <&ipu1_clkctrl ((0x20) - 0x20) 24>;
   assigned-clock-parents = <&dpll_core_h22x2_ck>;
  };
 };

 ipu_cm: ipu_cm@540 {
  compatible = "ti,omap4-cm";
  reg = <0x540 0xc0>;
  #address-cells = <1>;
  #size-cells = <1>;
  ranges = <0 0x540 0xc0>;

  ipu_clkctrl: clk@0 {
   compatible = "ti,clkctrl";
   reg = <0x0 0x44>;
   #clock-cells = <2>;
  };
 };

 dsp2_cm: dsp2_cm@600 {
  compatible = "ti,omap4-cm";
  reg = <0x600 0x100>;
  #address-cells = <1>;
  #size-cells = <1>;
  ranges = <0 0x600 0x100>;

  dsp2_clkctrl: clk@20 {
   compatible = "ti,clkctrl";
   reg = <0x20 0x4>;
   #clock-cells = <2>;
  };
 };

 rtc_cm: rtc_cm@700 {
  compatible = "ti,omap4-cm";
  reg = <0x700 0x100>;
  #address-cells = <1>;
  #size-cells = <1>;
  ranges = <0 0x700 0x100>;

  rtc_clkctrl: clk@40 {
   compatible = "ti,clkctrl";
   reg = <0x40 0x8>;
   #clock-cells = <2>;
  };
 };

};

&cm_core {
 coreaon_cm: coreaon_cm@600 {
  compatible = "ti,omap4-cm";
  reg = <0x600 0x100>;
  #address-cells = <1>;
  #size-cells = <1>;
  ranges = <0 0x600 0x100>;

  coreaon_clkctrl: clk@20 {
   compatible = "ti,clkctrl";
   reg = <0x20 0x1c>;
   #clock-cells = <2>;
  };
 };

 l3main1_cm: l3main1_cm@700 {
  compatible = "ti,omap4-cm";
  reg = <0x700 0x100>;
  #address-cells = <1>;
  #size-cells = <1>;
  ranges = <0 0x700 0x100>;

  l3main1_clkctrl: clk@20 {
   compatible = "ti,clkctrl";
   reg = <0x20 0x74>;
   #clock-cells = <2>;
  };
 };

 ipu2_cm: ipu2_cm@900 {
  compatible = "ti,omap4-cm";
  reg = <0x900 0x100>;
  #address-cells = <1>;
  #size-cells = <1>;
  ranges = <0 0x900 0x100>;

  ipu2_clkctrl: clk@20 {
   compatible = "ti,clkctrl";
   reg = <0x20 0x4>;
   #clock-cells = <2>;
  };
 };

 dma_cm: dma_cm@a00 {
  compatible = "ti,omap4-cm";
  reg = <0xa00 0x100>;
  #address-cells = <1>;
  #size-cells = <1>;
  ranges = <0 0xa00 0x100>;

  dma_clkctrl: clk@20 {
   compatible = "ti,clkctrl";
   reg = <0x20 0x4>;
   #clock-cells = <2>;
  };
 };

 emif_cm: emif_cm@b00 {
  compatible = "ti,omap4-cm";
  reg = <0xb00 0x100>;
  #address-cells = <1>;
  #size-cells = <1>;
  ranges = <0 0xb00 0x100>;

  emif_clkctrl: clk@20 {
   compatible = "ti,clkctrl";
   reg = <0x20 0x4>;
   #clock-cells = <2>;
  };
 };

 atl_cm: atl_cm@c00 {
  compatible = "ti,omap4-cm";
  reg = <0xc00 0x100>;
  #address-cells = <1>;
  #size-cells = <1>;
  ranges = <0 0xc00 0x100>;

  atl_clkctrl: clk@0 {
   compatible = "ti,clkctrl";
   reg = <0x0 0x4>;
   #clock-cells = <2>;
  };
 };

 l4cfg_cm: l4cfg_cm@d00 {
  compatible = "ti,omap4-cm";
  reg = <0xd00 0x100>;
  #address-cells = <1>;
  #size-cells = <1>;
  ranges = <0 0xd00 0x100>;

  l4cfg_clkctrl: clk@20 {
   compatible = "ti,clkctrl";
   reg = <0x20 0x84>;
   #clock-cells = <2>;
  };
 };

 l3instr_cm: l3instr_cm@e00 {
  compatible = "ti,omap4-cm";
  reg = <0xe00 0x100>;
  #address-cells = <1>;
  #size-cells = <1>;
  ranges = <0 0xe00 0x100>;

  l3instr_clkctrl: clk@20 {
   compatible = "ti,clkctrl";
   reg = <0x20 0xc>;
   #clock-cells = <2>;
  };
 };

 dss_cm: dss_cm@1100 {
  compatible = "ti,omap4-cm";
  reg = <0x1100 0x100>;
  #address-cells = <1>;
  #size-cells = <1>;
  ranges = <0 0x1100 0x100>;

  dss_clkctrl: clk@20 {
   compatible = "ti,clkctrl";
   reg = <0x20 0x14>;
   #clock-cells = <2>;
  };
 };

 l3init_cm: l3init_cm@1300 {
  compatible = "ti,omap4-cm";
  reg = <0x1300 0x100>;
  #address-cells = <1>;
  #size-cells = <1>;
  ranges = <0 0x1300 0x100>;

  l3init_clkctrl: clk@20 {
   compatible = "ti,clkctrl";
   reg = <0x20 0xd4>;
   #clock-cells = <2>;
  };
 };

 l4per_cm: l4per_cm@1700 {
  compatible = "ti,omap4-cm";
  reg = <0x1700 0x300>;
  #address-cells = <1>;
  #size-cells = <1>;
  ranges = <0 0x1700 0x300>;

  l4per_clkctrl: clk@0 {
   compatible = "ti,clkctrl";
   reg = <0x0 0x20c>;
   #clock-cells = <2>;

   assigned-clocks = <&l4per_clkctrl ((0x168) - 0x0) 24>;
   assigned-clock-parents = <&abe_24m_fclk>;
  };
 };

};

&prm {
 wkupaon_cm: wkupaon_cm@1800 {
  compatible = "ti,omap4-cm";
  reg = <0x1800 0x100>;
  #address-cells = <1>;
  #size-cells = <1>;
  ranges = <0 0x1800 0x100>;

  wkupaon_clkctrl: clk@20 {
   compatible = "ti,clkctrl";
   reg = <0x20 0x6c>;
   #clock-cells = <2>;
  };
 };
};
# 2483 "arch/arm/boot/dts/dra7.dtsi" 2

&core_crit {
 temperature = <120000>;
};

&gpu_crit {
 temperature = <120000>;
};

&dspeve_crit {
 temperature = <120000>;
};

&iva_crit {
 temperature = <120000>;
};
# 11 "arch/arm/boot/dts/dra72x.dtsi" 2

/ {
 compatible = "ti,dra722", "ti,dra72", "ti,dra7";

 aliases {
  rproc0 = &ipu1;
  rproc1 = &ipu2;
  rproc2 = &dsp1;
 };

 pmu {
  compatible = "arm,cortex-a15-pmu";
  interrupt-parent = <&wakeupgen>;
  interrupts = <0 131 4>;
 };

 ocp {
  cal: cal@4845b000 {
   compatible = "ti,dra72-cal";
   ti,hwmods = "cal";
   reg = <0x4845B000 0x400>,
         <0x4845B800 0x40>,
         <0x4845B900 0x40>;
   reg-names = "cal_top",
        "cal_rx_core0",
        "cal_rx_core1";
   interrupts = <0 119 4>;
   syscon-camerrx = <&scm_conf 0xE94>;
   #address-cells = <1>;
   #size-cells = <0>;
   status = "disabled";

   ports {
    #address-cells = <1>;
    #size-cells = <0>;

    csi2_0: port@0 {
     reg = <0>;
    };
    csi2_1: port@1 {
     reg = <1>;
    };
   };
  };
 };
};

&scm {
 dra72_vip_mux: pinmux@4a002e8c {
  compatible = "pinctrl-single";
  reg = <0xe8c 0x4>;
  #address-cells = <1>;
  #size-cells = <0>;
  pinctrl-single,register-width = <32>;
  pinctrl-single,function-mask = <0x7f>;
 };
};

&dss {
 reg = <0x58000000 0x80>,
       <0x58004054 0x4>,
       <0x58004300 0x20>;
 reg-names = "dss", "pll1_clkctrl", "pll1";

 clocks = <&dss_clkctrl ((0x20) - 0x20) 8>,
   <&dss_clkctrl ((0x20) - 0x20) 12>;
 clock-names = "fck", "video1_clk";
};

&mailbox5 {
 mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
  ti,mbox-tx = <6 2 2>;
  ti,mbox-rx = <4 2 2>;
  status = "disabled";
 };
 mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
  ti,mbox-tx = <5 2 2>;
  ti,mbox-rx = <1 2 2>;
  status = "disabled";
 };
};

&mailbox6 {
 mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
  ti,mbox-tx = <6 2 2>;
  ti,mbox-rx = <4 2 2>;
  status = "disabled";
 };
};

&pcie1_rc {
 compatible = "ti,dra726-pcie-rc", "ti,dra7-pcie";
};

&pcie1_ep {
 compatible = "ti,dra726-pcie-ep", "ti,dra7-pcie-ep";
};

&pcie2_rc {
 compatible = "ti,dra726-pcie-rc", "ti,dra7-pcie";
};
# 12 "arch/arm/boot/dts/am571x-tqma57xx.dtsi" 2
# 1 "arch/arm/boot/dts/dra72x-mmc-iodelay.dtsi" 1
# 42 "arch/arm/boot/dts/dra72x-mmc-iodelay.dtsi"
&dra7_pmx_core {
 mmc1_pins_default: mmc1_pins_default {
  pinctrl-single,pins = <
   (((0x3754) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x0)
   (((0x3758) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x0)
   (((0x375c) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x0)
   (((0x3760) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x0)
   (((0x3764) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x0)
   (((0x3768) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x0)
  >;
 };

 mmc1_pins_sdr12: mmc1_pins_sdr12 {
  pinctrl-single,pins = <
   (((0x3754) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x0)
   (((0x3758) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x0)
   (((0x375c) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x0)
   (((0x3760) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x0)
   (((0x3764) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x0)
   (((0x3768) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x0)
  >;
 };

 mmc1_pins_hs: mmc1_pins_hs {
  pinctrl-single,pins = <
   (((0x3754) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x0)
   (((0x3758) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x0)
   (((0x375c) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x0)
   (((0x3760) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x0)
   (((0x3764) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x0)
   (((0x3768) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x0)
  >;
 };

 mmc1_pins_sdr25: mmc1_pins_sdr25 {
  pinctrl-single,pins = <
   (((0x3754) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x0)
   (((0x3758) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x0)
   (((0x375c) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x0)
   (((0x3760) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x0)
   (((0x3764) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x0)
   (((0x3768) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x0)
  >;
 };

 mmc1_pins_sdr50: mmc1_pins_sdr50 {
  pinctrl-single,pins = <
   (((0x3754) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | ((1 << 8) | (0xf << 4)) | 0x0)
   (((0x3758) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | ((1 << 8) | (0xf << 4)) | 0x0)
   (((0x375c) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | ((1 << 8) | (0xf << 4)) | 0x0)
   (((0x3760) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | ((1 << 8) | (0xf << 4)) | 0x0)
   (((0x3764) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | ((1 << 8) | (0xf << 4)) | 0x0)
   (((0x3768) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | ((1 << 8) | (0xf << 4)) | 0x0)
  >;
 };

 mmc1_pins_ddr50_rev10: mmc1_pins_ddr50_rev10 {
  pinctrl-single,pins = <
   (((0x3754) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | ((1 << 8) | (0xe << 4)) | 0x0)
   (((0x3758) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | ((1 << 8) | (0xe << 4)) | 0x0)
   (((0x375C) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | ((1 << 8) | (0xe << 4)) | 0x0)
   (((0x3760) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | ((1 << 8) | (0xe << 4)) | 0x0)
   (((0x3764) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | ((1 << 8) | (0xe << 4)) | 0x0)
   (((0x3768) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | ((1 << 8) | (0xe << 4)) | 0x0)
  >;
 };

 mmc1_pins_ddr50_rev20: mmc1_pins_ddr50_rev20 {
  pinctrl-single,pins = <
   (((0x3754) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x0)
   (((0x3758) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x0)
   (((0x375c) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x0)
   (((0x3760) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x0)
   (((0x3764) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x0)
   (((0x3768) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x0)
  >;
 };

 mmc1_pins_sdr104: mmc1_pins_sdr104 {
  pinctrl-single,pins = <
   (((0x3754) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x0)
   (((0x3758) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x0)
   (((0x375c) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x0)
   (((0x3760) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x0)
   (((0x3764) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x0)
   (((0x3768) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x0)
  >;
 };

 mmc2_pins_default: mmc2_pins_default {
  pinctrl-single,pins = <
   (((0x349c) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x1)
   (((0x34b0) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x1)
   (((0x34a0) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x1)
   (((0x34a4) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x1)
   (((0x34a8) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x1)
   (((0x34ac) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x1)
   (((0x348c) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x1)
   (((0x3490) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x1)
   (((0x3494) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x1)
   (((0x3498) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x1)
  >;
 };

 mmc2_pins_hs: mmc2_pins_hs {
  pinctrl-single,pins = <
   (((0x349c) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x1)
   (((0x34b0) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x1)
   (((0x34a0) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x1)
   (((0x34a4) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x1)
   (((0x34a8) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x1)
   (((0x34ac) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x1)
   (((0x348c) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x1)
   (((0x3490) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x1)
   (((0x3494) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x1)
   (((0x3498) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x1)
  >;
 };

 mmc2_pins_ddr_rev10: mmc2_pins_ddr_rev10 {
  pinctrl-single,pins = <
   (((0x348c) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x1)
   (((0x3490) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x1)
   (((0x3494) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x1)
   (((0x3498) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x1)
   (((0x349c) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x1)
   (((0x34a0) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x1)
   (((0x34a4) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x1)
   (((0x34a8) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x1)
   (((0x34ac) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x1)
   (((0x34b0) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x1)
  >;
 };

 mmc2_pins_ddr_rev20: mmc2_pins_ddr_rev20 {
  pinctrl-single,pins = <
   (((0x349c) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x1)
   (((0x34b0) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x1)
   (((0x34a0) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x1)
   (((0x34a4) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x1)
   (((0x34a8) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x1)
   (((0x34ac) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x1)
   (((0x348c) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x1)
   (((0x3490) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x1)
   (((0x3494) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x1)
   (((0x3498) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x1)
  >;
 };

 mmc2_pins_hs200: mmc2_pins_hs200 {
  pinctrl-single,pins = <
   (((0x349c) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x1)
   (((0x34b0) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x1)
   (((0x34a0) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x1)
   (((0x34a4) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x1)
   (((0x34a8) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x1)
   (((0x34ac) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x1)
   (((0x348c) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x1)
   (((0x3490) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x1)
   (((0x3494) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x1)
   (((0x3498) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | (1 << 8) | 0x1)
  >;
 };

 mmc4_pins_default: mmc4_pins_default {
  pinctrl-single,pins = <
   (((0x37e8) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x3)
   (((0x37ec) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x3)
   (((0x37f0) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x3)
   (((0x37f4) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x3)
   (((0x37f8) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x3)
   (((0x37fc) & 0xffff) - 0x3400) (((0 << 16) | (1 << 18) | (1 << 17)) | 0x3)
  >;
 };
};

&dra7_iodelay_core {


 mmc1_iodelay_ddr50_conf: mmc1_iodelay_ddr50_conf {
  pinctrl-pin-array = <
   0x618 ((588) & 0xffff) ((0) & 0xffff)
   0x624 ((1000) & 0xffff) ((0) & 0xffff)
   0x630 ((1375) & 0xffff) ((0) & 0xffff)
   0x63C ((1000) & 0xffff) ((0) & 0xffff)
   0x648 ((1000) & 0xffff) ((0) & 0xffff)
   0x654 ((1000) & 0xffff) ((0) & 0xffff)
   0x620 ((1230) & 0xffff) ((0) & 0xffff)
   0x62C ((0) & 0xffff) ((0) & 0xffff)
   0x638 ((56) & 0xffff) ((0) & 0xffff)
   0x644 ((76) & 0xffff) ((0) & 0xffff)
   0x650 ((91) & 0xffff) ((0) & 0xffff)
   0x65C ((99) & 0xffff) ((0) & 0xffff)
   0x628 ((0) & 0xffff) ((0) & 0xffff)
   0x634 ((0) & 0xffff) ((0) & 0xffff)
   0x640 ((0) & 0xffff) ((0) & 0xffff)
   0x64C ((0) & 0xffff) ((0) & 0xffff)
   0x658 ((0) & 0xffff) ((0) & 0xffff)
  >;
 };


 mmc1_iodelay_sdr104_rev10_conf: mmc1_iodelay_sdr104_rev10_conf {
  pinctrl-pin-array = <
   0x620 ((560) & 0xffff) ((365) & 0xffff)
   0x62c ((0) & 0xffff) ((0) & 0xffff)
   0x638 ((29) & 0xffff) ((0) & 0xffff)
   0x644 ((0) & 0xffff) ((0) & 0xffff)
   0x650 ((47) & 0xffff) ((0) & 0xffff)
   0x65c ((30) & 0xffff) ((0) & 0xffff)
   0x628 ((125) & 0xffff) ((0) & 0xffff)
   0x634 ((43) & 0xffff) ((0) & 0xffff)
   0x640 ((433) & 0xffff) ((0) & 0xffff)
   0x64c ((287) & 0xffff) ((0) & 0xffff)
   0x658 ((351) & 0xffff) ((0) & 0xffff)
  >;
 };


 mmc1_iodelay_sdr104_rev20_conf: mmc1_iodelay_sdr104_rev20_conf {
  pinctrl-pin-array = <
   0x620 ((520) & 0xffff) ((320) & 0xffff)
   0x62c ((0) & 0xffff) ((0) & 0xffff)
   0x638 ((40) & 0xffff) ((0) & 0xffff)
   0x644 ((83) & 0xffff) ((0) & 0xffff)
   0x650 ((98) & 0xffff) ((0) & 0xffff)
   0x65c ((106) & 0xffff) ((0) & 0xffff)
   0x628 ((51) & 0xffff) ((0) & 0xffff)
   0x634 ((0) & 0xffff) ((0) & 0xffff)
   0x640 ((363) & 0xffff) ((0) & 0xffff)
   0x64c ((199) & 0xffff) ((0) & 0xffff)
   0x658 ((273) & 0xffff) ((0) & 0xffff)
  >;
 };


 mmc2_iodelay_ddr_conf: mmc2_iodelay_ddr_conf {
  pinctrl-pin-array = <
   0x18c ((0) & 0xffff) ((0) & 0xffff)
   0x1a4 ((119) & 0xffff) ((0) & 0xffff)
   0x1b0 ((0) & 0xffff) ((0) & 0xffff)
   0x1bc ((18) & 0xffff) ((0) & 0xffff)
   0x1c8 ((894) & 0xffff) ((0) & 0xffff)
   0x1d4 ((30) & 0xffff) ((0) & 0xffff)
   0x1e0 ((0) & 0xffff) ((0) & 0xffff)
   0x1ec ((23) & 0xffff) ((0) & 0xffff)
   0x1f8 ((0) & 0xffff) ((0) & 0xffff)
   0x360 ((0) & 0xffff) ((0) & 0xffff)
   0x194 ((152) & 0xffff) ((0) & 0xffff)
   0x1ac ((206) & 0xffff) ((0) & 0xffff)
   0x1b8 ((78) & 0xffff) ((0) & 0xffff)
   0x1c4 ((2) & 0xffff) ((0) & 0xffff)
   0x1d0 ((266) & 0xffff) ((0) & 0xffff)
   0x1dc ((0) & 0xffff) ((0) & 0xffff)
   0x1e8 ((0) & 0xffff) ((0) & 0xffff)
   0x1f4 ((43) & 0xffff) ((0) & 0xffff)
   0x200 ((0) & 0xffff) ((0) & 0xffff)
   0x368 ((0) & 0xffff) ((0) & 0xffff)
   0x190 ((0) & 0xffff) ((0) & 0xffff)
   0x1a8 ((0) & 0xffff) ((0) & 0xffff)
   0x1b4 ((0) & 0xffff) ((0) & 0xffff)
   0x1c0 ((0) & 0xffff) ((0) & 0xffff)
   0x1d8 ((0) & 0xffff) ((0) & 0xffff)
   0x1e4 ((0) & 0xffff) ((0) & 0xffff)
   0x1f0 ((0) & 0xffff) ((0) & 0xffff)
   0x1fc ((0) & 0xffff) ((0) & 0xffff)
   0x364 ((0) & 0xffff) ((0) & 0xffff)
  >;
 };


 mmc2_iodelay_hs200_rev10_conf: mmc2_iodelay_hs200_rev10_conf {
  pinctrl-pin-array = <
   0x194 ((150) & 0xffff) ((95) & 0xffff)
   0x1ac ((250) & 0xffff) ((0) & 0xffff)
   0x1b8 ((125) & 0xffff) ((0) & 0xffff)
   0x1c4 ((100) & 0xffff) ((0) & 0xffff)
   0x1d0 ((870) & 0xffff) ((415) & 0xffff)
   0x1dc ((30) & 0xffff) ((0) & 0xffff)
   0x1e8 ((200) & 0xffff) ((0) & 0xffff)
   0x1f4 ((200) & 0xffff) ((0) & 0xffff)
   0x200 ((0) & 0xffff) ((0) & 0xffff)
   0x368 ((240) & 0xffff) ((0) & 0xffff)
   0x190 ((695) & 0xffff) ((0) & 0xffff)
   0x1a8 ((924) & 0xffff) ((0) & 0xffff)
   0x1b4 ((719) & 0xffff) ((0) & 0xffff)
   0x1c0 ((824) & 0xffff) ((0) & 0xffff)
   0x1d8 ((877) & 0xffff) ((0) & 0xffff)
   0x1e4 ((446) & 0xffff) ((0) & 0xffff)
   0x1f0 ((847) & 0xffff) ((0) & 0xffff)
   0x1fc ((586) & 0xffff) ((0) & 0xffff)
   0x364 ((1039) & 0xffff) ((0) & 0xffff)
  >;
 };


 mmc2_iodelay_hs200_rev20_conf: mmc2_iodelay_hs200_rev20_conf {
  pinctrl-pin-array = <
   0x194 ((285) & 0xffff) ((0) & 0xffff)
   0x1ac ((189) & 0xffff) ((0) & 0xffff)
   0x1b8 ((0) & 0xffff) ((120) & 0xffff)
   0x1c4 ((0) & 0xffff) ((70) & 0xffff)
   0x1d0 ((730) & 0xffff) ((360) & 0xffff)
   0x1dc ((0) & 0xffff) ((0) & 0xffff)
   0x1e8 ((0) & 0xffff) ((0) & 0xffff)
   0x1f4 ((70) & 0xffff) ((0) & 0xffff)
   0x200 ((0) & 0xffff) ((0) & 0xffff)
   0x368 ((0) & 0xffff) ((120) & 0xffff)
   0x190 ((0) & 0xffff) ((0) & 0xffff)
   0x1a8 ((231) & 0xffff) ((0) & 0xffff)
   0x1b4 ((39) & 0xffff) ((0) & 0xffff)
   0x1c0 ((91) & 0xffff) ((0) & 0xffff)
   0x1d8 ((176) & 0xffff) ((0) & 0xffff)
   0x1e4 ((0) & 0xffff) ((0) & 0xffff)
   0x1f0 ((101) & 0xffff) ((0) & 0xffff)
   0x1fc ((0) & 0xffff) ((0) & 0xffff)
   0x364 ((360) & 0xffff) ((0) & 0xffff)
  >;
 };
};
# 13 "arch/arm/boot/dts/am571x-tqma57xx.dtsi" 2
# 1 "arch/arm/boot/dts/am57xx-tqma57xx.dtsi" 1
# 11 "arch/arm/boot/dts/am57xx-tqma57xx.dtsi"
# 1 "arch/arm/boot/dts/am57xx-industrial-grade.dtsi" 1

&cpu_alert0 {
 temperature = <90000>;
};

&cpu_crit {
 temperature = <105000>;
};

&gpu_crit {
 temperature = <105000>;
};

&core_crit {
 temperature = <105000>;
};

&dspeve_crit {
 temperature = <105000>;
};

&iva_crit {
 temperature = <105000>;
};
# 12 "arch/arm/boot/dts/am57xx-tqma57xx.dtsi" 2
# 1 "./scripts/dtc/include-prefixes/dt-bindings/gpio/gpio.h" 1
# 13 "arch/arm/boot/dts/am57xx-tqma57xx.dtsi" 2


/ {
 aliases {
  rtc1 = &tps659038_rtc;
  rtc0 = &ds1339_rtc;
 };

 reserved-memory {
  #address-cells = <2>;
  #size-cells = <2>;
  ranges;

  ipu2_cma_pool: ipu2_cma@95800000 {
   compatible = "shared-dma-pool";
   reg = <0x0 0x95800000 0x0 0x3800000>;
   reusable;
   status = "okay";
  };

  dsp1_cma_pool: dsp1_cma@99000000 {
   compatible = "shared-dma-pool";
   reg = <0x0 0x99000000 0x0 0x4000000>;
   reusable;
   status = "okay";
  };

  ipu1_cma_pool: ipu1_cma@9d000000 {
   compatible = "shared-dma-pool";
   reg = <0x0 0x9d000000 0x0 0x2000000>;
   reusable;
   status = "okay";
  };
 };

 vdd_5v: fixedregulator-vdd_5v {
  compatible = "regulator-fixed";
  regulator-name = "VDD5V";
  regulator-min-microvolt = <5000000>;
  regulator-max-microvolt = <5000000>;
  regulator-always-on;
  regulator-boot-on;
 };

 vdd_3v3: fixedregulator-vdd_3v3 {
  compatible = "regulator-fixed";
  regulator-name = "VDD3V3";
  vin-supply = <&smps9_reg>;
  regulator-min-microvolt = <3300000>;
  regulator-max-microvolt = <3300000>;
  regulator-always-on;
  regulator-boot-on;
 };

 vtt_fixed: fixedregulator-vtt {

  compatible = "regulator-fixed";
  regulator-name = "vtt_fixed";
  vin-supply = <&vdd_3v3>;
  regulator-min-microvolt = <3300000>;
  regulator-max-microvolt = <3300000>;
  regulator-always-on;
  regulator-boot-on;
 };

 src_clk_x1: src_clk_x1 {
  #clock-cells = <0>;
  compatible = "fixed-clock";
  clock-frequency = <20000000>;
 };

 ocp {
  /delete-node/ rtc@48838000;

  axi@1 {
   status = "okay";
  };
 };
};

&i2c1 {
 status = "okay";
 clock-frequency = <400000>;

 tps659038: tps659038@58 {
  compatible = "ti,tps659038";
  reg = <0x58>;
  interrupts-extended = <&gpio4 1 4
          &dra7_pmx_core 0x168>;
  #interrupt-cells = <2>;
  interrupt-controller;
  ti,system-power-controller;
  ti,palmas-override-powerhold;

  tps659038_pmic {
   compatible = "ti,tps659038-pmic";
   smps12-in-supply = <&vdd_5v>;
   smps3-in-supply = <&vdd_5v>;
   smps45-in-supply = <&vdd_5v>;
   smps6-in-supply = <&vdd_5v>;
   smps7-in-supply = <&vdd_5v>;
   smps8-in-supply = <&vdd_5v>;
   smps9-in-supply = <&vdd_5v>;
   ldo1-in-supply = <&vdd_5v>;
   ldo2-in-supply = <&vdd_5v>;
   ldo3-in-supply = <&vdd_5v>;
   ldo4-in-supply = <&vdd_5v>;
   ldo9-in-supply = <&vdd_5v>;
   ldoln-in-supply = <&vdd_5v>;
   ldousb-in-supply = <&vdd_5v>;
   ldortc-in-supply = <&vdd_5v>;

   regulators {
    smps12_reg: smps12 {

     regulator-name = "smps12";
     regulator-min-microvolt = <850000>;
     regulator-max-microvolt = <1250000>;
     regulator-always-on;
     regulator-boot-on;
    };

    smps3_reg: smps3 {

     regulator-name = "smps3";
     regulator-min-microvolt = <1350000>;
     regulator-max-microvolt = <1350000>;
     regulator-always-on;
     regulator-boot-on;
    };

    smps45_reg: smps45 {


     regulator-name = "smps45";
     regulator-min-microvolt = <850000>;
     regulator-max-microvolt = <1250000>;
     regulator-always-on;
     regulator-boot-on;
    };

    smps6_reg: smps6 {

     regulator-name = "smps6";
     regulator-min-microvolt = <850000>;
     regulator-max-microvolt = <1250000>;
     regulator-always-on;
     regulator-boot-on;
    };

    smps7_reg: smps7 {

     regulator-name = "smps7";
     regulator-min-microvolt = <850000>;
     regulator-max-microvolt = <1150000>;
     regulator-always-on;
     regulator-boot-on;
    };

    smps8_reg: smps8 {


     regulator-name = "smps8";
    };

    smps9_reg: smps9 {

     regulator-name = "smps9";
     regulator-min-microvolt = <3300000>;
     regulator-max-microvolt = <3300000>;
     regulator-always-on;
     regulator-boot-on;
    };

    ldo1_reg: ldo1 {

     regulator-name = "ldo1";
     regulator-min-microvolt = <1800000>;
     regulator-max-microvolt = <3300000>;
     regulator-boot-on;
     regulator-always-on;
    };

    ldo2_reg: ldo2 {

     regulator-name = "ldo2";
     regulator-min-microvolt = <1800000>;
     regulator-max-microvolt = <1800000>;
     regulator-always-on;
     regulator-boot-on;
    };

    ldo3_reg: ldo3 {

     regulator-name = "ldo3";
     regulator-min-microvolt = <1800000>;
     regulator-max-microvolt = <1800000>;
     regulator-always-on;
     regulator-boot-on;
    };

    ldo4_reg: ldo4 {

     regulator-name = "ldo4";
     regulator-min-microvolt = <1800000>;
     regulator-max-microvolt = <1800000>;
     regulator-always-on;
     regulator-boot-on;
    };



    ldo9_reg: ldo9 {

     regulator-name = "ldo9";
     regulator-min-microvolt = <840000>;
     regulator-max-microvolt = <1160000>;
     regulator-always-on;
     regulator-boot-on;
    };

    ldoln_reg: ldoln {

     regulator-name = "ldoln";
     regulator-min-microvolt = <1800000>;
     regulator-max-microvolt = <1800000>;
     regulator-always-on;
     regulator-boot-on;
    };

    ldousb_reg: ldousb {

     regulator-name = "ldousb";
     regulator-min-microvolt = <3300000>;
     regulator-max-microvolt = <3300000>;
     regulator-always-on;
     regulator-boot-on;
    };

    ldortc_reg: ldortc {

     regulator-name = "ldortc";
     regulator-min-microvolt = <1800000>;
     regulator-max-microvolt = <1800000>;
     regulator-always-on;
     regulator-boot-on;
    };

    regen1: regen1 {

     regulator-name = "regen1";
     regulator-boot-on;
     regulator-always-on;
    };

    regen2: regen2 {

     regulator-name = "regen2";
     regulator-boot-on;
     regulator-always-on;
    };
   };
  };

  tps659038_rtc: tps659038_rtc {
   compatible = "ti,palmas-rtc";
   interrupt-parent = <&tps659038>;
   interrupts = <8 2>;
   wakeup-source;
  };

  tps659038_pwr_button: tps659038_pwr_button {
   compatible = "ti,palmas-pwrbutton";
   interrupt-parent = <&tps659038>;
   interrupts = <1 2>;
   wakeup-source;
   ti,palmas-long-press-seconds = <12>;
  };

  tps659038_gpio: tps659038_gpio {
   compatible = "ti,palmas-gpio";
   gpio-controller;
   #gpio-cells = <2>;
  };

  extcon_usb2: tps659038_usb {
   compatible = "ti,palmas-usb-vid";
   ti,enable-vbus-detection;
   ti,enable-id-detection;

  };
 };


 sensor1: se97@1f {
  compatible = "nxp,se97", "jedec,jc-42.4-temp";
  reg = <0x1f>;
  status = "okay";
 };


 eeprom1: se97@57 {
  compatible = "nxp,spd";
  reg = <0x57>;
  pagesize = <16>;
  status = "okay";
 };


 eeprom2: 24c64@54 {
  compatible = "at,24c64";
  pagesize = <32>;
  reg = <0x54>;
  status = "okay";
 };


 ds1339_rtc: ds1339@68 {
  compatible = "dallas,ds1339";
  reg = <0x68>;
  interrupt-parent = <&gpio1>;
  interrupts = <0 2>;
  vcc-supply = <&vdd_3v3>;
  wakeup-source;
  status = "okay";
 };
};

&mac {
 status = "okay";
 dual_emac;
};

&usb2_phy1 {
 phy-supply = <&ldousb_reg>;
};

&usb2_phy2 {
 phy-supply = <&ldousb_reg>;
};


&mmc2 {
 status = "okay";
 vqmmc-supply = <&ldo2_reg>;
 vmmc-supply = <&vdd_3v3>;
 bus-width = <8>;
 ti,non-removable;
 max-frequency = <96000000>;

 pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v";
 pinctrl-0 = <&mmc2_pins_default>;
 pinctrl-1 = <&mmc2_pins_hs>;
};

&qspi {
 status = "okay";
 spi-max-frequency = <76800000>;

 m25p80@0 {
  compatible = "jedec,spi-nor";
  reg = <0>;
  spi-tx-bus-width = <1>;
  spi-rx-bus-width = <4>;
  #address-cells = <1>;
  #size-cells = <1>;
  spi-max-frequency = <166000000>;






  partition@0 {
   label = "QSPI.SPL";
   reg = <0x00000000 0x000040000>;
  };
  partition@1 {
   label = "QSPI.u-boot";
   reg = <0x00040000 0x00100000>;
  };
  partition@2 {
   label = "QSPI.u-boot-spl-os";
   reg = <0x00140000 0x00080000>;
  };
  partition@3 {
   label = "QSPI.u-boot-env";
   reg = <0x001c0000 0x00010000>;
  };
  partition@4 {
   label = "QSPI.u-boot-env.backup1";
   reg = <0x001d0000 0x0010000>;
  };
  partition@5 {
   label = "QSPI.kernel";
   reg = <0x001e0000 0x0800000>;
  };
  partition@6 {
   label = "QSPI.file-system";
   reg = <0x009e0000 0x01620000>;
  };
 };
};


&bb2d {
 status = "okay";
};

&cpu0 {
 vdd-supply = <&smps12_reg>;
};

&mailbox5 {
 status = "okay";
 mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
  status = "okay";
 };
 mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
  status = "okay";
 };
};

&mailbox6 {
 status = "okay";
 mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
  status = "okay";
 };
};

&mmu0_dsp1 {
 status = "okay";
};

&mmu1_dsp1 {
 status = "okay";
};

&mmu_ipu1 {
 status = "okay";
};

&mmu_ipu2 {
 status = "okay";
};

&ipu2 {
 status = "okay";
 memory-region = <&ipu2_cma_pool>;
 mboxes = <&mailbox6 &mbox_ipu2_ipc3x>;
 timers = <&timer3>;
 watchdog-timers = <&timer4>, <&timer9>;
};

&ipu1 {
 status = "okay";
 memory-region = <&ipu1_cma_pool>;
 mboxes = <&mailbox5 &mbox_ipu1_ipc3x>;
 timers = <&timer11>;
 watchdog-timers = <&timer7>, <&timer8>;
};

&dsp1 {
 status = "okay";
 memory-region = <&dsp1_cma_pool>;
 mboxes = <&mailbox5 &mbox_dsp1_ipc3x>;
 timers = <&timer5>;
 watchdog-timers = <&timer10>;
};

&dra7_pmx_core {
 gpio1_pins: pinmux_gpio1_pins {
  pinctrl-single,pins = <
   (((0x3818) & 0xffff) - 0x3400) (0xe | ((1 << 18) | (1 << 16)) | (1 << 24))
  >;
 };
};

&gpio1 {
 pinctrl-names = "default";
 pinctrl-0 = <&gpio1_pins>;
};
# 14 "arch/arm/boot/dts/am571x-tqma57xx.dtsi" 2

/ {
 memory@80000000 {
  device_type = "memory";
  reg = <0x0 0x80000000 0x0 0x40000000>;
 };
};

&mmc2 {
 pinctrl-2 = <&mmc2_pins_ddr_rev20>;
 pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev20_conf>;
};
# 14 "arch/arm/boot/dts/am571x-art57xx.dts" 2

/ {
 model = "TQ TQMa5718 Art57xx (TI)";
 compatible = "tq,art57xx", "tq,tqma5718", "ti,am5718",
       "ti,dra7";

 chosen {
  stdout-path = &uart3;
 };

 leds-iio {
  status = "okay";
  compatible = "gpio-leds";

  led-act-A15 {
   label = "led-act-A15";
   linux,default-trigger = "heartbeat";
   gpios = <&gpio6 23 0>;
  };
 };

 ocp {
  /delete-node/ rtc@48838000;

  axi@1 {
   status = "disabled";
  };
  axi@0 {
   status = "okay";
  };
 };


 pruss1_eth {
  status = "disabled";
  compatible = "ti,am57-prueth";
  prus = <&pru1_0>, <&pru1_1>;
  firmware-name = "ti-pruss/am57xx-pru0-prueth-fw.elf",
    "ti-pruss/am57xx-pru1-prueth-fw.elf";
  sram = <&ocmcram1>;
  interrupt-parent = <&pruss1_intc>;
  mii-rt = <&pruss1_mii_rt>;

  pruss1_emac0: ethernet-mii0 {
   phy-handle = <&pruss1_eth0_phy>;
   phy-mode = "mii";
   interrupts = <20>, <22>, <23>, <26>;
   interrupt-names = "rx", "tx", "hsrprp_ptp_tx",
       "emac_ptp_tx";

   local-mac-address = [00 00 00 00 00 00];
  };

  pruss1_emac1: ethernet-mii1 {
   phy-handle = <&pruss1_eth1_phy>;
   phy-mode = "mii";
   interrupts = <21>, <23>, <24>, <27>;
   interrupt-names = "rx", "tx", "hsrprp_ptp_tx",
       "emac_ptp_tx";

   local-mac-address = [00 00 00 00 00 00];
  };
 };


 pruss2_eth {
  status = "disabled";
  compatible = "ti,am57-prueth";
  prus = <&pru2_0>, <&pru2_1>;
  firmware-name = "ti-pruss/am57xx-pru0-prueth-fw.elf",
    "ti-pruss/am57xx-pru1-prueth-fw.elf";
  sram = <&ocmcram1>;
  interrupt-parent = <&pruss2_intc>;
  mii-rt = <&pruss2_mii_rt>;

  pruss2_emac0: ethernet-mii0 {
   phy-handle = <&pruss2_eth0_phy>;
   phy-mode = "mii";
   interrupts = <20>, <22>, <23>, <26>;
   interrupt-names = "rx", "tx", "hsrprp_ptp_tx",
       "emac_ptp_tx";

   local-mac-address = [00 00 00 00 00 00];
  };

  pruss2_emac1: ethernet-mii1 {
   phy-handle = <&pruss2_eth1_phy>;
   phy-mode = "mii";
   interrupts = <21>, <23>, <24>, <27>;
   interrupt-names = "rx", "tx", "hsrprp_ptp_tx",
       "emac_ptp_tx";

   local-mac-address = [00 00 00 00 00 00];
  };
 };

};

&mac {
 status = "disabled";
};

&qspi {
 status = "disabled";
};


&mmc1 {
 status = "disabled";
};

&pruss_soc_bus1 {
 status = "disabled";
 pruss1: pruss@4b200000 {
  status = "okay";
  pru1_0: pru@4b234000 {
   interrupt-parent = <&pruss1_intc>;
   interrupts = <16>, <17>;
   interrupt-names = "vring", "kick";
   status = "okay";
  };
  pru1_1: pru@4b238000 {
   interrupt-parent = <&pruss1_intc>;
   interrupts = <18>, <19>;
   interrupt-names = "vring", "kick";
   status = "okay";
  };
 };
};

&pruss_soc_bus2 {
 status = "okay";
 pruss2: pruss@4b280000 {
  status = "okay";
  pru2_0: pru@4b2b4000 {
   interrupt-parent = <&pruss2_intc>;
   interrupts = <16>, <17>;
   interrupt-names = "vring", "kick";
   status = "okay";
  };
  pru2_1: pru@4b2b8000 {
   interrupt-parent = <&pruss2_intc>;
   interrupts = <18>, <19>;
   interrupt-names = "vring", "kick";
   status = "okay";
  };
 };
};

&pruss1_mdio {
    status = "okay";

    reset-delay-us = <2>;
    pruss1_eth0_phy: ethernet-phy@0 {
            reg = <0>;
    };

    pruss1_eth1_phy: ethernet-phy@1 {
            reg = <1>;
    };
};

&pruss2_mdio {
 status = "okay";


 reset-delay-us = <2>;

 pruss2_eth0_phy: ethernet-phy@0 {
  reg = <0>;
 };

 pruss2_eth1_phy: ethernet-phy@1 {
  reg = <1>;
 };
};

&dra7_pmx_core {
 gpio1_pins: pinmux_gpio1_pins {
  pinctrl-single,pins = <
   (((0x37D0) & 0xffff) - 0x3400) (0xe | (0 | (1 << 16)) | (1 << 19))
   (((0x37D4) & 0xffff) - 0x3400) (0xe | ((1 << 18) | (1 << 16)) | (1 << 19))
  >;
 };

 gpio3_pins: pinmux_gpio3_pins {
  pinctrl-single,pins = <
   (((0x3554) & 0xffff) - 0x3400) (0xe | ((1 << 18) | (1 << 16)))
   (((0x3558) & 0xffff) - 0x3400) (0xe | ((1 << 18) | (1 << 16)))
   (((0x355C) & 0xffff) - 0x3400) (0xe | (0 | (1 << 16)))
  >;
 };

 gpio4_pins: pinmux_gpio4_pins {
  pinctrl-single,pins = <
   (((0x3570) & 0xffff) - 0x3400) (0xe | ((1 << 18) | (1 << 16)))

   (((0x357C) & 0xffff) - 0x3400) (0xe | (0 | (1 << 16)))
  >;
 };

 gpio5_pins: pinmux_gpio5_pins {
  pinctrl-single,pins = <
   (((0x36CC) & 0xffff) - 0x3400) (0xe | (0 | (1 << 16)))
   (((0x36D0) & 0xffff) - 0x3400) (0xe | ((1 << 18) | (1 << 16)))
  >;
 };

 gpio6_pins: pinmux_gpio6_pins {
  pinctrl-single,pins = <
   (((0x36A0) & 0xffff) - 0x3400) (0xe | (0 | (1 << 16)))
   (((0x3754) & 0xffff) - 0x3400) (0xe | (0 | (1 << 16)))
   (((0x3758) & 0xffff) - 0x3400) (0xe | ((1 << 18) | (1 << 16)))
   (((0x375C) & 0xffff) - 0x3400) (0xe | (0 | (1 << 16)))
   (((0x3760) & 0xffff) - 0x3400) (0xe | ((1 << 18) | (1 << 16)))
   (((0x3764) & 0xffff) - 0x3400) (0xe | ((1 << 18) | (1 << 16)))
   (((0x3768) & 0xffff) - 0x3400) (0xe | ((1 << 18) | (1 << 16)))
  >;
 };

 gpio7_pins: pinmux_gpio7_pins {
  pinctrl-single,pins = <
   (((0x37BC) & 0xffff) - 0x3400) (0xe | (0 | (1 << 16)) | (1 << 19))
   (((0x37CC) & 0xffff) - 0x3400) (0xe | (0 | (1 << 16)) | (1 << 19))
   (((0x37F0) & 0xffff) - 0x3400) (0xe | ((1 << 18) | (1 << 16)))
   (((0x37F4) & 0xffff) - 0x3400) (0xe | (0 | (1 << 16)))
  >;
 };
};

&gpio1 {
    status = "okay";
 pinctrl-names = "default";
 pinctrl-0 = <&gpio1_pins>;
};

&gpio3 {
    status = "okay";
 pinctrl-names = "default";
 pinctrl-0 = <&gpio3_pins>;
 p30 {
  gpio-hog;
  gpios = <30 0>;
  output-high;
  line-name = "USB_DATA_EN";
 };
};

&gpio4 {
    status = "okay";
 pinctrl-names = "default";
 pinctrl-0 = <&gpio4_pins>;
 p6 {

  gpio-hog;
  gpios = <6 0>;
  output-high;
  line-name = "USB_PWR_EN";
 };
};

&gpio5 {
    status = "okay";
 pinctrl-names = "default";
 pinctrl-0 = <&gpio5_pins>;
};

&gpio6 {
    status = "okay";
 pinctrl-names = "default";
 pinctrl-0 = <&gpio6_pins>;
};

&gpio7 {
    status = "okay";
 pinctrl-names = "default";
 pinctrl-0 = <&gpio7_pins>;

 p30 {
  gpio-hog;
  gpios = <13 0>;
  output-high;
  line-name = "PCIE_RST";
 };

};


&uart3 {
 status = "okay";
 interrupts-extended = <&crossbar_mpu 0 69 4
          &dra7_pmx_core 0x3f8>;
 wakeup-source;
};

&uart1 {
 status = "okay";
};

&uart6 {
 status = "okay";
};

&gpu {
 status = "okay";
};

&usb1 {
 status = "okay";
 dr_mode = "host";
};

&usb2 {
 status = "okay";
 dr_mode = "otg";
};

&dra7_pmx_core {
 edt_ft5426_ts_pins: edt_ft5426_ts_pins {
   pinctrl-single,pins = <
  (((0x3574) & 0xffff) - 0x3400) (0xe | ((1 << 18) | (1 << 16)))
   >;
 };
};

&i2c3 {
   status = "okay";
   clock-frequency = <400000>;

 lm77@48 {
  compatible = "national,lm77";
  reg = <0x48>;
  status = "okay";
 };

 eeprom_carrier: 24c256@50 {
  compatible = "at,24c256";
  pagesize = <32>;
  reg = <0x50>;
  status = "okay";
 };


 touch: ft5x06_ts@38 {


  status = "okay";
  compatible = "edt,edt-ft5406", "edt,edt-ft5x06";
        pinctrl-names = "default";
        pinctrl-0 = <&edt_ft5426_ts_pins>;

  reg = <0x38>;
  interrupt-parent = <&gpio4>;
  interrupts = <4 0>;

  touchscreen-size-x = <800>;
  touchscreen-size-y = <600>;
  wakeup-source;
     };


 backlight@2c {


  status = "okay";
  compatible = "ti,lp8556";
  reg = <0x2c>;

  bl-name = "lcd-bl";
  dev-ctrl = /bits/ 8 <0x85>;
  init-brt = /bits/ 8 <0x10>;

        rom_a5h {
            rom-addr = /bits/ 8 <0xa5>;
            rom-val = /bits/ 8 <0x74>;
        };
 };


 expander1: pca9555@20 {
  compatible = "nxp,pca9555";
  reg = <0x20>;
  #gpio-cells = <2>;
  gpio-controller;
  status = "okay";
 };

 expander2: pca9555@21 {
  compatible = "nxp,pca9555";
  reg = <0x21>;
  #gpio-cells = <2>;
  gpio-controller;
  status = "okay";
 };

 expander3: pca9555@22 {
  compatible = "nxp,pca9555";
  reg = <0x22>;
  #gpio-cells = <2>;
  gpio-controller;
  status = "okay";
 };
};

&i2c4 {
   status = "okay";
};

&epwmss1 {
 status = "okay";

 ehrpwm1 {
  status = "okay";
 };
};

&mailbox3 {
 status = "okay";
 mbox_pru1_0: mbox_pru1_0 {
  status = "okay";
 };
 mbox_pru1_1: mbox_pru1_1 {
  status = "okay";
 };
};

&mailbox4 {
 status = "okay";
 mbox_pru2_0: mbox_pru2_0 {
  status = "okay";
 };
 mbox_pru2_1: mbox_pru2_1 {
  status = "okay";
 };
};

&mcspi1 {
 status = "okay";






 spidev1_0: spidev@0 {
  compatible = "rohm,dh2228fv";
  reg = <0>;
  spi-max-frequency = <100000>;
 };

 spidev1_2: spidev@2 {
  compatible = "rohm,dh2228fv";
  reg = <2>;
  spi-max-frequency = <100000>;
 };
};

&mcspi2 {
 status = "okay";

 spidev2_1: spidev@1 {
  compatible = "rohm,dh2228fv";
  reg = <1>;
  spi-max-frequency = <100000>;
 };
};

&mcspi4 {
 status = "okay";

 spidev4_0: spidev@0 {
  compatible = "rohm,dh2228fv";
  reg = <0>;
  spi-max-frequency = <100000>;
 };
};


&pcie1_rc {
 status = "okay";

};


&gpmc {
 status = "okay";


 ranges = <0 0 0x1000000 0x1000000>;


 mram@0,0{
  reg = <0 0 0x200000>;
  status = "okay";


  bank-width = <2>;

  gpmc,device-width = <2>;




  gpmc,cs-on-ns = <3>;
  gpmc,cs-rd-off-ns = <40>;
  gpmc,cs-wr-off-ns = <40>;


  gpmc,adv-on-ns = <0>;
  gpmc,adv-rd-off-ns = <40>;
  gpmc,adv-wr-off-ns = <40>;


  gpmc,we-on-ns = <5>;
  gpmc,we-off-ns = <40>;
  gpmc,oe-on-ns = <5>;
  gpmc,oe-off-ns = <40>;


  gpmc,access-ns = <40>;
  gpmc,rd-cycle-ns = <40>;
  gpmc,wr-cycle-ns = <40>;
# 558 "arch/arm/boot/dts/am571x-art57xx.dts"
 };
};