diff --git a/core/arch/arm/plat-k3/drivers/ti_sci.c b/core/arch/arm/plat-k3/drivers/ti_sci.c
index 9d7c7dcb4..b116a8bc8 100644
--- a/core/arch/arm/plat-k3/drivers/ti_sci.c
+++ b/core/arch/arm/plat-k3/drivers/ti_sci.c
@@ -18,6 +18,12 @@
 #include "sec_proxy.h"
 #include "ti_sci.h"
 #include "ti_sci_protocol.h"
+#include <mm/core_memprot.h>
+#include <mm/core_mmu.h>
+#include "csp_s1_dec_data.h"
+#include "csp_s1_ref_data.h"
+#include "csp_s2_dec_data.h"
+#include "csp_s2_ref_data.h"
 
 static uint8_t message_sequence;
 
@@ -31,6 +37,9 @@ struct ti_sci_xfer {
 	struct k3_sec_proxy_msg rx_message;
 };
 
+#define SRAM_SCRATCH_BASE 	0x43C3B000
+#define SRAM_SCRATCH_SIZE 	0x4000
+register_phys_mem_pgdir(MEM_AREA_IO_SEC, SRAM_SCRATCH_BASE, SRAM_SCRATCH_SIZE);
 /**
  * ti_sci_setup_xfer() - Setup message transfer
  *
@@ -476,6 +485,106 @@ int ti_sci_get_keycnt_keyrev(uint32_t *key_cnt, uint32_t *key_rev)
 	return 0;
 }
 
+#define DEBUG_PRT
+int ti_sci_csp_dec(uint8_t *key_ptr, uint8_t *csp_dec_data_bin, uint32_t len_in, uint8_t *csp_ref_data_bin, uint32_t len_ref, uint8_t *dest_ptr)
+{
+	struct ti_sci_msq_req_csp_aes req = { };
+	struct ti_sci_msq_resp_csp_aes resp = { };
+	struct ti_sci_xfer xfer = { };
+	int ret = 0;
+	uint8_t *ctx_ptr;
+	uint32_t i;
+
+	for (i = 0; i < 32; i++){
+		csp_dec_data_bin[i+24] = *key_ptr++;
+	}
+	ctx_ptr = (uint8_t *)phys_to_virt(SRAM_SCRATCH_BASE, MEM_AREA_IO_SEC, SRAM_SCRATCH_SIZE);
+	memcpy(ctx_ptr, csp_dec_data_bin, len_in);
+
+	ret = ti_sci_setup_xfer(TI_SCI_MSG_SA2UL_AES_DECRYPT, 0,
+				&req, sizeof(req), &resp, sizeof(resp), &xfer);
+	if (ret)
+		return ret;
+	req.ctx_address_lo	= SRAM_SCRATCH_BASE;
+	req.ctx_address_hi	= 0;
+#ifdef DEBUG_PRT
+	IMSG("len_in = 0x%08X  \n", len_in);
+	IMSG("len_ref = 0x%08X  \n", len_ref);
+	for (i = 0; i < 32; i++){
+		IMSG("encrypted_input[%u] = 0x%X\t", i, csp_dec_data_bin[i+88]);
+	}
+	IMSG("req.ctx_address_lo = 0x%08X  \n", req.ctx_address_lo);
+	IMSG("req.ctx_address_hi = 0x%08X  \n", req.ctx_address_hi);
+	IMSG("req.hdr.type = 0x%0X  \n", req.hdr.type);
+	IMSG("req.hdr.host = 0x%0X  \n", req.hdr.host);
+	IMSG("req.hdr.seq = 0x%0X  \n", req.hdr.seq);
+	IMSG("req.hdr.flags = 0x%0X  \n", req.hdr.flags);
+#endif
+	ret = ti_sci_do_xfer(&xfer);
+	if (ret){
+		EMSG(">>>> ti_sci_do_xfer() failed with ret = 0x%0x  \n", ret);
+		return ret;
+	}
+	if (memcmp(dest_ptr, csp_ref_data_bin, len_ref))
+		return -1;
+	IMSG(">>>>>>>> The decrypted data matchs the reference data");
+#ifdef DEBUG_PRT
+	IMSG("resp.hdr.type = 0x%0X  \n", resp.hdr.type);
+	IMSG("resp.hdr.host = 0x%0X  \n", resp.hdr.host);
+	IMSG("resp.hdr.seq = 0x%0X  \n", resp.hdr.seq);
+	IMSG("resp.hdr.flags = 0x%0X  \n", resp.hdr.flags);
+#endif
+	memzero_explicit(&resp, sizeof(resp));
+	return 0;
+}
+
+int ti_sci_csp_dec_test(void)
+{
+	volatile int spin_flag = 0;
+	uint8_t key[32];
+	uint32_t i;
+	int ret = 0;
+	uint32_t otp_key[8];
+	uint8_t *key_ptr;
+	uint32_t len_in, len_ref;
+	uint8_t *dest_ptr;
+	IMSG("TIFS CSP AES-CBC-256 decryption S1");
+	dest_ptr = (uint8_t *)phys_to_virt(SRAM_SCRATCH_BASE+0x2000, MEM_AREA_IO_SEC, SRAM_SCRATCH_SIZE/2);
+	for (i = 0; i < 8; i++){
+		ret = ti_sci_read_otp_mmr(i, &otp_key[i]);
+		if (ret)
+			return ret;
+	}
+	key_ptr = (uint8_t *) &otp_key[0];
+	len_in = sizeof(csp_s1_dec_data_bin);
+	len_ref = sizeof(d_key_bin);
+	if (!ti_sci_csp_dec(key_ptr, &csp_s1_dec_data_bin[0], len_in, &d_key_bin[0], len_ref, dest_ptr))
+		IMSG(">>>> ti_sci_csp_dec() return success!!!");
+	for (i = 0; i < 32; i++){
+		IMSG("output[%u] = 0x%X\t", i, *dest_ptr++);
+	}
+	IMSG("TIFS CSP AES-CBC-256 decryption S2");
+	key_ptr = (uint8_t *)phys_to_virt(SRAM_SCRATCH_BASE+0x2000, MEM_AREA_IO_SEC, SRAM_SCRATCH_SIZE/2);
+	dest_ptr = (uint8_t *)phys_to_virt(SRAM_SCRATCH_BASE+0x2000, MEM_AREA_IO_SEC, SRAM_SCRATCH_SIZE/2);
+	for (i = 0; i < 32; i++){
+		key[i] = *key_ptr++;
+	}
+	len_in = sizeof(csp_s2_dec_data_bin);
+	len_ref = sizeof(input_data_bin);
+	if (!ti_sci_csp_dec(&key[0], &csp_s2_dec_data_bin[0], len_in, &input_data_bin[0], len_ref, dest_ptr))
+		IMSG(">>>> ti_sci_csp_dec() return success!!!");
+	for (i = 0; i < 32; i++){
+		IMSG("output[%u] = 0x%X\t", i, *dest_ptr++);
+	}
+#if 0
+	IMSG("TIFS CSP AES-CBC-256 encryption test");
+	if (!ti_sci_csp_enc_test())
+		IMSG(">>>> ti_sci_csp_enc_test() return success!!!");
+#endif
+	while (spin_flag == 1);
+	return 0;
+}
+
 int ti_sci_init(void)
 {
 	struct ti_sci_msg_resp_version rev_info = { };
@@ -491,6 +600,7 @@ int ti_sci_init(void)
 	     rev_info.abi_major, rev_info.abi_minor,
 	     rev_info.firmware_revision,
 	     rev_info.firmware_description);
+	ret = ti_sci_csp_dec_test();
 
 	return 0;
 }
diff --git a/core/arch/arm/plat-k3/drivers/ti_sci.h b/core/arch/arm/plat-k3/drivers/ti_sci.h
index 497c4d905..9e37bb0f3 100644
--- a/core/arch/arm/plat-k3/drivers/ti_sci.h
+++ b/core/arch/arm/plat-k3/drivers/ti_sci.h
@@ -183,6 +183,9 @@ int ti_sci_get_swrev(uint32_t *swrev);
  */
 int ti_sci_get_keycnt_keyrev(uint32_t *key_cnt, uint32_t *key_rev);
 
+int ti_sci_csp_dec(uint8_t*, uint8_t*, uint32_t, uint8_t *, uint32_t, uint8_t *);
+int ti_sci_csp_dec_test(void);
+
 /**
  * ti_sci_init() - Basic initialization
  *
diff --git a/core/arch/arm/plat-k3/drivers/ti_sci_protocol.h b/core/arch/arm/plat-k3/drivers/ti_sci_protocol.h
index 12e309864..f38f657be 100644
--- a/core/arch/arm/plat-k3/drivers/ti_sci_protocol.h
+++ b/core/arch/arm/plat-k3/drivers/ti_sci_protocol.h
@@ -33,6 +33,9 @@
 #define TI_SCI_MSG_READ_KEYCNT_KEYREV    0x9034
 #define TI_SCI_MSG_WRITE_KEYREV          0x9035
 
+#define TI_SCI_MSG_SA2UL_AES_ENCRYPT     0x9040
+#define TI_SCI_MSG_SA2UL_AES_DECRYPT     0x9041
+
 /**
  * struct ti_sci_secure_msg_hdr - Secure Message Header for All messages
  *				 and responses
@@ -449,4 +452,15 @@ struct ti_sci_msq_resp_get_keycnt_keyrev {
 	uint32_t keycnt;
 	uint32_t keyrev;
 } __packed;
+
+struct ti_sci_msq_req_csp_aes {
+    struct ti_sci_msg_hdr	hdr;
+    uint32_t	ctx_address_lo;
+    uint32_t	ctx_address_hi;
+} __packed;
+
+struct ti_sci_msq_resp_csp_aes {
+    struct ti_sci_msg_hdr hdr;
+    uint8_t tag[16];
+} __packed;
 #endif