Processing config file ..\testvecs\config\infer\tidl_config_jdetnet.txt !
Param1: 20, Param2: 10, Margin: 20
  0, TIDL_DataLayer                ,  0,  -1 ,  1 ,  x ,  x ,  x ,  x ,  x ,  x ,  x ,  x ,  0 ,    0 ,    0 ,    0 ,    0 ,    1 ,    3 ,  320 ,  768 ,
  1, TIDL_BatchNormLayer           ,  1,   1 ,  1 ,  0 ,  x ,  x ,  x ,  x ,  x ,  x ,  x ,  1 ,    1 ,    3 ,  320 ,  768 ,    1 ,    3 ,  320 ,  768 ,
  2, TIDL_ConvolutionLayer         ,  1,   1 ,  1 ,  1 ,  x ,  x ,  x ,  x ,  x ,  x ,  x ,  2 ,    1 ,    3 ,  320 ,  768 ,    1 ,   32 ,  160 ,  384 ,
  3, TIDL_ConvolutionLayer         ,  1,   1 ,  1 ,  2 ,  x ,  x ,  x ,  x ,  x ,  x ,  x ,  3 ,    1 ,   32 ,  160 ,  384 ,    1 ,   32 ,   80 ,  192 ,
  4, TIDL_ConvolutionLayer         ,  1,   1 ,  1 ,  3 ,  x ,  x ,  x ,  x ,  x ,  x ,  x ,  4 ,    1 ,   32 ,   80 ,  192 ,    1 ,   64 ,   80 ,  192 ,
  5, TIDL_ConvolutionLayer         ,  1,   1 ,  1 ,  4 ,  x ,  x ,  x ,  x ,  x ,  x ,  x ,  5 ,    1 ,   64 ,   80 ,  192 ,    1 ,   64 ,   40 ,   96 ,
  6, TIDL_ConvolutionLayer         ,  1,   1 ,  1 ,  5 ,  x ,  x ,  x ,  x ,  x ,  x ,  x ,  6 ,    1 ,   64 ,   40 ,   96 ,    1 ,  128 ,   40 ,   96 ,
  7, TIDL_ConvolutionLayer         ,  1,   1 ,  1 ,  6 ,  x ,  x ,  x ,  x ,  x ,  x ,  x ,  7 ,    1 ,  128 ,   40 ,   96 ,    1 ,  128 ,   40 ,   96 ,
  8, TIDL_PoolingLayer             ,  1,   1 ,  1 ,  7 ,  x ,  x ,  x ,  x ,  x ,  x ,  x ,  8 ,    1 ,  128 ,   40 ,   96 ,    1 ,  128 ,   20 ,   48 ,
  9, TIDL_ConvolutionLayer         ,  1,   1 ,  1 ,  8 ,  x ,  x ,  x ,  x ,  x ,  x ,  x ,  9 ,    1 ,  128 ,   20 ,   48 ,    1 ,  256 ,   20 ,   48 ,
 10, TIDL_ConvolutionLayer         ,  1,   1 ,  1 ,  9 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 10 ,    1 ,  256 ,   20 ,   48 ,    1 ,  256 ,   10 ,   24 ,
 11, TIDL_ConvolutionLayer         ,  1,   1 ,  1 , 10 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 11 ,    1 ,  256 ,   10 ,   24 ,    1 ,  512 ,   10 ,   24 ,
 12, TIDL_ConvolutionLayer         ,  1,   1 ,  1 , 11 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 12 ,    1 ,  512 ,   10 ,   24 ,    1 ,  512 ,   10 ,   24 ,
 13, TIDL_PoolingLayer             ,  1,   1 ,  1 , 12 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 13 ,    1 ,  512 ,   10 ,   24 ,    1 ,  512 ,    5 ,   12 ,
 14, TIDL_PoolingLayer             ,  1,   1 ,  1 , 13 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 14 ,    1 ,  512 ,    5 ,   12 ,    1 ,  512 ,    3 ,    6 ,
 15, TIDL_PoolingLayer             ,  1,   1 ,  1 , 14 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 15 ,    1 ,  512 ,    3 ,    6 ,    1 ,  512 ,    2 ,    3 ,
 16, TIDL_ConvolutionLayer         ,  1,   1 ,  1 ,  7 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 16 ,    1 ,  128 ,   40 ,   96 ,    1 ,  256 ,   40 ,   96 ,
 17, TIDL_ConvolutionLayer         ,  1,   1 ,  1 , 12 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 17 ,    1 ,  512 ,   10 ,   24 ,    1 ,  256 ,   10 ,   24 ,
 18, TIDL_ConvolutionLayer         ,  1,   1 ,  1 , 13 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 18 ,    1 ,  512 ,    5 ,   12 ,    1 ,  256 ,    5 ,   12 ,
 19, TIDL_ConvolutionLayer         ,  1,   1 ,  1 , 14 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 19 ,    1 ,  512 ,    3 ,    6 ,    1 ,  256 ,    3 ,    6 ,
 20, TIDL_ConvolutionLayer         ,  1,   1 ,  1 , 15 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 20 ,    1 ,  512 ,    2 ,    3 ,    1 ,  256 ,    2 ,    3 ,
 21, TIDL_ConvolutionLayer         ,  1,   1 ,  1 , 16 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 21 ,    1 ,  256 ,   40 ,   96 ,    1 ,   16 ,   40 ,   96 ,
 22, TIDL_FlattenLayer             ,  1,   1 ,  1 , 21 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 22 ,    1 ,   16 ,   40 ,   96 ,    1 ,    1 ,    1 ,61440 ,
 23, TIDL_ConvolutionLayer         ,  1,   1 ,  1 , 16 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 23 ,    1 ,  256 ,   40 ,   96 ,    1 ,   16 ,   40 ,   96 ,
 24, TIDL_FlattenLayer             ,  1,   1 ,  1 , 23 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 24 ,    1 ,   16 ,   40 ,   96 ,    1 ,    1 ,    1 ,61440 ,
 25, TIDL_ConvolutionLayer         ,  1,   1 ,  1 , 17 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 26 ,    1 ,  256 ,   10 ,   24 ,    1 ,   24 ,   10 ,   24 ,
 26, TIDL_FlattenLayer             ,  1,   1 ,  1 , 26 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 27 ,    1 ,   24 ,   10 ,   24 ,    1 ,    1 ,    1 , 5760 ,
 27, TIDL_ConvolutionLayer         ,  1,   1 ,  1 , 17 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 28 ,    1 ,  256 ,   10 ,   24 ,    1 ,   24 ,   10 ,   24 ,
 28, TIDL_FlattenLayer             ,  1,   1 ,  1 , 28 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 29 ,    1 ,   24 ,   10 ,   24 ,    1 ,    1 ,    1 , 5760 ,
 29, TIDL_ConvolutionLayer         ,  1,   1 ,  1 , 18 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 31 ,    1 ,  256 ,    5 ,   12 ,    1 ,   24 ,    5 ,   12 ,
 30, TIDL_FlattenLayer             ,  1,   1 ,  1 , 31 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 32 ,    1 ,   24 ,    5 ,   12 ,    1 ,    1 ,    1 , 1440 ,
 31, TIDL_ConvolutionLayer         ,  1,   1 ,  1 , 18 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 33 ,    1 ,  256 ,    5 ,   12 ,    1 ,   24 ,    5 ,   12 ,
 32, TIDL_FlattenLayer             ,  1,   1 ,  1 , 33 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 34 ,    1 ,   24 ,    5 ,   12 ,    1 ,    1 ,    1 , 1440 ,
 33, TIDL_ConvolutionLayer         ,  1,   1 ,  1 , 19 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 36 ,    1 ,  256 ,    3 ,    6 ,    1 ,   24 ,    3 ,    6 ,
 34, TIDL_FlattenLayer             ,  1,   1 ,  1 , 36 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 37 ,    1 ,   24 ,    3 ,    6 ,    1 ,    1 ,    1 ,  432 ,
 35, TIDL_ConvolutionLayer         ,  1,   1 ,  1 , 19 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 38 ,    1 ,  256 ,    3 ,    6 ,    1 ,   24 ,    3 ,    6 ,
 36, TIDL_FlattenLayer             ,  1,   1 ,  1 , 38 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 39 ,    1 ,   24 ,    3 ,    6 ,    1 ,    1 ,    1 ,  432 ,
 37, TIDL_ConvolutionLayer         ,  1,   1 ,  1 , 20 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 41 ,    1 ,  256 ,    2 ,    3 ,    1 ,   16 ,    2 ,    3 ,
 38, TIDL_FlattenLayer             ,  1,   1 ,  1 , 41 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 42 ,    1 ,   16 ,    2 ,    3 ,    1 ,    1 ,    1 ,   96 ,
 39, TIDL_ConvolutionLayer         ,  1,   1 ,  1 , 20 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 43 ,    1 ,  256 ,    2 ,    3 ,    1 ,   16 ,    2 ,    3 ,
 40, TIDL_FlattenLayer             ,  1,   1 ,  1 , 43 ,  x ,  x ,  x ,  x ,  x ,  x ,  x , 44 ,    1 ,   16 ,    2 ,    3 ,    1 ,    1 ,    1 ,   96 ,
 41, TIDL_ConcatLayer              ,  1,   5 ,  1 , 22 , 27 , 32 , 37 , 42 ,  x ,  x ,  x , 46 ,    1 ,    1 ,    1 ,61440 ,    1 ,    1 ,    1 ,69168 ,
 42, TIDL_ConcatLayer              ,  1,   5 ,  1 , 24 , 29 , 34 , 39 , 44 ,  x ,  x ,  x , 47 ,    1 ,    1 ,    1 ,61440 ,    1 ,    1 ,    1 ,69168 ,
 43, TIDL_DetectionOutputLayer     ,  1,   2 ,  1 , 46 , 47 ,  x ,  x ,  x ,  x ,  x ,  x , 48 ,    1 ,    1 ,    1 ,69168 ,    1 ,    1 ,    1 ,  560 ,
 44, TIDL_DataLayer                ,  0,   1 , -1 , 48 ,  x ,  x ,  x ,  x ,  x ,  x ,  x ,  0 ,    1 ,    1 ,    1 ,  560 ,    0 ,    0 ,    0 ,    0 ,
Layer ID    ,inBlkWidth  ,inBlkHeight ,inBlkPitch  ,outBlkWidth ,outBlkHeight,outBlkPitch ,numInChs    ,numOutChs   ,numProcInChs,numLclInChs ,numLclOutChs,numProcItrs ,numAccItrs  ,numHorBlock ,numVerBlock ,inBlkChPitch,outBlkChPitc,alignOrNot 
      2           72           72           72           32           32           32            3           32            3            1            8            1            3           12            5         5184         1024            1    
      3           40           34           40           32           32           32            8            8            8            4            8            1            2           12            5         1360         1024            1    
      4           40           22           40           32           20           32           32           64           32            8            8            1            4            6            4          880          640            1    
      5           40           22           40           32           20           32           16           16           16            8            8            1            2            6            4          880          640            1    
      6           40           22           40           32           20           32           64          128           64            8            8            1            8            3            2          880          640            1    
      7           40           22           40           32           20           32           32           32           32            8            8            1            4            3            2          880          640            1    
      9           56           22           56           48           20           48          128          256          128            7            8            1           19            1            1         1232          960            1    
     10           56           22           56           48           20           48           64           64           64            7            8            1           10            1            1         1232          960            1    
     11           40           12           40           32           10           32          256          512          256            8            8            1           32            1            1          480          320            1    
     12           40           12           40           32           10           32          128          128          128            8            8            1           16            1            1          480          320            1    
     16           96            4           96           96            4           96          128          256          128           32            8            1            4            1           10          384          384            1    
     17           24           10           24           24           10           24          512          256          512           32           32            1           16            1            1          240          240            1    
     18           12            5           12           12            5           12          512          256          512           32           32            1           16            1            1           60           60            1    
     19            6            3            6            6            3            6          512          256          512           32           32            1           16            1            1           18           18            1    
     20            3            2            3            3            2            3          512          256          512           32           32            1           16            1            1            6            6            1    
     21           96            4           96           96            4           96          256           16          256           32            8            1            8            1           10          384          384            1    
     23           96            4           96           96            4           96          256           16          256           32            8            1            8            1           10          384          384            1    
     25           24           10           24           24           10           24          256           24          256           32           24            1            8            1            1          240          240            1    
     27           24           10           24           24           10           24          256           24          256           32           24            1            8            1            1          240          240            1    
     29           12            5           12           12            5           12          256           24          256           32           24            1            8            1            1           60           60            1    
     31           12            5           12           12            5           12          256           24          256           32           24            1            8            1            1           60           60            1    
     33            6            3            6            6            3            6          256           24          256           32           24            1            8            1            1           18           18            1    
     35            6            3            6            6            3            6          256           24          256           32           24            1            8            1            1           18           18            1    
     37            3            2            3            3            2            3          256           16          256           32           16            1            8            1            1            6            6            1    
     39            3            2            3            3            2            3          256           16          256           32           16            1            8            1            1            6            6            1    
Opening ..\..\test\testvecs\input\trace_dump_0_768x320.y file for reading 

Processing Frame Number : 0 

 Layer    1 : TSC Cycles =   1.01, SCTM Cycles =   0.65  ARP32 OVERHEAD =    54.93, MAC/CYCLE =   0.73 #MMACs =     0.74,     0.00,     0.74, Sparsity :   0.00, 100.00
 Layer    2 : TSC Cycles =   7.74, SCTM Cycles =   6.78  ARP32 OVERHEAD =    14.11, MAC/CYCLE =  10.19 #MMACs =   147.46,    72.31,    78.89, Sparsity :  46.50,  50.96
 Layer    3 : TSC Cycles =   6.13, SCTM Cycles =   4.80  ARP32 OVERHEAD =    27.64, MAC/CYCLE =   8.38 #MMACs =   141.56,    45.34,    51.36, Sparsity :  63.72,  67.97
 Layer    4 : TSC Cycles =   7.85, SCTM Cycles =   6.85  ARP32 OVERHEAD =    14.52, MAC/CYCLE =  10.71 #MMACs =   283.12,    78.41,    84.05, Sparsity :  70.31,  72.30
 Layer    5 : TSC Cycles =   7.18, SCTM Cycles =   5.35  ARP32 OVERHEAD =    34.11, MAC/CYCLE =   8.81 #MMACs =   141.56,    60.73,    63.22, Sparsity :  55.34,  57.10
 Layer    6 : TSC Cycles =   8.11, SCTM Cycles =   7.59  ARP32 OVERHEAD =     6.94, MAC/CYCLE =  11.99 #MMACs =   283.12,    91.63,    97.24, Sparsity :  65.65,  67.64
 Layer    7 : TSC Cycles =   5.16, SCTM Cycles =   4.22  ARP32 OVERHEAD =    22.30, MAC/CYCLE =  10.20 #MMACs =   141.56,    49.58,    52.59, Sparsity :  62.85,  64.98
 Layer    8 : TSC Cycles =   2.18, SCTM Cycles =   0.17  ARP32 OVERHEAD =  1202.26, MAC/CYCLE =   0.06 #MMACs =     0.12,     0.00,     0.12, Sparsity :   0.00, 100.00
 Layer    9 : TSC Cycles =   6.00, SCTM Cycles =   5.56  ARP32 OVERHEAD =     7.98, MAC/CYCLE =  12.70 #MMACs =   283.12,    69.28,    76.25, Sparsity :  73.07,  75.53
 Layer   10 : TSC Cycles =   4.09, SCTM Cycles =   3.31  ARP32 OVERHEAD =    23.51, MAC/CYCLE =  10.86 #MMACs =   141.56,    40.77,    44.39, Sparsity :  68.64,  71.20
 Layer   11 : TSC Cycles =  11.40, SCTM Cycles =   6.56  ARP32 OVERHEAD =    73.78, MAC/CYCLE =   4.69 #MMACs =   283.12,    48.62,    53.41, Sparsity :  81.14,  82.83
 Layer   12 : TSC Cycles =   6.96, SCTM Cycles =   3.90  ARP32 OVERHEAD =    78.19, MAC/CYCLE =   4.48 #MMACs =   141.56,    28.21,    31.14, Sparsity :  78.00,  80.07
 Layer   13 : TSC Cycles =   0.91, SCTM Cycles =   0.08  ARP32 OVERHEAD =  1075.42, MAC/CYCLE =   0.03 #MMACs =     0.03,     0.00,     0.03, Sparsity :   0.00, 100.00
 Layer   14 : TSC Cycles =   0.88, SCTM Cycles =   0.06  ARP32 OVERHEAD =  1354.11, MAC/CYCLE =   0.01 #MMACs =     0.01,     0.00,     0.01, Sparsity :   0.00, 100.00
 Layer   15 : TSC Cycles =   0.87, SCTM Cycles =   0.06  ARP32 OVERHEAD =  1388.50, MAC/CYCLE =   0.00 #MMACs =     0.00,     0.00,     0.00, Sparsity :   0.00, 100.00
 Layer   16 : TSC Cycles =   9.09, SCTM Cycles =   8.70  ARP32 OVERHEAD =     4.46, MAC/CYCLE =  13.84 #MMACs =   125.83,     0.00,   125.83, Sparsity :   0.00, 100.00
 Layer   17 : TSC Cycles =   2.25, SCTM Cycles =   2.07  ARP32 OVERHEAD =     8.95, MAC/CYCLE =  13.97 #MMACs =    31.46,     0.00,    31.46, Sparsity :   0.00, 100.00
 Layer   18 : TSC Cycles =   0.77, SCTM Cycles =   0.56  ARP32 OVERHEAD =    38.22, MAC/CYCLE =  10.21 #MMACs =     7.86,     0.00,     7.86, Sparsity :   0.00, 100.00
 Layer   19 : TSC Cycles =   0.55, SCTM Cycles =   0.28  ARP32 OVERHEAD =    93.04, MAC/CYCLE =   4.32 #MMACs =     2.36,     0.00,     2.36, Sparsity :   0.00, 100.00
 Layer   20 : TSC Cycles =   0.54, SCTM Cycles =   0.15  ARP32 OVERHEAD =   268.38, MAC/CYCLE =   1.46 #MMACs =     0.79,     0.00,     0.79, Sparsity :   0.00, 100.00
 Layer   21 : TSC Cycles =   1.38, SCTM Cycles =   1.06  ARP32 OVERHEAD =    30.77, MAC/CYCLE =  11.39 #MMACs =    15.73,     0.00,    15.73, Sparsity :   0.00, 100.00
 Layer   22 : TSC Cycles =   0.10, SCTM Cycles =   0.00  ARP32 OVERHEAD =     +inf, MAC/CYCLE =   0.64 #MMACs =     0.06,     0.00,     0.06, Sparsity :   0.00, 100.00
 Layer   23 : TSC Cycles =   1.38, SCTM Cycles =   1.06  ARP32 OVERHEAD =    30.67, MAC/CYCLE =  11.40 #MMACs =    15.73,     0.00,    15.73, Sparsity :   0.00, 100.00
 Layer   24 : TSC Cycles =   0.10, SCTM Cycles =   0.00  ARP32 OVERHEAD =     +inf, MAC/CYCLE =   0.63 #MMACs =     0.06,     0.00,     0.06, Sparsity :   0.00, 100.00
 Layer   25 : TSC Cycles =   0.26, SCTM Cycles =   0.10  ARP32 OVERHEAD =   165.84, MAC/CYCLE =   5.63 #MMACs =     1.47,     0.00,     1.47, Sparsity :   0.00, 100.00
 Layer   26 : TSC Cycles =   0.09, SCTM Cycles =   0.00  ARP32 OVERHEAD =     +inf, MAC/CYCLE =   0.07 #MMACs =     0.01,     0.00,     0.01, Sparsity :   0.00, 100.00
 Layer   27 : TSC Cycles =   0.26, SCTM Cycles =   0.10  ARP32 OVERHEAD =   165.55, MAC/CYCLE =   5.64 #MMACs =     1.47,     0.00,     1.47, Sparsity :   0.00, 100.00
 Layer   28 : TSC Cycles =   0.09, SCTM Cycles =   0.00  ARP32 OVERHEAD =     +inf, MAC/CYCLE =   0.06 #MMACs =     0.01,     0.00,     0.01, Sparsity :   0.00, 100.00
 Layer   29 : TSC Cycles =   0.21, SCTM Cycles =   0.03  ARP32 OVERHEAD =   668.22, MAC/CYCLE =   1.80 #MMACs =     0.37,     0.00,     0.37, Sparsity :   0.00, 100.00
 Layer   30 : TSC Cycles =   0.09, SCTM Cycles =   0.00  ARP32 OVERHEAD =     +inf, MAC/CYCLE =   0.02 #MMACs =     0.00,     0.00,     0.00, Sparsity :   0.00, 100.00
 Layer   31 : TSC Cycles =   0.21, SCTM Cycles =   0.03  ARP32 OVERHEAD =   672.36, MAC/CYCLE =   1.79 #MMACs =     0.37,     0.00,     0.37, Sparsity :   0.00, 100.00
 Layer   32 : TSC Cycles =   0.09, SCTM Cycles =   0.00  ARP32 OVERHEAD =     +inf, MAC/CYCLE =   0.02 #MMACs =     0.00,     0.00,     0.00, Sparsity :   0.00, 100.00
 Layer   33 : TSC Cycles =   0.20, SCTM Cycles =   0.01  ARP32 OVERHEAD =  1372.05, MAC/CYCLE =   0.55 #MMACs =     0.11,     0.00,     0.11, Sparsity :   0.00, 100.00
 Layer   34 : TSC Cycles =   0.09, SCTM Cycles =   0.00  ARP32 OVERHEAD =     +inf, MAC/CYCLE =   0.00 #MMACs =     0.00,     0.00,     0.00, Sparsity :   0.00, 100.00
 Layer   35 : TSC Cycles =   0.20, SCTM Cycles =   0.01  ARP32 OVERHEAD =  1369.78, MAC/CYCLE =   0.55 #MMACs =     0.11,     0.00,     0.11, Sparsity :   0.00, 100.00
 Layer   36 : TSC Cycles =   0.09, SCTM Cycles =   0.00  ARP32 OVERHEAD =     +inf, MAC/CYCLE =   0.00 #MMACs =     0.00,     0.00,     0.00, Sparsity :   0.00, 100.00
 Layer   37 : TSC Cycles =   0.19, SCTM Cycles =   0.01  ARP32 OVERHEAD =  3750.24, MAC/CYCLE =   0.13 #MMACs =     0.02,     0.00,     0.02, Sparsity :   0.00, 100.00
 Layer   38 : TSC Cycles =   0.08, SCTM Cycles =   0.00  ARP32 OVERHEAD =     +inf, MAC/CYCLE =   0.00 #MMACs =     0.00,     0.00,     0.00, Sparsity :   0.00, 100.00
 Layer   39 : TSC Cycles =   0.19, SCTM Cycles =   0.01  ARP32 OVERHEAD =  3765.67, MAC/CYCLE =   0.13 #MMACs =     0.02,     0.00,     0.02, Sparsity :   0.00, 100.00
 Layer   40 : TSC Cycles =   0.08, SCTM Cycles =   0.00  ARP32 OVERHEAD =     +inf, MAC/CYCLE =   0.00 #MMACs =     0.00,     0.00,     0.00, Sparsity :   0.00, 100.00
 Layer   41 : TSC Cycles =  36.73, SCTM Cycles =   0.00  ARP32 OVERHEAD =     +inf, MAC/CYCLE =   0.00 #MMACs =     0.00,     0.00,     0.00, Sparsity :    nan,    nan
 Layer   42 : TSC Cycles =  36.73, SCTM Cycles =   0.00  ARP32 OVERHEAD =     +inf, MAC/CYCLE =   0.00 #MMACs =     0.00,     0.00,     0.00, Sparsity :    nan,    nan
 Layer   43 : TSC Cycles = 1371.50, SCTM Cycles =   0.00  ARP32 OVERHEAD =     +inf, MAC/CYCLE =   0.00 #MMACs =     0.00,     0.00,     0.00, Sparsity :   0.00, 100.00
TEST_REPORT_PROCESS_PROFILE_DATA : TSC cycles = 1553601318, SCTM VCOP BUSY cycles = 70090474, SCTM VCOP Overhead = 0
I/O Bytes :        0 (        0 +        0 ) :        0 (        0 +        0 ) 
Out Q (0): 0