From 7596c1a71f53d6fed8ff0b33831df205ce6c290d Mon Sep 17 00:00:00 2001
From: Karan Saxena <karan@ti.com>
Date: Fri, 29 May 2020 10:00:31 +0530
Subject: [PATCH 3/4] mcuss_demos: profiling: can: Memory placement changes

- Use DDR carved out section for MCU2_1
- Put the MPU and cache setup functions in ATCM

Signed-off-by: Karan Saxena <karan@ti.com>
---
 .../j721e/mcu2_1/linker_r5_sysbios.lds        | 70 ++++++++++---------
 1 file changed, 38 insertions(+), 32 deletions(-)

diff --git a/mcuss_demos/profiling/can/overrides/j721e/mcu2_1/linker_r5_sysbios.lds b/mcuss_demos/profiling/can/overrides/j721e/mcu2_1/linker_r5_sysbios.lds
index c6f081e..f9d0479 100644
--- a/mcuss_demos/profiling/can/overrides/j721e/mcu2_1/linker_r5_sysbios.lds
+++ b/mcuss_demos/profiling/can/overrides/j721e/mcu2_1/linker_r5_sysbios.lds
@@ -44,7 +44,9 @@
 MEMORY
 {
     /* MCU0_R5F_0 local view 												  */
-    MCU0_R5F_TCMA (X)		: origin=0x0			length=0x8000
+    MCU0_R5F_TCMA (X)		: origin=0x0			length=0x100
+    /* For MPU and Cache setup functions */
+    NEW_ATCM (X)                : origin=0x100          length=0x8000 - 0x100
     MCU0_R5F_TCMB0 (RWIX)	: origin=0x41010000	length=0x8000
 
     /* MCU0_R5F_1 SoC view													  */
@@ -55,8 +57,8 @@ MEMORY
     OCMRAM 	(RWIX) 			: origin=0x41C00100 length=0x80000 - 0x1100	     /* ~510KB */
 
 
-    /* Used in this file */
-    DDR0_MCU_2_1 (RWIX)     : origin=0x9B000000 length=0x4000000
+    /* DDR region carved out from kernel accessible DDR space, for MCU2_1 */
+    DDR0_MCU_2_1 (RWIX)     : origin=0xA3100400 length=0x100000
 
     VECTORS (X)             : origin=0x70500200 length=0x1000
     RESET_VECTORS (X)       : origin=0x70501200 length=0x100
@@ -76,31 +78,35 @@ SECTIONS
     .vecs : {
          __VECS_ENTRY_POINT = .;
     } palign(8) > MCU0_R5F_TCMA
-    .intvecs 	: {} palign(8) 		> MAIN_MSRAM_0
-    .vecs 	: {} palign(8) 		> MAIN_MSRAM_0
-    .intc_text 	: {} palign(8) 		> MAIN_MSRAM_0
-    .rstvectors 	: {} palign(8) 		> MAIN_MSRAM_0
-    .text    	: {} palign(8) 		> MAIN_MSRAM_0
-    .const   	: {} palign(8) 		> MAIN_MSRAM_0
-    .cinit   	: {} palign(8) 		> MAIN_MSRAM_0
-    .pinit   	: {} palign(8) 		> MAIN_MSRAM_0
-
-    /* For NDK packet memory, we need to map this sections before .bss*/
-    .bss:NDK_MMBUFFER  (NOLOAD) {} ALIGN (128) > DDR0_MCU_2_1
-    .bss:NDK_PACKETMEM (NOLOAD) {} ALIGN (128) > DDR0_MCU_2_1
-
-    .bss     	: {} align(4)  		> MAIN_MSRAM_0
-    .far     	: {} align(4)  		> MAIN_MSRAM_0
-    .data    	: {} palign(128) 	> MAIN_MSRAM_0
-    .data_buffer: {} palign(128) 	> MAIN_MSRAM_0
-	.sysmem  	: {} 				> MAIN_MSRAM_0
-	.stack  	: {} align(4)		> MAIN_MSRAM_0  (HIGH)  fill=FILL_PATTERN
+
+    .text_boot {
+        *boot.aer5f<*boot.o*>(.text)
+     }  palign(8)   > NEW_ATCM
+    .text:xdc_runtime_Startup_reset__I     : {} palign(8) > NEW_ATCM
+    .text:ti_sysbios_family_arm_v7r_Cache* : {} palign(8) > NEW_ATCM
+    .text:ti_sysbios_family_arm_MPU*       : {} palign(8) > NEW_ATCM
+
+    .intvecs 	: {} palign(8) 		> DDR0_MCU_2_1
+    .vecs 	: {} palign(8) 		> DDR0_MCU_2_1
+    .intc_text 	: {} palign(8) 		> DDR0_MCU_2_1
+    .rstvectors 	: {} palign(8) 		> DDR0_MCU_2_1
+    .text    	: {} palign(8) 		> DDR0_MCU_2_1
+    .const   	: {} palign(8) 		> DDR0_MCU_2_1
+    .cinit   	: {} palign(8) 		> DDR0_MCU_2_1
+    .pinit   	: {} palign(8) 		> DDR0_MCU_2_1
+
+    .bss     	: {} align(4)  		> DDR0_MCU_2_1
+    .far     	: {} align(4)  		> DDR0_MCU_2_1
+    .data    	: {} palign(128) 	> DDR0_MCU_2_1
+    .data_buffer: {} palign(128) 	> DDR0_MCU_2_1
+	.sysmem  	: {} 				> DDR0_MCU_2_1
+	.stack  	: {} align(4)		> DDR0_MCU_2_1  (HIGH)  fill=FILL_PATTERN
 
     /* USB or any other LLD buffer for benchmarking */
-    .benchmark_buffer (NOLOAD) {} ALIGN (8) > MAIN_MSRAM_0
+    .benchmark_buffer (NOLOAD) {} ALIGN (8) > DDR0_MCU_2_1
 
     /* Additional sections settings     */
-    McalTextSection : fill=FILL_PATTERN, align=4, load > MAIN_MSRAM_0
+    McalTextSection : fill=FILL_PATTERN, align=4, load > DDR0_MCU_2_1
     {
         .=align(4);
         __linker_spi_text_start = .;
@@ -190,7 +196,7 @@ SECTIONS
         __linker_cdd_ipc_text_end = .;
 
     }
-    McalConstSection : fill=FILL_PATTERN, align=4, load > MAIN_MSRAM_0
+    McalConstSection : fill=FILL_PATTERN, align=4, load > DDR0_MCU_2_1
     {
         .=align(4);
         __linker_spi_const_start = .;
@@ -285,7 +291,7 @@ SECTIONS
         __linker_cdd_ipc_const_end = .;
     }
 
-    McalInitSection : fill=FILL_PATTERN, align=4, load > MAIN_MSRAM_0
+    McalInitSection : fill=FILL_PATTERN, align=4, load > DDR0_MCU_2_1
     {
         .=align(4);
         __linker_spi_init_start = .;
@@ -371,7 +377,7 @@ SECTIONS
         . += FILL_LENGTH;
         __linker_cdd_ipc_init_end = .;
     }
-    McalNoInitSection : fill=FILL_PATTERN, align=4, load > MAIN_MSRAM_0, type = NOINIT
+    McalNoInitSection : fill=FILL_PATTERN, align=4, load > DDR0_MCU_2_1, type = NOINIT
     {
         .=align(4);
         __linker_spi_no_init_start = .;
@@ -456,7 +462,7 @@ SECTIONS
 
     }
     /* Example Utility specifics */
-    UtilityNoInitSection : align=4, load > MAIN_MSRAM_0, type = NOINIT
+    UtilityNoInitSection : align=4, load > DDR0_MCU_2_1, type = NOINIT
     {
         .=align(4);
         __linker_utility_no_init_start = .;
@@ -466,7 +472,7 @@ SECTIONS
         . += FILL_LENGTH;
         __linker_utility_no_init_end = .;
     }
-    SciClientBoardCfgSection : align=128, load > MAIN_MSRAM_0, type = NOINIT
+    SciClientBoardCfgSection : align=128, load > DDR0_MCU_2_1, type = NOINIT
     {
         .=align(128);
         __linker_boardcfg_data_start = .;
@@ -478,7 +484,7 @@ SECTIONS
     }
     /* This section is used for descs and ring mems. It's best to have
      * it in OCMRAM or MSMC3 */
-    McalUdmaSection : fill=FILL_PATTERN, align=128, load > MAIN_MSRAM_0
+    McalUdmaSection : fill=FILL_PATTERN, align=128, load > DDR0_MCU_2_1
     {
         .=align(128);
         __linker_eth_udma_start = .;
@@ -488,7 +494,7 @@ SECTIONS
         . += FILL_LENGTH;
         __linker_eth_udma_end = .;
     }
-    McalTxDataSection : fill=FILL_PATTERN, align=128, load > MAIN_MSRAM_0, type = NOINIT
+    McalTxDataSection : fill=FILL_PATTERN, align=128, load > DDR0_MCU_2_1, type = NOINIT
     {
         .=align(128);
         __linker_eth_tx_data_start = .;
@@ -498,7 +504,7 @@ SECTIONS
         . += FILL_LENGTH;
         __linker_eth_tx_data_end = .;
     }
-    McalRxDataSection : fill=FILL_PATTERN, align=128, load > MAIN_MSRAM_0, type = NOINIT
+    McalRxDataSection : fill=FILL_PATTERN, align=128, load > DDR0_MCU_2_1, type = NOINIT
     {
         .=align(128);
         __linker_eth_rx_data_start = .;
-- 
2.26.2

