|------------------------------------------------------------------------------| | VERSION INFO | |------------------------------------------------------------------------------| | K3CONF | (version v0.1-88-g982f5c2 built Wed Mar 15 10:49:12 IST 2023) | | SoC | J721E SR2.0 | | SYSFW | ABI: 3.1 (firmware version 0x0009 '9.0.6--v09.00.06 (Kool Koala))') | |------------------------------------------------------------------------------| |------------------------------------------------------------------------------------------------------------------------------------------------| | Device ID | Clock ID | Clock Name | Status | Clock Frequency | |------------------------------------------------------------------------------------------------------------------------------------------------| | 4 | 0 | DEV_A72SS0_PLL_CTRL_CLK | CLK_STATE_READY | 500000000 | | 4 | 1 | DEV_A72SS0_MSMC_CLK | CLK_STATE_READY | 1000000000 | | 4 | 2 | DEV_A72SS0_ARM_CLK_CLK | CLK_STATE_READY | 2000000000 | | 202 | 2 | DEV_A72SS0_CORE0_ARM_CLK_CLK | CLK_STATE_READY | 2000000000 | | 203 | 0 | DEV_A72SS0_CORE1_ARM_CLK_CLK | CLK_STATE_READY | 2000000000 | | 139 | 0 | DEV_AASRC0_SYS_CLK | CLK_STATE_READY | 200000000 | | 139 | 1 | DEV_AASRC0_VBUSP_CLK | CLK_STATE_READY | 250000000 | | 139 | 2 | DEV_AASRC0_RX0_SYNC | CLK_STATE_READY | 0 | | 139 | 3 | DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP0_AFSR_OUT | CLK_STATE_READY | 0 | | 139 | 4 | DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP1_AFSR_OUT | CLK_STATE_READY | 0 | | 139 | 5 | DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP2_AFSR_OUT | CLK_STATE_READY | 0 | | 139 | 6 | DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP3_AFSR_OUT | CLK_STATE_READY | 0 | | 139 | 7 | DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP4_AFSR_OUT | CLK_STATE_READY | 0 | | 139 | 8 | DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP5_AFSR_OUT | CLK_STATE_READY | 0 | | 139 | 9 | DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP6_AFSR_OUT | CLK_STATE_READY | 0 | | 139 | 10 | DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP7_AFSR_OUT | CLK_STATE_READY | 0 | | 139 | 11 | DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP8_AFSR_OUT | CLK_STATE_READY | 0 | | 139 | 12 | DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP9_AFSR_OUT | CLK_STATE_READY | 0 | | 139 | 13 | DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP10_AFSR_OUT | CLK_STATE_READY | 0 | | 139 | 14 | DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP11_AFSR_OUT | CLK_STATE_READY | 0 | | 139 | 15 | DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 16 | DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 17 | DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 18 | DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 19 | DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 20 | DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 21 | DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 22 | DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 23 | DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 24 | DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 25 | DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 26 | DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 27 | DEV_AASRC0_RX0_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT0 | CLK_STATE_READY | 0 | | 139 | 28 | DEV_AASRC0_RX0_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT1 | CLK_STATE_READY | 0 | | 139 | 29 | DEV_AASRC0_RX0_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT2 | CLK_STATE_READY | 0 | | 139 | 30 | DEV_AASRC0_RX0_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT3 | CLK_STATE_READY | 0 | | 139 | 31 | DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MLB0_MLBCLK_OUT | CLK_STATE_READY | 0 | | 139 | 32 | DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MLB0_MLBCP_OUT2 | CLK_STATE_READY | 0 | | 139 | 33 | DEV_AASRC0_RX0_SYNC_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK | CLK_STATE_READY | 12288000 | | 139 | 34 | DEV_AASRC0_RX0_SYNC_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK | CLK_STATE_READY | 11289600 | | 139 | 35 | DEV_AASRC0_RX0_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT0 | CLK_STATE_READY | 19200000 | | 139 | 36 | DEV_AASRC0_RX0_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT1 | CLK_STATE_READY | 19200000 | | 139 | 37 | DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 139 | 38 | DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 139 | 39 | DEV_AASRC0_RX1_SYNC | CLK_STATE_READY | 0 | | 139 | 40 | DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP0_AFSR_OUT | CLK_STATE_READY | 0 | | 139 | 41 | DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP1_AFSR_OUT | CLK_STATE_READY | 0 | | 139 | 42 | DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP2_AFSR_OUT | CLK_STATE_READY | 0 | | 139 | 43 | DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP3_AFSR_OUT | CLK_STATE_READY | 0 | | 139 | 44 | DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP4_AFSR_OUT | CLK_STATE_READY | 0 | | 139 | 45 | DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP5_AFSR_OUT | CLK_STATE_READY | 0 | | 139 | 46 | DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP6_AFSR_OUT | CLK_STATE_READY | 0 | | 139 | 47 | DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP7_AFSR_OUT | CLK_STATE_READY | 0 | | 139 | 48 | DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP8_AFSR_OUT | CLK_STATE_READY | 0 | | 139 | 49 | DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP9_AFSR_OUT | CLK_STATE_READY | 0 | | 139 | 50 | DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP10_AFSR_OUT | CLK_STATE_READY | 0 | | 139 | 51 | DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP11_AFSR_OUT | CLK_STATE_READY | 0 | | 139 | 52 | DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 53 | DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 54 | DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 55 | DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 56 | DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 57 | DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 58 | DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 59 | DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 60 | DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 61 | DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 62 | DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 63 | DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 64 | DEV_AASRC0_RX1_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT0 | CLK_STATE_READY | 0 | | 139 | 65 | DEV_AASRC0_RX1_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT1 | CLK_STATE_READY | 0 | | 139 | 66 | DEV_AASRC0_RX1_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT2 | CLK_STATE_READY | 0 | | 139 | 67 | DEV_AASRC0_RX1_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT3 | CLK_STATE_READY | 0 | | 139 | 68 | DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MLB0_MLBCLK_OUT | CLK_STATE_READY | 0 | | 139 | 69 | DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MLB0_MLBCP_OUT2 | CLK_STATE_READY | 0 | | 139 | 70 | DEV_AASRC0_RX1_SYNC_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK | CLK_STATE_READY | 12288000 | | 139 | 71 | DEV_AASRC0_RX1_SYNC_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK | CLK_STATE_READY | 11289600 | | 139 | 72 | DEV_AASRC0_RX1_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT0 | CLK_STATE_READY | 19200000 | | 139 | 73 | DEV_AASRC0_RX1_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT1 | CLK_STATE_READY | 19200000 | | 139 | 74 | DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 139 | 75 | DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 139 | 76 | DEV_AASRC0_RX2_SYNC | CLK_STATE_READY | 0 | | 139 | 77 | DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP0_AFSR_OUT | CLK_STATE_READY | 0 | | 139 | 78 | DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP1_AFSR_OUT | CLK_STATE_READY | 0 | | 139 | 79 | DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP2_AFSR_OUT | CLK_STATE_READY | 0 | | 139 | 80 | DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP3_AFSR_OUT | CLK_STATE_READY | 0 | | 139 | 81 | DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP4_AFSR_OUT | CLK_STATE_READY | 0 | | 139 | 82 | DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP5_AFSR_OUT | CLK_STATE_READY | 0 | | 139 | 83 | DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP6_AFSR_OUT | CLK_STATE_READY | 0 | | 139 | 84 | DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP7_AFSR_OUT | CLK_STATE_READY | 0 | | 139 | 85 | DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP8_AFSR_OUT | CLK_STATE_READY | 0 | | 139 | 86 | DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP9_AFSR_OUT | CLK_STATE_READY | 0 | | 139 | 87 | DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP10_AFSR_OUT | CLK_STATE_READY | 0 | | 139 | 88 | DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP11_AFSR_OUT | CLK_STATE_READY | 0 | | 139 | 89 | DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 90 | DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 91 | DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 92 | DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 93 | DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 94 | DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 95 | DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 96 | DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 97 | DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 98 | DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 99 | DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 100 | DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 101 | DEV_AASRC0_RX2_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT0 | CLK_STATE_READY | 0 | | 139 | 102 | DEV_AASRC0_RX2_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT1 | CLK_STATE_READY | 0 | | 139 | 103 | DEV_AASRC0_RX2_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT2 | CLK_STATE_READY | 0 | | 139 | 104 | DEV_AASRC0_RX2_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT3 | CLK_STATE_READY | 0 | | 139 | 105 | DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MLB0_MLBCLK_OUT | CLK_STATE_READY | 0 | | 139 | 106 | DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MLB0_MLBCP_OUT2 | CLK_STATE_READY | 0 | | 139 | 107 | DEV_AASRC0_RX2_SYNC_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK | CLK_STATE_READY | 12288000 | | 139 | 108 | DEV_AASRC0_RX2_SYNC_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK | CLK_STATE_READY | 11289600 | | 139 | 109 | DEV_AASRC0_RX2_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT0 | CLK_STATE_READY | 19200000 | | 139 | 110 | DEV_AASRC0_RX2_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT1 | CLK_STATE_READY | 19200000 | | 139 | 111 | DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 139 | 112 | DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 139 | 113 | DEV_AASRC0_RX3_SYNC | CLK_STATE_READY | 0 | | 139 | 114 | DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP0_AFSR_OUT | CLK_STATE_READY | 0 | | 139 | 115 | DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP1_AFSR_OUT | CLK_STATE_READY | 0 | | 139 | 116 | DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP2_AFSR_OUT | CLK_STATE_READY | 0 | | 139 | 117 | DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP3_AFSR_OUT | CLK_STATE_READY | 0 | | 139 | 118 | DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP4_AFSR_OUT | CLK_STATE_READY | 0 | | 139 | 119 | DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP5_AFSR_OUT | CLK_STATE_READY | 0 | | 139 | 120 | DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP6_AFSR_OUT | CLK_STATE_READY | 0 | | 139 | 121 | DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP7_AFSR_OUT | CLK_STATE_READY | 0 | | 139 | 122 | DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP8_AFSR_OUT | CLK_STATE_READY | 0 | | 139 | 123 | DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP9_AFSR_OUT | CLK_STATE_READY | 0 | | 139 | 124 | DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP10_AFSR_OUT | CLK_STATE_READY | 0 | | 139 | 125 | DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP11_AFSR_OUT | CLK_STATE_READY | 0 | | 139 | 126 | DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 127 | DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 128 | DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 129 | DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 130 | DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 131 | DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 132 | DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 133 | DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 134 | DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 135 | DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 136 | DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 137 | DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 138 | DEV_AASRC0_RX3_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT0 | CLK_STATE_READY | 0 | | 139 | 139 | DEV_AASRC0_RX3_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT1 | CLK_STATE_READY | 0 | | 139 | 140 | DEV_AASRC0_RX3_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT2 | CLK_STATE_READY | 0 | | 139 | 141 | DEV_AASRC0_RX3_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT3 | CLK_STATE_READY | 0 | | 139 | 142 | DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MLB0_MLBCLK_OUT | CLK_STATE_READY | 0 | | 139 | 143 | DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MLB0_MLBCP_OUT2 | CLK_STATE_READY | 0 | | 139 | 144 | DEV_AASRC0_RX3_SYNC_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK | CLK_STATE_READY | 12288000 | | 139 | 145 | DEV_AASRC0_RX3_SYNC_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK | CLK_STATE_READY | 11289600 | | 139 | 146 | DEV_AASRC0_RX3_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT0 | CLK_STATE_READY | 19200000 | | 139 | 147 | DEV_AASRC0_RX3_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT1 | CLK_STATE_READY | 19200000 | | 139 | 148 | DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 139 | 149 | DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 139 | 150 | DEV_AASRC0_TX0_SYNC | CLK_STATE_READY | 0 | | 139 | 151 | DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 152 | DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 153 | DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0 | CLK_STATE_READY | 0 | | 139 | 154 | DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0 | CLK_STATE_READY | 0 | | 139 | 155 | DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0 | CLK_STATE_READY | 0 | | 139 | 156 | DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT_DUP0 | CLK_STATE_READY | 0 | | 139 | 157 | DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT_DUP0 | CLK_STATE_READY | 0 | | 139 | 158 | DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT_DUP0 | CLK_STATE_READY | 0 | | 139 | 159 | DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT_DUP0 | CLK_STATE_READY | 0 | | 139 | 160 | DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT_DUP0 | CLK_STATE_READY | 0 | | 139 | 161 | DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 162 | DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 163 | DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0 | CLK_STATE_READY | 0 | | 139 | 164 | DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0 | CLK_STATE_READY | 0 | | 139 | 165 | DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 166 | DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 167 | DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 168 | DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 169 | DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 170 | DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 171 | DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 172 | DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 173 | DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT_DUP0 | CLK_STATE_READY | 0 | | 139 | 174 | DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT_DUP0 | CLK_STATE_READY | 0 | | 139 | 175 | DEV_AASRC0_TX0_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT0 | CLK_STATE_READY | 0 | | 139 | 176 | DEV_AASRC0_TX0_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT1 | CLK_STATE_READY | 0 | | 139 | 177 | DEV_AASRC0_TX0_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT2 | CLK_STATE_READY | 0 | | 139 | 178 | DEV_AASRC0_TX0_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT3 | CLK_STATE_READY | 0 | | 139 | 179 | DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MLB0_MLBCLK_OUT | CLK_STATE_READY | 0 | | 139 | 180 | DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MLB0_MLBCP_OUT2 | CLK_STATE_READY | 0 | | 139 | 181 | DEV_AASRC0_TX0_SYNC_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK | CLK_STATE_READY | 12288000 | | 139 | 182 | DEV_AASRC0_TX0_SYNC_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK | CLK_STATE_READY | 11289600 | | 139 | 183 | DEV_AASRC0_TX0_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT0 | CLK_STATE_READY | 19200000 | | 139 | 184 | DEV_AASRC0_TX0_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT1 | CLK_STATE_READY | 19200000 | | 139 | 185 | DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 139 | 186 | DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 139 | 187 | DEV_AASRC0_TX1_SYNC | CLK_STATE_READY | 0 | | 139 | 188 | DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 189 | DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 190 | DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0 | CLK_STATE_READY | 0 | | 139 | 191 | DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0 | CLK_STATE_READY | 0 | | 139 | 192 | DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0 | CLK_STATE_READY | 0 | | 139 | 193 | DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT_DUP0 | CLK_STATE_READY | 0 | | 139 | 194 | DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT_DUP0 | CLK_STATE_READY | 0 | | 139 | 195 | DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT_DUP0 | CLK_STATE_READY | 0 | | 139 | 196 | DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT_DUP0 | CLK_STATE_READY | 0 | | 139 | 197 | DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT_DUP0 | CLK_STATE_READY | 0 | | 139 | 198 | DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 199 | DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 200 | DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0 | CLK_STATE_READY | 0 | | 139 | 201 | DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0 | CLK_STATE_READY | 0 | | 139 | 202 | DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 203 | DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 204 | DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 205 | DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 206 | DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 207 | DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 208 | DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 209 | DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 210 | DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT_DUP0 | CLK_STATE_READY | 0 | | 139 | 211 | DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT_DUP0 | CLK_STATE_READY | 0 | | 139 | 212 | DEV_AASRC0_TX1_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT0 | CLK_STATE_READY | 0 | | 139 | 213 | DEV_AASRC0_TX1_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT1 | CLK_STATE_READY | 0 | | 139 | 214 | DEV_AASRC0_TX1_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT2 | CLK_STATE_READY | 0 | | 139 | 215 | DEV_AASRC0_TX1_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT3 | CLK_STATE_READY | 0 | | 139 | 216 | DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MLB0_MLBCLK_OUT | CLK_STATE_READY | 0 | | 139 | 217 | DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MLB0_MLBCP_OUT2 | CLK_STATE_READY | 0 | | 139 | 218 | DEV_AASRC0_TX1_SYNC_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK | CLK_STATE_READY | 12288000 | | 139 | 219 | DEV_AASRC0_TX1_SYNC_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK | CLK_STATE_READY | 11289600 | | 139 | 220 | DEV_AASRC0_TX1_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT0 | CLK_STATE_READY | 19200000 | | 139 | 221 | DEV_AASRC0_TX1_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT1 | CLK_STATE_READY | 19200000 | | 139 | 222 | DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 139 | 223 | DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 139 | 224 | DEV_AASRC0_TX2_SYNC | CLK_STATE_READY | 0 | | 139 | 225 | DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 226 | DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 227 | DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0 | CLK_STATE_READY | 0 | | 139 | 228 | DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0 | CLK_STATE_READY | 0 | | 139 | 229 | DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0 | CLK_STATE_READY | 0 | | 139 | 230 | DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT_DUP0 | CLK_STATE_READY | 0 | | 139 | 231 | DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT_DUP0 | CLK_STATE_READY | 0 | | 139 | 232 | DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT_DUP0 | CLK_STATE_READY | 0 | | 139 | 233 | DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT_DUP0 | CLK_STATE_READY | 0 | | 139 | 234 | DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT_DUP0 | CLK_STATE_READY | 0 | | 139 | 235 | DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 236 | DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 237 | DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0 | CLK_STATE_READY | 0 | | 139 | 238 | DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0 | CLK_STATE_READY | 0 | | 139 | 239 | DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 240 | DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 241 | DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 242 | DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 243 | DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 244 | DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 245 | DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 246 | DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 247 | DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT_DUP0 | CLK_STATE_READY | 0 | | 139 | 248 | DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT_DUP0 | CLK_STATE_READY | 0 | | 139 | 249 | DEV_AASRC0_TX2_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT0 | CLK_STATE_READY | 0 | | 139 | 250 | DEV_AASRC0_TX2_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT1 | CLK_STATE_READY | 0 | | 139 | 251 | DEV_AASRC0_TX2_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT2 | CLK_STATE_READY | 0 | | 139 | 252 | DEV_AASRC0_TX2_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT3 | CLK_STATE_READY | 0 | | 139 | 253 | DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MLB0_MLBCLK_OUT | CLK_STATE_READY | 0 | | 139 | 254 | DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MLB0_MLBCP_OUT2 | CLK_STATE_READY | 0 | | 139 | 255 | DEV_AASRC0_TX2_SYNC_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK | CLK_STATE_READY | 12288000 | | 139 | 256 | DEV_AASRC0_TX2_SYNC_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK | CLK_STATE_READY | 11289600 | | 139 | 257 | DEV_AASRC0_TX2_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT0 | CLK_STATE_READY | 19200000 | | 139 | 258 | DEV_AASRC0_TX2_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT1 | CLK_STATE_READY | 19200000 | | 139 | 259 | DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 139 | 260 | DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 139 | 261 | DEV_AASRC0_TX3_SYNC | CLK_STATE_READY | 0 | | 139 | 262 | DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 263 | DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 264 | DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0 | CLK_STATE_READY | 0 | | 139 | 265 | DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0 | CLK_STATE_READY | 0 | | 139 | 266 | DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0 | CLK_STATE_READY | 0 | | 139 | 267 | DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT_DUP0 | CLK_STATE_READY | 0 | | 139 | 268 | DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT_DUP0 | CLK_STATE_READY | 0 | | 139 | 269 | DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT_DUP0 | CLK_STATE_READY | 0 | | 139 | 270 | DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT_DUP0 | CLK_STATE_READY | 0 | | 139 | 271 | DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT_DUP0 | CLK_STATE_READY | 0 | | 139 | 272 | DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 273 | DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 274 | DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0 | CLK_STATE_READY | 0 | | 139 | 275 | DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0 | CLK_STATE_READY | 0 | | 139 | 276 | DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 277 | DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 278 | DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 279 | DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 280 | DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 281 | DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 282 | DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 283 | DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT | CLK_STATE_READY | 0 | | 139 | 284 | DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT_DUP0 | CLK_STATE_READY | 0 | | 139 | 285 | DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT_DUP0 | CLK_STATE_READY | 0 | | 139 | 286 | DEV_AASRC0_TX3_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT0 | CLK_STATE_READY | 0 | | 139 | 287 | DEV_AASRC0_TX3_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT1 | CLK_STATE_READY | 0 | | 139 | 288 | DEV_AASRC0_TX3_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT2 | CLK_STATE_READY | 0 | | 139 | 289 | DEV_AASRC0_TX3_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT3 | CLK_STATE_READY | 0 | | 139 | 290 | DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MLB0_MLBCLK_OUT | CLK_STATE_READY | 0 | | 139 | 291 | DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MLB0_MLBCP_OUT2 | CLK_STATE_READY | 0 | | 139 | 292 | DEV_AASRC0_TX3_SYNC_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK | CLK_STATE_READY | 12288000 | | 139 | 293 | DEV_AASRC0_TX3_SYNC_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK | CLK_STATE_READY | 11289600 | | 139 | 294 | DEV_AASRC0_TX3_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT0 | CLK_STATE_READY | 19200000 | | 139 | 295 | DEV_AASRC0_TX3_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT1 | CLK_STATE_READY | 19200000 | | 139 | 296 | DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 139 | 297 | DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 337 | 0 | DEV_ASCPCIE_BUFFER0_CLKIN0 | CLK_STATE_NOT_READY | 0 | | 337 | 1 | DEV_ASCPCIE_BUFFER0_CLKIN0_PARENT_WIZ16B4M4CS_MAIN_0_REF_DER_OUT_CLK | CLK_STATE_NOT_READY | 0 | | 337 | 2 | DEV_ASCPCIE_BUFFER0_CLKIN0_PARENT_WIZ16B4M4CS_MAIN_1_REF_DER_OUT_CLK | CLK_STATE_READY | 0 | | 337 | 3 | DEV_ASCPCIE_BUFFER0_CLKIN0_PARENT_WIZ16B4M4CS_MAIN_0_REF1_OUT_CLK | CLK_STATE_NOT_READY | 0 | | 337 | 4 | DEV_ASCPCIE_BUFFER0_CLKIN0_PARENT_WIZ16B4M4CS_MAIN_1_REF1_OUT_CLK | CLK_STATE_READY | 0 | | 337 | 5 | DEV_ASCPCIE_BUFFER0_CLKIN1 | CLK_STATE_READY | 0 | | 337 | 6 | DEV_ASCPCIE_BUFFER0_CLKIN1_PARENT_WIZ16B4M4CS_MAIN_0_REF_DER_OUT_CLK | CLK_STATE_NOT_READY | 0 | | 337 | 7 | DEV_ASCPCIE_BUFFER0_CLKIN1_PARENT_WIZ16B4M4CS_MAIN_1_REF_DER_OUT_CLK | CLK_STATE_READY | 0 | | 337 | 8 | DEV_ASCPCIE_BUFFER0_CLKIN1_PARENT_WIZ16B4M4CS_MAIN_0_REF1_OUT_CLK | CLK_STATE_NOT_READY | 0 | | 337 | 9 | DEV_ASCPCIE_BUFFER0_CLKIN1_PARENT_WIZ16B4M4CS_MAIN_1_REF1_OUT_CLK | CLK_STATE_READY | 0 | | 337 | 10 | DEV_ASCPCIE_BUFFER0_CLKOUT0_N | CLK_STATE_READY | 0 | | 337 | 11 | DEV_ASCPCIE_BUFFER0_CLKOUT0_P | CLK_STATE_READY | 0 | | 337 | 12 | DEV_ASCPCIE_BUFFER0_CLKOUT1_N | CLK_STATE_READY | 0 | | 337 | 13 | DEV_ASCPCIE_BUFFER0_CLKOUT1_P | CLK_STATE_READY | 0 | | 338 | 0 | DEV_ASCPCIE_BUFFER1_CLKIN0 | CLK_STATE_READY | 0 | | 338 | 1 | DEV_ASCPCIE_BUFFER1_CLKIN0_PARENT_WIZ16B4M4CS_MAIN_2_REF_DER_OUT_CLK | CLK_STATE_READY | 0 | | 338 | 2 | DEV_ASCPCIE_BUFFER1_CLKIN0_PARENT_WIZ16B4M4CS_MAIN_3_REF_DER_OUT_CLK | CLK_STATE_READY | 0 | | 338 | 3 | DEV_ASCPCIE_BUFFER1_CLKIN0_PARENT_WIZ16B4M4CS_MAIN_2_REF1_OUT_CLK | CLK_STATE_READY | 0 | | 338 | 4 | DEV_ASCPCIE_BUFFER1_CLKIN0_PARENT_WIZ16B4M4CS_MAIN_3_REF1_OUT_CLK | CLK_STATE_READY | 0 | | 338 | 5 | DEV_ASCPCIE_BUFFER1_CLKIN1 | CLK_STATE_READY | 0 | | 338 | 6 | DEV_ASCPCIE_BUFFER1_CLKIN1_PARENT_WIZ16B4M4CS_MAIN_2_REF_DER_OUT_CLK | CLK_STATE_READY | 0 | | 338 | 7 | DEV_ASCPCIE_BUFFER1_CLKIN1_PARENT_WIZ16B4M4CS_MAIN_3_REF_DER_OUT_CLK | CLK_STATE_READY | 0 | | 338 | 8 | DEV_ASCPCIE_BUFFER1_CLKIN1_PARENT_WIZ16B4M4CS_MAIN_2_REF1_OUT_CLK | CLK_STATE_READY | 0 | | 338 | 9 | DEV_ASCPCIE_BUFFER1_CLKIN1_PARENT_WIZ16B4M4CS_MAIN_3_REF1_OUT_CLK | CLK_STATE_READY | 0 | | 338 | 10 | DEV_ASCPCIE_BUFFER1_CLKOUT0_N | CLK_STATE_READY | 0 | | 338 | 11 | DEV_ASCPCIE_BUFFER1_CLKOUT0_P | CLK_STATE_READY | 0 | | 338 | 12 | DEV_ASCPCIE_BUFFER1_CLKOUT1_N | CLK_STATE_READY | 0 | | 338 | 13 | DEV_ASCPCIE_BUFFER1_CLKOUT1_P | CLK_STATE_READY | 0 | | 2 | 0 | DEV_ATL0_VBUS_CLK | CLK_STATE_READY | 250000000 | | 2 | 1 | DEV_ATL0_ATL_CLK | CLK_STATE_READY | 294912000 | | 2 | 2 | DEV_ATL0_ATL_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT1_CLK | CLK_STATE_READY | 294912000 | | 2 | 3 | DEV_ATL0_ATL_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | 2 | 4 | DEV_ATL0_ATL_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT1_CLK | CLK_STATE_READY | 270950400 | | 2 | 5 | DEV_ATL0_ATL_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT7_CLK | CLK_STATE_READY | 200000000 | | 2 | 6 | DEV_ATL0_ATL_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 2 | 7 | DEV_ATL0_ATL_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 2 | 8 | DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_READY | 0 | | 2 | 9 | DEV_ATL0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_READY | 0 | | 2 | 10 | DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_READY | 0 | | 2 | 11 | DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_READY | 0 | | 157 | 0 | DEV_BOARD0_SPI0_CLK_IN | CLK_STATE_READY | 0 | | 157 | 2 | DEV_BOARD0_SPI1_CLK_IN | CLK_STATE_READY | 0 | | 157 | 4 | DEV_BOARD0_SPI2_CLK_IN | CLK_STATE_READY | 0 | | 157 | 6 | DEV_BOARD0_SPI3_CLK_IN | CLK_STATE_READY | 0 | | 157 | 8 | DEV_BOARD0_SPI5_CLK_IN | CLK_STATE_READY | 0 | | 157 | 10 | DEV_BOARD0_SPI6_CLK_IN | CLK_STATE_READY | 0 | | 157 | 12 | DEV_BOARD0_SPI7_CLK_IN | CLK_STATE_READY | 0 | | 157 | 14 | DEV_BOARD0_MCU_SPI0_CLK_IN | CLK_STATE_READY | 0 | | 157 | 16 | DEV_BOARD0_MCU_SPI1_CLK_IN | CLK_STATE_READY | 0 | | 157 | 18 | DEV_BOARD0_MCU_OSPI0_CLK_IN | CLK_STATE_READY | 0 | | 157 | 19 | DEV_BOARD0_MCU_OSPI0_LBCLKO_IN | CLK_STATE_READY | 0 | | 157 | 20 | DEV_BOARD0_MCU_OSPI0_DQS_OUT | CLK_STATE_READY | 0 | | 157 | 21 | DEV_BOARD0_MCU_OSPI1_CLK_IN | CLK_STATE_READY | 0 | | 157 | 22 | DEV_BOARD0_MCU_OSPI1_LBCLKO_IN | CLK_STATE_READY | 0 | | 157 | 23 | DEV_BOARD0_MCU_OSPI1_DQS_OUT | CLK_STATE_READY | 0 | | 157 | 25 | DEV_BOARD0_I2C0_SCL_OUT | CLK_STATE_READY | 0 | | 157 | 27 | DEV_BOARD0_I2C1_SCL_OUT | CLK_STATE_READY | 0 | | 157 | 29 | DEV_BOARD0_I2C2_SCL_OUT | CLK_STATE_READY | 0 | | 157 | 31 | DEV_BOARD0_I2C3_SCL_OUT | CLK_STATE_READY | 0 | | 157 | 33 | DEV_BOARD0_I2C4_SCL_OUT | CLK_STATE_READY | 0 | | 157 | 35 | DEV_BOARD0_I2C5_SCL_OUT | CLK_STATE_READY | 0 | | 157 | 37 | DEV_BOARD0_I2C6_SCL_OUT | CLK_STATE_READY | 0 | | 157 | 38 | DEV_BOARD0_MCU_I2C0_SCL_IN | CLK_STATE_READY | 0 | | 157 | 39 | DEV_BOARD0_MCU_I2C0_SCL_OUT | CLK_STATE_READY | 0 | | 157 | 41 | DEV_BOARD0_MCU_I2C1_SCL_OUT | CLK_STATE_READY | 0 | | 157 | 42 | DEV_BOARD0_WKUP_I2C0_SCL_IN | CLK_STATE_READY | 0 | | 157 | 43 | DEV_BOARD0_WKUP_I2C0_SCL_OUT | CLK_STATE_READY | 0 | | 157 | 44 | DEV_BOARD0_I3C0_SCL_IN | CLK_STATE_READY | 0 | | 157 | 45 | DEV_BOARD0_I3C0_SCL_OUT | CLK_STATE_READY | 0 | | 157 | 46 | DEV_BOARD0_MCU_I3C0_SCL_IN | CLK_STATE_READY | 0 | | 157 | 47 | DEV_BOARD0_MCU_I3C0_SCL_OUT | CLK_STATE_READY | 0 | | 157 | 48 | DEV_BOARD0_MCU_I3C1_SCL_IN | CLK_STATE_READY | 0 | | 157 | 49 | DEV_BOARD0_MCU_I3C1_SCL_OUT | CLK_STATE_READY | 0 | | 157 | 50 | DEV_BOARD0_MCU_HYPERBUS0_CK_IN | CLK_STATE_READY | 0 | | 157 | 51 | DEV_BOARD0_MCU_HYPERBUS0_CKN_IN | CLK_STATE_READY | 0 | | 157 | 52 | DEV_BOARD0_DSI_TXCLKP_IN | CLK_STATE_READY | 0 | | 157 | 53 | DEV_BOARD0_DSI_TXCLKN_IN | CLK_STATE_READY | 0 | | 157 | 54 | DEV_BOARD0_PRG0_MDIO0_MDC_IN | CLK_STATE_READY | 0 | | 157 | 55 | DEV_BOARD0_PRG0_RGMII1_TXC_IN | CLK_STATE_READY | 0 | | 157 | 56 | DEV_BOARD0_PRG0_RGMII1_TXC_OUT | CLK_STATE_READY | 0 | | 157 | 57 | DEV_BOARD0_PRG0_RGMII1_RXC_OUT | CLK_STATE_READY | 0 | | 157 | 58 | DEV_BOARD0_PRG0_RGMII2_TXC_IN | CLK_STATE_READY | 0 | | 157 | 59 | DEV_BOARD0_PRG0_RGMII2_TXC_OUT | CLK_STATE_READY | 0 | | 157 | 60 | DEV_BOARD0_PRG0_RGMII2_RXC_OUT | CLK_STATE_READY | 0 | | 157 | 61 | DEV_BOARD0_PRG1_MDIO0_MDC_IN | CLK_STATE_READY | 0 | | 157 | 62 | DEV_BOARD0_PRG1_RGMII1_TXC_IN | CLK_STATE_READY | 0 | | 157 | 63 | DEV_BOARD0_PRG1_RGMII1_TXC_OUT | CLK_STATE_READY | 0 | | 157 | 64 | DEV_BOARD0_PRG1_RGMII1_RXC_OUT | CLK_STATE_READY | 0 | | 157 | 65 | DEV_BOARD0_PRG1_RGMII2_TXC_IN | CLK_STATE_READY | 0 | | 157 | 66 | DEV_BOARD0_PRG1_RGMII2_TXC_OUT | CLK_STATE_READY | 0 | | 157 | 67 | DEV_BOARD0_PRG1_RGMII2_RXC_OUT | CLK_STATE_READY | 0 | | 157 | 68 | DEV_BOARD0_MDIO0_MDC_IN | CLK_STATE_READY | 0 | | 157 | 70 | DEV_BOARD0_RGMII3_RXC_OUT | CLK_STATE_READY | 0 | | 157 | 72 | DEV_BOARD0_RGMII4_RXC_OUT | CLK_STATE_READY | 0 | | 157 | 74 | DEV_BOARD0_RGMII5_RXC_OUT | CLK_STATE_READY | 0 | | 157 | 76 | DEV_BOARD0_RGMII6_RXC_OUT | CLK_STATE_READY | 0 | | 157 | 78 | DEV_BOARD0_RGMII7_RXC_OUT | CLK_STATE_READY | 0 | | 157 | 80 | DEV_BOARD0_RGMII8_RXC_OUT | CLK_STATE_READY | 0 | | 157 | 81 | DEV_BOARD0_RMII_REF_CLK_OUT | CLK_STATE_READY | 0 | | 157 | 82 | DEV_BOARD0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 157 | 83 | DEV_BOARD0_MCU_MDIO0_MDC_IN | CLK_STATE_READY | 0 | | 157 | 84 | DEV_BOARD0_MCU_RGMII1_TXC_IN | CLK_STATE_READY | 0 | | 157 | 85 | DEV_BOARD0_MCU_RGMII1_TXC_OUT | CLK_STATE_READY | 0 | | 157 | 86 | DEV_BOARD0_MCU_RGMII1_RXC_OUT | CLK_STATE_READY | 0 | | 157 | 87 | DEV_BOARD0_MCU_RMII1_REF_CLK_OUT | CLK_STATE_READY | 0 | | 157 | 88 | DEV_BOARD0_MCU_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 157 | 89 | DEV_BOARD0_UFS0_REF_CLK_IN | CLK_STATE_READY | 0 | | 157 | 91 | DEV_BOARD0_DDR0_CK0_IN | CLK_STATE_READY | 0 | | 157 | 92 | DEV_BOARD0_DDR0_CK0_N_IN | CLK_STATE_READY | 0 | | 157 | 99 | DEV_BOARD0_MMC0_CLK_IN | CLK_STATE_READY | 0 | | 157 | 100 | DEV_BOARD0_MMC1_CLK_IN | CLK_STATE_READY | 0 | | 157 | 101 | DEV_BOARD0_MMC2_CLK_IN | CLK_STATE_READY | 0 | | 157 | 102 | DEV_BOARD0_GPMC0_CLK_IN | CLK_STATE_READY | 0 | | 157 | 103 | DEV_BOARD0_GPMC0_CLK_OUT | CLK_STATE_READY | 0 | | 157 | 104 | DEV_BOARD0_GPMC0_FCLK_MUX_IN | CLK_STATE_READY | 125000000 | | 157 | 105 | DEV_BOARD0_MLB0_MLBCLK_OUT | CLK_STATE_READY | 0 | | 157 | 106 | DEV_BOARD0_MLB0_MLBCP_OUT | CLK_STATE_READY | 0 | | 157 | 108 | DEV_BOARD0_VPFE0_PCLK_OUT | CLK_STATE_READY | 0 | | 157 | 109 | DEV_BOARD0_VOUT1_PCLK_IN | CLK_STATE_READY | 600000000 | | 157 | 110 | DEV_BOARD0_VOUT1_EXTPCLKIN_OUT | CLK_STATE_READY | 0 | | 157 | 111 | DEV_BOARD0_VOUT2_PCLK_IN | CLK_STATE_READY | 600000000 | | 157 | 112 | DEV_BOARD0_VOUT2_EXTPCLKIN_OUT | CLK_STATE_READY | 0 | | 157 | 113 | DEV_BOARD0_OBSCLK0_IN | CLK_STATE_READY | 19200000 | | 157 | 114 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK | CLK_STATE_READY | 500000000 | | 157 | 115 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT0_CLK | CLK_STATE_READY | 192000000 | | 157 | 116 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK | CLK_STATE_READY | 225000000 | | 157 | 117 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK | CLK_STATE_READY | 250000000 | | 157 | 118 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK | CLK_STATE_READY | 196608000 | | 157 | 119 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV3_16FFT_MAIN_5_HSDIVOUT0_CLK | CLK_STATE_READY | 687500000 | | 157 | 120 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_6_HSDIVOUT0_CLK | CLK_STATE_READY | 750000000 | | 157 | 126 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_12_HSDIVOUT0_CLK | CLK_STATE_READY | 1066500000 | | 157 | 127 | DEV_BOARD0_OBSCLK0_IN_PARENT_OBSCLK1_MUX_OUT0 | CLK_STATE_READY | 250000000 | | 157 | 128 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_14_HSDIVOUT0_CLK | CLK_STATE_READY | 1000000000 | | 157 | 129 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK | CLK_STATE_READY | 180633600 | | 157 | 130 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK | CLK_STATE_READY | 600000000 | | 157 | 131 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK | CLK_STATE_READY | 600000000 | | 157 | 132 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_18_HSDIVOUT0_CLK | CLK_STATE_READY | 600000000 | | 157 | 133 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_19_HSDIVOUT0_CLK | CLK_STATE_READY | 600000000 | | 157 | 137 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_23_HSDIVOUT0_CLK | CLK_STATE_READY | 600000000 | | 157 | 138 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_24_HSDIVOUT0_CLK | CLK_STATE_NOT_READY | 0 | | 157 | 139 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_25_HSDIVOUT0_CLK | CLK_STATE_READY | 520000000 | | 157 | 140 | DEV_BOARD0_OBSCLK0_IN_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | 157 | 141 | DEV_BOARD0_OBSCLK0_IN_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 157 | 142 | DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 157 | 143 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK_DUP0 | CLK_STATE_READY | 500000000 | | 157 | 144 | DEV_BOARD0_OBSCLK0_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 157 | 145 | DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 157 | 146 | DEV_BOARD0_OBSCLK1_IN | CLK_STATE_READY | 250000000 | | 157 | 147 | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV0_16FFT_MAIN_7_HSDIVOUT0_CLK4 | CLK_STATE_READY | 250000000 | | 157 | 148 | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV0_16FFT_MAIN_8_HSDIVOUT0_CLK8 | CLK_STATE_READY | 250000000 | | 157 | 149 | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV3_16FFT_MAIN_13_HSDIVOUT0_CLK4 | CLK_STATE_READY | 337500000 | | 157 | 152 | DEV_BOARD0_MCU_OBSCLK0_IN | CLK_STATE_READY | 12500000 | | 157 | 153 | DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_MCU_OBSCLK_DIV_OUT0 | CLK_STATE_READY | 12500000 | | 157 | 154 | DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 157 | 169 | DEV_BOARD0_SYSCLKOUT0_IN | CLK_STATE_READY | 500000000 | | 157 | 170 | DEV_BOARD0_MCU_SYSCLKOUT0_IN | CLK_STATE_READY | 1000000000 | | 157 | 171 | DEV_BOARD0_TRC_CLK_IN | CLK_STATE_READY | 0 | | 157 | 172 | DEV_BOARD0_CLKOUT_IN | CLK_STATE_READY | 50000000 | | 157 | 173 | DEV_BOARD0_CLKOUT_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK5 | CLK_STATE_READY | 50000000 | | 157 | 174 | DEV_BOARD0_CLKOUT_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK10 | CLK_STATE_READY | 25000000 | | 157 | 175 | DEV_BOARD0_MCU_CLKOUT0_IN | CLK_STATE_READY | 50000000 | | 157 | 176 | DEV_BOARD0_MCU_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT0_CLK5 | CLK_STATE_READY | 50000000 | | 157 | 177 | DEV_BOARD0_MCU_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT0_CLK10 | CLK_STATE_READY | 25000000 | | 157 | 178 | DEV_BOARD0_LED_CLK_OUT | CLK_STATE_READY | 0 | | 157 | 179 | DEV_BOARD0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 157 | 180 | DEV_BOARD0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 157 | 181 | DEV_BOARD0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 157 | 182 | DEV_BOARD0_TCK_OUT | CLK_STATE_READY | 0 | | 157 | 183 | DEV_BOARD0_PCIE_REFCLK0P_IN | CLK_STATE_READY | 0 | | 157 | 184 | DEV_BOARD0_PCIE_REFCLK0N_IN | CLK_STATE_READY | 0 | | 157 | 185 | DEV_BOARD0_PCIE_REFCLK0P_OUT | CLK_STATE_READY | 0 | | 157 | 186 | DEV_BOARD0_PCIE_REFCLK0N_OUT | CLK_STATE_READY | 0 | | 157 | 187 | DEV_BOARD0_PCIE_REFCLK0P_OUT_IN | CLK_STATE_READY | 0 | | 157 | 188 | DEV_BOARD0_PCIE_REFCLK0N_OUT_IN | CLK_STATE_READY | 0 | | 157 | 189 | DEV_BOARD0_PCIE_REFCLK1P_IN | CLK_STATE_READY | 0 | | 157 | 190 | DEV_BOARD0_PCIE_REFCLK1N_IN | CLK_STATE_READY | 0 | | 157 | 191 | DEV_BOARD0_PCIE_REFCLK1P_OUT | CLK_STATE_READY | 0 | | 157 | 192 | DEV_BOARD0_PCIE_REFCLK1N_OUT | CLK_STATE_READY | 0 | | 157 | 193 | DEV_BOARD0_PCIE_REFCLK1P_OUT_IN | CLK_STATE_READY | 0 | | 157 | 194 | DEV_BOARD0_PCIE_REFCLK1N_OUT_IN | CLK_STATE_READY | 0 | | 157 | 195 | DEV_BOARD0_PCIE_REFCLK2P_IN | CLK_STATE_READY | 0 | | 157 | 196 | DEV_BOARD0_PCIE_REFCLK2N_IN | CLK_STATE_READY | 0 | | 157 | 197 | DEV_BOARD0_PCIE_REFCLK2P_OUT | CLK_STATE_READY | 0 | | 157 | 198 | DEV_BOARD0_PCIE_REFCLK2N_OUT | CLK_STATE_READY | 0 | | 157 | 201 | DEV_BOARD0_PCIE_REFCLK3P_OUT | CLK_STATE_READY | 0 | | 157 | 202 | DEV_BOARD0_PCIE_REFCLK3N_OUT | CLK_STATE_READY | 0 | | 157 | 203 | DEV_BOARD0_PCIE_REFCLK3P_IN | CLK_STATE_READY | 0 | | 157 | 204 | DEV_BOARD0_PCIE_REFCLK3N_IN | CLK_STATE_READY | 0 | | 157 | 217 | DEV_BOARD0_MCASP0_ACLKR_IN | CLK_STATE_READY | 0 | | 157 | 218 | DEV_BOARD0_MCASP0_ACLKR_OUT | CLK_STATE_READY | 0 | | 157 | 219 | DEV_BOARD0_MCASP0_AFSR_OUT | CLK_STATE_READY | 0 | | 157 | 220 | DEV_BOARD0_MCASP0_ACLKX_IN | CLK_STATE_READY | 0 | | 157 | 221 | DEV_BOARD0_MCASP0_ACLKX_OUT | CLK_STATE_READY | 0 | | 157 | 222 | DEV_BOARD0_MCASP0_AFSX_OUT | CLK_STATE_READY | 0 | | 157 | 223 | DEV_BOARD0_MCASP1_ACLKR_IN | CLK_STATE_READY | 0 | | 157 | 224 | DEV_BOARD0_MCASP1_ACLKR_OUT | CLK_STATE_READY | 0 | | 157 | 225 | DEV_BOARD0_MCASP1_AFSR_OUT | CLK_STATE_READY | 0 | | 157 | 226 | DEV_BOARD0_MCASP1_ACLKX_IN | CLK_STATE_READY | 0 | | 157 | 227 | DEV_BOARD0_MCASP1_ACLKX_OUT | CLK_STATE_READY | 0 | | 157 | 228 | DEV_BOARD0_MCASP1_AFSX_OUT | CLK_STATE_READY | 0 | | 157 | 229 | DEV_BOARD0_MCASP2_ACLKR_IN | CLK_STATE_READY | 0 | | 157 | 230 | DEV_BOARD0_MCASP2_ACLKR_OUT | CLK_STATE_READY | 0 | | 157 | 231 | DEV_BOARD0_MCASP2_AFSR_OUT | CLK_STATE_READY | 0 | | 157 | 232 | DEV_BOARD0_MCASP2_ACLKX_IN | CLK_STATE_READY | 0 | | 157 | 233 | DEV_BOARD0_MCASP2_ACLKX_OUT | CLK_STATE_READY | 0 | | 157 | 234 | DEV_BOARD0_MCASP2_AFSX_OUT | CLK_STATE_READY | 0 | | 157 | 235 | DEV_BOARD0_MCASP3_ACLKR_IN | CLK_STATE_READY | 0 | | 157 | 236 | DEV_BOARD0_MCASP3_ACLKR_OUT | CLK_STATE_READY | 0 | | 157 | 237 | DEV_BOARD0_MCASP3_AFSR_OUT | CLK_STATE_READY | 0 | | 157 | 238 | DEV_BOARD0_MCASP3_ACLKX_IN | CLK_STATE_READY | 0 | | 157 | 239 | DEV_BOARD0_MCASP3_ACLKX_OUT | CLK_STATE_READY | 0 | | 157 | 240 | DEV_BOARD0_MCASP3_AFSX_OUT | CLK_STATE_READY | 0 | | 157 | 241 | DEV_BOARD0_MCASP4_ACLKR_IN | CLK_STATE_READY | 0 | | 157 | 242 | DEV_BOARD0_MCASP4_ACLKR_OUT | CLK_STATE_READY | 0 | | 157 | 243 | DEV_BOARD0_MCASP4_AFSR_OUT | CLK_STATE_READY | 0 | | 157 | 244 | DEV_BOARD0_MCASP4_ACLKX_IN | CLK_STATE_READY | 0 | | 157 | 245 | DEV_BOARD0_MCASP4_ACLKX_OUT | CLK_STATE_READY | 0 | | 157 | 246 | DEV_BOARD0_MCASP4_AFSX_OUT | CLK_STATE_READY | 0 | | 157 | 247 | DEV_BOARD0_MCASP5_ACLKR_IN | CLK_STATE_READY | 0 | | 157 | 248 | DEV_BOARD0_MCASP5_ACLKR_OUT | CLK_STATE_READY | 0 | | 157 | 249 | DEV_BOARD0_MCASP5_AFSR_OUT | CLK_STATE_READY | 0 | | 157 | 250 | DEV_BOARD0_MCASP5_ACLKX_IN | CLK_STATE_READY | 0 | | 157 | 251 | DEV_BOARD0_MCASP5_ACLKX_OUT | CLK_STATE_READY | 0 | | 157 | 252 | DEV_BOARD0_MCASP5_AFSX_OUT | CLK_STATE_READY | 0 | | 157 | 253 | DEV_BOARD0_MCASP6_ACLKR_IN | CLK_STATE_READY | 0 | | 157 | 254 | DEV_BOARD0_MCASP6_ACLKR_OUT | CLK_STATE_READY | 0 | | 157 | 255 | DEV_BOARD0_MCASP6_AFSR_OUT | CLK_STATE_READY | 0 | | 157 | 256 | DEV_BOARD0_MCASP6_ACLKX_IN | CLK_STATE_READY | 0 | | 157 | 257 | DEV_BOARD0_MCASP6_ACLKX_OUT | CLK_STATE_READY | 0 | | 157 | 258 | DEV_BOARD0_MCASP6_AFSX_OUT | CLK_STATE_READY | 0 | | 157 | 259 | DEV_BOARD0_MCASP7_ACLKR_IN | CLK_STATE_READY | 0 | | 157 | 260 | DEV_BOARD0_MCASP7_ACLKR_OUT | CLK_STATE_READY | 0 | | 157 | 261 | DEV_BOARD0_MCASP7_AFSR_OUT | CLK_STATE_READY | 0 | | 157 | 262 | DEV_BOARD0_MCASP7_ACLKX_IN | CLK_STATE_READY | 0 | | 157 | 263 | DEV_BOARD0_MCASP7_ACLKX_OUT | CLK_STATE_READY | 0 | | 157 | 264 | DEV_BOARD0_MCASP7_AFSX_OUT | CLK_STATE_READY | 0 | | 157 | 265 | DEV_BOARD0_MCASP8_ACLKR_IN | CLK_STATE_READY | 0 | | 157 | 267 | DEV_BOARD0_MCASP8_ACLKR_OUT | CLK_STATE_READY | 0 | | 157 | 268 | DEV_BOARD0_MCASP8_AFSR_OUT | CLK_STATE_READY | 0 | | 157 | 269 | DEV_BOARD0_MCASP8_ACLKX_IN | CLK_STATE_READY | 0 | | 157 | 270 | DEV_BOARD0_MCASP8_ACLKX_OUT | CLK_STATE_READY | 0 | | 157 | 271 | DEV_BOARD0_MCASP8_AFSX_OUT | CLK_STATE_READY | 0 | | 157 | 272 | DEV_BOARD0_MCASP9_ACLKR_IN | CLK_STATE_READY | 0 | | 157 | 273 | DEV_BOARD0_MCASP9_ACLKR_OUT | CLK_STATE_READY | 0 | | 157 | 274 | DEV_BOARD0_MCASP9_AFSR_OUT | CLK_STATE_READY | 0 | | 157 | 275 | DEV_BOARD0_MCASP9_ACLKX_IN | CLK_STATE_READY | 0 | | 157 | 276 | DEV_BOARD0_MCASP9_ACLKX_OUT | CLK_STATE_READY | 0 | | 157 | 278 | DEV_BOARD0_MCASP9_AFSX_OUT | CLK_STATE_READY | 0 | | 157 | 279 | DEV_BOARD0_MCASP10_ACLKR_IN | CLK_STATE_READY | 0 | | 157 | 280 | DEV_BOARD0_MCASP10_ACLKR_OUT | CLK_STATE_READY | 0 | | 157 | 281 | DEV_BOARD0_MCASP10_AFSR_OUT | CLK_STATE_READY | 0 | | 157 | 282 | DEV_BOARD0_MCASP10_ACLKX_IN | CLK_STATE_READY | 0 | | 157 | 283 | DEV_BOARD0_MCASP10_ACLKX_OUT | CLK_STATE_READY | 0 | | 157 | 284 | DEV_BOARD0_MCASP10_AFSX_OUT | CLK_STATE_READY | 0 | | 157 | 285 | DEV_BOARD0_MCASP11_ACLKR_IN | CLK_STATE_READY | 0 | | 157 | 286 | DEV_BOARD0_MCASP11_ACLKR_OUT | CLK_STATE_READY | 0 | | 157 | 287 | DEV_BOARD0_MCASP11_AFSR_OUT | CLK_STATE_READY | 0 | | 157 | 288 | DEV_BOARD0_MCASP11_ACLKX_IN | CLK_STATE_READY | 0 | | 157 | 289 | DEV_BOARD0_MCASP11_ACLKX_OUT | CLK_STATE_READY | 0 | | 157 | 290 | DEV_BOARD0_MCASP11_AFSX_OUT | CLK_STATE_READY | 0 | | 157 | 300 | DEV_BOARD0_AUDIO_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 157 | 301 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN | CLK_STATE_READY | 0 | | 157 | 302 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 157 | 303 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 157 | 304 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 157 | 305 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 157 | 306 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 157 | 307 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 157 | 308 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 157 | 309 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 157 | 310 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 157 | 311 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 157 | 312 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 157 | 313 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 157 | 314 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 157 | 315 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 157 | 316 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 157 | 317 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 157 | 318 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 157 | 319 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 157 | 320 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 157 | 321 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 157 | 322 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 157 | 323 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 157 | 324 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 157 | 325 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 157 | 326 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | 157 | 327 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | 157 | 328 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | 157 | 329 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | 157 | 330 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | 157 | 331 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK | CLK_STATE_READY | 180633600 | | 157 | 334 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 157 | 335 | DEV_BOARD0_AUDIO_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 157 | 336 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN | CLK_STATE_READY | 0 | | 157 | 337 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 157 | 338 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 157 | 339 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 157 | 340 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 157 | 341 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 157 | 342 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 157 | 343 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 157 | 344 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 157 | 345 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 157 | 346 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 157 | 347 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 157 | 348 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 157 | 349 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 157 | 350 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 157 | 351 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 157 | 352 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 157 | 353 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 157 | 354 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 157 | 355 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 157 | 356 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 157 | 357 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 157 | 358 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 157 | 359 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 157 | 360 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 157 | 361 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | 157 | 362 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | 157 | 363 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | 157 | 364 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | 157 | 365 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | 157 | 366 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK | CLK_STATE_READY | 180633600 | | 157 | 369 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 157 | 370 | DEV_BOARD0_AUDIO_EXT_REFCLK2_OUT | CLK_STATE_READY | 0 | | 157 | 371 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN | CLK_STATE_READY | 0 | | 157 | 372 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 157 | 373 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 157 | 374 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 157 | 375 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 157 | 376 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 157 | 377 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 157 | 378 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 157 | 379 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 157 | 380 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 157 | 381 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 157 | 382 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 157 | 383 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 157 | 384 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 157 | 385 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 157 | 386 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 157 | 387 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 157 | 388 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 157 | 389 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 157 | 390 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 157 | 391 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 157 | 392 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 157 | 393 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 157 | 394 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 157 | 395 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 157 | 396 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | 157 | 397 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | 157 | 398 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | 157 | 399 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | 157 | 400 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | 157 | 401 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK | CLK_STATE_READY | 180633600 | | 157 | 404 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT | CLK_STATE_READY | 0 | | 157 | 405 | DEV_BOARD0_AUDIO_EXT_REFCLK3_OUT | CLK_STATE_READY | 0 | | 157 | 406 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN | CLK_STATE_READY | 0 | | 157 | 407 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 157 | 408 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 157 | 409 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 157 | 410 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 157 | 411 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 157 | 412 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 157 | 413 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 157 | 414 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 157 | 415 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 157 | 416 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 157 | 417 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 157 | 418 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 157 | 419 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 157 | 420 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 157 | 421 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 157 | 422 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 157 | 423 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 157 | 424 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 157 | 425 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 157 | 426 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 157 | 427 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 157 | 428 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 157 | 429 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 157 | 430 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 157 | 431 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | 157 | 432 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | 157 | 433 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | 157 | 434 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | 157 | 435 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | 157 | 436 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK | CLK_STATE_READY | 180633600 | | 157 | 439 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_BOARD_0_AUDIO_EXT_REFCLK3_OUT | CLK_STATE_READY | 0 | | 142 | 0 | DEV_C66SS0_CORE0_GEM_TRC_CLK | CLK_STATE_READY | 0 | | 142 | 1 | DEV_C66SS0_CORE0_GEM_CLK2_OUT_CLK | CLK_STATE_READY | 0 | | 142 | 4 | DEV_C66SS0_CORE0_GEM_PBIST_ROM_CLK | CLK_STATE_READY | 0 | | 142 | 6 | DEV_C66SS0_CORE0_GEM_CLKIN_CLK | CLK_STATE_READY | 1350000000 | | 121 | 0 | DEV_C66SS0_INTROUTER0_INTR_CLK | CLK_STATE_READY | 125000000 | | 143 | 0 | DEV_C66SS1_CORE0_GEM_TRC_CLK | CLK_STATE_READY | 0 | | 143 | 1 | DEV_C66SS1_CORE0_GEM_CLK2_OUT_CLK | CLK_STATE_READY | 0 | | 143 | 4 | DEV_C66SS1_CORE0_GEM_PBIST_ROM_CLK | CLK_STATE_READY | 0 | | 143 | 6 | DEV_C66SS1_CORE0_GEM_CLKIN_CLK | CLK_STATE_READY | 1350000000 | | 122 | 0 | DEV_C66SS1_INTROUTER0_INTR_CLK | CLK_STATE_READY | 125000000 | | 15 | 0 | DEV_C71SS0_C7X_CLK | CLK_STATE_READY | 1000000000 | | 15 | 1 | DEV_C71SS0_PLL_CTRL_CLK | CLK_STATE_READY | 500000000 | | 16 | 0 | DEV_C71SS0_MMA_PLL_CTRL_CLK | CLK_STATE_READY | 500000000 | | 16 | 1 | DEV_C71SS0_MMA_MMA_CLK | CLK_STATE_READY | 1000000000 | | 123 | 0 | DEV_CMPEVENT_INTRTR0_INTR_CLK | CLK_STATE_READY | 125000000 | | 5 | 0 | DEV_COMPUTE_CLUSTER0_CFG_WRAP_CLK4_CLK | CLK_STATE_READY | 250000000 | | 6 | 0 | DEV_COMPUTE_CLUSTER0_CLEC_CLK4_CLK | CLK_STATE_READY | 250000000 | | 6 | 1 | DEV_COMPUTE_CLUSTER0_CLEC_CLK1_CLK | CLK_STATE_READY | 500000000 | | 7 | 0 | DEV_COMPUTE_CLUSTER0_CORE_CORE_PSIL_LEAF_CLK | CLK_STATE_READY | 500000000 | | 7 | 1 | DEV_COMPUTE_CLUSTER0_CORE_CORE_CLK1_CLK | CLK_STATE_READY | 500000000 | | 8 | 0 | DEV_COMPUTE_CLUSTER0_DDR32SS_EMIF0_EW_PLL_CTRL_CLK | CLK_STATE_READY | 500000000 | | 8 | 1 | DEV_COMPUTE_CLUSTER0_DDR32SS_EMIF0_EW_DDRSS_DDR_PLL_CLK | CLK_STATE_READY | 1066500000 | | 9 | 0 | DEV_COMPUTE_CLUSTER0_DEBUG_WRAP_CLK1_CLK_CLK | CLK_STATE_READY | 1000000000 | | 9 | 1 | DEV_COMPUTE_CLUSTER0_DEBUG_WRAP_CLK2_CLK_CLK | CLK_STATE_READY | 500000000 | | 12 | 0 | DEV_COMPUTE_CLUSTER0_DMSC_WRAP_CLK4_CLK_CLK | CLK_STATE_READY | 250000000 | | 13 | 0 | DEV_COMPUTE_CLUSTER0_EN_MSMC_DOMAIN_MSMC_CLK1_CLK | CLK_STATE_READY | 500000000 | | 14 | 0 | DEV_COMPUTE_CLUSTER0_GIC500SS_VCLK_CLK | CLK_STATE_READY | 500000000 | | 17 | 0 | DEV_COMPUTE_CLUSTER0_PBIST_WRAP_DIVP_CLK1_CLK_CLK | CLK_STATE_READY | 1000000000 | | 17 | 1 | DEV_COMPUTE_CLUSTER0_PBIST_WRAP_DIVH_CLK4_CLK_CLK | CLK_STATE_READY | 250000000 | | 17 | 2 | DEV_COMPUTE_CLUSTER0_PBIST_WRAP_DIVH_CLK2_CLK_CLK | CLK_STATE_READY | 500000000 | | 19 | 0 | DEV_CPSW0_GMII3_MT_CLK | CLK_STATE_READY | 25000000 | | 19 | 1 | DEV_CPSW0_SERDES6_TXFCLK | CLK_STATE_READY | 0 | | 19 | 2 | DEV_CPSW0_SERDES8_TXMCLK | CLK_STATE_READY | 0 | | 19 | 3 | DEV_CPSW0_GMII2_MR_CLK | CLK_STATE_READY | 25000000 | | 19 | 4 | DEV_CPSW0_SERDES2_TXFCLK | CLK_STATE_READY | 0 | | 19 | 5 | DEV_CPSW0_SERDES4_RXCLK | CLK_STATE_READY | 0 | | 19 | 6 | DEV_CPSW0_SERDES7_TXMCLK | CLK_STATE_READY | 0 | | 19 | 7 | DEV_CPSW0_SERDES7_RXCLK | CLK_STATE_READY | 0 | | 19 | 8 | DEV_CPSW0_SERDES6_REFCLK | CLK_STATE_READY | 0 | | 19 | 9 | DEV_CPSW0_SERDES5_TXFCLK | CLK_STATE_READY | 0 | | 19 | 10 | DEV_CPSW0_SERDES5_RXCLK | CLK_STATE_READY | 0 | | 19 | 11 | DEV_CPSW0_GMII4_MT_CLK | CLK_STATE_READY | 25000000 | | 19 | 12 | DEV_CPSW0_SERDES3_TXFCLK | CLK_STATE_READY | 0 | | 19 | 13 | DEV_CPSW0_SERDES2_REFCLK | CLK_STATE_READY | 0 | | 19 | 14 | DEV_CPSW0_SERDES4_RXFCLK | CLK_STATE_READY | 0 | | 19 | 15 | DEV_CPSW0_SERDES6_RXFCLK | CLK_STATE_READY | 0 | | 19 | 16 | DEV_CPSW0_CPTS_RFT_CLK | CLK_STATE_READY | 200000000 | | 19 | 17 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | 19 | 18 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK | CLK_STATE_READY | 250000000 | | 19 | 19 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 19 | 20 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 19 | 21 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 19 | 22 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 19 | 23 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK | CLK_STATE_NOT_READY | 0 | | 19 | 24 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK | CLK_STATE_NOT_READY | 0 | | 19 | 25 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK | CLK_STATE_READY | 0 | | 19 | 26 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK | CLK_STATE_READY | 0 | | 19 | 27 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK | CLK_STATE_READY | 0 | | 19 | 28 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK | CLK_STATE_READY | 0 | | 19 | 29 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN0_TXMCLK | CLK_STATE_READY | 0 | | 19 | 30 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN1_TXMCLK | CLK_STATE_READY | 0 | | 19 | 31 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK | CLK_STATE_READY | 500000000 | | 19 | 32 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK | CLK_STATE_READY | 500000000 | | 19 | 33 | DEV_CPSW0_SERDES5_RXFCLK | CLK_STATE_READY | 0 | | 19 | 34 | DEV_CPSW0_SERDES5_TXMCLK | CLK_STATE_READY | 0 | | 19 | 35 | DEV_CPSW0_GMII5_MT_CLK | CLK_STATE_READY | 25000000 | | 19 | 36 | DEV_CPSW0_SERDES2_RXCLK | CLK_STATE_READY | 0 | | 19 | 37 | DEV_CPSW0_SERDES8_RXFCLK | CLK_STATE_READY | 0 | | 19 | 38 | DEV_CPSW0_SERDES1_RXFCLK | CLK_STATE_READY | 0 | | 19 | 39 | DEV_CPSW0_SERDES8_RXCLK | CLK_STATE_READY | 0 | | 19 | 40 | DEV_CPSW0_GMII_RFT_CLK | CLK_STATE_READY | 125000000 | | 19 | 41 | DEV_CPSW0_SERDES3_REFCLK | CLK_STATE_READY | 0 | | 19 | 42 | DEV_CPSW0_RGMII_MHZ_250_CLK | CLK_STATE_READY | 250000000 | | 19 | 43 | DEV_CPSW0_SERDES7_REFCLK | CLK_STATE_READY | 0 | | 19 | 44 | DEV_CPSW0_GMII6_MT_CLK | CLK_STATE_READY | 25000000 | | 19 | 45 | DEV_CPSW0_SERDES6_TXMCLK | CLK_STATE_READY | 0 | | 19 | 46 | DEV_CPSW0_RMII_MHZ_50_CLK | CLK_STATE_READY | 0 | | 19 | 47 | DEV_CPSW0_GMII4_MR_CLK | CLK_STATE_READY | 25000000 | | 19 | 48 | DEV_CPSW0_SERDES2_TXMCLK | CLK_STATE_READY | 0 | | 19 | 49 | DEV_CPSW0_RGMII_MHZ_50_CLK | CLK_STATE_READY | 50000000 | | 19 | 50 | DEV_CPSW0_SERDES4_TXMCLK | CLK_STATE_READY | 0 | | 19 | 51 | DEV_CPSW0_SERDES3_RXFCLK | CLK_STATE_READY | 0 | | 19 | 52 | DEV_CPSW0_GMII8_MT_CLK | CLK_STATE_READY | 25000000 | | 19 | 53 | DEV_CPSW0_SERDES7_TXFCLK | CLK_STATE_READY | 0 | | 19 | 54 | DEV_CPSW0_GMII7_MT_CLK | CLK_STATE_READY | 25000000 | | 19 | 55 | DEV_CPSW0_GMII7_MR_CLK | CLK_STATE_READY | 25000000 | | 19 | 56 | DEV_CPSW0_SERDES6_RXCLK | CLK_STATE_READY | 0 | | 19 | 57 | DEV_CPSW0_SERDES3_RXCLK | CLK_STATE_READY | 0 | | 19 | 58 | DEV_CPSW0_SERDES4_REFCLK | CLK_STATE_READY | 0 | | 19 | 59 | DEV_CPSW0_SERDES1_RXCLK | CLK_STATE_READY | 0 | | 19 | 60 | DEV_CPSW0_SERDES1_TXFCLK | CLK_STATE_READY | 0 | | 19 | 61 | DEV_CPSW0_GMII6_MR_CLK | CLK_STATE_READY | 25000000 | | 19 | 62 | DEV_CPSW0_SERDES1_REFCLK | CLK_STATE_READY | 0 | | 19 | 63 | DEV_CPSW0_RGMII_MHZ_5_CLK | CLK_STATE_READY | 5000000 | | 19 | 64 | DEV_CPSW0_SERDES5_REFCLK | CLK_STATE_READY | 0 | | 19 | 65 | DEV_CPSW0_GMII2_MT_CLK | CLK_STATE_READY | 25000000 | | 19 | 66 | DEV_CPSW0_SERDES8_TXFCLK | CLK_STATE_READY | 0 | | 19 | 67 | DEV_CPSW0_GMII8_MR_CLK | CLK_STATE_READY | 25000000 | | 19 | 68 | DEV_CPSW0_GMII1_MR_CLK | CLK_STATE_READY | 25000000 | | 19 | 69 | DEV_CPSW0_SERDES8_REFCLK | CLK_STATE_READY | 0 | | 19 | 70 | DEV_CPSW0_SERDES3_TXMCLK | CLK_STATE_READY | 0 | | 19 | 71 | DEV_CPSW0_GMII3_MR_CLK | CLK_STATE_READY | 25000000 | | 19 | 72 | DEV_CPSW0_SERDES1_TXMCLK | CLK_STATE_READY | 0 | | 19 | 73 | DEV_CPSW0_SERDES7_RXFCLK | CLK_STATE_READY | 0 | | 19 | 74 | DEV_CPSW0_GMII5_MR_CLK | CLK_STATE_READY | 25000000 | | 19 | 75 | DEV_CPSW0_GMII1_MT_CLK | CLK_STATE_READY | 25000000 | | 19 | 76 | DEV_CPSW0_SERDES2_RXFCLK | CLK_STATE_READY | 0 | | 19 | 77 | DEV_CPSW0_SERDES4_TXFCLK | CLK_STATE_READY | 0 | | 19 | 78 | DEV_CPSW0_SERDES3_TXCLK | CLK_STATE_READY | 0 | | 19 | 79 | DEV_CPSW0_CPTS_GENF0 | CLK_STATE_READY | 0 | | 19 | 80 | DEV_CPSW0_SERDES5_TXCLK | CLK_STATE_READY | 0 | | 19 | 81 | DEV_CPSW0_SERDES6_TXCLK | CLK_STATE_READY | 0 | | 19 | 82 | DEV_CPSW0_SERDES8_TXCLK | CLK_STATE_READY | 0 | | 19 | 83 | DEV_CPSW0_SERDES1_TXCLK | CLK_STATE_READY | 0 | | 19 | 84 | DEV_CPSW0_SERDES4_TXCLK | CLK_STATE_READY | 0 | | 19 | 85 | DEV_CPSW0_SERDES2_TXCLK | CLK_STATE_READY | 0 | | 19 | 86 | DEV_CPSW0_SERDES7_TXCLK | CLK_STATE_READY | 0 | | 19 | 87 | DEV_CPSW0_MDIO_MDCLK_O | CLK_STATE_READY | 0 | | 19 | 89 | DEV_CPSW0_CPPI_CLK_CLK | CLK_STATE_READY | 320000000 | | 20 | 0 | DEV_CPT2_AGGR0_VCLK_CLK | CLK_STATE_READY | 500000000 | | 21 | 0 | DEV_CPT2_AGGR1_VCLK_CLK | CLK_STATE_READY | 500000000 | | 23 | 0 | DEV_CPT2_AGGR2_VCLK_CLK | CLK_STATE_READY | 250000000 | | 25 | 0 | DEV_CSI_PSILSS0_MAIN_CLK | CLK_STATE_READY | 250000000 | | 26 | 0 | DEV_CSI_RX_IF0_VBUS_CLK_CLK | CLK_STATE_READY | 500000000 | | 26 | 1 | DEV_CSI_RX_IF0_PPI_RX_BYTE_CLK | CLK_STATE_READY | 0 | | 26 | 2 | DEV_CSI_RX_IF0_MAIN_CLK_CLK | CLK_STATE_READY | 500000000 | | 26 | 3 | DEV_CSI_RX_IF0_VP_CLK_CLK | CLK_STATE_READY | 650000000 | | 27 | 0 | DEV_CSI_RX_IF1_VBUS_CLK_CLK | CLK_STATE_READY | 500000000 | | 27 | 1 | DEV_CSI_RX_IF1_PPI_RX_BYTE_CLK | CLK_STATE_READY | 0 | | 27 | 2 | DEV_CSI_RX_IF1_MAIN_CLK_CLK | CLK_STATE_READY | 500000000 | | 27 | 3 | DEV_CSI_RX_IF1_VP_CLK_CLK | CLK_STATE_READY | 650000000 | | 28 | 0 | DEV_CSI_TX_IF0_ESC_CLK_CLK | CLK_STATE_READY | 20000000 | | 28 | 1 | DEV_CSI_TX_IF0_DPHY_TXBYTECLKHS_CL_CLK | CLK_STATE_READY | 0 | | 28 | 2 | DEV_CSI_TX_IF0_VBUS_CLK_CLK | CLK_STATE_READY | 250000000 | | 28 | 3 | DEV_CSI_TX_IF0_MAIN_CLK_CLK | CLK_STATE_READY | 500000000 | | 30 | 0 | DEV_DCC0_DCC_INPUT10_CLK | CLK_STATE_READY | 250000000 | | 30 | 1 | DEV_DCC0_DCC_INPUT01_CLK | CLK_STATE_READY | 0 | | 30 | 2 | DEV_DCC0_DCC_CLKSRC2_CLK | CLK_STATE_READY | 133333333 | | 30 | 3 | DEV_DCC0_DCC_CLKSRC7_CLK | CLK_STATE_READY | 0 | | 30 | 4 | DEV_DCC0_DCC_CLKSRC0_CLK | CLK_STATE_READY | 250000000 | | 30 | 5 | DEV_DCC0_VBUS_CLK | CLK_STATE_READY | 125000000 | | 30 | 6 | DEV_DCC0_DCC_CLKSRC4_CLK | CLK_STATE_READY | 19200000 | | 30 | 7 | DEV_DCC0_DCC_CLKSRC1_CLK | CLK_STATE_READY | 200000000 | | 30 | 8 | DEV_DCC0_DCC_CLKSRC3_CLK | CLK_STATE_READY | 80000000 | | 30 | 9 | DEV_DCC0_DCC_INPUT00_CLK | CLK_STATE_READY | 19200000 | | 30 | 10 | DEV_DCC0_DCC_CLKSRC5_CLK | CLK_STATE_READY | 0 | | 30 | 11 | DEV_DCC0_DCC_CLKSRC6_CLK | CLK_STATE_READY | 500000000 | | 30 | 12 | DEV_DCC0_DCC_INPUT02_CLK | CLK_STATE_READY | 12500000 | | 31 | 0 | DEV_DCC1_DCC_INPUT10_CLK | CLK_STATE_READY | 125000000 | | 31 | 1 | DEV_DCC1_DCC_INPUT01_CLK | CLK_STATE_READY | 0 | | 31 | 2 | DEV_DCC1_DCC_CLKSRC2_CLK | CLK_STATE_READY | 200000000 | | 31 | 3 | DEV_DCC1_DCC_CLKSRC7_CLK | CLK_STATE_READY | 19200000 | | 31 | 4 | DEV_DCC1_DCC_CLKSRC0_CLK | CLK_STATE_READY | 50000000 | | 31 | 5 | DEV_DCC1_VBUS_CLK | CLK_STATE_READY | 125000000 | | 31 | 6 | DEV_DCC1_DCC_CLKSRC4_CLK | CLK_STATE_READY | 320000000 | | 31 | 7 | DEV_DCC1_DCC_CLKSRC1_CLK | CLK_STATE_READY | 250000000 | | 31 | 8 | DEV_DCC1_DCC_CLKSRC3_CLK | CLK_STATE_READY | 192000000 | | 31 | 9 | DEV_DCC1_DCC_INPUT00_CLK | CLK_STATE_READY | 19200000 | | 31 | 10 | DEV_DCC1_DCC_CLKSRC5_CLK | CLK_STATE_READY | 192000000 | | 31 | 11 | DEV_DCC1_DCC_CLKSRC6_CLK | CLK_STATE_READY | 192000000 | | 31 | 12 | DEV_DCC1_DCC_INPUT02_CLK | CLK_STATE_READY | 12500000 | | 41 | 0 | DEV_DCC10_DCC_INPUT10_CLK | CLK_STATE_READY | 250000000 | | 41 | 1 | DEV_DCC10_DCC_INPUT01_CLK | CLK_STATE_READY | 0 | | 41 | 2 | DEV_DCC10_DCC_CLKSRC2_CLK | CLK_STATE_READY | 0 | | 41 | 3 | DEV_DCC10_DCC_CLKSRC7_CLK | CLK_STATE_READY | 0 | | 41 | 4 | DEV_DCC10_DCC_CLKSRC0_CLK | CLK_STATE_READY | 0 | | 41 | 5 | DEV_DCC10_VBUS_CLK | CLK_STATE_READY | 125000000 | | 41 | 6 | DEV_DCC10_DCC_CLKSRC4_CLK | CLK_STATE_READY | 0 | | 41 | 7 | DEV_DCC10_DCC_CLKSRC1_CLK | CLK_STATE_READY | 0 | | 41 | 8 | DEV_DCC10_DCC_CLKSRC3_CLK | CLK_STATE_READY | 0 | | 41 | 9 | DEV_DCC10_DCC_INPUT00_CLK | CLK_STATE_READY | 19200000 | | 41 | 10 | DEV_DCC10_DCC_CLKSRC5_CLK | CLK_STATE_READY | 0 | | 41 | 11 | DEV_DCC10_DCC_CLKSRC6_CLK | CLK_STATE_READY | 0 | | 41 | 12 | DEV_DCC10_DCC_INPUT02_CLK | CLK_STATE_READY | 12500000 | | 42 | 0 | DEV_DCC11_DCC_INPUT10_CLK | CLK_STATE_READY | 250000000 | | 42 | 1 | DEV_DCC11_DCC_INPUT01_CLK | CLK_STATE_READY | 0 | | 42 | 2 | DEV_DCC11_DCC_CLKSRC2_CLK | CLK_STATE_READY | 0 | | 42 | 3 | DEV_DCC11_DCC_CLKSRC7_CLK | CLK_STATE_READY | 0 | | 42 | 4 | DEV_DCC11_DCC_CLKSRC0_CLK | CLK_STATE_READY | 0 | | 42 | 5 | DEV_DCC11_VBUS_CLK | CLK_STATE_READY | 125000000 | | 42 | 6 | DEV_DCC11_DCC_CLKSRC4_CLK | CLK_STATE_READY | 0 | | 42 | 7 | DEV_DCC11_DCC_CLKSRC1_CLK | CLK_STATE_READY | 0 | | 42 | 8 | DEV_DCC11_DCC_CLKSRC3_CLK | CLK_STATE_READY | 0 | | 42 | 9 | DEV_DCC11_DCC_INPUT00_CLK | CLK_STATE_READY | 19200000 | | 42 | 10 | DEV_DCC11_DCC_CLKSRC5_CLK | CLK_STATE_READY | 0 | | 42 | 11 | DEV_DCC11_DCC_CLKSRC6_CLK | CLK_STATE_READY | 0 | | 42 | 12 | DEV_DCC11_DCC_INPUT02_CLK | CLK_STATE_READY | 12500000 | | 43 | 0 | DEV_DCC12_DCC_INPUT10_CLK | CLK_STATE_READY | 250000000 | | 43 | 1 | DEV_DCC12_DCC_INPUT01_CLK | CLK_STATE_READY | 0 | | 43 | 2 | DEV_DCC12_DCC_CLKSRC2_CLK | CLK_STATE_READY | 0 | | 43 | 3 | DEV_DCC12_DCC_CLKSRC7_CLK | CLK_STATE_READY | 0 | | 43 | 4 | DEV_DCC12_DCC_CLKSRC0_CLK | CLK_STATE_READY | 0 | | 43 | 5 | DEV_DCC12_VBUS_CLK | CLK_STATE_READY | 125000000 | | 43 | 6 | DEV_DCC12_DCC_CLKSRC4_CLK | CLK_STATE_READY | 0 | | 43 | 7 | DEV_DCC12_DCC_CLKSRC1_CLK | CLK_STATE_READY | 0 | | 43 | 8 | DEV_DCC12_DCC_CLKSRC3_CLK | CLK_STATE_READY | 0 | | 43 | 9 | DEV_DCC12_DCC_INPUT00_CLK | CLK_STATE_READY | 19200000 | | 43 | 10 | DEV_DCC12_DCC_CLKSRC5_CLK | CLK_STATE_READY | 0 | | 43 | 11 | DEV_DCC12_DCC_CLKSRC6_CLK | CLK_STATE_READY | 0 | | 43 | 12 | DEV_DCC12_DCC_INPUT02_CLK | CLK_STATE_READY | 12500000 | | 32 | 0 | DEV_DCC2_DCC_INPUT10_CLK | CLK_STATE_READY | 125000000 | | 32 | 1 | DEV_DCC2_DCC_INPUT01_CLK | CLK_STATE_READY | 0 | | 32 | 2 | DEV_DCC2_DCC_CLKSRC2_CLK | CLK_STATE_READY | 225000000 | | 32 | 3 | DEV_DCC2_DCC_CLKSRC7_CLK | CLK_STATE_READY | 250000000 | | 32 | 4 | DEV_DCC2_DCC_CLKSRC0_CLK | CLK_STATE_READY | 24000000 | | 32 | 5 | DEV_DCC2_VBUS_CLK | CLK_STATE_READY | 125000000 | | 32 | 6 | DEV_DCC2_DCC_CLKSRC4_CLK | CLK_STATE_READY | 225000000 | | 32 | 7 | DEV_DCC2_DCC_CLKSRC1_CLK | CLK_STATE_READY | 20000000 | | 32 | 8 | DEV_DCC2_DCC_CLKSRC3_CLK | CLK_STATE_READY | 100000000 | | 32 | 9 | DEV_DCC2_DCC_INPUT00_CLK | CLK_STATE_READY | 19200000 | | 32 | 10 | DEV_DCC2_DCC_CLKSRC5_CLK | CLK_STATE_READY | 300000000 | | 32 | 11 | DEV_DCC2_DCC_CLKSRC6_CLK | CLK_STATE_READY | 200000000 | | 32 | 12 | DEV_DCC2_DCC_INPUT02_CLK | CLK_STATE_READY | 12500000 | | 33 | 0 | DEV_DCC3_DCC_INPUT10_CLK | CLK_STATE_READY | 125000000 | | 33 | 1 | DEV_DCC3_DCC_INPUT01_CLK | CLK_STATE_READY | 0 | | 33 | 2 | DEV_DCC3_DCC_CLKSRC2_CLK | CLK_STATE_READY | 275000000 | | 33 | 3 | DEV_DCC3_DCC_CLKSRC7_CLK | CLK_STATE_READY | 500000000 | | 33 | 4 | DEV_DCC3_DCC_CLKSRC0_CLK | CLK_STATE_READY | 196608000 | | 33 | 5 | DEV_DCC3_VBUS_CLK | CLK_STATE_READY | 125000000 | | 33 | 6 | DEV_DCC3_DCC_CLKSRC4_CLK | CLK_STATE_READY | 0 | | 33 | 7 | DEV_DCC3_DCC_CLKSRC1_CLK | CLK_STATE_READY | 343750000 | | 33 | 8 | DEV_DCC3_DCC_CLKSRC3_CLK | CLK_STATE_READY | 333333333 | | 33 | 9 | DEV_DCC3_DCC_INPUT00_CLK | CLK_STATE_READY | 19200000 | | 33 | 10 | DEV_DCC3_DCC_CLKSRC5_CLK | CLK_STATE_READY | 187500000 | | 33 | 11 | DEV_DCC3_DCC_CLKSRC6_CLK | CLK_STATE_READY | 250000000 | | 33 | 12 | DEV_DCC3_DCC_INPUT02_CLK | CLK_STATE_READY | 12500000 | | 34 | 0 | DEV_DCC4_DCC_INPUT10_CLK | CLK_STATE_READY | 250000000 | | 34 | 1 | DEV_DCC4_DCC_INPUT01_CLK | CLK_STATE_READY | 0 | | 34 | 2 | DEV_DCC4_DCC_CLKSRC2_CLK | CLK_STATE_READY | 266625000 | | 34 | 3 | DEV_DCC4_DCC_CLKSRC7_CLK | CLK_STATE_READY | 300000000 | | 34 | 4 | DEV_DCC4_DCC_CLKSRC0_CLK | CLK_STATE_READY | 225000000 | | 34 | 5 | DEV_DCC4_VBUS_CLK | CLK_STATE_READY | 125000000 | | 34 | 6 | DEV_DCC4_DCC_CLKSRC4_CLK | CLK_STATE_READY | 250000000 | | 34 | 7 | DEV_DCC4_DCC_CLKSRC1_CLK | CLK_STATE_READY | 337500000 | | 34 | 8 | DEV_DCC4_DCC_CLKSRC3_CLK | CLK_STATE_READY | 337500000 | | 34 | 9 | DEV_DCC4_DCC_INPUT00_CLK | CLK_STATE_READY | 19200000 | | 34 | 10 | DEV_DCC4_DCC_CLKSRC5_CLK | CLK_STATE_READY | 250000000 | | 34 | 11 | DEV_DCC4_DCC_CLKSRC6_CLK | CLK_STATE_READY | 180633600 | | 34 | 12 | DEV_DCC4_DCC_INPUT02_CLK | CLK_STATE_READY | 12500000 | | 36 | 0 | DEV_DCC5_DCC_INPUT10_CLK | CLK_STATE_READY | 500000000 | | 36 | 1 | DEV_DCC5_DCC_INPUT01_CLK | CLK_STATE_READY | 0 | | 36 | 2 | DEV_DCC5_DCC_CLKSRC2_CLK | CLK_STATE_READY | 300000000 | | 36 | 3 | DEV_DCC5_DCC_CLKSRC7_CLK | CLK_STATE_READY | 0 | | 36 | 4 | DEV_DCC5_DCC_CLKSRC0_CLK | CLK_STATE_READY | 300000000 | | 36 | 5 | DEV_DCC5_VBUS_CLK | CLK_STATE_READY | 125000000 | | 36 | 6 | DEV_DCC5_DCC_CLKSRC4_CLK | CLK_STATE_READY | 650000000 | | 36 | 7 | DEV_DCC5_DCC_CLKSRC1_CLK | CLK_STATE_READY | 300000000 | | 36 | 8 | DEV_DCC5_DCC_CLKSRC3_CLK | CLK_STATE_READY | 520000000 | | 36 | 9 | DEV_DCC5_DCC_INPUT00_CLK | CLK_STATE_READY | 19200000 | | 36 | 10 | DEV_DCC5_DCC_CLKSRC5_CLK | CLK_STATE_READY | 300000000 | | 36 | 11 | DEV_DCC5_DCC_CLKSRC6_CLK | CLK_STATE_READY | 0 | | 36 | 12 | DEV_DCC5_DCC_INPUT02_CLK | CLK_STATE_READY | 12500000 | | 37 | 0 | DEV_DCC6_DCC_INPUT10_CLK | CLK_STATE_READY | 125000000 | | 37 | 1 | DEV_DCC6_DCC_INPUT01_CLK | CLK_STATE_READY | 0 | | 37 | 2 | DEV_DCC6_DCC_CLKSRC2_CLK | CLK_STATE_READY | 0 | | 37 | 3 | DEV_DCC6_DCC_CLKSRC7_CLK | CLK_STATE_READY | 0 | | 37 | 4 | DEV_DCC6_DCC_CLKSRC0_CLK | CLK_STATE_READY | 0 | | 37 | 5 | DEV_DCC6_VBUS_CLK | CLK_STATE_READY | 125000000 | | 37 | 6 | DEV_DCC6_DCC_CLKSRC4_CLK | CLK_STATE_READY | 0 | | 37 | 7 | DEV_DCC6_DCC_CLKSRC1_CLK | CLK_STATE_READY | 0 | | 37 | 8 | DEV_DCC6_DCC_CLKSRC3_CLK | CLK_STATE_READY | 0 | | 37 | 9 | DEV_DCC6_DCC_INPUT00_CLK | CLK_STATE_READY | 19200000 | | 37 | 10 | DEV_DCC6_DCC_CLKSRC5_CLK | CLK_STATE_READY | 0 | | 37 | 11 | DEV_DCC6_DCC_CLKSRC6_CLK | CLK_STATE_READY | 0 | | 37 | 12 | DEV_DCC6_DCC_INPUT02_CLK | CLK_STATE_READY | 12500000 | | 38 | 0 | DEV_DCC7_DCC_INPUT10_CLK | CLK_STATE_READY | 250000000 | | 38 | 1 | DEV_DCC7_DCC_INPUT01_CLK | CLK_STATE_READY | 0 | | 38 | 2 | DEV_DCC7_DCC_CLKSRC2_CLK | CLK_STATE_READY | 0 | | 38 | 3 | DEV_DCC7_DCC_CLKSRC7_CLK | CLK_STATE_READY | 0 | | 38 | 4 | DEV_DCC7_DCC_CLKSRC0_CLK | CLK_STATE_READY | 0 | | 38 | 5 | DEV_DCC7_VBUS_CLK | CLK_STATE_READY | 125000000 | | 38 | 6 | DEV_DCC7_DCC_CLKSRC4_CLK | CLK_STATE_READY | 0 | | 38 | 7 | DEV_DCC7_DCC_CLKSRC1_CLK | CLK_STATE_READY | 0 | | 38 | 8 | DEV_DCC7_DCC_CLKSRC3_CLK | CLK_STATE_READY | 0 | | 38 | 9 | DEV_DCC7_DCC_INPUT00_CLK | CLK_STATE_READY | 19200000 | | 38 | 10 | DEV_DCC7_DCC_CLKSRC5_CLK | CLK_STATE_READY | 0 | | 38 | 11 | DEV_DCC7_DCC_CLKSRC6_CLK | CLK_STATE_READY | 0 | | 38 | 12 | DEV_DCC7_DCC_INPUT02_CLK | CLK_STATE_READY | 12500000 | | 39 | 0 | DEV_DCC8_DCC_INPUT10_CLK | CLK_STATE_READY | 250000000 | | 39 | 1 | DEV_DCC8_DCC_INPUT01_CLK | CLK_STATE_READY | 0 | | 39 | 2 | DEV_DCC8_DCC_CLKSRC2_CLK | CLK_STATE_READY | 0 | | 39 | 3 | DEV_DCC8_DCC_CLKSRC7_CLK | CLK_STATE_READY | 200000000 | | 39 | 4 | DEV_DCC8_DCC_CLKSRC0_CLK | CLK_STATE_READY | 32000 | | 39 | 5 | DEV_DCC8_VBUS_CLK | CLK_STATE_READY | 125000000 | | 39 | 6 | DEV_DCC8_DCC_CLKSRC4_CLK | CLK_STATE_READY | 0 | | 39 | 7 | DEV_DCC8_DCC_CLKSRC1_CLK | CLK_STATE_READY | 32768 | | 39 | 8 | DEV_DCC8_DCC_CLKSRC3_CLK | CLK_STATE_READY | 0 | | 39 | 9 | DEV_DCC8_DCC_INPUT00_CLK | CLK_STATE_READY | 19200000 | | 39 | 10 | DEV_DCC8_DCC_CLKSRC5_CLK | CLK_STATE_READY | 0 | | 39 | 11 | DEV_DCC8_DCC_CLKSRC6_CLK | CLK_STATE_READY | 200000000 | | 39 | 12 | DEV_DCC8_DCC_INPUT02_CLK | CLK_STATE_READY | 12500000 | | 40 | 0 | DEV_DCC9_DCC_INPUT10_CLK | CLK_STATE_READY | 250000000 | | 40 | 1 | DEV_DCC9_DCC_INPUT01_CLK | CLK_STATE_READY | 0 | | 40 | 2 | DEV_DCC9_DCC_CLKSRC2_CLK | CLK_STATE_READY | 0 | | 40 | 3 | DEV_DCC9_DCC_CLKSRC7_CLK | CLK_STATE_READY | 0 | | 40 | 4 | DEV_DCC9_DCC_CLKSRC0_CLK | CLK_STATE_READY | 250000000 | | 40 | 5 | DEV_DCC9_VBUS_CLK | CLK_STATE_READY | 125000000 | | 40 | 6 | DEV_DCC9_DCC_CLKSRC4_CLK | CLK_STATE_READY | 0 | | 40 | 7 | DEV_DCC9_DCC_CLKSRC1_CLK | CLK_STATE_READY | 153846153 | | 40 | 8 | DEV_DCC9_DCC_CLKSRC3_CLK | CLK_STATE_READY | 0 | | 40 | 9 | DEV_DCC9_DCC_INPUT00_CLK | CLK_STATE_READY | 19200000 | | 40 | 10 | DEV_DCC9_DCC_CLKSRC5_CLK | CLK_STATE_READY | 0 | | 40 | 11 | DEV_DCC9_DCC_CLKSRC6_CLK | CLK_STATE_READY | 0 | | 40 | 12 | DEV_DCC9_DCC_INPUT02_CLK | CLK_STATE_READY | 12500000 | | 47 | 0 | DEV_DDR0_DDRSS_VBUS_CLK | CLK_STATE_READY | 1000000000 | | 47 | 1 | DEV_DDR0_PLL_CTRL_CLK | CLK_STATE_READY | 500000000 | | 47 | 2 | DEV_DDR0_DDRSS_DDR_PLL_CLK | CLK_STATE_READY | 1066500000 | | 47 | 3 | DEV_DDR0_DDRSS_CFG_CLK | CLK_STATE_READY | 125000000 | | 47 | 4 | DEV_DDR0_DDRSS_IO_CK_N | CLK_STATE_READY | 0 | | 47 | 5 | DEV_DDR0_DDRSS_IO_CK | CLK_STATE_READY | 0 | | 304 | 5 | DEV_DEBUGSS_WRAP0_TREXPT_CLK | CLK_STATE_READY | 300000000 | | 304 | 9 | DEV_DEBUGSS_WRAP0_CORE_CLK | CLK_STATE_READY | 125000000 | | 304 | 25 | DEV_DEBUGSS_WRAP0_JTAG_TCK | CLK_STATE_READY | 0 | | 304 | 32 | DEV_DEBUGSS_WRAP0_CSTPIU_TRACECLK | CLK_STATE_READY | 0 | | 304 | 35 | DEV_DEBUGSS_WRAP0_ATB_CLK | CLK_STATE_READY | 250000000 | | 144 | 0 | DEV_DECODER0_SYS_CLK | CLK_STATE_READY | 550000000 | | 48 | 0 | DEV_DMPAC0_CLK | CLK_STATE_READY | 520000000 | | 48 | 1 | DEV_DMPAC0_PLL_DCO_CLK | CLK_STATE_READY | 2600000000 | | 305 | 0 | DEV_DMPAC0_SDE_0_CLK | CLK_STATE_READY | 520000000 | | 147 | 0 | DEV_DPHY_RX0_MAIN_CLK_CLK | CLK_STATE_READY | 125000000 | | 147 | 1 | DEV_DPHY_RX0_PPI_RX_BYTE_CLK | CLK_STATE_READY | 0 | | 148 | 0 | DEV_DPHY_RX1_MAIN_CLK_CLK | CLK_STATE_READY | 125000000 | | 148 | 1 | DEV_DPHY_RX1_PPI_RX_BYTE_CLK | CLK_STATE_READY | 0 | | 296 | 0 | DEV_DPHY_TX0_CLK | CLK_STATE_READY | 125000000 | | 296 | 1 | DEV_DPHY_TX0_PSM_CLK | CLK_STATE_READY | 20000000 | | 296 | 2 | DEV_DPHY_TX0_IP1_PPI_M_TXCLKESC_CLK | CLK_STATE_READY | 20000000 | | 296 | 3 | DEV_DPHY_TX0_DPHY_REF_CLK | CLK_STATE_READY | 19200000 | | 296 | 4 | DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 296 | 5 | DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 296 | 6 | DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK | CLK_STATE_READY | 153846153 | | 296 | 7 | DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK | CLK_STATE_READY | 100000000 | | 296 | 8 | DEV_DPHY_TX0_IP1_PPI_TXBYTECLKHS_CL_CLK | CLK_STATE_READY | 0 | | 296 | 9 | DEV_DPHY_TX0_IP1_PPI_M_RXCLKESC_CLK | CLK_STATE_READY | 0 | | 296 | 10 | DEV_DPHY_TX0_CK_P | CLK_STATE_READY | 0 | | 296 | 11 | DEV_DPHY_TX0_CK_M | CLK_STATE_READY | 0 | | 296 | 12 | DEV_DPHY_TX0_IP2_PPI_TXBYTECLKHS_CL_CLK | CLK_STATE_READY | 0 | | 152 | 0 | DEV_DSS0_DSS_FUNC_CLK | CLK_STATE_READY | 600000000 | | 152 | 1 | DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK | CLK_STATE_READY | 600000000 | | 152 | 2 | DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK | CLK_STATE_READY | 600000000 | | 152 | 3 | DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK_PARENT_DPI_1_PCLK_SEL_OUT0 | CLK_STATE_READY | 600000000 | | 152 | 4 | DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK | CLK_STATE_READY | 600000000 | | 152 | 5 | DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK | CLK_STATE_READY | 600000000 | | 152 | 6 | DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0 | CLK_STATE_READY | 600000000 | | 152 | 7 | DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_DPI1_EXT_CLKSEL_OUT0 | CLK_STATE_READY | 600000000 | | 152 | 8 | DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK | CLK_STATE_READY | 600000000 | | 152 | 9 | DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK | CLK_STATE_READY | 600000000 | | 152 | 10 | DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK | CLK_STATE_READY | 600000000 | | 152 | 11 | DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_18_HSDIVOUT0_CLK | CLK_STATE_READY | 600000000 | | 152 | 12 | DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0 | CLK_STATE_READY | 600000000 | | 152 | 13 | DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK | CLK_STATE_READY | 600000000 | | 152 | 14 | DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT1_CLK | CLK_STATE_READY | 600000000 | | 152 | 15 | DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT1_CLK | CLK_STATE_READY | 600000000 | | 152 | 16 | DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_18_HSDIVOUT1_CLK | CLK_STATE_READY | 600000000 | | 152 | 17 | DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0 | CLK_STATE_READY | 600000000 | | 152 | 18 | DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_DPI1_EXT_CLKSEL_OUT0 | CLK_STATE_READY | 600000000 | | 152 | 23 | DEV_DSS0_DSS_INST0_DPI_0_OUT_CLK | CLK_STATE_READY | 0 | | 152 | 24 | DEV_DSS0_DSS_INST0_DPI_0_OUT_2X_CLK | CLK_STATE_READY | 0 | | 152 | 25 | DEV_DSS0_DSS_INST0_DPI_1_OUT_CLK | CLK_STATE_READY | 0 | | 152 | 27 | DEV_DSS0_DSS_INST0_DPI_2_OUT_CLK | CLK_STATE_READY | 0 | | 152 | 29 | DEV_DSS0_DSS_INST0_DPI_3_OUT_CLK | CLK_STATE_READY | 0 | | 152 | 31 | DEV_DSS0_DPI0_EXT_CLKSEL | CLK_STATE_READY | 600000000 | | 152 | 32 | DEV_DSS0_DPI0_EXT_CLKSEL_PARENT_HSDIV1_16FFT_MAIN_19_HSDIVOUT0_CLK | CLK_STATE_READY | 600000000 | | 152 | 33 | DEV_DSS0_DPI0_EXT_CLKSEL_PARENT_BOARD_0_VOUT1_EXTPCLKIN_OUT | CLK_STATE_READY | 0 | | 152 | 34 | DEV_DSS0_DPI1_EXT_CLKSEL | CLK_STATE_READY | 600000000 | | 152 | 35 | DEV_DSS0_DPI1_EXT_CLKSEL_PARENT_HSDIV1_16FFT_MAIN_23_HSDIVOUT0_CLK | CLK_STATE_READY | 600000000 | | 152 | 36 | DEV_DSS0_DPI1_EXT_CLKSEL_PARENT_BOARD_0_VOUT2_EXTPCLKIN_OUT | CLK_STATE_READY | 0 | | 150 | 0 | DEV_DSS_DSI0_DPHY_0_RX_ESC_CLK | CLK_STATE_READY | 0 | | 150 | 1 | DEV_DSS_DSI0_DPI_0_CLK | CLK_STATE_READY | 0 | | 150 | 2 | DEV_DSS_DSI0_PLL_CTRL_CLK | CLK_STATE_READY | 500000000 | | 150 | 3 | DEV_DSS_DSI0_PPI_0_TXBYTECLKHS_CL_CLK | CLK_STATE_READY | 0 | | 150 | 4 | DEV_DSS_DSI0_DPHY_0_TX_ESC_CLK | CLK_STATE_READY | 20000000 | | 150 | 5 | DEV_DSS_DSI0_SYS_CLK | CLK_STATE_READY | 250000000 | | 151 | 0 | DEV_DSS_EDP0_PHY_LN1_TXFCLK | CLK_STATE_READY | 0 | | 151 | 1 | DEV_DSS_EDP0_DPI_2_CLK | CLK_STATE_READY | 0 | | 151 | 2 | DEV_DSS_EDP0_PHY_LN2_TXFCLK | CLK_STATE_READY | 0 | | 151 | 3 | DEV_DSS_EDP0_PHY_LN0_RXCLK | CLK_STATE_READY | 0 | | 151 | 4 | DEV_DSS_EDP0_PHY_LN2_TXMCLK | CLK_STATE_READY | 0 | | 151 | 5 | DEV_DSS_EDP0_PHY_LN0_RXFCLK | CLK_STATE_READY | 0 | | 151 | 6 | DEV_DSS_EDP0_PHY_LN0_REFCLK | CLK_STATE_READY | 0 | | 151 | 7 | DEV_DSS_EDP0_PHY_LN1_RXCLK | CLK_STATE_READY | 0 | | 151 | 8 | DEV_DSS_EDP0_PHY_LN2_RXFCLK | CLK_STATE_READY | 0 | | 151 | 9 | DEV_DSS_EDP0_DPI_4_CLK | CLK_STATE_READY | 0 | | 151 | 10 | DEV_DSS_EDP0_DPI_2_2X_CLK | CLK_STATE_READY | 0 | | 151 | 11 | DEV_DSS_EDP0_PHY_LN0_TXFCLK | CLK_STATE_READY | 0 | | 151 | 12 | DEV_DSS_EDP0_PHY_LN2_RXCLK | CLK_STATE_READY | 0 | | 151 | 13 | DEV_DSS_EDP0_PHY_LN2_REFCLK | CLK_STATE_READY | 0 | | 151 | 14 | DEV_DSS_EDP0_PHY_LN3_REFCLK | CLK_STATE_READY | 0 | | 151 | 15 | DEV_DSS_EDP0_DPI_5_CLK | CLK_STATE_READY | 0 | | 151 | 16 | DEV_DSS_EDP0_PHY_LN3_RXCLK | CLK_STATE_READY | 0 | | 151 | 17 | DEV_DSS_EDP0_PHY_LN1_REFCLK | CLK_STATE_READY | 0 | | 151 | 18 | DEV_DSS_EDP0_AIF_I2S_CLK | CLK_STATE_READY | 0 | | 151 | 19 | DEV_DSS_EDP0_PHY_LN3_TXFCLK | CLK_STATE_READY | 0 | | 151 | 20 | DEV_DSS_EDP0_DPI_3_CLK | CLK_STATE_READY | 0 | | 151 | 21 | DEV_DSS_EDP0_PHY_LN1_RXFCLK | CLK_STATE_READY | 0 | | 151 | 22 | DEV_DSS_EDP0_PHY_LN1_TXMCLK | CLK_STATE_READY | 0 | | 151 | 23 | DEV_DSS_EDP0_PLL_CTRL_CLK | CLK_STATE_READY | 500000000 | | 151 | 24 | DEV_DSS_EDP0_PHY_LN3_TXMCLK | CLK_STATE_READY | 0 | | 151 | 25 | DEV_DSS_EDP0_PHY_LN3_RXFCLK | CLK_STATE_READY | 0 | | 151 | 26 | DEV_DSS_EDP0_PHY_LN0_TXMCLK | CLK_STATE_READY | 0 | | 151 | 27 | DEV_DSS_EDP0_PHY_LN2_TXCLK | CLK_STATE_READY | 0 | | 151 | 28 | DEV_DSS_EDP0_PHY_LN3_TXCLK | CLK_STATE_READY | 0 | | 151 | 29 | DEV_DSS_EDP0_PHY_LN0_TXCLK | CLK_STATE_READY | 0 | | 151 | 30 | DEV_DSS_EDP0_PHY_LN1_TXCLK | CLK_STATE_READY | 0 | | 151 | 36 | DEV_DSS_EDP0_DPTX_MOD_CLK | CLK_STATE_READY | 125000000 | | 80 | 0 | DEV_ECAP0_VBUS_CLK | CLK_STATE_READY | 125000000 | | 81 | 0 | DEV_ECAP1_VBUS_CLK | CLK_STATE_READY | 125000000 | | 82 | 0 | DEV_ECAP2_VBUS_CLK | CLK_STATE_READY | 125000000 | | 83 | 0 | DEV_EHRPWM0_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 84 | 0 | DEV_EHRPWM1_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 85 | 0 | DEV_EHRPWM2_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 86 | 0 | DEV_EHRPWM3_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 87 | 0 | DEV_EHRPWM4_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 88 | 0 | DEV_EHRPWM5_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 89 | 0 | DEV_ELM0_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 153 | 0 | DEV_ENCODER0_SYS_CLK | CLK_STATE_READY | 687500000 | | 94 | 0 | DEV_EQEP0_VBUS_CLK | CLK_STATE_READY | 125000000 | | 95 | 0 | DEV_EQEP1_VBUS_CLK | CLK_STATE_READY | 125000000 | | 96 | 0 | DEV_EQEP2_VBUS_CLK | CLK_STATE_READY | 125000000 | | 97 | 0 | DEV_ESM0_CLK | CLK_STATE_READY | 125000000 | | 105 | 0 | DEV_GPIO0_MMR_CLK | CLK_STATE_READY | 125000000 | | 106 | 0 | DEV_GPIO1_MMR_CLK | CLK_STATE_READY | 125000000 | | 107 | 0 | DEV_GPIO2_MMR_CLK | CLK_STATE_READY | 125000000 | | 108 | 0 | DEV_GPIO3_MMR_CLK | CLK_STATE_READY | 125000000 | | 109 | 0 | DEV_GPIO4_MMR_CLK | CLK_STATE_READY | 125000000 | | 110 | 0 | DEV_GPIO5_MMR_CLK | CLK_STATE_READY | 125000000 | | 111 | 0 | DEV_GPIO6_MMR_CLK | CLK_STATE_READY | 125000000 | | 112 | 0 | DEV_GPIO7_MMR_CLK | CLK_STATE_READY | 125000000 | | 131 | 0 | DEV_GPIOMUX_INTRTR0_INTR_CLK | CLK_STATE_READY | 125000000 | | 115 | 0 | DEV_GPMC0_PI_GPMC_RET_CLK | CLK_STATE_READY | 0 | | 115 | 1 | DEV_GPMC0_VBUSP_CLK | CLK_STATE_READY | 250000000 | | 115 | 2 | DEV_GPMC0_FUNC_CLK | CLK_STATE_READY | 125000000 | | 115 | 3 | DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK | CLK_STATE_READY | 133333333 | | 115 | 4 | DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK6 | CLK_STATE_READY | 100000000 | | 115 | 5 | DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK4 | CLK_STATE_READY | 150000000 | | 115 | 6 | DEV_GPMC0_FUNC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK4 | CLK_STATE_READY | 125000000 | | 115 | 7 | DEV_GPMC0_PO_GPMC_DEV_CLK | CLK_STATE_READY | 0 | | 125 | 0 | DEV_GPU0_GPU_0_GPU_PLL_CLK | CLK_STATE_READY | 750000000 | | 61 | 0 | DEV_GTC0_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 61 | 1 | DEV_GTC0_GTC_CLK | CLK_STATE_READY | 200000000 | | 61 | 2 | DEV_GTC0_GTC_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | 61 | 3 | DEV_GTC0_GTC_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK | CLK_STATE_READY | 250000000 | | 61 | 4 | DEV_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 61 | 5 | DEV_GTC0_GTC_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 61 | 6 | DEV_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 61 | 7 | DEV_GTC0_GTC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 61 | 8 | DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK | CLK_STATE_NOT_READY | 0 | | 61 | 9 | DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK | CLK_STATE_NOT_READY | 0 | | 61 | 10 | DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK | CLK_STATE_READY | 0 | | 61 | 11 | DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK | CLK_STATE_READY | 0 | | 61 | 12 | DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK | CLK_STATE_READY | 0 | | 61 | 13 | DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK | CLK_STATE_READY | 0 | | 61 | 14 | DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN0_TXMCLK | CLK_STATE_READY | 0 | | 61 | 15 | DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN1_TXMCLK | CLK_STATE_READY | 0 | | 61 | 16 | DEV_GTC0_GTC_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK | CLK_STATE_READY | 500000000 | | 61 | 17 | DEV_GTC0_GTC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK | CLK_STATE_READY | 500000000 | | 187 | 0 | DEV_I2C0_PISYS_CLK | CLK_STATE_READY | 96000000 | | 187 | 1 | DEV_I2C0_PISCL | CLK_STATE_READY | 0 | | 187 | 2 | DEV_I2C0_CLK | CLK_STATE_READY | 125000000 | | 187 | 3 | DEV_I2C0_PORSCL | CLK_STATE_READY | 0 | | 188 | 0 | DEV_I2C1_PISYS_CLK | CLK_STATE_READY | 96000000 | | 188 | 1 | DEV_I2C1_PISCL | CLK_STATE_READY | 0 | | 188 | 2 | DEV_I2C1_CLK | CLK_STATE_READY | 125000000 | | 188 | 3 | DEV_I2C1_PORSCL | CLK_STATE_READY | 0 | | 189 | 0 | DEV_I2C2_PISYS_CLK | CLK_STATE_READY | 96000000 | | 189 | 1 | DEV_I2C2_PISCL | CLK_STATE_READY | 0 | | 189 | 2 | DEV_I2C2_CLK | CLK_STATE_READY | 125000000 | | 189 | 3 | DEV_I2C2_PORSCL | CLK_STATE_READY | 0 | | 190 | 0 | DEV_I2C3_PISYS_CLK | CLK_STATE_READY | 96000000 | | 190 | 1 | DEV_I2C3_PISCL | CLK_STATE_READY | 0 | | 190 | 2 | DEV_I2C3_CLK | CLK_STATE_READY | 125000000 | | 190 | 3 | DEV_I2C3_PORSCL | CLK_STATE_READY | 0 | | 191 | 0 | DEV_I2C4_PISYS_CLK | CLK_STATE_READY | 96000000 | | 191 | 1 | DEV_I2C4_PISCL | CLK_STATE_READY | 0 | | 191 | 2 | DEV_I2C4_CLK | CLK_STATE_READY | 125000000 | | 191 | 3 | DEV_I2C4_PORSCL | CLK_STATE_READY | 0 | | 192 | 0 | DEV_I2C5_PISYS_CLK | CLK_STATE_READY | 96000000 | | 192 | 1 | DEV_I2C5_PISCL | CLK_STATE_READY | 0 | | 192 | 2 | DEV_I2C5_CLK | CLK_STATE_READY | 125000000 | | 192 | 3 | DEV_I2C5_PORSCL | CLK_STATE_READY | 0 | | 193 | 0 | DEV_I2C6_PISYS_CLK | CLK_STATE_READY | 96000000 | | 193 | 1 | DEV_I2C6_PISCL | CLK_STATE_READY | 0 | | 193 | 2 | DEV_I2C6_CLK | CLK_STATE_READY | 125000000 | | 193 | 3 | DEV_I2C6_PORSCL | CLK_STATE_READY | 0 | | 116 | 0 | DEV_I3C0_I3C_PCLK_CLK | CLK_STATE_READY | 125000000 | | 116 | 1 | DEV_I3C0_I3C_SCL_DI | CLK_STATE_READY | 0 | | 116 | 2 | DEV_I3C0_I3C_SCLK_CLK | CLK_STATE_READY | 125000000 | | 116 | 3 | DEV_I3C0_I3C_SCL_DO | CLK_STATE_READY | 0 | | 127 | 0 | DEV_LED0_LED_CLK | CLK_STATE_READY | 0 | | 127 | 1 | DEV_LED0_VBUS_CLK | CLK_STATE_READY | 250000000 | | 128 | 0 | DEV_MAIN2MCU_LVL_INTRTR0_INTR_CLK | CLK_STATE_READY | 125000000 | | 130 | 0 | DEV_MAIN2MCU_PLS_INTRTR0_INTR_CLK | CLK_STATE_READY | 250000000 | | 156 | 0 | DEV_MCAN0_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | 156 | 1 | DEV_MCAN0_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | 156 | 2 | DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | 156 | 3 | DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 156 | 4 | DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 156 | 5 | DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 158 | 0 | DEV_MCAN1_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | 158 | 1 | DEV_MCAN1_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | 158 | 2 | DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | 158 | 3 | DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 158 | 4 | DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 158 | 5 | DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 168 | 0 | DEV_MCAN10_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | 168 | 1 | DEV_MCAN10_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | 168 | 2 | DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | 168 | 3 | DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 168 | 4 | DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 168 | 5 | DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 169 | 0 | DEV_MCAN11_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | 169 | 1 | DEV_MCAN11_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | 169 | 2 | DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | 169 | 3 | DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 169 | 4 | DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 169 | 5 | DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 170 | 0 | DEV_MCAN12_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | 170 | 1 | DEV_MCAN12_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | 170 | 2 | DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | 170 | 3 | DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 170 | 4 | DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 170 | 5 | DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 171 | 0 | DEV_MCAN13_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | 171 | 1 | DEV_MCAN13_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | 171 | 2 | DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | 171 | 3 | DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 171 | 4 | DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 171 | 5 | DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 160 | 0 | DEV_MCAN2_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | 160 | 1 | DEV_MCAN2_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | 160 | 2 | DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | 160 | 3 | DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 160 | 4 | DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 160 | 5 | DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 161 | 0 | DEV_MCAN3_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | 161 | 1 | DEV_MCAN3_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | 161 | 2 | DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | 161 | 3 | DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 161 | 4 | DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 161 | 5 | DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 162 | 0 | DEV_MCAN4_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | 162 | 1 | DEV_MCAN4_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | 162 | 2 | DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | 162 | 3 | DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 162 | 4 | DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 162 | 5 | DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 163 | 0 | DEV_MCAN5_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | 163 | 1 | DEV_MCAN5_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | 163 | 2 | DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | 163 | 3 | DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 163 | 4 | DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 163 | 5 | DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 164 | 0 | DEV_MCAN6_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | 164 | 1 | DEV_MCAN6_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | 164 | 2 | DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | 164 | 3 | DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 164 | 4 | DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 164 | 5 | DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 165 | 0 | DEV_MCAN7_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | 165 | 1 | DEV_MCAN7_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | 165 | 2 | DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | 165 | 3 | DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 165 | 4 | DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 165 | 5 | DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 166 | 0 | DEV_MCAN8_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | 166 | 1 | DEV_MCAN8_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | 166 | 2 | DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | 166 | 3 | DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 166 | 4 | DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 166 | 5 | DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 167 | 0 | DEV_MCAN9_MCANSS_HCLK_CLK | CLK_STATE_READY | 125000000 | | 167 | 1 | DEV_MCAN9_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | 167 | 2 | DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | CLK_STATE_READY | 80000000 | | 167 | 3 | DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 167 | 4 | DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 167 | 5 | DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 174 | 0 | DEV_MCASP0_VBUSP_CLK | CLK_STATE_READY | 250000000 | | 174 | 1 | DEV_MCASP0_AUX_CLK | CLK_STATE_READY | 196608000 | | 174 | 2 | DEV_MCASP0_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK | CLK_STATE_READY | 196608000 | | 174 | 3 | DEV_MCASP0_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | 174 | 4 | DEV_MCASP0_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK | CLK_STATE_READY | 180633600 | | 174 | 6 | DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | 174 | 7 | DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | 174 | 8 | DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | 174 | 9 | DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | 174 | 10 | DEV_MCASP0_MCASP_ACLKX_POUT | CLK_STATE_READY | 0 | | 174 | 11 | DEV_MCASP0_MCASP_ACLKX_PIN | CLK_STATE_READY | 0 | | 174 | 12 | DEV_MCASP0_MCASP_ACLKR_POUT | CLK_STATE_READY | 0 | | 174 | 13 | DEV_MCASP0_MCASP_ACLKR_PIN | CLK_STATE_READY | 0 | | 174 | 14 | DEV_MCASP0_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 174 | 15 | DEV_MCASP0_MCASP_AHCLKX_PIN | CLK_STATE_READY | 0 | | 174 | 16 | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 174 | 17 | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 174 | 18 | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0 | CLK_STATE_READY | 0 | | 174 | 19 | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1 | CLK_STATE_READY | 0 | | 174 | 20 | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2 | CLK_STATE_READY | 0 | | 174 | 21 | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3 | CLK_STATE_READY | 0 | | 174 | 22 | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT | CLK_STATE_READY | 0 | | 174 | 23 | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2 | CLK_STATE_READY | 0 | | 174 | 24 | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | 174 | 25 | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | 174 | 26 | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | 174 | 27 | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | 174 | 28 | DEV_MCASP0_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 174 | 29 | DEV_MCASP0_MCASP_AHCLKR_PIN | CLK_STATE_READY | 0 | | 174 | 30 | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 174 | 31 | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 174 | 32 | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0 | CLK_STATE_READY | 0 | | 174 | 33 | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1 | CLK_STATE_READY | 0 | | 174 | 34 | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2 | CLK_STATE_READY | 0 | | 174 | 35 | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3 | CLK_STATE_READY | 0 | | 174 | 36 | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT | CLK_STATE_READY | 0 | | 174 | 37 | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2 | CLK_STATE_READY | 0 | | 174 | 38 | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | 174 | 39 | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | 174 | 40 | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | 174 | 41 | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | 175 | 0 | DEV_MCASP1_VBUSP_CLK | CLK_STATE_READY | 250000000 | | 175 | 1 | DEV_MCASP1_AUX_CLK | CLK_STATE_READY | 196608000 | | 175 | 2 | DEV_MCASP1_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK | CLK_STATE_READY | 196608000 | | 175 | 3 | DEV_MCASP1_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | 175 | 4 | DEV_MCASP1_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK | CLK_STATE_READY | 180633600 | | 175 | 6 | DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | 175 | 7 | DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | 175 | 8 | DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | 175 | 9 | DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | 175 | 10 | DEV_MCASP1_MCASP_ACLKX_POUT | CLK_STATE_READY | 0 | | 175 | 11 | DEV_MCASP1_MCASP_ACLKX_PIN | CLK_STATE_READY | 0 | | 175 | 12 | DEV_MCASP1_MCASP_ACLKR_POUT | CLK_STATE_READY | 0 | | 175 | 13 | DEV_MCASP1_MCASP_ACLKR_PIN | CLK_STATE_READY | 0 | | 175 | 14 | DEV_MCASP1_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 175 | 15 | DEV_MCASP1_MCASP_AHCLKX_PIN | CLK_STATE_READY | 0 | | 175 | 16 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 175 | 17 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 175 | 18 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0 | CLK_STATE_READY | 0 | | 175 | 19 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1 | CLK_STATE_READY | 0 | | 175 | 20 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2 | CLK_STATE_READY | 0 | | 175 | 21 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3 | CLK_STATE_READY | 0 | | 175 | 22 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT | CLK_STATE_READY | 0 | | 175 | 23 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2 | CLK_STATE_READY | 0 | | 175 | 24 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | 175 | 25 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | 175 | 26 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | 175 | 27 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | 175 | 28 | DEV_MCASP1_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 175 | 29 | DEV_MCASP1_MCASP_AHCLKR_PIN | CLK_STATE_READY | 0 | | 175 | 30 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 175 | 31 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 175 | 32 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0 | CLK_STATE_READY | 0 | | 175 | 33 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1 | CLK_STATE_READY | 0 | | 175 | 34 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2 | CLK_STATE_READY | 0 | | 175 | 35 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3 | CLK_STATE_READY | 0 | | 175 | 36 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT | CLK_STATE_READY | 0 | | 175 | 37 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2 | CLK_STATE_READY | 0 | | 175 | 38 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | 175 | 39 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | 175 | 40 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | 175 | 41 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | 184 | 0 | DEV_MCASP10_VBUSP_CLK | CLK_STATE_READY | 250000000 | | 184 | 1 | DEV_MCASP10_AUX_CLK | CLK_STATE_READY | 196608000 | | 184 | 2 | DEV_MCASP10_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK | CLK_STATE_READY | 196608000 | | 184 | 3 | DEV_MCASP10_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | 184 | 4 | DEV_MCASP10_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK | CLK_STATE_READY | 180633600 | | 184 | 6 | DEV_MCASP10_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | 184 | 7 | DEV_MCASP10_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | 184 | 8 | DEV_MCASP10_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | 184 | 9 | DEV_MCASP10_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | 184 | 10 | DEV_MCASP10_MCASP_ACLKX_POUT | CLK_STATE_READY | 0 | | 184 | 11 | DEV_MCASP10_MCASP_ACLKX_PIN | CLK_STATE_READY | 0 | | 184 | 12 | DEV_MCASP10_MCASP_ACLKR_POUT | CLK_STATE_READY | 0 | | 184 | 13 | DEV_MCASP10_MCASP_ACLKR_PIN | CLK_STATE_READY | 0 | | 184 | 14 | DEV_MCASP10_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 184 | 15 | DEV_MCASP10_MCASP_AHCLKX_PIN | CLK_STATE_READY | 0 | | 184 | 16 | DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 184 | 17 | DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 184 | 18 | DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0 | CLK_STATE_READY | 0 | | 184 | 19 | DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1 | CLK_STATE_READY | 0 | | 184 | 20 | DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2 | CLK_STATE_READY | 0 | | 184 | 21 | DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3 | CLK_STATE_READY | 0 | | 184 | 22 | DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT | CLK_STATE_READY | 0 | | 184 | 23 | DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2 | CLK_STATE_READY | 0 | | 184 | 24 | DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | 184 | 25 | DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | 184 | 26 | DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | 184 | 27 | DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | 184 | 28 | DEV_MCASP10_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 184 | 29 | DEV_MCASP10_MCASP_AHCLKR_PIN | CLK_STATE_READY | 0 | | 184 | 30 | DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 184 | 31 | DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 184 | 32 | DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0 | CLK_STATE_READY | 0 | | 184 | 33 | DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1 | CLK_STATE_READY | 0 | | 184 | 34 | DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2 | CLK_STATE_READY | 0 | | 184 | 35 | DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3 | CLK_STATE_READY | 0 | | 184 | 36 | DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT | CLK_STATE_READY | 0 | | 184 | 37 | DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2 | CLK_STATE_READY | 0 | | 184 | 38 | DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | 184 | 39 | DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | 184 | 40 | DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | 184 | 41 | DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | 185 | 0 | DEV_MCASP11_VBUSP_CLK | CLK_STATE_READY | 250000000 | | 185 | 1 | DEV_MCASP11_AUX_CLK | CLK_STATE_READY | 196608000 | | 185 | 2 | DEV_MCASP11_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK | CLK_STATE_READY | 196608000 | | 185 | 3 | DEV_MCASP11_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | 185 | 4 | DEV_MCASP11_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK | CLK_STATE_READY | 180633600 | | 185 | 6 | DEV_MCASP11_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | 185 | 7 | DEV_MCASP11_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | 185 | 8 | DEV_MCASP11_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | 185 | 9 | DEV_MCASP11_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | 185 | 10 | DEV_MCASP11_MCASP_ACLKX_POUT | CLK_STATE_READY | 0 | | 185 | 11 | DEV_MCASP11_MCASP_ACLKX_PIN | CLK_STATE_READY | 0 | | 185 | 12 | DEV_MCASP11_MCASP_ACLKR_POUT | CLK_STATE_READY | 0 | | 185 | 13 | DEV_MCASP11_MCASP_ACLKR_PIN | CLK_STATE_READY | 0 | | 185 | 14 | DEV_MCASP11_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 185 | 15 | DEV_MCASP11_MCASP_AHCLKX_PIN | CLK_STATE_READY | 0 | | 185 | 16 | DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 185 | 17 | DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 185 | 18 | DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0 | CLK_STATE_READY | 0 | | 185 | 19 | DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1 | CLK_STATE_READY | 0 | | 185 | 20 | DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2 | CLK_STATE_READY | 0 | | 185 | 21 | DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3 | CLK_STATE_READY | 0 | | 185 | 22 | DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT | CLK_STATE_READY | 0 | | 185 | 23 | DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2 | CLK_STATE_READY | 0 | | 185 | 24 | DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | 185 | 25 | DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | 185 | 26 | DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | 185 | 27 | DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | 185 | 28 | DEV_MCASP11_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 185 | 29 | DEV_MCASP11_MCASP_AHCLKR_PIN | CLK_STATE_READY | 0 | | 185 | 30 | DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 185 | 31 | DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 185 | 32 | DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0 | CLK_STATE_READY | 0 | | 185 | 33 | DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1 | CLK_STATE_READY | 0 | | 185 | 34 | DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2 | CLK_STATE_READY | 0 | | 185 | 35 | DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3 | CLK_STATE_READY | 0 | | 185 | 36 | DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT | CLK_STATE_READY | 0 | | 185 | 37 | DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2 | CLK_STATE_READY | 0 | | 185 | 38 | DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | 185 | 39 | DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | 185 | 40 | DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | 185 | 41 | DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | 176 | 0 | DEV_MCASP2_VBUSP_CLK | CLK_STATE_READY | 250000000 | | 176 | 1 | DEV_MCASP2_AUX_CLK | CLK_STATE_READY | 196608000 | | 176 | 2 | DEV_MCASP2_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK | CLK_STATE_READY | 196608000 | | 176 | 3 | DEV_MCASP2_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | 176 | 4 | DEV_MCASP2_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK | CLK_STATE_READY | 180633600 | | 176 | 6 | DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | 176 | 7 | DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | 176 | 8 | DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | 176 | 9 | DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | 176 | 10 | DEV_MCASP2_MCASP_ACLKX_POUT | CLK_STATE_READY | 0 | | 176 | 11 | DEV_MCASP2_MCASP_ACLKX_PIN | CLK_STATE_READY | 0 | | 176 | 12 | DEV_MCASP2_MCASP_ACLKR_POUT | CLK_STATE_READY | 0 | | 176 | 13 | DEV_MCASP2_MCASP_ACLKR_PIN | CLK_STATE_READY | 0 | | 176 | 14 | DEV_MCASP2_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 176 | 15 | DEV_MCASP2_MCASP_AHCLKX_PIN | CLK_STATE_READY | 0 | | 176 | 16 | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 176 | 17 | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 176 | 18 | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0 | CLK_STATE_READY | 0 | | 176 | 19 | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1 | CLK_STATE_READY | 0 | | 176 | 20 | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2 | CLK_STATE_READY | 0 | | 176 | 21 | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3 | CLK_STATE_READY | 0 | | 176 | 22 | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT | CLK_STATE_READY | 0 | | 176 | 23 | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2 | CLK_STATE_READY | 0 | | 176 | 24 | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | 176 | 25 | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | 176 | 26 | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | 176 | 27 | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | 176 | 28 | DEV_MCASP2_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 176 | 29 | DEV_MCASP2_MCASP_AHCLKR_PIN | CLK_STATE_READY | 0 | | 176 | 30 | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 176 | 31 | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 176 | 32 | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0 | CLK_STATE_READY | 0 | | 176 | 33 | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1 | CLK_STATE_READY | 0 | | 176 | 34 | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2 | CLK_STATE_READY | 0 | | 176 | 35 | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3 | CLK_STATE_READY | 0 | | 176 | 36 | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT | CLK_STATE_READY | 0 | | 176 | 37 | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2 | CLK_STATE_READY | 0 | | 176 | 38 | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | 176 | 39 | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | 176 | 40 | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | 176 | 41 | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | 177 | 0 | DEV_MCASP3_VBUSP_CLK | CLK_STATE_READY | 250000000 | | 177 | 1 | DEV_MCASP3_AUX_CLK | CLK_STATE_READY | 196608000 | | 177 | 2 | DEV_MCASP3_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK | CLK_STATE_READY | 196608000 | | 177 | 3 | DEV_MCASP3_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | 177 | 4 | DEV_MCASP3_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK | CLK_STATE_READY | 180633600 | | 177 | 6 | DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | 177 | 7 | DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | 177 | 8 | DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | 177 | 9 | DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | 177 | 10 | DEV_MCASP3_MCASP_ACLKX_POUT | CLK_STATE_READY | 0 | | 177 | 11 | DEV_MCASP3_MCASP_ACLKX_PIN | CLK_STATE_READY | 0 | | 177 | 12 | DEV_MCASP3_MCASP_ACLKR_POUT | CLK_STATE_READY | 0 | | 177 | 13 | DEV_MCASP3_MCASP_ACLKR_PIN | CLK_STATE_READY | 0 | | 177 | 14 | DEV_MCASP3_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 177 | 15 | DEV_MCASP3_MCASP_AHCLKX_PIN | CLK_STATE_READY | 0 | | 177 | 16 | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 177 | 17 | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 177 | 18 | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0 | CLK_STATE_READY | 0 | | 177 | 19 | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1 | CLK_STATE_READY | 0 | | 177 | 20 | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2 | CLK_STATE_READY | 0 | | 177 | 21 | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3 | CLK_STATE_READY | 0 | | 177 | 22 | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT | CLK_STATE_READY | 0 | | 177 | 23 | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2 | CLK_STATE_READY | 0 | | 177 | 24 | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | 177 | 25 | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | 177 | 26 | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | 177 | 27 | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | 177 | 28 | DEV_MCASP3_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 177 | 29 | DEV_MCASP3_MCASP_AHCLKR_PIN | CLK_STATE_READY | 0 | | 177 | 30 | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 177 | 31 | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 177 | 32 | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0 | CLK_STATE_READY | 0 | | 177 | 33 | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1 | CLK_STATE_READY | 0 | | 177 | 34 | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2 | CLK_STATE_READY | 0 | | 177 | 35 | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3 | CLK_STATE_READY | 0 | | 177 | 36 | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT | CLK_STATE_READY | 0 | | 177 | 37 | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2 | CLK_STATE_READY | 0 | | 177 | 38 | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | 177 | 39 | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | 177 | 40 | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | 177 | 41 | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | 178 | 0 | DEV_MCASP4_VBUSP_CLK | CLK_STATE_READY | 250000000 | | 178 | 1 | DEV_MCASP4_AUX_CLK | CLK_STATE_READY | 196608000 | | 178 | 2 | DEV_MCASP4_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK | CLK_STATE_READY | 196608000 | | 178 | 3 | DEV_MCASP4_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | 178 | 4 | DEV_MCASP4_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK | CLK_STATE_READY | 180633600 | | 178 | 6 | DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | 178 | 7 | DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | 178 | 8 | DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | 178 | 9 | DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | 178 | 10 | DEV_MCASP4_MCASP_ACLKX_POUT | CLK_STATE_READY | 0 | | 178 | 11 | DEV_MCASP4_MCASP_ACLKX_PIN | CLK_STATE_READY | 0 | | 178 | 12 | DEV_MCASP4_MCASP_ACLKR_POUT | CLK_STATE_READY | 0 | | 178 | 13 | DEV_MCASP4_MCASP_ACLKR_PIN | CLK_STATE_READY | 0 | | 178 | 14 | DEV_MCASP4_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 178 | 15 | DEV_MCASP4_MCASP_AHCLKX_PIN | CLK_STATE_READY | 0 | | 178 | 16 | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 178 | 17 | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 178 | 18 | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0 | CLK_STATE_READY | 0 | | 178 | 19 | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1 | CLK_STATE_READY | 0 | | 178 | 20 | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2 | CLK_STATE_READY | 0 | | 178 | 21 | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3 | CLK_STATE_READY | 0 | | 178 | 22 | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT | CLK_STATE_READY | 0 | | 178 | 23 | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2 | CLK_STATE_READY | 0 | | 178 | 24 | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | 178 | 25 | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | 178 | 26 | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | 178 | 27 | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | 178 | 28 | DEV_MCASP4_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 178 | 29 | DEV_MCASP4_MCASP_AHCLKR_PIN | CLK_STATE_READY | 0 | | 178 | 30 | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 178 | 31 | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 178 | 32 | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0 | CLK_STATE_READY | 0 | | 178 | 33 | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1 | CLK_STATE_READY | 0 | | 178 | 34 | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2 | CLK_STATE_READY | 0 | | 178 | 35 | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3 | CLK_STATE_READY | 0 | | 178 | 36 | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT | CLK_STATE_READY | 0 | | 178 | 37 | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2 | CLK_STATE_READY | 0 | | 178 | 38 | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | 178 | 39 | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | 178 | 40 | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | 178 | 41 | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | 179 | 0 | DEV_MCASP5_VBUSP_CLK | CLK_STATE_READY | 250000000 | | 179 | 1 | DEV_MCASP5_AUX_CLK | CLK_STATE_READY | 196608000 | | 179 | 2 | DEV_MCASP5_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK | CLK_STATE_READY | 196608000 | | 179 | 3 | DEV_MCASP5_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | 179 | 4 | DEV_MCASP5_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK | CLK_STATE_READY | 180633600 | | 179 | 6 | DEV_MCASP5_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | 179 | 7 | DEV_MCASP5_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | 179 | 8 | DEV_MCASP5_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | 179 | 9 | DEV_MCASP5_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | 179 | 10 | DEV_MCASP5_MCASP_ACLKX_POUT | CLK_STATE_READY | 0 | | 179 | 11 | DEV_MCASP5_MCASP_ACLKX_PIN | CLK_STATE_READY | 0 | | 179 | 12 | DEV_MCASP5_MCASP_ACLKR_POUT | CLK_STATE_READY | 0 | | 179 | 13 | DEV_MCASP5_MCASP_ACLKR_PIN | CLK_STATE_READY | 0 | | 179 | 14 | DEV_MCASP5_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 179 | 15 | DEV_MCASP5_MCASP_AHCLKX_PIN | CLK_STATE_READY | 0 | | 179 | 16 | DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 179 | 17 | DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 179 | 18 | DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0 | CLK_STATE_READY | 0 | | 179 | 19 | DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1 | CLK_STATE_READY | 0 | | 179 | 20 | DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2 | CLK_STATE_READY | 0 | | 179 | 21 | DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3 | CLK_STATE_READY | 0 | | 179 | 22 | DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT | CLK_STATE_READY | 0 | | 179 | 23 | DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2 | CLK_STATE_READY | 0 | | 179 | 24 | DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | 179 | 25 | DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | 179 | 26 | DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | 179 | 27 | DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | 179 | 28 | DEV_MCASP5_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 179 | 29 | DEV_MCASP5_MCASP_AHCLKR_PIN | CLK_STATE_READY | 0 | | 179 | 30 | DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 179 | 31 | DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 179 | 32 | DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0 | CLK_STATE_READY | 0 | | 179 | 33 | DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1 | CLK_STATE_READY | 0 | | 179 | 34 | DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2 | CLK_STATE_READY | 0 | | 179 | 35 | DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3 | CLK_STATE_READY | 0 | | 179 | 36 | DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT | CLK_STATE_READY | 0 | | 179 | 37 | DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2 | CLK_STATE_READY | 0 | | 179 | 38 | DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | 179 | 39 | DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | 179 | 40 | DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | 179 | 41 | DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | 180 | 0 | DEV_MCASP6_VBUSP_CLK | CLK_STATE_READY | 250000000 | | 180 | 1 | DEV_MCASP6_AUX_CLK | CLK_STATE_READY | 196608000 | | 180 | 2 | DEV_MCASP6_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK | CLK_STATE_READY | 196608000 | | 180 | 3 | DEV_MCASP6_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | 180 | 4 | DEV_MCASP6_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK | CLK_STATE_READY | 180633600 | | 180 | 6 | DEV_MCASP6_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | 180 | 7 | DEV_MCASP6_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | 180 | 8 | DEV_MCASP6_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | 180 | 9 | DEV_MCASP6_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | 180 | 10 | DEV_MCASP6_MCASP_ACLKX_POUT | CLK_STATE_READY | 0 | | 180 | 11 | DEV_MCASP6_MCASP_ACLKX_PIN | CLK_STATE_READY | 0 | | 180 | 12 | DEV_MCASP6_MCASP_ACLKR_POUT | CLK_STATE_READY | 0 | | 180 | 13 | DEV_MCASP6_MCASP_ACLKR_PIN | CLK_STATE_READY | 0 | | 180 | 14 | DEV_MCASP6_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 180 | 15 | DEV_MCASP6_MCASP_AHCLKX_PIN | CLK_STATE_READY | 0 | | 180 | 16 | DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 180 | 17 | DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 180 | 18 | DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0 | CLK_STATE_READY | 0 | | 180 | 19 | DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1 | CLK_STATE_READY | 0 | | 180 | 20 | DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2 | CLK_STATE_READY | 0 | | 180 | 21 | DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3 | CLK_STATE_READY | 0 | | 180 | 22 | DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT | CLK_STATE_READY | 0 | | 180 | 23 | DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2 | CLK_STATE_READY | 0 | | 180 | 24 | DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | 180 | 25 | DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | 180 | 26 | DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | 180 | 27 | DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | 180 | 28 | DEV_MCASP6_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 180 | 29 | DEV_MCASP6_MCASP_AHCLKR_PIN | CLK_STATE_READY | 0 | | 180 | 30 | DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 180 | 31 | DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 180 | 32 | DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0 | CLK_STATE_READY | 0 | | 180 | 33 | DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1 | CLK_STATE_READY | 0 | | 180 | 34 | DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2 | CLK_STATE_READY | 0 | | 180 | 35 | DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3 | CLK_STATE_READY | 0 | | 180 | 36 | DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT | CLK_STATE_READY | 0 | | 180 | 37 | DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2 | CLK_STATE_READY | 0 | | 180 | 38 | DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | 180 | 39 | DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | 180 | 40 | DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | 180 | 41 | DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | 181 | 0 | DEV_MCASP7_VBUSP_CLK | CLK_STATE_READY | 250000000 | | 181 | 1 | DEV_MCASP7_AUX_CLK | CLK_STATE_READY | 196608000 | | 181 | 2 | DEV_MCASP7_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK | CLK_STATE_READY | 196608000 | | 181 | 3 | DEV_MCASP7_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | 181 | 4 | DEV_MCASP7_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK | CLK_STATE_READY | 180633600 | | 181 | 6 | DEV_MCASP7_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | 181 | 7 | DEV_MCASP7_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | 181 | 8 | DEV_MCASP7_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | 181 | 9 | DEV_MCASP7_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | 181 | 10 | DEV_MCASP7_MCASP_ACLKX_POUT | CLK_STATE_READY | 0 | | 181 | 11 | DEV_MCASP7_MCASP_ACLKX_PIN | CLK_STATE_READY | 0 | | 181 | 12 | DEV_MCASP7_MCASP_ACLKR_POUT | CLK_STATE_READY | 0 | | 181 | 13 | DEV_MCASP7_MCASP_ACLKR_PIN | CLK_STATE_READY | 0 | | 181 | 14 | DEV_MCASP7_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 181 | 15 | DEV_MCASP7_MCASP_AHCLKX_PIN | CLK_STATE_READY | 0 | | 181 | 16 | DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 181 | 17 | DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 181 | 18 | DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0 | CLK_STATE_READY | 0 | | 181 | 19 | DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1 | CLK_STATE_READY | 0 | | 181 | 20 | DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2 | CLK_STATE_READY | 0 | | 181 | 21 | DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3 | CLK_STATE_READY | 0 | | 181 | 22 | DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT | CLK_STATE_READY | 0 | | 181 | 23 | DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2 | CLK_STATE_READY | 0 | | 181 | 24 | DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | 181 | 25 | DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | 181 | 26 | DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | 181 | 27 | DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | 181 | 28 | DEV_MCASP7_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 181 | 29 | DEV_MCASP7_MCASP_AHCLKR_PIN | CLK_STATE_READY | 0 | | 181 | 30 | DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 181 | 31 | DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 181 | 32 | DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0 | CLK_STATE_READY | 0 | | 181 | 33 | DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1 | CLK_STATE_READY | 0 | | 181 | 34 | DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2 | CLK_STATE_READY | 0 | | 181 | 35 | DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3 | CLK_STATE_READY | 0 | | 181 | 36 | DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT | CLK_STATE_READY | 0 | | 181 | 37 | DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2 | CLK_STATE_READY | 0 | | 181 | 38 | DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | 181 | 39 | DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | 181 | 40 | DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | 181 | 41 | DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | 182 | 0 | DEV_MCASP8_VBUSP_CLK | CLK_STATE_READY | 250000000 | | 182 | 1 | DEV_MCASP8_AUX_CLK | CLK_STATE_READY | 196608000 | | 182 | 2 | DEV_MCASP8_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK | CLK_STATE_READY | 196608000 | | 182 | 3 | DEV_MCASP8_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | 182 | 4 | DEV_MCASP8_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK | CLK_STATE_READY | 180633600 | | 182 | 6 | DEV_MCASP8_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | 182 | 7 | DEV_MCASP8_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | 182 | 8 | DEV_MCASP8_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | 182 | 9 | DEV_MCASP8_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | 182 | 10 | DEV_MCASP8_MCASP_ACLKX_POUT | CLK_STATE_READY | 0 | | 182 | 11 | DEV_MCASP8_MCASP_ACLKX_PIN | CLK_STATE_READY | 0 | | 182 | 12 | DEV_MCASP8_MCASP_ACLKR_POUT | CLK_STATE_READY | 0 | | 182 | 13 | DEV_MCASP8_MCASP_ACLKR_PIN | CLK_STATE_READY | 0 | | 182 | 14 | DEV_MCASP8_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 182 | 15 | DEV_MCASP8_MCASP_AHCLKX_PIN | CLK_STATE_READY | 0 | | 182 | 16 | DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 182 | 17 | DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 182 | 18 | DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0 | CLK_STATE_READY | 0 | | 182 | 19 | DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1 | CLK_STATE_READY | 0 | | 182 | 20 | DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2 | CLK_STATE_READY | 0 | | 182 | 21 | DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3 | CLK_STATE_READY | 0 | | 182 | 22 | DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT | CLK_STATE_READY | 0 | | 182 | 23 | DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2 | CLK_STATE_READY | 0 | | 182 | 24 | DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | 182 | 25 | DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | 182 | 26 | DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | 182 | 27 | DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | 182 | 28 | DEV_MCASP8_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 182 | 29 | DEV_MCASP8_MCASP_AHCLKR_PIN | CLK_STATE_READY | 0 | | 182 | 30 | DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 182 | 31 | DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 182 | 32 | DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0 | CLK_STATE_READY | 0 | | 182 | 33 | DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1 | CLK_STATE_READY | 0 | | 182 | 34 | DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2 | CLK_STATE_READY | 0 | | 182 | 35 | DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3 | CLK_STATE_READY | 0 | | 182 | 36 | DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT | CLK_STATE_READY | 0 | | 182 | 37 | DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2 | CLK_STATE_READY | 0 | | 182 | 38 | DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | 182 | 39 | DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | 182 | 40 | DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | 182 | 41 | DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | 183 | 0 | DEV_MCASP9_VBUSP_CLK | CLK_STATE_READY | 250000000 | | 183 | 1 | DEV_MCASP9_AUX_CLK | CLK_STATE_READY | 196608000 | | 183 | 2 | DEV_MCASP9_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK | CLK_STATE_READY | 196608000 | | 183 | 3 | DEV_MCASP9_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | 183 | 4 | DEV_MCASP9_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK | CLK_STATE_READY | 180633600 | | 183 | 6 | DEV_MCASP9_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | 183 | 7 | DEV_MCASP9_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | 183 | 8 | DEV_MCASP9_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | 183 | 9 | DEV_MCASP9_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | 183 | 10 | DEV_MCASP9_MCASP_ACLKX_POUT | CLK_STATE_READY | 0 | | 183 | 11 | DEV_MCASP9_MCASP_ACLKX_PIN | CLK_STATE_READY | 0 | | 183 | 12 | DEV_MCASP9_MCASP_ACLKR_POUT | CLK_STATE_READY | 0 | | 183 | 13 | DEV_MCASP9_MCASP_ACLKR_PIN | CLK_STATE_READY | 0 | | 183 | 14 | DEV_MCASP9_MCASP_AHCLKX_POUT | CLK_STATE_READY | 0 | | 183 | 15 | DEV_MCASP9_MCASP_AHCLKX_PIN | CLK_STATE_READY | 0 | | 183 | 16 | DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 183 | 17 | DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 183 | 18 | DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0 | CLK_STATE_READY | 0 | | 183 | 19 | DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1 | CLK_STATE_READY | 0 | | 183 | 20 | DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2 | CLK_STATE_READY | 0 | | 183 | 21 | DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3 | CLK_STATE_READY | 0 | | 183 | 22 | DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT | CLK_STATE_READY | 0 | | 183 | 23 | DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2 | CLK_STATE_READY | 0 | | 183 | 24 | DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | 183 | 25 | DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | 183 | 26 | DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | 183 | 27 | DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | 183 | 28 | DEV_MCASP9_MCASP_AHCLKR_POUT | CLK_STATE_READY | 0 | | 183 | 29 | DEV_MCASP9_MCASP_AHCLKR_PIN | CLK_STATE_READY | 0 | | 183 | 30 | DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 183 | 31 | DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 183 | 32 | DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0 | CLK_STATE_READY | 0 | | 183 | 33 | DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1 | CLK_STATE_READY | 0 | | 183 | 34 | DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2 | CLK_STATE_READY | 0 | | 183 | 35 | DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3 | CLK_STATE_READY | 0 | | 183 | 36 | DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT | CLK_STATE_READY | 0 | | 183 | 37 | DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2 | CLK_STATE_READY | 0 | | 183 | 38 | DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | CLK_STATE_NOT_READY | 0 | | 183 | 39 | DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | CLK_STATE_NOT_READY | 0 | | 183 | 40 | DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | CLK_STATE_NOT_READY | 0 | | 183 | 41 | DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | CLK_STATE_NOT_READY | 0 | | 266 | 0 | DEV_MCSPI0_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 266 | 1 | DEV_MCSPI0_CLKSPIREF_CLK | CLK_STATE_READY | 50000000 | | 266 | 2 | DEV_MCSPI0_IO_CLKSPIO_CLK | CLK_STATE_READY | 0 | | 267 | 0 | DEV_MCSPI1_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 267 | 1 | DEV_MCSPI1_CLKSPIREF_CLK | CLK_STATE_READY | 50000000 | | 267 | 2 | DEV_MCSPI1_IO_CLKSPIO_CLK | CLK_STATE_READY | 0 | | 268 | 0 | DEV_MCSPI2_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 268 | 1 | DEV_MCSPI2_CLKSPIREF_CLK | CLK_STATE_READY | 50000000 | | 268 | 2 | DEV_MCSPI2_IO_CLKSPIO_CLK | CLK_STATE_READY | 0 | | 269 | 0 | DEV_MCSPI3_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 269 | 1 | DEV_MCSPI3_CLKSPIREF_CLK | CLK_STATE_READY | 50000000 | | 269 | 2 | DEV_MCSPI3_IO_CLKSPII_CLK | CLK_STATE_READY | 0 | | 269 | 3 | DEV_MCSPI3_IO_CLKSPII_CLK_PARENT_SPI_MAIN_3_IO_CLKSPIO_CLK | CLK_STATE_READY | 0 | | 269 | 4 | DEV_MCSPI3_IO_CLKSPIO_CLK | CLK_STATE_READY | 0 | | 270 | 0 | DEV_MCSPI4_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 270 | 1 | DEV_MCSPI4_CLKSPIREF_CLK | CLK_STATE_READY | 50000000 | | 270 | 2 | DEV_MCSPI4_IO_CLKSPII_CLK | CLK_STATE_READY | 0 | | 270 | 3 | DEV_MCSPI4_IO_CLKSPIO_CLK | CLK_STATE_READY | 0 | | 271 | 0 | DEV_MCSPI5_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 271 | 1 | DEV_MCSPI5_CLKSPIREF_CLK | CLK_STATE_READY | 50000000 | | 271 | 2 | DEV_MCSPI5_IO_CLKSPIO_CLK | CLK_STATE_READY | 0 | | 272 | 0 | DEV_MCSPI6_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 272 | 1 | DEV_MCSPI6_CLKSPIREF_CLK | CLK_STATE_READY | 50000000 | | 272 | 2 | DEV_MCSPI6_IO_CLKSPIO_CLK | CLK_STATE_READY | 0 | | 273 | 0 | DEV_MCSPI7_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 273 | 1 | DEV_MCSPI7_CLKSPIREF_CLK | CLK_STATE_READY | 50000000 | | 273 | 2 | DEV_MCSPI7_IO_CLKSPIO_CLK | CLK_STATE_READY | 0 | | 0 | 0 | DEV_MCU_ADC12_16FFC0_SYS_CLK | CLK_STATE_READY | 1000000000 | | 0 | 1 | DEV_MCU_ADC12_16FFC0_ADC_CLK | CLK_STATE_READY | 19200000 | | 0 | 2 | DEV_MCU_ADC12_16FFC0_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 0 | 3 | DEV_MCU_ADC12_16FFC0_ADC_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT1_CLK | CLK_STATE_READY | 60000000 | | 0 | 4 | DEV_MCU_ADC12_16FFC0_ADC_CLK_PARENT_HSDIV1_16FFT_MCU_0_HSDIVOUT1_CLK | CLK_STATE_READY | 58823529 | | 0 | 5 | DEV_MCU_ADC12_16FFC0_ADC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 0 | 6 | DEV_MCU_ADC12_16FFC0_VBUS_CLK | CLK_STATE_READY | 1000000000 | | 1 | 0 | DEV_MCU_ADC12_16FFC1_SYS_CLK | CLK_STATE_READY | 1000000000 | | 1 | 1 | DEV_MCU_ADC12_16FFC1_ADC_CLK | CLK_STATE_READY | 19200000 | | 1 | 2 | DEV_MCU_ADC12_16FFC1_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 1 | 3 | DEV_MCU_ADC12_16FFC1_ADC_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT1_CLK | CLK_STATE_READY | 60000000 | | 1 | 4 | DEV_MCU_ADC12_16FFC1_ADC_CLK_PARENT_HSDIV1_16FFT_MCU_0_HSDIVOUT1_CLK | CLK_STATE_READY | 58823529 | | 1 | 5 | DEV_MCU_ADC12_16FFC1_ADC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 1 | 6 | DEV_MCU_ADC12_16FFC1_VBUS_CLK | CLK_STATE_READY | 1000000000 | | 18 | 0 | DEV_MCU_CPSW0_RGMII1_RXC_I | CLK_STATE_READY | 0 | | 18 | 1 | DEV_MCU_CPSW0_RGMII_MHZ_250_CLK | CLK_STATE_READY | 250000000 | | 18 | 2 | DEV_MCU_CPSW0_CPTS_RFT_CLK | CLK_STATE_READY | 500000000 | | 18 | 3 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | 18 | 4 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK | CLK_STATE_READY | 250000000 | | 18 | 5 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 18 | 6 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 18 | 7 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 18 | 8 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 18 | 9 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK | CLK_STATE_NOT_READY | 0 | | 18 | 10 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK | CLK_STATE_NOT_READY | 0 | | 18 | 11 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK | CLK_STATE_READY | 0 | | 18 | 12 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK | CLK_STATE_READY | 0 | | 18 | 13 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK | CLK_STATE_READY | 0 | | 18 | 14 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK | CLK_STATE_READY | 0 | | 18 | 15 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN0_TXMCLK | CLK_STATE_READY | 0 | | 18 | 16 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN1_TXMCLK | CLK_STATE_READY | 0 | | 18 | 17 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK | CLK_STATE_READY | 500000000 | | 18 | 18 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK2 | CLK_STATE_READY | 500000000 | | 18 | 19 | DEV_MCU_CPSW0_GMII_RFT_CLK | CLK_STATE_READY | 125000000 | | 18 | 20 | DEV_MCU_CPSW0_RMII_MHZ_50_CLK | CLK_STATE_READY | 0 | | 18 | 21 | DEV_MCU_CPSW0_RGMII_MHZ_50_CLK | CLK_STATE_READY | 50000000 | | 18 | 22 | DEV_MCU_CPSW0_CPPI_CLK_CLK | CLK_STATE_READY | 333333333 | | 18 | 23 | DEV_MCU_CPSW0_RGMII_MHZ_5_CLK | CLK_STATE_READY | 5000000 | | 18 | 24 | DEV_MCU_CPSW0_GMII1_MR_CLK | CLK_STATE_READY | 25000000 | | 18 | 25 | DEV_MCU_CPSW0_GMII1_MT_CLK | CLK_STATE_READY | 25000000 | | 18 | 26 | DEV_MCU_CPSW0_RGMII1_TXC_I | CLK_STATE_READY | 0 | | 18 | 27 | DEV_MCU_CPSW0_RGMII1_TXC_O | CLK_STATE_READY | 0 | | 18 | 28 | DEV_MCU_CPSW0_CPTS_GENF0 | CLK_STATE_READY | 0 | | 18 | 29 | DEV_MCU_CPSW0_MDIO_MDCLK_O | CLK_STATE_READY | 0 | | 24 | 0 | DEV_MCU_CPT2_AGGR0_VCLK_CLK | CLK_STATE_READY | 333333333 | | 44 | 0 | DEV_MCU_DCC0_DCC_INPUT10_CLK | CLK_STATE_READY | 333333333 | | 44 | 1 | DEV_MCU_DCC0_DCC_INPUT01_CLK | CLK_STATE_READY | 32000 | | 44 | 2 | DEV_MCU_DCC0_DCC_CLKSRC2_CLK | CLK_STATE_READY | 80000000 | | 44 | 3 | DEV_MCU_DCC0_DCC_CLKSRC7_CLK | CLK_STATE_READY | 0 | | 44 | 4 | DEV_MCU_DCC0_DCC_CLKSRC0_CLK | CLK_STATE_READY | 200000000 | | 44 | 5 | DEV_MCU_DCC0_VBUS_CLK | CLK_STATE_READY | 166666666 | | 44 | 6 | DEV_MCU_DCC0_DCC_CLKSRC4_CLK | CLK_STATE_READY | 133333333 | | 44 | 7 | DEV_MCU_DCC0_DCC_CLKSRC1_CLK | CLK_STATE_READY | 60000000 | | 44 | 8 | DEV_MCU_DCC0_DCC_CLKSRC3_CLK | CLK_STATE_READY | 96000000 | | 44 | 9 | DEV_MCU_DCC0_DCC_INPUT00_CLK | CLK_STATE_READY | 19200000 | | 44 | 10 | DEV_MCU_DCC0_DCC_CLKSRC5_CLK | CLK_STATE_READY | 32000 | | 44 | 11 | DEV_MCU_DCC0_DCC_CLKSRC6_CLK | CLK_STATE_READY | 32768 | | 44 | 12 | DEV_MCU_DCC0_DCC_INPUT02_CLK | CLK_STATE_READY | 12500000 | | 45 | 0 | DEV_MCU_DCC1_DCC_INPUT10_CLK | CLK_STATE_READY | 250000000 | | 45 | 1 | DEV_MCU_DCC1_DCC_INPUT01_CLK | CLK_STATE_READY | 32768 | | 45 | 2 | DEV_MCU_DCC1_DCC_CLKSRC2_CLK | CLK_STATE_READY | 80000000 | | 45 | 3 | DEV_MCU_DCC1_DCC_CLKSRC7_CLK | CLK_STATE_READY | 0 | | 45 | 4 | DEV_MCU_DCC1_DCC_CLKSRC0_CLK | CLK_STATE_READY | 250000000 | | 45 | 5 | DEV_MCU_DCC1_VBUS_CLK | CLK_STATE_READY | 166666666 | | 45 | 6 | DEV_MCU_DCC1_DCC_CLKSRC4_CLK | CLK_STATE_READY | 250000000 | | 45 | 7 | DEV_MCU_DCC1_DCC_CLKSRC1_CLK | CLK_STATE_READY | 200000000 | | 45 | 8 | DEV_MCU_DCC1_DCC_CLKSRC3_CLK | CLK_STATE_READY | 166666666 | | 45 | 9 | DEV_MCU_DCC1_DCC_INPUT00_CLK | CLK_STATE_READY | 19200000 | | 45 | 10 | DEV_MCU_DCC1_DCC_CLKSRC5_CLK | CLK_STATE_READY | 58823529 | | 45 | 11 | DEV_MCU_DCC1_DCC_CLKSRC6_CLK | CLK_STATE_READY | 0 | | 45 | 12 | DEV_MCU_DCC1_DCC_INPUT02_CLK | CLK_STATE_READY | 12500000 | | 46 | 0 | DEV_MCU_DCC2_DCC_INPUT10_CLK | CLK_STATE_READY | 333333333 | | 46 | 1 | DEV_MCU_DCC2_DCC_INPUT01_CLK | CLK_STATE_READY | 0 | | 46 | 2 | DEV_MCU_DCC2_DCC_CLKSRC7_CLK | CLK_STATE_READY | 19200000 | | 46 | 3 | DEV_MCU_DCC2_DCC_CLKSRC0_CLK | CLK_STATE_READY | 0 | | 46 | 4 | DEV_MCU_DCC2_VBUS_CLK | CLK_STATE_READY | 166666666 | | 46 | 5 | DEV_MCU_DCC2_DCC_CLKSRC4_CLK | CLK_STATE_READY | 0 | | 46 | 6 | DEV_MCU_DCC2_DCC_CLKSRC1_CLK | CLK_STATE_READY | 0 | | 46 | 7 | DEV_MCU_DCC2_DCC_CLKSRC3_CLK | CLK_STATE_READY | 192000000 | | 46 | 8 | DEV_MCU_DCC2_DCC_INPUT00_CLK | CLK_STATE_READY | 19200000 | | 46 | 9 | DEV_MCU_DCC2_DCC_CLKSRC6_CLK | CLK_STATE_READY | 12500000 | | 46 | 10 | DEV_MCU_DCC2_DCC_INPUT02_CLK | CLK_STATE_READY | 12500000 | | 98 | 0 | DEV_MCU_ESM0_CLK | CLK_STATE_READY | 166666666 | | 101 | 0 | DEV_MCU_FSS0_FSAS_0_GCLK | CLK_STATE_READY | 1000000000 | | 102 | 0 | DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX2_INV_CLK | CLK_STATE_READY | 166666666 | | 102 | 1 | DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX1_INV_CLK | CLK_STATE_READY | 83333333 | | 102 | 2 | DEV_MCU_FSS0_HYPERBUS1P0_0_CBA_CLK | CLK_STATE_READY | 1000000000 | | 102 | 3 | DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX2_CLK | CLK_STATE_READY | 166666666 | | 102 | 4 | DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX1_CLK | CLK_STATE_READY | 83333333 | | 102 | 5 | DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_OUT_CLK_N | CLK_STATE_READY | 0 | | 102 | 6 | DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_OUT_CLK_P | CLK_STATE_READY | 0 | | 103 | 0 | DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK | CLK_STATE_READY | 166666666 | | 103 | 1 | DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT4_CLK | CLK_STATE_READY | 133333333 | | 103 | 2 | DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT4_CLK | CLK_STATE_READY | 166666666 | | 103 | 3 | DEV_MCU_FSS0_OSPI_0_OSPI_HCLK_CLK | CLK_STATE_READY | 1000000000 | | 103 | 4 | DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK | CLK_STATE_READY | 0 | | 103 | 5 | DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_BOARD_0_MCU_OSPI0_DQS_OUT | CLK_STATE_READY | 0 | | 103 | 6 | DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_FSS_MCU_0_OSPI_0_OSPI_OCLK_CLK | CLK_STATE_READY | 0 | | 103 | 7 | DEV_MCU_FSS0_OSPI_0_OSPI_PCLK_CLK | CLK_STATE_READY | 1000000000 | | 103 | 8 | DEV_MCU_FSS0_OSPI_0_OSPI_DQS_CLK | CLK_STATE_READY | 0 | | 103 | 9 | DEV_MCU_FSS0_OSPI_0_OSPI_OCLK_CLK | CLK_STATE_READY | 0 | | 104 | 0 | DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK | CLK_STATE_READY | 133333333 | | 104 | 1 | DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT4_CLK | CLK_STATE_READY | 133333333 | | 104 | 2 | DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT4_CLK | CLK_STATE_READY | 166666666 | | 104 | 3 | DEV_MCU_FSS0_OSPI_1_OSPI_HCLK_CLK | CLK_STATE_READY | 1000000000 | | 104 | 4 | DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK | CLK_STATE_READY | 0 | | 104 | 5 | DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK_PARENT_BOARD_0_MCU_OSPI1_DQS_OUT | CLK_STATE_READY | 0 | | 104 | 6 | DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK_PARENT_FSS_MCU_0_OSPI_1_OSPI_OCLK_CLK | CLK_STATE_READY | 0 | | 104 | 7 | DEV_MCU_FSS0_OSPI_1_OSPI_PCLK_CLK | CLK_STATE_READY | 1000000000 | | 104 | 8 | DEV_MCU_FSS0_OSPI_1_OSPI_DQS_CLK | CLK_STATE_READY | 0 | | 104 | 9 | DEV_MCU_FSS0_OSPI_1_OSPI_OCLK_CLK | CLK_STATE_READY | 0 | | 194 | 0 | DEV_MCU_I2C0_PISYS_CLK | CLK_STATE_READY | 96000000 | | 194 | 1 | DEV_MCU_I2C0_PISCL | CLK_STATE_READY | 0 | | 194 | 2 | DEV_MCU_I2C0_CLK | CLK_STATE_READY | 166666666 | | 194 | 3 | DEV_MCU_I2C0_PORSCL | CLK_STATE_READY | 0 | | 195 | 0 | DEV_MCU_I2C1_PISYS_CLK | CLK_STATE_READY | 96000000 | | 195 | 1 | DEV_MCU_I2C1_PISCL | CLK_STATE_READY | 0 | | 195 | 2 | DEV_MCU_I2C1_CLK | CLK_STATE_READY | 166666666 | | 195 | 3 | DEV_MCU_I2C1_PORSCL | CLK_STATE_READY | 0 | | 117 | 0 | DEV_MCU_I3C0_I3C_PCLK_CLK | CLK_STATE_READY | 166666666 | | 117 | 1 | DEV_MCU_I3C0_I3C_SCL_DI | CLK_STATE_READY | 0 | | 117 | 2 | DEV_MCU_I3C0_I3C_SCLK_CLK | CLK_STATE_READY | 166666666 | | 117 | 3 | DEV_MCU_I3C0_I3C_SCL_DO | CLK_STATE_READY | 0 | | 118 | 0 | DEV_MCU_I3C1_I3C_PCLK_CLK | CLK_STATE_READY | 166666666 | | 118 | 1 | DEV_MCU_I3C1_I3C_SCL_DI | CLK_STATE_READY | 0 | | 118 | 2 | DEV_MCU_I3C1_I3C_SCLK_CLK | CLK_STATE_READY | 166666666 | | 118 | 3 | DEV_MCU_I3C1_I3C_SCL_DO | CLK_STATE_READY | 0 | | 172 | 0 | DEV_MCU_MCAN0_MCANSS_HCLK_CLK | CLK_STATE_READY | 166666666 | | 172 | 1 | DEV_MCU_MCAN0_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | 172 | 2 | DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT3_CLK | CLK_STATE_READY | 80000000 | | 172 | 3 | DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 172 | 4 | DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT2_CLK | CLK_STATE_READY | 80000000 | | 172 | 5 | DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 173 | 0 | DEV_MCU_MCAN1_MCANSS_HCLK_CLK | CLK_STATE_READY | 166666666 | | 173 | 1 | DEV_MCU_MCAN1_MCANSS_CCLK_CLK | CLK_STATE_READY | 80000000 | | 173 | 2 | DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT3_CLK | CLK_STATE_READY | 80000000 | | 173 | 3 | DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 173 | 4 | DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT2_CLK | CLK_STATE_READY | 80000000 | | 173 | 5 | DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 274 | 0 | DEV_MCU_MCSPI0_VBUSP_CLK | CLK_STATE_READY | 166666666 | | 274 | 1 | DEV_MCU_MCSPI0_CLKSPIREF_CLK | CLK_STATE_READY | 50000000 | | 274 | 2 | DEV_MCU_MCSPI0_IO_CLKSPIO_CLK | CLK_STATE_READY | 0 | | 275 | 0 | DEV_MCU_MCSPI1_VBUSP_CLK | CLK_STATE_READY | 166666666 | | 275 | 1 | DEV_MCU_MCSPI1_CLKSPIREF_CLK | CLK_STATE_READY | 50000000 | | 275 | 2 | DEV_MCU_MCSPI1_IO_CLKSPII_CLK | CLK_STATE_NOT_READY | 0 | | 275 | 3 | DEV_MCU_MCSPI1_IO_CLKSPII_CLK_PARENT_SPI_MAIN_3_IO_CLKSPIO_CLK | CLK_STATE_READY | 0 | | 275 | 4 | DEV_MCU_MCSPI1_IO_CLKSPIO_CLK | CLK_STATE_READY | 0 | | 276 | 0 | DEV_MCU_MCSPI2_VBUSP_CLK | CLK_STATE_READY | 166666666 | | 276 | 1 | DEV_MCU_MCSPI2_CLKSPIREF_CLK | CLK_STATE_READY | 50000000 | | 276 | 2 | DEV_MCU_MCSPI2_IO_CLKSPII_CLK | CLK_STATE_READY | 0 | | 276 | 3 | DEV_MCU_MCSPI2_IO_CLKSPIO_CLK | CLK_STATE_READY | 0 | | 237 | 0 | DEV_MCU_NAVSS0_INTR_0_INTR_CLK | CLK_STATE_READY | 1000000000 | | 238 | 0 | DEV_MCU_NAVSS0_MCRC_0_CLK | CLK_STATE_READY | 1000000000 | | 302 | 0 | DEV_MCU_NAVSS0_MODSS_VD2CLK | CLK_STATE_READY | 1000000000 | | 234 | 0 | DEV_MCU_NAVSS0_PROXY0_CLK_CLK | CLK_STATE_READY | 1000000000 | | 235 | 0 | DEV_MCU_NAVSS0_RINGACC0_SYS_CLK | CLK_STATE_READY | 1000000000 | | 236 | 0 | DEV_MCU_NAVSS0_UDMAP_0_SYS_CLK | CLK_STATE_READY | 1000000000 | | 303 | 0 | DEV_MCU_NAVSS0_UDMASS_VD2CLK | CLK_STATE_READY | 1000000000 | | 233 | 0 | DEV_MCU_NAVSS0_UDMASS_INTA_0_SYS_CLK | CLK_STATE_READY | 1000000000 | | 250 | 0 | DEV_MCU_R5FSS0_CORE0_CPU_CLK | CLK_STATE_READY | 1000000000 | | 250 | 1 | DEV_MCU_R5FSS0_CORE0_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK | CLK_STATE_READY | 1000000000 | | 250 | 2 | DEV_MCU_R5FSS0_CORE0_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK3 | CLK_STATE_READY | 333333333 | | 250 | 3 | DEV_MCU_R5FSS0_CORE0_INTERFACE_CLK | CLK_STATE_READY | 1000000000 | | 250 | 4 | DEV_MCU_R5FSS0_CORE0_INTERFACE_PHASE | CLK_STATE_READY | 333333333 | | 251 | 0 | DEV_MCU_R5FSS0_CORE1_CPU_CLK | CLK_STATE_READY | 1000000000 | | 251 | 1 | DEV_MCU_R5FSS0_CORE1_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK | CLK_STATE_READY | 1000000000 | | 251 | 2 | DEV_MCU_R5FSS0_CORE1_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK3 | CLK_STATE_READY | 333333333 | | 251 | 3 | DEV_MCU_R5FSS0_CORE1_INTERFACE_CLK | CLK_STATE_READY | 1000000000 | | 251 | 4 | DEV_MCU_R5FSS0_CORE1_INTERFACE_PHASE | CLK_STATE_READY | 333333333 | | 262 | 0 | DEV_MCU_RTI0_VBUSP_CLK | CLK_STATE_READY | 166666666 | | 262 | 1 | DEV_MCU_RTI0_RTI_CLK | CLK_STATE_READY | 19200000 | | 262 | 2 | DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 262 | 3 | DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 262 | 4 | DEV_MCU_RTI0_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 262 | 5 | DEV_MCU_RTI0_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32000 | | 263 | 0 | DEV_MCU_RTI1_VBUSP_CLK | CLK_STATE_READY | 166666666 | | 263 | 1 | DEV_MCU_RTI1_RTI_CLK | CLK_STATE_READY | 19200000 | | 263 | 2 | DEV_MCU_RTI1_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 263 | 3 | DEV_MCU_RTI1_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 263 | 4 | DEV_MCU_RTI1_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 263 | 5 | DEV_MCU_RTI1_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32000 | | 265 | 0 | DEV_MCU_SA2_UL0_X2_CLK | CLK_STATE_READY | 333333333 | | 265 | 1 | DEV_MCU_SA2_UL0_PKA_IN_CLK | CLK_STATE_READY | 400000000 | | 265 | 2 | DEV_MCU_SA2_UL0_X1_CLK | CLK_STATE_READY | 166666666 | | 35 | 0 | DEV_MCU_TIMER0_TIMER_HCLK_CLK | CLK_STATE_READY | 166666666 | | 35 | 1 | DEV_MCU_TIMER0_TIMER_TCLK_CLK | CLK_STATE_READY | 166666666 | | 35 | 2 | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 35 | 3 | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6 | CLK_STATE_READY | 166666666 | | 35 | 4 | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 35 | 5 | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | 35 | 6 | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 35 | 7 | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 35 | 8 | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | 35 | 9 | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32000 | | 35 | 10 | DEV_MCU_TIMER0_TIMER_PWM | CLK_STATE_READY | 0 | | 71 | 0 | DEV_MCU_TIMER1_TIMER_HCLK_CLK | CLK_STATE_READY | 166666666 | | 71 | 1 | DEV_MCU_TIMER1_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | 71 | 2 | DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT1 | CLK_STATE_READY | 19200000 | | 71 | 3 | DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_0_TIMER_PWM | CLK_STATE_READY | 0 | | 322 | 0 | DEV_MCU_TIMER1_CLKSEL_VD_CLK | CLK_STATE_READY | 19200000 | | 322 | 1 | DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 322 | 2 | DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6 | CLK_STATE_READY | 166666666 | | 322 | 3 | DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 322 | 4 | DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | 322 | 5 | DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 322 | 6 | DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 322 | 7 | DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | 322 | 8 | DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32000 | | 72 | 0 | DEV_MCU_TIMER2_TIMER_HCLK_CLK | CLK_STATE_READY | 166666666 | | 72 | 1 | DEV_MCU_TIMER2_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | 72 | 2 | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 72 | 3 | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6 | CLK_STATE_READY | 166666666 | | 72 | 4 | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 72 | 5 | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | 72 | 6 | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 72 | 7 | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 72 | 8 | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | 72 | 9 | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32000 | | 72 | 10 | DEV_MCU_TIMER2_TIMER_PWM | CLK_STATE_READY | 0 | | 73 | 0 | DEV_MCU_TIMER3_TIMER_HCLK_CLK | CLK_STATE_READY | 166666666 | | 73 | 1 | DEV_MCU_TIMER3_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | 73 | 2 | DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT3 | CLK_STATE_READY | 19200000 | | 73 | 3 | DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_2_TIMER_PWM | CLK_STATE_READY | 0 | | 323 | 0 | DEV_MCU_TIMER3_CLKSEL_VD_CLK | CLK_STATE_READY | 19200000 | | 323 | 1 | DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 323 | 2 | DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6 | CLK_STATE_READY | 166666666 | | 323 | 3 | DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 323 | 4 | DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | 323 | 5 | DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 323 | 6 | DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 323 | 7 | DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | 323 | 8 | DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32000 | | 74 | 0 | DEV_MCU_TIMER4_TIMER_HCLK_CLK | CLK_STATE_READY | 166666666 | | 74 | 1 | DEV_MCU_TIMER4_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | 74 | 2 | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 74 | 3 | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6 | CLK_STATE_READY | 166666666 | | 74 | 4 | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 74 | 5 | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | 74 | 6 | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 74 | 7 | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 74 | 8 | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | 74 | 9 | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32000 | | 74 | 10 | DEV_MCU_TIMER4_TIMER_PWM | CLK_STATE_READY | 0 | | 75 | 0 | DEV_MCU_TIMER5_TIMER_HCLK_CLK | CLK_STATE_READY | 166666666 | | 75 | 1 | DEV_MCU_TIMER5_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | 75 | 2 | DEV_MCU_TIMER5_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT5 | CLK_STATE_READY | 19200000 | | 75 | 3 | DEV_MCU_TIMER5_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_4_TIMER_PWM | CLK_STATE_READY | 0 | | 324 | 0 | DEV_MCU_TIMER5_CLKSEL_VD_CLK | CLK_STATE_READY | 19200000 | | 324 | 1 | DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 324 | 2 | DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6 | CLK_STATE_READY | 166666666 | | 324 | 3 | DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 324 | 4 | DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | 324 | 5 | DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 324 | 6 | DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 324 | 7 | DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | 324 | 8 | DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32000 | | 76 | 0 | DEV_MCU_TIMER6_TIMER_HCLK_CLK | CLK_STATE_READY | 166666666 | | 76 | 1 | DEV_MCU_TIMER6_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | 76 | 2 | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 76 | 3 | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6 | CLK_STATE_READY | 166666666 | | 76 | 4 | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 76 | 5 | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | 76 | 6 | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 76 | 7 | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 76 | 8 | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | 76 | 9 | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32000 | | 76 | 10 | DEV_MCU_TIMER6_TIMER_PWM | CLK_STATE_READY | 0 | | 77 | 0 | DEV_MCU_TIMER7_TIMER_HCLK_CLK | CLK_STATE_READY | 166666666 | | 77 | 1 | DEV_MCU_TIMER7_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | 77 | 2 | DEV_MCU_TIMER7_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT7 | CLK_STATE_READY | 19200000 | | 77 | 3 | DEV_MCU_TIMER7_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_6_TIMER_PWM | CLK_STATE_READY | 0 | | 325 | 0 | DEV_MCU_TIMER7_CLKSEL_VD_CLK | CLK_STATE_READY | 19200000 | | 325 | 1 | DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 325 | 2 | DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6 | CLK_STATE_READY | 166666666 | | 325 | 3 | DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 325 | 4 | DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | 325 | 5 | DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 325 | 6 | DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 325 | 7 | DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | 325 | 8 | DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32000 | | 78 | 0 | DEV_MCU_TIMER8_TIMER_HCLK_CLK | CLK_STATE_READY | 166666666 | | 78 | 1 | DEV_MCU_TIMER8_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | 78 | 2 | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 78 | 3 | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6 | CLK_STATE_READY | 166666666 | | 78 | 4 | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 78 | 5 | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | 78 | 6 | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 78 | 7 | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 78 | 8 | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | 78 | 9 | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32000 | | 78 | 10 | DEV_MCU_TIMER8_TIMER_PWM | CLK_STATE_READY | 0 | | 79 | 0 | DEV_MCU_TIMER9_TIMER_HCLK_CLK | CLK_STATE_READY | 166666666 | | 79 | 1 | DEV_MCU_TIMER9_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | 79 | 2 | DEV_MCU_TIMER9_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT9 | CLK_STATE_READY | 19200000 | | 79 | 3 | DEV_MCU_TIMER9_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_8_TIMER_PWM | CLK_STATE_READY | 0 | | 326 | 0 | DEV_MCU_TIMER9_CLKSEL_VD_CLK | CLK_STATE_READY | 19200000 | | 326 | 1 | DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 326 | 2 | DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6 | CLK_STATE_READY | 166666666 | | 326 | 3 | DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 326 | 4 | DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | 326 | 5 | DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 326 | 6 | DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 326 | 7 | DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | 326 | 8 | DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32000 | | 149 | 0 | DEV_MCU_UART0_FCLK_CLK | CLK_STATE_READY | 96000000 | | 149 | 1 | DEV_MCU_UART0_FCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT3_CLK | CLK_STATE_READY | 96000000 | | 149 | 2 | DEV_MCU_UART0_FCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_1_HSDIVOUT5_CLK | CLK_STATE_READY | 192000000 | | 149 | 3 | DEV_MCU_UART0_VBUSP_CLK | CLK_STATE_READY | 166666666 | | 186 | 0 | DEV_MLB0_MLBSS_MLB_CLK | CLK_STATE_READY | 0 | | 186 | 1 | DEV_MLB0_MLBSS_SCLK_CLK | CLK_STATE_READY | 250000000 | | 186 | 2 | DEV_MLB0_MLBSS_HCLK_CLK | CLK_STATE_READY | 250000000 | | 186 | 3 | DEV_MLB0_MLBSS_PCLK_CLK | CLK_STATE_READY | 250000000 | | 186 | 4 | DEV_MLB0_MLBSS_AMLB_CLK | CLK_STATE_READY | 0 | | 91 | 0 | DEV_MMCSD0_EMMCSS_VBUS_CLK | CLK_STATE_READY | 250000000 | | 91 | 1 | DEV_MMCSD0_EMMCSS_XIN_CLK | CLK_STATE_READY | 200000000 | | 91 | 2 | DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | 91 | 3 | DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK | CLK_STATE_READY | 192000000 | | 91 | 4 | DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | 91 | 5 | DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | 91 | 6 | DEV_MMCSD0_EMMCSS_IO_CLK | CLK_STATE_READY | 0 | | 92 | 0 | DEV_MMCSD1_EMMCSDSS_XIN_CLK | CLK_STATE_READY | 200000000 | | 92 | 1 | DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | 92 | 2 | DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK | CLK_STATE_READY | 192000000 | | 92 | 3 | DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | 92 | 4 | DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | 92 | 5 | DEV_MMCSD1_EMMCSDSS_VBUS_CLK | CLK_STATE_READY | 250000000 | | 92 | 6 | DEV_MMCSD1_EMMCSDSS_IO_CLK_I | CLK_STATE_READY | 0 | | 92 | 7 | DEV_MMCSD1_EMMCSDSS_IO_CLK_O | CLK_STATE_READY | 0 | | 93 | 0 | DEV_MMCSD2_EMMCSDSS_XIN_CLK | CLK_STATE_READY | 200000000 | | 93 | 1 | DEV_MMCSD2_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | 93 | 2 | DEV_MMCSD2_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK | CLK_STATE_READY | 192000000 | | 93 | 3 | DEV_MMCSD2_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | 93 | 4 | DEV_MMCSD2_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK | CLK_STATE_READY | 200000000 | | 93 | 5 | DEV_MMCSD2_EMMCSDSS_VBUS_CLK | CLK_STATE_READY | 250000000 | | 93 | 6 | DEV_MMCSD2_EMMCSDSS_IO_CLK_I | CLK_STATE_READY | 0 | | 93 | 7 | DEV_MMCSD2_EMMCSDSS_IO_CLK_O | CLK_STATE_READY | 0 | | 199 | 0 | DEV_NAVSS0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | 199 | 1 | DEV_NAVSS0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | 201 | 0 | DEV_NAVSS0_CPTS_0_VBUSP_GCLK | CLK_STATE_READY | 500000000 | | 201 | 1 | DEV_NAVSS0_CPTS_0_RCLK | CLK_STATE_READY | 200000000 | | 201 | 2 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | 201 | 3 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK | CLK_STATE_READY | 250000000 | | 201 | 4 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 201 | 5 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 201 | 6 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 201 | 7 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 201 | 8 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK | CLK_STATE_NOT_READY | 0 | | 201 | 9 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK | CLK_STATE_NOT_READY | 0 | | 201 | 10 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK | CLK_STATE_READY | 0 | | 201 | 11 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK | CLK_STATE_READY | 0 | | 201 | 12 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK | CLK_STATE_READY | 0 | | 201 | 13 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK | CLK_STATE_READY | 0 | | 201 | 14 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN0_TXMCLK | CLK_STATE_READY | 0 | | 201 | 15 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN1_TXMCLK | CLK_STATE_READY | 0 | | 201 | 16 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK | CLK_STATE_READY | 500000000 | | 201 | 17 | DEV_NAVSS0_CPTS_0_RCLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK | CLK_STATE_READY | 500000000 | | 201 | 18 | DEV_NAVSS0_CPTS_0_TS_GENF0 | CLK_STATE_READY | 0 | | 201 | 19 | DEV_NAVSS0_CPTS_0_TS_GENF1 | CLK_STATE_READY | 0 | | 206 | 0 | DEV_NAVSS0_DTI_0_CLK_CLK | CLK_STATE_READY | 500000000 | | 206 | 1 | DEV_NAVSS0_DTI_0_EXT0_DTI_CLK_CLK | CLK_STATE_READY | 500000000 | | 206 | 2 | DEV_NAVSS0_DTI_0_EXT3_DTI_CLK_CLK | CLK_STATE_READY | 500000000 | | 206 | 3 | DEV_NAVSS0_DTI_0_EXT1_DTI_CLK_CLK | CLK_STATE_READY | 500000000 | | 206 | 4 | DEV_NAVSS0_DTI_0_EXT2_DTI_CLK_CLK | CLK_STATE_READY | 500000000 | | 213 | 0 | DEV_NAVSS0_INTR_ROUTER_0_INTR_CLK | CLK_STATE_READY | 500000000 | | 214 | 0 | DEV_NAVSS0_MAILBOX_0_VCLK_CLK | CLK_STATE_READY | 500000000 | | 215 | 0 | DEV_NAVSS0_MAILBOX_1_VCLK_CLK | CLK_STATE_READY | 500000000 | | 224 | 0 | DEV_NAVSS0_MAILBOX_10_VCLK_CLK | CLK_STATE_READY | 500000000 | | 225 | 0 | DEV_NAVSS0_MAILBOX_11_VCLK_CLK | CLK_STATE_READY | 500000000 | | 216 | 0 | DEV_NAVSS0_MAILBOX_2_VCLK_CLK | CLK_STATE_READY | 500000000 | | 217 | 0 | DEV_NAVSS0_MAILBOX_3_VCLK_CLK | CLK_STATE_READY | 500000000 | | 218 | 0 | DEV_NAVSS0_MAILBOX_4_VCLK_CLK | CLK_STATE_READY | 500000000 | | 219 | 0 | DEV_NAVSS0_MAILBOX_5_VCLK_CLK | CLK_STATE_READY | 500000000 | | 220 | 0 | DEV_NAVSS0_MAILBOX_6_VCLK_CLK | CLK_STATE_READY | 500000000 | | 221 | 0 | DEV_NAVSS0_MAILBOX_7_VCLK_CLK | CLK_STATE_READY | 500000000 | | 222 | 0 | DEV_NAVSS0_MAILBOX_8_VCLK_CLK | CLK_STATE_READY | 500000000 | | 223 | 0 | DEV_NAVSS0_MAILBOX_9_VCLK_CLK | CLK_STATE_READY | 500000000 | | 227 | 0 | DEV_NAVSS0_MCRC_0_CLK | CLK_STATE_READY | 500000000 | | 299 | 0 | DEV_NAVSS0_MODSS_VD2CLK | CLK_STATE_READY | 500000000 | | 207 | 0 | DEV_NAVSS0_MODSS_INTAGGR_0_SYS_CLK | CLK_STATE_READY | 500000000 | | 208 | 0 | DEV_NAVSS0_MODSS_INTAGGR_1_SYS_CLK | CLK_STATE_READY | 500000000 | | 210 | 0 | DEV_NAVSS0_PROXY_0_CLK_CLK | CLK_STATE_READY | 500000000 | | 339 | 0 | DEV_NAVSS0_PVU_0_CLK_CLK | CLK_STATE_READY | 500000000 | | 340 | 0 | DEV_NAVSS0_PVU_1_CLK_CLK | CLK_STATE_READY | 500000000 | | 341 | 0 | DEV_NAVSS0_PVU_2_CLK_CLK | CLK_STATE_READY | 500000000 | | 211 | 0 | DEV_NAVSS0_RINGACC_0_SYS_CLK | CLK_STATE_READY | 500000000 | | 226 | 0 | DEV_NAVSS0_SPINLOCK_0_CLK | CLK_STATE_READY | 500000000 | | 228 | 0 | DEV_NAVSS0_TBU_0_CLK_CLK | CLK_STATE_READY | 500000000 | | 229 | 0 | DEV_NAVSS0_TCU_0_CLK_CLK | CLK_STATE_READY | 500000000 | | 230 | 0 | DEV_NAVSS0_TIMERMGR_0_VCLK_CLK | CLK_STATE_READY | 500000000 | | 230 | 1 | DEV_NAVSS0_TIMERMGR_0_EON_TICK_EVT | CLK_STATE_READY | 0 | | 231 | 0 | DEV_NAVSS0_TIMERMGR_1_VCLK_CLK | CLK_STATE_READY | 500000000 | | 231 | 1 | DEV_NAVSS0_TIMERMGR_1_EON_TICK_EVT | CLK_STATE_READY | 0 | | 212 | 0 | DEV_NAVSS0_UDMAP_0_SYS_CLK | CLK_STATE_READY | 500000000 | | 300 | 0 | DEV_NAVSS0_UDMASS_VD2CLK | CLK_STATE_READY | 500000000 | | 209 | 0 | DEV_NAVSS0_UDMASS_INTAGGR_0_SYS_CLK | CLK_STATE_READY | 500000000 | | 301 | 0 | DEV_NAVSS0_VIRTSS_VD2CLK | CLK_STATE_READY | 500000000 | | 239 | 0 | DEV_PCIE0_PCIE_LANE1_TXMCLK | CLK_STATE_READY | 0 | | 239 | 1 | DEV_PCIE0_PCIE_CBA_CLK | CLK_STATE_READY | 500000000 | | 239 | 2 | DEV_PCIE0_PCIE_LANE1_RXCLK | CLK_STATE_READY | 0 | | 239 | 3 | DEV_PCIE0_PCIE_CPTS_RCLK_CLK | CLK_STATE_READY | 200000000 | | 239 | 4 | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | 239 | 5 | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK | CLK_STATE_READY | 250000000 | | 239 | 6 | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 239 | 7 | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 239 | 8 | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 239 | 9 | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 239 | 10 | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK | CLK_STATE_NOT_READY | 0 | | 239 | 11 | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK | CLK_STATE_NOT_READY | 0 | | 239 | 12 | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK | CLK_STATE_READY | 0 | | 239 | 13 | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK | CLK_STATE_READY | 0 | | 239 | 14 | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK | CLK_STATE_READY | 0 | | 239 | 15 | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK | CLK_STATE_READY | 0 | | 239 | 16 | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK_DUP0 | CLK_STATE_READY | 0 | | 239 | 17 | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK_DUP0 | CLK_STATE_READY | 0 | | 239 | 18 | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK | CLK_STATE_READY | 500000000 | | 239 | 19 | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK | CLK_STATE_READY | 500000000 | | 239 | 20 | DEV_PCIE0_PCIE_LANE1_TXFCLK | CLK_STATE_READY | 0 | | 239 | 21 | DEV_PCIE0_PCIE_LANE1_REFCLK | CLK_STATE_READY | 0 | | 239 | 22 | DEV_PCIE0_PCIE_LANE0_REFCLK | CLK_STATE_READY | 0 | | 239 | 23 | DEV_PCIE0_PCIE_LANE0_TXMCLK | CLK_STATE_READY | 0 | | 239 | 24 | DEV_PCIE0_PCIE_LANE0_TXFCLK | CLK_STATE_READY | 0 | | 239 | 25 | DEV_PCIE0_PCIE_PM_CLK | CLK_STATE_READY | 12500000 | | 239 | 26 | DEV_PCIE0_PCIE_LANE0_RXFCLK | CLK_STATE_READY | 0 | | 239 | 27 | DEV_PCIE0_PCIE_LANE1_RXFCLK | CLK_STATE_READY | 0 | | 239 | 28 | DEV_PCIE0_PCIE_LANE0_RXCLK | CLK_STATE_READY | 0 | | 239 | 29 | DEV_PCIE0_PCIE_LANE1_TXCLK | CLK_STATE_READY | 0 | | 239 | 30 | DEV_PCIE0_PCIE_LANE0_TXCLK | CLK_STATE_READY | 0 | | 240 | 0 | DEV_PCIE1_PCIE_LANE1_TXMCLK | CLK_STATE_READY | 0 | | 240 | 1 | DEV_PCIE1_PCIE_CBA_CLK | CLK_STATE_READY | 500000000 | | 240 | 2 | DEV_PCIE1_PCIE_LANE1_RXCLK | CLK_STATE_READY | 0 | | 240 | 3 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK | CLK_STATE_READY | 200000000 | | 240 | 4 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | 240 | 5 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK | CLK_STATE_READY | 250000000 | | 240 | 6 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 240 | 7 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 240 | 8 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 240 | 9 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 240 | 10 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK | CLK_STATE_NOT_READY | 0 | | 240 | 11 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK | CLK_STATE_NOT_READY | 0 | | 240 | 12 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK | CLK_STATE_READY | 0 | | 240 | 13 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK | CLK_STATE_READY | 0 | | 240 | 14 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK | CLK_STATE_READY | 0 | | 240 | 15 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK | CLK_STATE_READY | 0 | | 240 | 16 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK_DUP0 | CLK_STATE_READY | 0 | | 240 | 17 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK_DUP0 | CLK_STATE_READY | 0 | | 240 | 18 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK | CLK_STATE_READY | 500000000 | | 240 | 19 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK | CLK_STATE_READY | 500000000 | | 240 | 20 | DEV_PCIE1_PCIE_LANE1_TXFCLK | CLK_STATE_READY | 0 | | 240 | 21 | DEV_PCIE1_PCIE_LANE1_REFCLK | CLK_STATE_READY | 0 | | 240 | 22 | DEV_PCIE1_PCIE_LANE0_REFCLK | CLK_STATE_READY | 0 | | 240 | 23 | DEV_PCIE1_PCIE_LANE0_TXMCLK | CLK_STATE_READY | 0 | | 240 | 24 | DEV_PCIE1_PCIE_LANE0_TXFCLK | CLK_STATE_READY | 0 | | 240 | 25 | DEV_PCIE1_PCIE_PM_CLK | CLK_STATE_READY | 12500000 | | 240 | 26 | DEV_PCIE1_PCIE_LANE0_RXFCLK | CLK_STATE_READY | 0 | | 240 | 27 | DEV_PCIE1_PCIE_LANE1_RXFCLK | CLK_STATE_READY | 0 | | 240 | 28 | DEV_PCIE1_PCIE_LANE0_RXCLK | CLK_STATE_READY | 0 | | 240 | 29 | DEV_PCIE1_PCIE_LANE1_TXCLK | CLK_STATE_READY | 0 | | 240 | 30 | DEV_PCIE1_PCIE_LANE0_TXCLK | CLK_STATE_READY | 0 | | 241 | 0 | DEV_PCIE2_PCIE_LANE1_TXMCLK | CLK_STATE_READY | 0 | | 241 | 1 | DEV_PCIE2_PCIE_CBA_CLK | CLK_STATE_READY | 500000000 | | 241 | 2 | DEV_PCIE2_PCIE_LANE1_RXCLK | CLK_STATE_READY | 0 | | 241 | 3 | DEV_PCIE2_PCIE_CPTS_RCLK_CLK | CLK_STATE_READY | 200000000 | | 241 | 4 | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | 241 | 5 | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK | CLK_STATE_READY | 250000000 | | 241 | 6 | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 241 | 7 | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 241 | 8 | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 241 | 9 | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 241 | 10 | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK | CLK_STATE_NOT_READY | 0 | | 241 | 11 | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK | CLK_STATE_NOT_READY | 0 | | 241 | 12 | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK | CLK_STATE_READY | 0 | | 241 | 13 | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK | CLK_STATE_READY | 0 | | 241 | 14 | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK | CLK_STATE_READY | 0 | | 241 | 15 | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK | CLK_STATE_READY | 0 | | 241 | 16 | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK_DUP0 | CLK_STATE_READY | 0 | | 241 | 17 | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK_DUP0 | CLK_STATE_READY | 0 | | 241 | 18 | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK | CLK_STATE_READY | 500000000 | | 241 | 19 | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK | CLK_STATE_READY | 500000000 | | 241 | 20 | DEV_PCIE2_PCIE_LANE1_TXFCLK | CLK_STATE_READY | 0 | | 241 | 21 | DEV_PCIE2_PCIE_LANE1_REFCLK | CLK_STATE_READY | 0 | | 241 | 22 | DEV_PCIE2_PCIE_LANE0_REFCLK | CLK_STATE_READY | 0 | | 241 | 23 | DEV_PCIE2_PCIE_LANE0_TXMCLK | CLK_STATE_READY | 0 | | 241 | 24 | DEV_PCIE2_PCIE_LANE0_TXFCLK | CLK_STATE_READY | 0 | | 241 | 25 | DEV_PCIE2_PCIE_PM_CLK | CLK_STATE_READY | 12500000 | | 241 | 26 | DEV_PCIE2_PCIE_LANE0_RXFCLK | CLK_STATE_READY | 0 | | 241 | 27 | DEV_PCIE2_PCIE_LANE1_RXFCLK | CLK_STATE_READY | 0 | | 241 | 28 | DEV_PCIE2_PCIE_LANE0_RXCLK | CLK_STATE_READY | 0 | | 241 | 29 | DEV_PCIE2_PCIE_LANE1_TXCLK | CLK_STATE_READY | 0 | | 241 | 30 | DEV_PCIE2_PCIE_LANE0_TXCLK | CLK_STATE_READY | 0 | | 242 | 0 | DEV_PCIE3_PCIE_LANE1_TXMCLK | CLK_STATE_READY | 0 | | 242 | 1 | DEV_PCIE3_PCIE_CBA_CLK | CLK_STATE_READY | 500000000 | | 242 | 2 | DEV_PCIE3_PCIE_LANE1_RXCLK | CLK_STATE_READY | 0 | | 242 | 3 | DEV_PCIE3_PCIE_CPTS_RCLK_CLK | CLK_STATE_READY | 200000000 | | 242 | 4 | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | 242 | 5 | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK | CLK_STATE_READY | 250000000 | | 242 | 6 | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 242 | 7 | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 242 | 8 | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 242 | 9 | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 242 | 10 | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK | CLK_STATE_NOT_READY | 0 | | 242 | 11 | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK | CLK_STATE_NOT_READY | 0 | | 242 | 12 | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK | CLK_STATE_READY | 0 | | 242 | 13 | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK | CLK_STATE_READY | 0 | | 242 | 14 | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK | CLK_STATE_READY | 0 | | 242 | 15 | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK | CLK_STATE_READY | 0 | | 242 | 16 | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK_DUP0 | CLK_STATE_READY | 0 | | 242 | 17 | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK_DUP0 | CLK_STATE_READY | 0 | | 242 | 18 | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK | CLK_STATE_READY | 500000000 | | 242 | 19 | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK | CLK_STATE_READY | 500000000 | | 242 | 20 | DEV_PCIE3_PCIE_LANE1_TXFCLK | CLK_STATE_READY | 0 | | 242 | 21 | DEV_PCIE3_PCIE_LANE1_REFCLK | CLK_STATE_READY | 0 | | 242 | 22 | DEV_PCIE3_PCIE_LANE0_REFCLK | CLK_STATE_READY | 0 | | 242 | 23 | DEV_PCIE3_PCIE_LANE0_TXMCLK | CLK_STATE_READY | 0 | | 242 | 24 | DEV_PCIE3_PCIE_LANE0_TXFCLK | CLK_STATE_READY | 0 | | 242 | 25 | DEV_PCIE3_PCIE_PM_CLK | CLK_STATE_READY | 12500000 | | 242 | 26 | DEV_PCIE3_PCIE_LANE0_RXFCLK | CLK_STATE_READY | 0 | | 242 | 27 | DEV_PCIE3_PCIE_LANE1_RXFCLK | CLK_STATE_READY | 0 | | 242 | 28 | DEV_PCIE3_PCIE_LANE0_RXCLK | CLK_STATE_READY | 0 | | 242 | 29 | DEV_PCIE3_PCIE_LANE1_TXCLK | CLK_STATE_READY | 0 | | 242 | 30 | DEV_PCIE3_PCIE_LANE0_TXCLK | CLK_STATE_READY | 0 | | 119 | 0 | DEV_PRU_ICSSG0_PR1_RGMII0_RXC_I | CLK_STATE_READY | 0 | | 119 | 1 | DEV_PRU_ICSSG0_VCLK_CLK | CLK_STATE_READY | 250000000 | | 119 | 2 | DEV_PRU_ICSSG0_PR1_RGMII1_TXC_I | CLK_STATE_READY | 0 | | 119 | 3 | DEV_PRU_ICSSG0_IEP_CLK | CLK_STATE_READY | 200000000 | | 119 | 4 | DEV_PRU_ICSSG0_IEP_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | 119 | 5 | DEV_PRU_ICSSG0_IEP_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK | CLK_STATE_READY | 250000000 | | 119 | 6 | DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 119 | 7 | DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 119 | 8 | DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 119 | 9 | DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 119 | 10 | DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK | CLK_STATE_NOT_READY | 0 | | 119 | 11 | DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK | CLK_STATE_NOT_READY | 0 | | 119 | 12 | DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK | CLK_STATE_READY | 0 | | 119 | 13 | DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK | CLK_STATE_READY | 0 | | 119 | 14 | DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK | CLK_STATE_READY | 0 | | 119 | 15 | DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK | CLK_STATE_READY | 0 | | 119 | 16 | DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN0_TXMCLK | CLK_STATE_READY | 0 | | 119 | 17 | DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN1_TXMCLK | CLK_STATE_READY | 0 | | 119 | 18 | DEV_PRU_ICSSG0_IEP_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK | CLK_STATE_READY | 500000000 | | 119 | 19 | DEV_PRU_ICSSG0_IEP_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK | CLK_STATE_READY | 500000000 | | 119 | 20 | DEV_PRU_ICSSG0_RGMII_MHZ_5_CLK | CLK_STATE_READY | 5000000 | | 119 | 21 | DEV_PRU_ICSSG0_PR1_RGMII1_RXC_I | CLK_STATE_READY | 0 | | 119 | 22 | DEV_PRU_ICSSG0_UCLK_CLK | CLK_STATE_READY | 192000000 | | 119 | 23 | DEV_PRU_ICSSG0_PR1_RGMII0_TXC_I | CLK_STATE_READY | 0 | | 119 | 24 | DEV_PRU_ICSSG0_CORE_CLK | CLK_STATE_READY | 225000000 | | 119 | 25 | DEV_PRU_ICSSG0_CORE_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK | CLK_STATE_READY | 225000000 | | 119 | 26 | DEV_PRU_ICSSG0_CORE_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | 119 | 27 | DEV_PRU_ICSSG0_RGMII_MHZ_250_CLK | CLK_STATE_READY | 250000000 | | 119 | 28 | DEV_PRU_ICSSG0_RGMII_MHZ_50_CLK | CLK_STATE_READY | 50000000 | | 119 | 29 | DEV_PRU_ICSSG0_PR1_RGMII1_TXC_O | CLK_STATE_READY | 0 | | 119 | 30 | DEV_PRU_ICSSG0_PR1_MDIO_MDCLK_O | CLK_STATE_READY | 0 | | 119 | 31 | DEV_PRU_ICSSG0_PR1_RGMII0_TXC_O | CLK_STATE_READY | 0 | | 120 | 0 | DEV_PRU_ICSSG1_SERDES0_RXCLK | CLK_STATE_READY | 0 | | 120 | 1 | DEV_PRU_ICSSG1_SERDES0_RXCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN0_RXCLK | CLK_STATE_READY | 0 | | 120 | 2 | DEV_PRU_ICSSG1_SERDES0_RXCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN0_RXCLK | CLK_STATE_READY | 0 | | 120 | 3 | DEV_PRU_ICSSG1_PR1_RGMII0_RXC_I | CLK_STATE_READY | 0 | | 120 | 4 | DEV_PRU_ICSSG1_VCLK_CLK | CLK_STATE_READY | 250000000 | | 120 | 5 | DEV_PRU_ICSSG1_PR1_RGMII1_TXC_I | CLK_STATE_READY | 0 | | 120 | 6 | DEV_PRU_ICSSG1_SERDES0_RXFCLK | CLK_STATE_READY | 0 | | 120 | 7 | DEV_PRU_ICSSG1_SERDES0_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN0_RXFCLK | CLK_STATE_READY | 0 | | 120 | 8 | DEV_PRU_ICSSG1_SERDES0_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN0_RXFCLK | CLK_STATE_READY | 0 | | 120 | 9 | DEV_PRU_ICSSG1_IEP_CLK | CLK_STATE_READY | 200000000 | | 120 | 10 | DEV_PRU_ICSSG1_IEP_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | 120 | 11 | DEV_PRU_ICSSG1_IEP_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK | CLK_STATE_READY | 250000000 | | 120 | 12 | DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 120 | 13 | DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 120 | 14 | DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 120 | 15 | DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 120 | 16 | DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK | CLK_STATE_NOT_READY | 0 | | 120 | 17 | DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK | CLK_STATE_NOT_READY | 0 | | 120 | 18 | DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK | CLK_STATE_READY | 0 | | 120 | 19 | DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK | CLK_STATE_READY | 0 | | 120 | 20 | DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK | CLK_STATE_READY | 0 | | 120 | 21 | DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK | CLK_STATE_READY | 0 | | 120 | 22 | DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN0_TXMCLK | CLK_STATE_READY | 0 | | 120 | 23 | DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN1_TXMCLK | CLK_STATE_READY | 0 | | 120 | 24 | DEV_PRU_ICSSG1_IEP_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK | CLK_STATE_READY | 500000000 | | 120 | 25 | DEV_PRU_ICSSG1_IEP_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK | CLK_STATE_READY | 500000000 | | 120 | 26 | DEV_PRU_ICSSG1_RGMII_MHZ_5_CLK | CLK_STATE_READY | 5000000 | | 120 | 27 | DEV_PRU_ICSSG1_SERDES0_TXMCLK | CLK_STATE_READY | 0 | | 120 | 28 | DEV_PRU_ICSSG1_SERDES0_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN0_TXMCLK | CLK_STATE_READY | 0 | | 120 | 29 | DEV_PRU_ICSSG1_SERDES0_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN0_TXMCLK | CLK_STATE_READY | 0 | | 120 | 30 | DEV_PRU_ICSSG1_SERDES0_REFCLK | CLK_STATE_READY | 0 | | 120 | 31 | DEV_PRU_ICSSG1_SERDES0_REFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN0_REFCLK | CLK_STATE_READY | 0 | | 120 | 32 | DEV_PRU_ICSSG1_SERDES0_REFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN0_REFCLK | CLK_STATE_READY | 0 | | 120 | 33 | DEV_PRU_ICSSG1_SERDES1_RXFCLK | CLK_STATE_READY | 0 | | 120 | 34 | DEV_PRU_ICSSG1_SERDES1_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN1_RXFCLK | CLK_STATE_READY | 0 | | 120 | 35 | DEV_PRU_ICSSG1_SERDES1_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN1_RXFCLK | CLK_STATE_READY | 0 | | 120 | 36 | DEV_PRU_ICSSG1_PR1_RGMII1_RXC_I | CLK_STATE_READY | 0 | | 120 | 37 | DEV_PRU_ICSSG1_SERDES1_RXCLK | CLK_STATE_READY | 0 | | 120 | 38 | DEV_PRU_ICSSG1_SERDES1_RXCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN1_RXCLK | CLK_STATE_READY | 0 | | 120 | 39 | DEV_PRU_ICSSG1_SERDES1_RXCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN1_RXCLK | CLK_STATE_READY | 0 | | 120 | 40 | DEV_PRU_ICSSG1_SERDES1_TXFCLK | CLK_STATE_READY | 0 | | 120 | 41 | DEV_PRU_ICSSG1_SERDES1_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN1_TXFCLK | CLK_STATE_READY | 0 | | 120 | 42 | DEV_PRU_ICSSG1_SERDES1_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN1_TXFCLK | CLK_STATE_READY | 0 | | 120 | 43 | DEV_PRU_ICSSG1_SERDES1_TXMCLK | CLK_STATE_READY | 0 | | 120 | 44 | DEV_PRU_ICSSG1_SERDES1_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN1_TXMCLK | CLK_STATE_READY | 0 | | 120 | 45 | DEV_PRU_ICSSG1_SERDES1_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN1_TXMCLK | CLK_STATE_READY | 0 | | 120 | 46 | DEV_PRU_ICSSG1_SERDES0_TXFCLK | CLK_STATE_READY | 0 | | 120 | 47 | DEV_PRU_ICSSG1_SERDES0_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN0_TXFCLK | CLK_STATE_READY | 0 | | 120 | 48 | DEV_PRU_ICSSG1_SERDES0_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN0_TXFCLK | CLK_STATE_READY | 0 | | 120 | 49 | DEV_PRU_ICSSG1_UCLK_CLK | CLK_STATE_READY | 192000000 | | 120 | 50 | DEV_PRU_ICSSG1_PR1_RGMII0_TXC_I | CLK_STATE_READY | 0 | | 120 | 51 | DEV_PRU_ICSSG1_SERDES1_REFCLK | CLK_STATE_READY | 0 | | 120 | 52 | DEV_PRU_ICSSG1_SERDES1_REFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN1_REFCLK | CLK_STATE_READY | 0 | | 120 | 53 | DEV_PRU_ICSSG1_SERDES1_REFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN1_REFCLK | CLK_STATE_READY | 0 | | 120 | 54 | DEV_PRU_ICSSG1_CORE_CLK | CLK_STATE_READY | 225000000 | | 120 | 55 | DEV_PRU_ICSSG1_CORE_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK | CLK_STATE_READY | 225000000 | | 120 | 56 | DEV_PRU_ICSSG1_CORE_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK | CLK_STATE_READY | 200000000 | | 120 | 57 | DEV_PRU_ICSSG1_RGMII_MHZ_250_CLK | CLK_STATE_READY | 250000000 | | 120 | 58 | DEV_PRU_ICSSG1_RGMII_MHZ_50_CLK | CLK_STATE_READY | 50000000 | | 120 | 59 | DEV_PRU_ICSSG1_PR1_RGMII1_TXC_O | CLK_STATE_READY | 0 | | 120 | 60 | DEV_PRU_ICSSG1_PR1_MDIO_MDCLK_O | CLK_STATE_READY | 0 | | 120 | 61 | DEV_PRU_ICSSG1_PR1_RGMII0_TXC_O | CLK_STATE_READY | 0 | | 120 | 62 | DEV_PRU_ICSSG1_SERDES0_TXCLK | CLK_STATE_READY | 0 | | 120 | 63 | DEV_PRU_ICSSG1_SERDES1_TXCLK | CLK_STATE_READY | 0 | | 133 | 0 | DEV_PSC0_SLOW_CLK | CLK_STATE_READY | 20833333 | | 133 | 1 | DEV_PSC0_CLK | CLK_STATE_READY | 125000000 | | 245 | 0 | DEV_R5FSS0_CORE0_CPU_CLK | CLK_STATE_READY | 1000000000 | | 245 | 1 | DEV_R5FSS0_CORE0_INTERFACE_CLK | CLK_STATE_READY | 1000000000 | | 245 | 2 | DEV_R5FSS0_CORE0_INTERFACE_PHASE | CLK_STATE_READY | 1000000000 | | 246 | 0 | DEV_R5FSS0_CORE1_CPU_CLK | CLK_STATE_READY | 1000000000 | | 246 | 1 | DEV_R5FSS0_CORE1_INTERFACE_CLK | CLK_STATE_READY | 1000000000 | | 246 | 2 | DEV_R5FSS0_CORE1_INTERFACE_PHASE | CLK_STATE_READY | 1000000000 | | 134 | 0 | DEV_R5FSS0_INTROUTER0_INTR_CLK | CLK_STATE_READY | 125000000 | | 247 | 0 | DEV_R5FSS1_CORE0_CPU_CLK | CLK_STATE_READY | 1000000000 | | 247 | 1 | DEV_R5FSS1_CORE0_INTERFACE_CLK | CLK_STATE_READY | 1000000000 | | 247 | 2 | DEV_R5FSS1_CORE0_INTERFACE_PHASE | CLK_STATE_READY | 1000000000 | | 248 | 0 | DEV_R5FSS1_CORE1_CPU_CLK | CLK_STATE_READY | 1000000000 | | 248 | 1 | DEV_R5FSS1_CORE1_INTERFACE_CLK | CLK_STATE_READY | 1000000000 | | 248 | 2 | DEV_R5FSS1_CORE1_INTERFACE_PHASE | CLK_STATE_READY | 1000000000 | | 135 | 0 | DEV_R5FSS1_INTROUTER0_INTR_CLK | CLK_STATE_READY | 125000000 | | 252 | 0 | DEV_RTI0_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 252 | 1 | DEV_RTI0_RTI_CLK | CLK_STATE_READY | 19200000 | | 252 | 2 | DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 252 | 3 | DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 252 | 4 | DEV_RTI0_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 252 | 5 | DEV_RTI0_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32000 | | 252 | 6 | DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 252 | 7 | DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0 | CLK_STATE_READY | 0 | | 252 | 8 | DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1 | CLK_STATE_READY | 0 | | 252 | 9 | DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2 | CLK_STATE_READY | 0 | | 253 | 0 | DEV_RTI1_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 253 | 1 | DEV_RTI1_RTI_CLK | CLK_STATE_READY | 19200000 | | 253 | 2 | DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 253 | 3 | DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 253 | 4 | DEV_RTI1_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 253 | 5 | DEV_RTI1_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32000 | | 253 | 6 | DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 253 | 7 | DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0 | CLK_STATE_READY | 0 | | 253 | 8 | DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1 | CLK_STATE_READY | 0 | | 253 | 9 | DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2 | CLK_STATE_READY | 0 | | 257 | 0 | DEV_RTI15_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 257 | 1 | DEV_RTI15_RTI_CLK | CLK_STATE_READY | 19200000 | | 257 | 2 | DEV_RTI15_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 257 | 3 | DEV_RTI15_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 257 | 4 | DEV_RTI15_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 257 | 5 | DEV_RTI15_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32000 | | 257 | 6 | DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 257 | 7 | DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0 | CLK_STATE_READY | 0 | | 257 | 8 | DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1 | CLK_STATE_READY | 0 | | 257 | 9 | DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2 | CLK_STATE_READY | 0 | | 256 | 0 | DEV_RTI16_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 256 | 1 | DEV_RTI16_RTI_CLK | CLK_STATE_READY | 19200000 | | 256 | 2 | DEV_RTI16_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 256 | 3 | DEV_RTI16_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 256 | 4 | DEV_RTI16_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 256 | 5 | DEV_RTI16_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32000 | | 256 | 6 | DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 256 | 7 | DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0 | CLK_STATE_READY | 0 | | 256 | 8 | DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1 | CLK_STATE_READY | 0 | | 256 | 9 | DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2 | CLK_STATE_READY | 0 | | 254 | 0 | DEV_RTI24_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 254 | 1 | DEV_RTI24_RTI_CLK | CLK_STATE_READY | 19200000 | | 254 | 2 | DEV_RTI24_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 254 | 3 | DEV_RTI24_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 254 | 4 | DEV_RTI24_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 254 | 5 | DEV_RTI24_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32000 | | 254 | 6 | DEV_RTI24_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 254 | 7 | DEV_RTI24_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0 | CLK_STATE_READY | 0 | | 254 | 8 | DEV_RTI24_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1 | CLK_STATE_READY | 0 | | 254 | 9 | DEV_RTI24_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2 | CLK_STATE_READY | 0 | | 255 | 0 | DEV_RTI25_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 255 | 1 | DEV_RTI25_RTI_CLK | CLK_STATE_READY | 19200000 | | 255 | 2 | DEV_RTI25_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 255 | 3 | DEV_RTI25_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 255 | 4 | DEV_RTI25_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 255 | 5 | DEV_RTI25_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32000 | | 255 | 6 | DEV_RTI25_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 255 | 7 | DEV_RTI25_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0 | CLK_STATE_READY | 0 | | 255 | 8 | DEV_RTI25_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1 | CLK_STATE_READY | 0 | | 255 | 9 | DEV_RTI25_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2 | CLK_STATE_READY | 0 | | 258 | 0 | DEV_RTI28_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 258 | 1 | DEV_RTI28_RTI_CLK | CLK_STATE_READY | 19200000 | | 258 | 2 | DEV_RTI28_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 258 | 3 | DEV_RTI28_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 258 | 4 | DEV_RTI28_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 258 | 5 | DEV_RTI28_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32000 | | 258 | 6 | DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 258 | 7 | DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0 | CLK_STATE_READY | 0 | | 258 | 8 | DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1 | CLK_STATE_READY | 0 | | 258 | 9 | DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2 | CLK_STATE_READY | 0 | | 259 | 0 | DEV_RTI29_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 259 | 1 | DEV_RTI29_RTI_CLK | CLK_STATE_READY | 19200000 | | 259 | 2 | DEV_RTI29_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 259 | 3 | DEV_RTI29_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 259 | 4 | DEV_RTI29_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 259 | 5 | DEV_RTI29_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32000 | | 259 | 6 | DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 259 | 7 | DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0 | CLK_STATE_READY | 0 | | 259 | 8 | DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1 | CLK_STATE_READY | 0 | | 259 | 9 | DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2 | CLK_STATE_READY | 0 | | 260 | 0 | DEV_RTI30_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 260 | 1 | DEV_RTI30_RTI_CLK | CLK_STATE_READY | 19200000 | | 260 | 2 | DEV_RTI30_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 260 | 3 | DEV_RTI30_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 260 | 4 | DEV_RTI30_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 260 | 5 | DEV_RTI30_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32000 | | 260 | 6 | DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 260 | 7 | DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0 | CLK_STATE_READY | 0 | | 260 | 8 | DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1 | CLK_STATE_READY | 0 | | 260 | 9 | DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2 | CLK_STATE_READY | 0 | | 261 | 0 | DEV_RTI31_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 261 | 1 | DEV_RTI31_RTI_CLK | CLK_STATE_READY | 19200000 | | 261 | 2 | DEV_RTI31_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 261 | 3 | DEV_RTI31_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 261 | 4 | DEV_RTI31_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 261 | 5 | DEV_RTI31_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | CLK_STATE_READY | 32000 | | 261 | 6 | DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 261 | 7 | DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0 | CLK_STATE_READY | 0 | | 261 | 8 | DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1 | CLK_STATE_READY | 0 | | 261 | 9 | DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2 | CLK_STATE_READY | 0 | | 264 | 0 | DEV_SA2_UL0_X2_CLK | CLK_STATE_READY | 250000000 | | 264 | 1 | DEV_SA2_UL0_PKA_IN_CLK | CLK_STATE_READY | 450000000 | | 264 | 2 | DEV_SA2_UL0_X1_CLK | CLK_STATE_READY | 125000000 | | 297 | 0 | DEV_SERDES_10G0_IP1_LN3_TXCLK | CLK_STATE_READY | 0 | | 297 | 1 | DEV_SERDES_10G0_CLK | CLK_STATE_READY | 125000000 | | 297 | 2 | DEV_SERDES_10G0_IP3_LN2_TXCLK | CLK_STATE_READY | 0 | | 297 | 3 | DEV_SERDES_10G0_IP1_LN2_TXCLK | CLK_STATE_READY | 0 | | 297 | 4 | DEV_SERDES_10G0_IP1_LN0_TXCLK | CLK_STATE_READY | 0 | | 297 | 5 | DEV_SERDES_10G0_IP3_LN1_TXCLK | CLK_STATE_READY | 0 | | 297 | 6 | DEV_SERDES_10G0_IP3_LN3_TXCLK | CLK_STATE_READY | 0 | | 297 | 7 | DEV_SERDES_10G0_IP3_LN0_TXCLK | CLK_STATE_READY | 0 | | 297 | 8 | DEV_SERDES_10G0_IP1_LN1_TXCLK | CLK_STATE_READY | 0 | | 297 | 9 | DEV_SERDES_10G0_CORE_REF_CLK | CLK_STATE_READY | 19200000 | | 297 | 10 | DEV_SERDES_10G0_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 297 | 11 | DEV_SERDES_10G0_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 297 | 12 | DEV_SERDES_10G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK | CLK_STATE_READY | 153846153 | | 297 | 13 | DEV_SERDES_10G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK | CLK_STATE_READY | 100000000 | | 297 | 14 | DEV_SERDES_10G0_IP1_LN1_REFCLK | CLK_STATE_READY | 0 | | 297 | 15 | DEV_SERDES_10G0_IP1_LN2_RXCLK | CLK_STATE_READY | 0 | | 297 | 16 | DEV_SERDES_10G0_IP3_LN1_TXFCLK | CLK_STATE_READY | 0 | | 297 | 17 | DEV_SERDES_10G0_IP1_LN0_RXFCLK | CLK_STATE_READY | 0 | | 297 | 18 | DEV_SERDES_10G0_IP1_LN3_RXCLK | CLK_STATE_READY | 0 | | 297 | 19 | DEV_SERDES_10G0_IP3_LN3_RXCLK | CLK_STATE_READY | 0 | | 297 | 20 | DEV_SERDES_10G0_IP3_LN1_TXMCLK | CLK_STATE_READY | 0 | | 297 | 21 | DEV_SERDES_10G0_IP3_LN3_RXFCLK | CLK_STATE_READY | 0 | | 297 | 22 | DEV_SERDES_10G0_IP3_LN3_REFCLK | CLK_STATE_READY | 0 | | 297 | 23 | DEV_SERDES_10G0_IP3_LN2_RXCLK | CLK_STATE_READY | 0 | | 297 | 24 | DEV_SERDES_10G0_IP1_LN0_TXFCLK | CLK_STATE_READY | 0 | | 297 | 25 | DEV_SERDES_10G0_IP3_LN3_TXMCLK | CLK_STATE_READY | 0 | | 297 | 26 | DEV_SERDES_10G0_IP3_LN1_RXFCLK | CLK_STATE_READY | 0 | | 297 | 27 | DEV_SERDES_10G0_IP3_LN0_RXFCLK | CLK_STATE_READY | 0 | | 297 | 28 | DEV_SERDES_10G0_IP1_LN1_TXMCLK | CLK_STATE_READY | 0 | | 297 | 29 | DEV_SERDES_10G0_IP1_LN1_RXFCLK | CLK_STATE_READY | 0 | | 297 | 30 | DEV_SERDES_10G0_IP3_LN3_TXFCLK | CLK_STATE_READY | 0 | | 297 | 31 | DEV_SERDES_10G0_IP1_LN3_TXFCLK | CLK_STATE_READY | 0 | | 297 | 32 | DEV_SERDES_10G0_IP1_LN3_TXMCLK | CLK_STATE_READY | 0 | | 297 | 33 | DEV_SERDES_10G0_IP3_LN1_REFCLK | CLK_STATE_READY | 0 | | 297 | 34 | DEV_SERDES_10G0_IP3_LN0_REFCLK | CLK_STATE_READY | 0 | | 297 | 35 | DEV_SERDES_10G0_IP1_LN3_REFCLK | CLK_STATE_READY | 0 | | 297 | 36 | DEV_SERDES_10G0_IP3_LN0_RXCLK | CLK_STATE_READY | 0 | | 297 | 37 | DEV_SERDES_10G0_IP3_LN2_REFCLK | CLK_STATE_READY | 0 | | 297 | 38 | DEV_SERDES_10G0_IP1_LN0_RXCLK | CLK_STATE_READY | 0 | | 297 | 39 | DEV_SERDES_10G0_IP1_LN0_REFCLK | CLK_STATE_READY | 0 | | 297 | 40 | DEV_SERDES_10G0_IP1_LN2_RXFCLK | CLK_STATE_READY | 0 | | 297 | 41 | DEV_SERDES_10G0_IP1_LN1_TXFCLK | CLK_STATE_READY | 0 | | 297 | 42 | DEV_SERDES_10G0_IP3_LN0_TXFCLK | CLK_STATE_READY | 0 | | 297 | 43 | DEV_SERDES_10G0_REF_OUT_CLK | CLK_STATE_READY | 0 | | 297 | 44 | DEV_SERDES_10G0_IP3_LN1_RXCLK | CLK_STATE_READY | 0 | | 297 | 45 | DEV_SERDES_10G0_IP1_LN2_TXFCLK | CLK_STATE_READY | 0 | | 297 | 46 | DEV_SERDES_10G0_IP1_LN0_TXMCLK | CLK_STATE_READY | 0 | | 297 | 47 | DEV_SERDES_10G0_IP3_LN2_RXFCLK | CLK_STATE_READY | 0 | | 297 | 48 | DEV_SERDES_10G0_IP1_LN2_TXMCLK | CLK_STATE_READY | 0 | | 297 | 49 | DEV_SERDES_10G0_IP3_LN2_TXMCLK | CLK_STATE_READY | 0 | | 297 | 50 | DEV_SERDES_10G0_IP1_LN2_REFCLK | CLK_STATE_READY | 0 | | 297 | 51 | DEV_SERDES_10G0_IP3_LN2_TXFCLK | CLK_STATE_READY | 0 | | 297 | 52 | DEV_SERDES_10G0_IP3_LN0_TXMCLK | CLK_STATE_READY | 0 | | 297 | 53 | DEV_SERDES_10G0_IP1_LN3_RXFCLK | CLK_STATE_READY | 0 | | 297 | 54 | DEV_SERDES_10G0_IP1_LN1_RXCLK | CLK_STATE_READY | 0 | | 292 | 0 | DEV_SERDES_16G0_CORE_REF1_CLK | CLK_STATE_READY | 19200000 | | 292 | 1 | DEV_SERDES_16G0_CORE_REF1_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 292 | 2 | DEV_SERDES_16G0_CORE_REF1_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 292 | 3 | DEV_SERDES_16G0_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK | CLK_STATE_READY | 153846153 | | 292 | 4 | DEV_SERDES_16G0_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK | CLK_STATE_READY | 100000000 | | 292 | 5 | DEV_SERDES_16G0_CLK | CLK_STATE_READY | 125000000 | | 292 | 6 | DEV_SERDES_16G0_IP1_LN0_TXCLK | CLK_STATE_READY | 0 | | 292 | 7 | DEV_SERDES_16G0_IP2_LN1_TXCLK | CLK_STATE_READY | 0 | | 292 | 8 | DEV_SERDES_16G0_IP3_LN1_TXCLK | CLK_STATE_READY | 0 | | 292 | 9 | DEV_SERDES_16G0_IP2_LN0_TXCLK | CLK_STATE_READY | 0 | | 292 | 10 | DEV_SERDES_16G0_IP1_LN1_TXCLK | CLK_STATE_READY | 0 | | 292 | 11 | DEV_SERDES_16G0_CORE_REF_CLK | CLK_STATE_READY | 19200000 | | 292 | 12 | DEV_SERDES_16G0_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 292 | 13 | DEV_SERDES_16G0_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 292 | 14 | DEV_SERDES_16G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK | CLK_STATE_READY | 153846153 | | 292 | 15 | DEV_SERDES_16G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK | CLK_STATE_READY | 100000000 | | 292 | 16 | DEV_SERDES_16G0_IP2_LN0_TXFCLK | CLK_STATE_READY | 0 | | 292 | 17 | DEV_SERDES_16G0_IP1_LN1_REFCLK | CLK_STATE_READY | 0 | | 292 | 18 | DEV_SERDES_16G0_IP3_LN1_TXMCLK | CLK_STATE_READY | 0 | | 292 | 19 | DEV_SERDES_16G0_IP3_LN1_TXFCLK | CLK_STATE_READY | 0 | | 292 | 20 | DEV_SERDES_16G0_IP1_LN0_RXFCLK | CLK_STATE_READY | 0 | | 292 | 21 | DEV_SERDES_16G0_IP2_LN1_REFCLK | CLK_STATE_READY | 0 | | 292 | 22 | DEV_SERDES_16G0_IP2_LN1_TXFCLK | CLK_STATE_READY | 0 | | 292 | 23 | DEV_SERDES_16G0_REF_DER_OUT_CLK | CLK_STATE_READY | 0 | | 292 | 24 | DEV_SERDES_16G0_IP1_LN0_TXFCLK | CLK_STATE_READY | 0 | | 292 | 25 | DEV_SERDES_16G0_IP3_LN1_RXFCLK | CLK_STATE_READY | 0 | | 292 | 26 | DEV_SERDES_16G0_IP1_LN1_TXMCLK | CLK_STATE_READY | 0 | | 292 | 27 | DEV_SERDES_16G0_IP1_LN1_RXFCLK | CLK_STATE_READY | 0 | | 292 | 28 | DEV_SERDES_16G0_IP3_LN1_RXCLK | CLK_STATE_READY | 0 | | 292 | 29 | DEV_SERDES_16G0_IP3_LN1_REFCLK | CLK_STATE_READY | 0 | | 292 | 30 | DEV_SERDES_16G0_IP2_LN1_RXCLK | CLK_STATE_READY | 0 | | 292 | 31 | DEV_SERDES_16G0_IP2_LN0_RXFCLK | CLK_STATE_READY | 0 | | 292 | 32 | DEV_SERDES_16G0_IP1_LN0_RXCLK | CLK_STATE_READY | 0 | | 292 | 33 | DEV_SERDES_16G0_REF_OUT_CLK | CLK_STATE_READY | 0 | | 292 | 34 | DEV_SERDES_16G0_REF1_OUT_CLK | CLK_STATE_READY | 0 | | 292 | 35 | DEV_SERDES_16G0_IP1_LN0_REFCLK | CLK_STATE_READY | 0 | | 292 | 36 | DEV_SERDES_16G0_IP1_LN0_TXMCLK | CLK_STATE_READY | 0 | | 292 | 37 | DEV_SERDES_16G0_IP2_LN1_RXFCLK | CLK_STATE_READY | 0 | | 292 | 38 | DEV_SERDES_16G0_IP2_LN1_TXMCLK | CLK_STATE_READY | 0 | | 292 | 39 | DEV_SERDES_16G0_IP2_LN0_REFCLK | CLK_STATE_READY | 0 | | 292 | 40 | DEV_SERDES_16G0_IP2_LN0_TXMCLK | CLK_STATE_READY | 0 | | 292 | 41 | DEV_SERDES_16G0_IP1_LN1_TXFCLK | CLK_STATE_READY | 0 | | 292 | 42 | DEV_SERDES_16G0_IP2_LN0_RXCLK | CLK_STATE_READY | 0 | | 292 | 43 | DEV_SERDES_16G0_IP1_LN1_RXCLK | CLK_STATE_READY | 0 | | 292 | 49 | DEV_SERDES_16G0_CMN_REFCLK1_M | CLK_STATE_READY | 0 | | 292 | 57 | DEV_SERDES_16G0_CMN_REFCLK1_P | CLK_STATE_READY | 0 | | 293 | 0 | DEV_SERDES_16G1_CORE_REF1_CLK | CLK_STATE_READY | 100000000 | | 293 | 1 | DEV_SERDES_16G1_CORE_REF1_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 293 | 2 | DEV_SERDES_16G1_CORE_REF1_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 293 | 3 | DEV_SERDES_16G1_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK | CLK_STATE_READY | 153846153 | | 293 | 4 | DEV_SERDES_16G1_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK | CLK_STATE_READY | 100000000 | | 293 | 5 | DEV_SERDES_16G1_CLK | CLK_STATE_READY | 125000000 | | 293 | 6 | DEV_SERDES_16G1_IP1_LN0_TXCLK | CLK_STATE_READY | 0 | | 293 | 7 | DEV_SERDES_16G1_IP2_LN1_TXCLK | CLK_STATE_READY | 0 | | 293 | 8 | DEV_SERDES_16G1_IP4_LN1_TXCLK | CLK_STATE_READY | 0 | | 293 | 9 | DEV_SERDES_16G1_IP4_LN0_TXCLK | CLK_STATE_READY | 0 | | 293 | 10 | DEV_SERDES_16G1_IP3_LN1_TXCLK | CLK_STATE_READY | 0 | | 293 | 11 | DEV_SERDES_16G1_IP2_LN0_TXCLK | CLK_STATE_READY | 0 | | 293 | 12 | DEV_SERDES_16G1_IP1_LN1_TXCLK | CLK_STATE_READY | 0 | | 293 | 13 | DEV_SERDES_16G1_CORE_REF_CLK | CLK_STATE_READY | 100000000 | | 293 | 14 | DEV_SERDES_16G1_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 293 | 15 | DEV_SERDES_16G1_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 293 | 16 | DEV_SERDES_16G1_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK | CLK_STATE_READY | 153846153 | | 293 | 17 | DEV_SERDES_16G1_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK | CLK_STATE_READY | 100000000 | | 293 | 18 | DEV_SERDES_16G1_IP2_LN0_TXFCLK | CLK_STATE_READY | 0 | | 293 | 19 | DEV_SERDES_16G1_IP1_LN1_REFCLK | CLK_STATE_READY | 0 | | 293 | 20 | DEV_SERDES_16G1_IP4_LN1_RXFCLK | CLK_STATE_READY | 0 | | 293 | 21 | DEV_SERDES_16G1_IP3_LN1_TXMCLK | CLK_STATE_READY | 0 | | 293 | 22 | DEV_SERDES_16G1_IP3_LN1_TXFCLK | CLK_STATE_READY | 0 | | 293 | 23 | DEV_SERDES_16G1_IP1_LN0_RXFCLK | CLK_STATE_READY | 0 | | 293 | 24 | DEV_SERDES_16G1_IP2_LN1_REFCLK | CLK_STATE_READY | 0 | | 293 | 25 | DEV_SERDES_16G1_IP2_LN1_TXFCLK | CLK_STATE_READY | 0 | | 293 | 26 | DEV_SERDES_16G1_REF_DER_OUT_CLK | CLK_STATE_READY | 0 | | 293 | 27 | DEV_SERDES_16G1_IP1_LN0_TXFCLK | CLK_STATE_READY | 0 | | 293 | 28 | DEV_SERDES_16G1_IP3_LN1_RXFCLK | CLK_STATE_READY | 0 | | 293 | 29 | DEV_SERDES_16G1_IP1_LN1_TXMCLK | CLK_STATE_READY | 0 | | 293 | 30 | DEV_SERDES_16G1_IP1_LN1_RXFCLK | CLK_STATE_READY | 0 | | 293 | 31 | DEV_SERDES_16G1_IP4_LN1_REFCLK | CLK_STATE_READY | 0 | | 293 | 32 | DEV_SERDES_16G1_IP3_LN1_RXCLK | CLK_STATE_READY | 0 | | 293 | 33 | DEV_SERDES_16G1_IP4_LN1_TXMCLK | CLK_STATE_READY | 0 | | 293 | 34 | DEV_SERDES_16G1_IP3_LN1_REFCLK | CLK_STATE_READY | 0 | | 293 | 35 | DEV_SERDES_16G1_IP4_LN0_REFCLK | CLK_STATE_READY | 0 | | 293 | 36 | DEV_SERDES_16G1_IP2_LN1_RXCLK | CLK_STATE_READY | 0 | | 293 | 37 | DEV_SERDES_16G1_IP2_LN0_RXFCLK | CLK_STATE_READY | 0 | | 293 | 38 | DEV_SERDES_16G1_IP1_LN0_RXCLK | CLK_STATE_READY | 0 | | 293 | 39 | DEV_SERDES_16G1_REF_OUT_CLK | CLK_STATE_READY | 0 | | 293 | 40 | DEV_SERDES_16G1_REF1_OUT_CLK | CLK_STATE_READY | 0 | | 293 | 41 | DEV_SERDES_16G1_IP4_LN1_RXCLK | CLK_STATE_READY | 0 | | 293 | 42 | DEV_SERDES_16G1_IP1_LN0_REFCLK | CLK_STATE_READY | 0 | | 293 | 43 | DEV_SERDES_16G1_IP1_LN0_TXMCLK | CLK_STATE_READY | 0 | | 293 | 44 | DEV_SERDES_16G1_IP4_LN0_TXFCLK | CLK_STATE_READY | 0 | | 293 | 45 | DEV_SERDES_16G1_IP4_LN0_RXCLK | CLK_STATE_READY | 0 | | 293 | 46 | DEV_SERDES_16G1_IP2_LN1_RXFCLK | CLK_STATE_READY | 0 | | 293 | 47 | DEV_SERDES_16G1_IP2_LN1_TXMCLK | CLK_STATE_READY | 0 | | 293 | 48 | DEV_SERDES_16G1_IP4_LN0_RXFCLK | CLK_STATE_READY | 0 | | 293 | 49 | DEV_SERDES_16G1_IP2_LN0_REFCLK | CLK_STATE_READY | 0 | | 293 | 50 | DEV_SERDES_16G1_IP2_LN0_TXMCLK | CLK_STATE_READY | 0 | | 293 | 51 | DEV_SERDES_16G1_IP1_LN1_TXFCLK | CLK_STATE_READY | 0 | | 293 | 52 | DEV_SERDES_16G1_IP2_LN0_RXCLK | CLK_STATE_READY | 0 | | 293 | 53 | DEV_SERDES_16G1_IP4_LN0_TXMCLK | CLK_STATE_READY | 0 | | 293 | 54 | DEV_SERDES_16G1_IP1_LN1_RXCLK | CLK_STATE_READY | 0 | | 293 | 55 | DEV_SERDES_16G1_IP4_LN1_TXFCLK | CLK_STATE_READY | 0 | | 293 | 60 | DEV_SERDES_16G1_CMN_REFCLK1_M | CLK_STATE_READY | 0 | | 293 | 67 | DEV_SERDES_16G1_CMN_REFCLK1_P | CLK_STATE_READY | 0 | | 294 | 0 | DEV_SERDES_16G2_CORE_REF1_CLK | CLK_STATE_READY | 100000000 | | 294 | 1 | DEV_SERDES_16G2_CORE_REF1_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 294 | 2 | DEV_SERDES_16G2_CORE_REF1_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 294 | 3 | DEV_SERDES_16G2_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK | CLK_STATE_READY | 153846153 | | 294 | 4 | DEV_SERDES_16G2_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK | CLK_STATE_READY | 100000000 | | 294 | 5 | DEV_SERDES_16G2_CLK | CLK_STATE_READY | 125000000 | | 294 | 6 | DEV_SERDES_16G2_IP2_LN1_TXCLK | CLK_STATE_READY | 0 | | 294 | 7 | DEV_SERDES_16G2_IP4_LN1_TXCLK | CLK_STATE_READY | 0 | | 294 | 8 | DEV_SERDES_16G2_IP4_LN0_TXCLK | CLK_STATE_READY | 0 | | 294 | 9 | DEV_SERDES_16G2_IP3_LN1_TXCLK | CLK_STATE_READY | 0 | | 294 | 10 | DEV_SERDES_16G2_IP2_LN0_TXCLK | CLK_STATE_READY | 0 | | 294 | 11 | DEV_SERDES_16G2_CORE_REF_CLK | CLK_STATE_READY | 100000000 | | 294 | 12 | DEV_SERDES_16G2_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 294 | 13 | DEV_SERDES_16G2_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 294 | 14 | DEV_SERDES_16G2_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK | CLK_STATE_READY | 153846153 | | 294 | 15 | DEV_SERDES_16G2_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK | CLK_STATE_READY | 100000000 | | 294 | 16 | DEV_SERDES_16G2_IP2_LN0_TXFCLK | CLK_STATE_READY | 0 | | 294 | 17 | DEV_SERDES_16G2_IP4_LN1_RXFCLK | CLK_STATE_READY | 0 | | 294 | 18 | DEV_SERDES_16G2_IP3_LN1_TXMCLK | CLK_STATE_READY | 0 | | 294 | 19 | DEV_SERDES_16G2_IP3_LN1_TXFCLK | CLK_STATE_READY | 0 | | 294 | 20 | DEV_SERDES_16G2_IP2_LN1_REFCLK | CLK_STATE_READY | 0 | | 294 | 21 | DEV_SERDES_16G2_IP2_LN1_TXFCLK | CLK_STATE_READY | 0 | | 294 | 22 | DEV_SERDES_16G2_REF_DER_OUT_CLK | CLK_STATE_READY | 0 | | 294 | 23 | DEV_SERDES_16G2_IP3_LN1_RXFCLK | CLK_STATE_READY | 0 | | 294 | 24 | DEV_SERDES_16G2_IP4_LN1_REFCLK | CLK_STATE_READY | 0 | | 294 | 25 | DEV_SERDES_16G2_IP3_LN1_RXCLK | CLK_STATE_READY | 0 | | 294 | 26 | DEV_SERDES_16G2_IP4_LN1_TXMCLK | CLK_STATE_READY | 0 | | 294 | 27 | DEV_SERDES_16G2_IP3_LN1_REFCLK | CLK_STATE_READY | 0 | | 294 | 28 | DEV_SERDES_16G2_IP4_LN0_REFCLK | CLK_STATE_READY | 0 | | 294 | 29 | DEV_SERDES_16G2_IP2_LN1_RXCLK | CLK_STATE_READY | 0 | | 294 | 30 | DEV_SERDES_16G2_IP2_LN0_RXFCLK | CLK_STATE_READY | 0 | | 294 | 31 | DEV_SERDES_16G2_REF_OUT_CLK | CLK_STATE_READY | 0 | | 294 | 32 | DEV_SERDES_16G2_REF1_OUT_CLK | CLK_STATE_READY | 0 | | 294 | 33 | DEV_SERDES_16G2_IP4_LN1_RXCLK | CLK_STATE_READY | 0 | | 294 | 34 | DEV_SERDES_16G2_IP4_LN0_TXFCLK | CLK_STATE_READY | 0 | | 294 | 35 | DEV_SERDES_16G2_IP4_LN0_RXCLK | CLK_STATE_READY | 0 | | 294 | 36 | DEV_SERDES_16G2_IP2_LN1_RXFCLK | CLK_STATE_READY | 0 | | 294 | 37 | DEV_SERDES_16G2_IP2_LN1_TXMCLK | CLK_STATE_READY | 0 | | 294 | 38 | DEV_SERDES_16G2_IP4_LN0_RXFCLK | CLK_STATE_READY | 0 | | 294 | 39 | DEV_SERDES_16G2_IP2_LN0_REFCLK | CLK_STATE_READY | 0 | | 294 | 40 | DEV_SERDES_16G2_IP2_LN0_TXMCLK | CLK_STATE_READY | 0 | | 294 | 41 | DEV_SERDES_16G2_IP2_LN0_RXCLK | CLK_STATE_READY | 0 | | 294 | 42 | DEV_SERDES_16G2_IP4_LN0_TXMCLK | CLK_STATE_READY | 0 | | 294 | 43 | DEV_SERDES_16G2_IP4_LN1_TXFCLK | CLK_STATE_READY | 0 | | 294 | 51 | DEV_SERDES_16G2_CMN_REFCLK1_M | CLK_STATE_READY | 0 | | 294 | 61 | DEV_SERDES_16G2_CMN_REFCLK1_P | CLK_STATE_READY | 0 | | 295 | 0 | DEV_SERDES_16G3_CORE_REF1_CLK | CLK_STATE_READY | 100000000 | | 295 | 1 | DEV_SERDES_16G3_CORE_REF1_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 295 | 2 | DEV_SERDES_16G3_CORE_REF1_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 295 | 3 | DEV_SERDES_16G3_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK | CLK_STATE_READY | 153846153 | | 295 | 4 | DEV_SERDES_16G3_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK | CLK_STATE_READY | 100000000 | | 295 | 5 | DEV_SERDES_16G3_CLK | CLK_STATE_READY | 125000000 | | 295 | 6 | DEV_SERDES_16G3_IP2_LN1_TXCLK | CLK_STATE_READY | 0 | | 295 | 7 | DEV_SERDES_16G3_IP3_LN1_TXCLK | CLK_STATE_READY | 0 | | 295 | 8 | DEV_SERDES_16G3_IP2_LN0_TXCLK | CLK_STATE_READY | 0 | | 295 | 9 | DEV_SERDES_16G3_CORE_REF_CLK | CLK_STATE_READY | 100000000 | | 295 | 10 | DEV_SERDES_16G3_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 295 | 11 | DEV_SERDES_16G3_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 295 | 12 | DEV_SERDES_16G3_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK | CLK_STATE_READY | 153846153 | | 295 | 13 | DEV_SERDES_16G3_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK | CLK_STATE_READY | 100000000 | | 295 | 14 | DEV_SERDES_16G3_IP2_LN0_TXFCLK | CLK_STATE_READY | 0 | | 295 | 15 | DEV_SERDES_16G3_IP3_LN1_TXMCLK | CLK_STATE_READY | 0 | | 295 | 16 | DEV_SERDES_16G3_IP3_LN1_TXFCLK | CLK_STATE_READY | 0 | | 295 | 17 | DEV_SERDES_16G3_IP2_LN1_REFCLK | CLK_STATE_READY | 0 | | 295 | 18 | DEV_SERDES_16G3_IP2_LN1_TXFCLK | CLK_STATE_READY | 0 | | 295 | 19 | DEV_SERDES_16G3_REF_DER_OUT_CLK | CLK_STATE_READY | 0 | | 295 | 20 | DEV_SERDES_16G3_IP3_LN1_RXFCLK | CLK_STATE_READY | 0 | | 295 | 21 | DEV_SERDES_16G3_IP3_LN1_RXCLK | CLK_STATE_READY | 0 | | 295 | 22 | DEV_SERDES_16G3_IP3_LN1_REFCLK | CLK_STATE_READY | 0 | | 295 | 23 | DEV_SERDES_16G3_IP2_LN1_RXCLK | CLK_STATE_READY | 0 | | 295 | 24 | DEV_SERDES_16G3_IP2_LN0_RXFCLK | CLK_STATE_READY | 0 | | 295 | 25 | DEV_SERDES_16G3_REF_OUT_CLK | CLK_STATE_READY | 0 | | 295 | 26 | DEV_SERDES_16G3_REF1_OUT_CLK | CLK_STATE_READY | 0 | | 295 | 27 | DEV_SERDES_16G3_IP2_LN1_RXFCLK | CLK_STATE_READY | 0 | | 295 | 28 | DEV_SERDES_16G3_IP2_LN1_TXMCLK | CLK_STATE_READY | 0 | | 295 | 29 | DEV_SERDES_16G3_IP2_LN0_REFCLK | CLK_STATE_READY | 0 | | 295 | 30 | DEV_SERDES_16G3_IP2_LN0_TXMCLK | CLK_STATE_READY | 0 | | 295 | 31 | DEV_SERDES_16G3_IP2_LN0_RXCLK | CLK_STATE_READY | 0 | | 295 | 40 | DEV_SERDES_16G3_CMN_REFCLK1_M | CLK_STATE_READY | 0 | | 295 | 51 | DEV_SERDES_16G3_CMN_REFCLK1_P | CLK_STATE_READY | 0 | | 29 | 0 | DEV_STM0_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 29 | 1 | DEV_STM0_CORE_CLK | CLK_STATE_READY | 250000000 | | 29 | 2 | DEV_STM0_ATB_CLK | CLK_STATE_READY | 250000000 | | 49 | 0 | DEV_TIMER0_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | 49 | 1 | DEV_TIMER0_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | 49 | 2 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 49 | 3 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 49 | 4 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 250000000 | | 49 | 5 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 49 | 6 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 250000000 | | 49 | 7 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 49 | 8 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 49 | 9 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 49 | 10 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 49 | 11 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | 49 | 12 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 225000000 | | 49 | 13 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | 49 | 14 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | 49 | 15 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | 49 | 16 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | 49 | 17 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK | CLK_STATE_READY | 180633600 | | 49 | 18 | DEV_TIMER0_TIMER_PWM | CLK_STATE_READY | 0 | | 50 | 0 | DEV_TIMER1_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | 50 | 1 | DEV_TIMER1_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | 50 | 2 | DEV_TIMER1_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT1 | CLK_STATE_READY | 19200000 | | 50 | 3 | DEV_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_0_TIMER_PWM | CLK_STATE_NOT_READY | 0 | | 60 | 0 | DEV_TIMER10_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | 60 | 1 | DEV_TIMER10_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | 60 | 2 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 60 | 3 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 60 | 4 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 250000000 | | 60 | 5 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 60 | 6 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 250000000 | | 60 | 7 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 60 | 8 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 60 | 9 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 60 | 10 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 60 | 11 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | 60 | 12 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 225000000 | | 60 | 13 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | 60 | 14 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | 60 | 15 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | 60 | 16 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | 60 | 17 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK | CLK_STATE_READY | 180633600 | | 60 | 18 | DEV_TIMER10_TIMER_PWM | CLK_STATE_READY | 0 | | 62 | 0 | DEV_TIMER11_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | 62 | 1 | DEV_TIMER11_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | 62 | 2 | DEV_TIMER11_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT11 | CLK_STATE_READY | 19200000 | | 62 | 3 | DEV_TIMER11_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_10_TIMER_PWM | CLK_STATE_READY | 0 | | 332 | 0 | DEV_TIMER11_CLKSEL_VD_CLK | CLK_STATE_READY | 19200000 | | 332 | 1 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 332 | 2 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 332 | 3 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 250000000 | | 332 | 4 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 332 | 5 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 250000000 | | 332 | 6 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 332 | 7 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 332 | 8 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 332 | 9 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 332 | 10 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | 332 | 11 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 225000000 | | 332 | 12 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | 332 | 13 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | 332 | 14 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | 332 | 15 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | 332 | 16 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK | CLK_STATE_READY | 180633600 | | 63 | 0 | DEV_TIMER12_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | 63 | 1 | DEV_TIMER12_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | 63 | 2 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 63 | 3 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 63 | 4 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 250000000 | | 63 | 5 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 63 | 6 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 250000000 | | 63 | 7 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 63 | 8 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 63 | 9 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 63 | 10 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 63 | 11 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | 63 | 12 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 225000000 | | 63 | 13 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | 63 | 14 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | 63 | 15 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | 63 | 16 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | 63 | 17 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK | CLK_STATE_READY | 180633600 | | 63 | 18 | DEV_TIMER12_TIMER_PWM | CLK_STATE_READY | 0 | | 64 | 0 | DEV_TIMER13_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | 64 | 1 | DEV_TIMER13_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | 64 | 2 | DEV_TIMER13_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT13 | CLK_STATE_READY | 19200000 | | 64 | 3 | DEV_TIMER13_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_12_TIMER_PWM | CLK_STATE_READY | 0 | | 333 | 0 | DEV_TIMER13_CLKSEL_VD_CLK | CLK_STATE_READY | 19200000 | | 333 | 1 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 333 | 2 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 333 | 3 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 250000000 | | 333 | 4 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 333 | 5 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 250000000 | | 333 | 6 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 333 | 7 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 333 | 8 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 333 | 9 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 333 | 10 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | 333 | 11 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 225000000 | | 333 | 12 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | 333 | 13 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | 333 | 14 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | 333 | 15 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | 333 | 16 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK | CLK_STATE_READY | 180633600 | | 65 | 0 | DEV_TIMER14_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | 65 | 1 | DEV_TIMER14_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | 65 | 2 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 65 | 3 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 65 | 4 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 250000000 | | 65 | 5 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 65 | 6 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 250000000 | | 65 | 7 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 65 | 8 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 65 | 9 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 65 | 10 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 65 | 11 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | 65 | 12 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 225000000 | | 65 | 13 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | 65 | 14 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | 65 | 15 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | 65 | 16 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | 65 | 17 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK | CLK_STATE_READY | 180633600 | | 65 | 18 | DEV_TIMER14_TIMER_PWM | CLK_STATE_READY | 0 | | 66 | 0 | DEV_TIMER15_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | 66 | 1 | DEV_TIMER15_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | 66 | 2 | DEV_TIMER15_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT15 | CLK_STATE_READY | 19200000 | | 66 | 3 | DEV_TIMER15_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_14_TIMER_PWM | CLK_STATE_READY | 0 | | 334 | 0 | DEV_TIMER15_CLKSEL_VD_CLK | CLK_STATE_READY | 19200000 | | 334 | 1 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 334 | 2 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 334 | 3 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 250000000 | | 334 | 4 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 334 | 5 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 250000000 | | 334 | 6 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 334 | 7 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 334 | 8 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 334 | 9 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 334 | 10 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | 334 | 11 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 225000000 | | 334 | 12 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | 334 | 13 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | 334 | 14 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | 334 | 15 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | 334 | 16 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK | CLK_STATE_READY | 180633600 | | 67 | 0 | DEV_TIMER16_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | 67 | 1 | DEV_TIMER16_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | 67 | 2 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 67 | 3 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 67 | 4 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 250000000 | | 67 | 5 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 67 | 6 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 250000000 | | 67 | 7 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 67 | 8 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 67 | 9 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 67 | 10 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 67 | 11 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | 67 | 12 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 225000000 | | 67 | 13 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | 67 | 14 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | 67 | 15 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | 67 | 16 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | 67 | 17 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK | CLK_STATE_READY | 180633600 | | 67 | 18 | DEV_TIMER16_TIMER_PWM | CLK_STATE_READY | 0 | | 68 | 0 | DEV_TIMER17_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | 68 | 1 | DEV_TIMER17_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | 68 | 2 | DEV_TIMER17_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT17 | CLK_STATE_READY | 19200000 | | 68 | 3 | DEV_TIMER17_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_16_TIMER_PWM | CLK_STATE_READY | 0 | | 335 | 0 | DEV_TIMER17_CLKSEL_VD_CLK | CLK_STATE_READY | 19200000 | | 335 | 1 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 335 | 2 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 335 | 3 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 250000000 | | 335 | 4 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 335 | 5 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 250000000 | | 335 | 6 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 335 | 7 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 335 | 8 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 335 | 9 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 335 | 10 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | 335 | 11 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 225000000 | | 335 | 12 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | 335 | 13 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | 335 | 14 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | 335 | 15 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | 335 | 16 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK | CLK_STATE_READY | 180633600 | | 69 | 0 | DEV_TIMER18_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | 69 | 1 | DEV_TIMER18_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | 69 | 2 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 69 | 3 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 69 | 4 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 250000000 | | 69 | 5 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 69 | 6 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 250000000 | | 69 | 7 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 69 | 8 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 69 | 9 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 69 | 10 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 69 | 11 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | 69 | 12 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 225000000 | | 69 | 13 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | 69 | 14 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | 69 | 15 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | 69 | 16 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | 69 | 17 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK | CLK_STATE_READY | 180633600 | | 69 | 18 | DEV_TIMER18_TIMER_PWM | CLK_STATE_READY | 0 | | 70 | 0 | DEV_TIMER19_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | 70 | 1 | DEV_TIMER19_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | 70 | 2 | DEV_TIMER19_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT19 | CLK_STATE_READY | 19200000 | | 70 | 3 | DEV_TIMER19_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_18_TIMER_PWM | CLK_STATE_READY | 0 | | 336 | 0 | DEV_TIMER19_CLKSEL_VD_CLK | CLK_STATE_READY | 19200000 | | 336 | 1 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 336 | 2 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 336 | 3 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 250000000 | | 336 | 4 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 336 | 5 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 250000000 | | 336 | 6 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 336 | 7 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 336 | 8 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 336 | 9 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 336 | 10 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | 336 | 11 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 225000000 | | 336 | 12 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | 336 | 13 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | 336 | 14 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | 336 | 15 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | 336 | 16 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK | CLK_STATE_READY | 180633600 | | 327 | 0 | DEV_TIMER1_CLKSEL_VD_CLK | CLK_STATE_READY | 19200000 | | 327 | 1 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 327 | 2 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 327 | 3 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 250000000 | | 327 | 4 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 327 | 5 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 250000000 | | 327 | 6 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 327 | 7 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 327 | 8 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 327 | 9 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 327 | 10 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | 327 | 11 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 225000000 | | 327 | 12 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | 327 | 13 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | 327 | 14 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | 327 | 15 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | 327 | 16 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK | CLK_STATE_READY | 180633600 | | 51 | 0 | DEV_TIMER2_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | 51 | 1 | DEV_TIMER2_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | 51 | 2 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 51 | 3 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 51 | 4 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 250000000 | | 51 | 5 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 51 | 6 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 250000000 | | 51 | 7 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 51 | 8 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 51 | 9 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 51 | 10 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 51 | 11 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | 51 | 12 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 225000000 | | 51 | 13 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | 51 | 14 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | 51 | 15 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | 51 | 16 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | 51 | 17 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK | CLK_STATE_READY | 180633600 | | 51 | 18 | DEV_TIMER2_TIMER_PWM | CLK_STATE_READY | 0 | | 52 | 0 | DEV_TIMER3_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | 52 | 1 | DEV_TIMER3_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | 52 | 2 | DEV_TIMER3_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT3 | CLK_STATE_READY | 19200000 | | 52 | 3 | DEV_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_2_TIMER_PWM | CLK_STATE_NOT_READY | 0 | | 328 | 0 | DEV_TIMER3_CLKSEL_VD_CLK | CLK_STATE_READY | 19200000 | | 328 | 1 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 328 | 2 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 328 | 3 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 250000000 | | 328 | 4 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 328 | 5 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 250000000 | | 328 | 6 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 328 | 7 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 328 | 8 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 328 | 9 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 328 | 10 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | 328 | 11 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 225000000 | | 328 | 12 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | 328 | 13 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | 328 | 14 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | 328 | 15 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | 328 | 16 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK | CLK_STATE_READY | 180633600 | | 53 | 0 | DEV_TIMER4_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | 53 | 1 | DEV_TIMER4_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | 53 | 2 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 53 | 3 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 53 | 4 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 250000000 | | 53 | 5 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 53 | 6 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 250000000 | | 53 | 7 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 53 | 8 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 53 | 9 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 53 | 10 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 53 | 11 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | 53 | 12 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 225000000 | | 53 | 13 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | 53 | 14 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | 53 | 15 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | 53 | 16 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | 53 | 17 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK | CLK_STATE_READY | 180633600 | | 53 | 18 | DEV_TIMER4_TIMER_PWM | CLK_STATE_READY | 0 | | 54 | 0 | DEV_TIMER5_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | 54 | 1 | DEV_TIMER5_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | 54 | 2 | DEV_TIMER5_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT5 | CLK_STATE_READY | 19200000 | | 54 | 3 | DEV_TIMER5_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_4_TIMER_PWM | CLK_STATE_READY | 0 | | 329 | 0 | DEV_TIMER5_CLKSEL_VD_CLK | CLK_STATE_READY | 19200000 | | 329 | 1 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 329 | 2 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 329 | 3 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 250000000 | | 329 | 4 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 329 | 5 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 250000000 | | 329 | 6 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 329 | 7 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 329 | 8 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 329 | 9 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 329 | 10 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | 329 | 11 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 225000000 | | 329 | 12 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | 329 | 13 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | 329 | 14 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | 329 | 15 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | 329 | 16 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK | CLK_STATE_READY | 180633600 | | 55 | 0 | DEV_TIMER6_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | 55 | 1 | DEV_TIMER6_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | 55 | 2 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 55 | 3 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 55 | 4 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 250000000 | | 55 | 5 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 55 | 6 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 250000000 | | 55 | 7 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 55 | 8 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 55 | 9 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 55 | 10 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 55 | 11 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | 55 | 12 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 225000000 | | 55 | 13 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | 55 | 14 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | 55 | 15 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | 55 | 16 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | 55 | 17 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK | CLK_STATE_READY | 180633600 | | 55 | 18 | DEV_TIMER6_TIMER_PWM | CLK_STATE_READY | 0 | | 57 | 0 | DEV_TIMER7_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | 57 | 1 | DEV_TIMER7_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | 57 | 2 | DEV_TIMER7_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT7 | CLK_STATE_READY | 19200000 | | 57 | 3 | DEV_TIMER7_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_6_TIMER_PWM | CLK_STATE_READY | 0 | | 330 | 0 | DEV_TIMER7_CLKSEL_VD_CLK | CLK_STATE_READY | 19200000 | | 330 | 1 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 330 | 2 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 330 | 3 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 250000000 | | 330 | 4 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 330 | 5 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 250000000 | | 330 | 6 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 330 | 7 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 330 | 8 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 330 | 9 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 330 | 10 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | 330 | 11 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 225000000 | | 330 | 12 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | 330 | 13 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | 330 | 14 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | 330 | 15 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | 330 | 16 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK | CLK_STATE_READY | 180633600 | | 58 | 0 | DEV_TIMER8_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | 58 | 1 | DEV_TIMER8_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | 58 | 2 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 58 | 3 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 58 | 4 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 250000000 | | 58 | 5 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 58 | 6 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 250000000 | | 58 | 7 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 58 | 8 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 58 | 9 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 58 | 10 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 58 | 11 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | 58 | 12 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 225000000 | | 58 | 13 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | 58 | 14 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | 58 | 15 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | 58 | 16 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | 58 | 17 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK | CLK_STATE_READY | 180633600 | | 58 | 18 | DEV_TIMER8_TIMER_PWM | CLK_STATE_READY | 0 | | 59 | 0 | DEV_TIMER9_TIMER_HCLK_CLK | CLK_STATE_READY | 125000000 | | 59 | 1 | DEV_TIMER9_TIMER_TCLK_CLK | CLK_STATE_READY | 19200000 | | 59 | 2 | DEV_TIMER9_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT9 | CLK_STATE_READY | 19200000 | | 59 | 3 | DEV_TIMER9_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_8_TIMER_PWM | CLK_STATE_READY | 0 | | 331 | 0 | DEV_TIMER9_CLKSEL_VD_CLK | CLK_STATE_READY | 19200000 | | 331 | 1 | DEV_TIMER9_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 331 | 2 | DEV_TIMER9_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 331 | 3 | DEV_TIMER9_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | CLK_STATE_READY | 250000000 | | 331 | 4 | DEV_TIMER9_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | CLK_STATE_READY | 12500000 | | 331 | 5 | DEV_TIMER9_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | CLK_STATE_READY | 250000000 | | 331 | 6 | DEV_TIMER9_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 | | 331 | 7 | DEV_TIMER9_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 331 | 8 | DEV_TIMER9_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | CLK_STATE_READY | 32768 | | 331 | 9 | DEV_TIMER9_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 | | 331 | 10 | DEV_TIMER9_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | CLK_STATE_READY | 192000000 | | 331 | 11 | DEV_TIMER9_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | CLK_STATE_READY | 225000000 | | 331 | 12 | DEV_TIMER9_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK | CLK_STATE_READY | 196608000 | | 331 | 13 | DEV_TIMER9_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2 | CLK_STATE_READY | 0 | | 331 | 14 | DEV_TIMER9_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3 | CLK_STATE_READY | 0 | | 331 | 15 | DEV_TIMER9_CLKSEL_VD_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0 | CLK_STATE_READY | 0 | | 331 | 16 | DEV_TIMER9_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK | CLK_STATE_READY | 180633600 | | 136 | 0 | DEV_TIMESYNC_INTRTR0_INTR_CLK | CLK_STATE_READY | 125000000 | | 146 | 0 | DEV_UART0_FCLK_CLK | CLK_STATE_READY | 48000000 | | 146 | 1 | DEV_UART0_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 278 | 0 | DEV_UART1_FCLK_CLK | CLK_STATE_READY | 48000000 | | 278 | 1 | DEV_UART1_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 279 | 0 | DEV_UART2_FCLK_CLK | CLK_STATE_READY | 48000000 | | 279 | 1 | DEV_UART2_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 280 | 0 | DEV_UART3_FCLK_CLK | CLK_STATE_READY | 48000000 | | 280 | 1 | DEV_UART3_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 281 | 0 | DEV_UART4_FCLK_CLK | CLK_STATE_READY | 48000000 | | 281 | 1 | DEV_UART4_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 282 | 0 | DEV_UART5_FCLK_CLK | CLK_STATE_READY | 48000000 | | 282 | 1 | DEV_UART5_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 283 | 0 | DEV_UART6_FCLK_CLK | CLK_STATE_READY | 48000000 | | 283 | 1 | DEV_UART6_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 284 | 0 | DEV_UART7_FCLK_CLK | CLK_STATE_READY | 48000000 | | 284 | 1 | DEV_UART7_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 285 | 0 | DEV_UART8_FCLK_CLK | CLK_STATE_READY | 48000000 | | 285 | 1 | DEV_UART8_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 286 | 0 | DEV_UART9_FCLK_CLK | CLK_STATE_READY | 48000000 | | 286 | 1 | DEV_UART9_VBUSP_CLK | CLK_STATE_READY | 125000000 | | 277 | 0 | DEV_UFS0_UFSHCI_HCLK_CLK | CLK_STATE_READY | 250000000 | | 277 | 1 | DEV_UFS0_UFSHCI_MCLK_CLK | CLK_STATE_READY | 19200000 | | 277 | 2 | DEV_UFS0_UFSHCI_MCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 277 | 3 | DEV_UFS0_UFSHCI_MCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 277 | 4 | DEV_UFS0_UFSHCI_MCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_1_HSDIVOUT6_CLK | CLK_STATE_READY | 19200000 | | 277 | 5 | DEV_UFS0_UFSHCI_MCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 | | 277 | 6 | DEV_UFS0_UFSHCI_MPHY_REFCLK | CLK_STATE_READY | 0 | | 288 | 0 | DEV_USB0_PIPE_REFCLK | CLK_STATE_READY | 0 | | 288 | 1 | DEV_USB0_PIPE_REFCLK_PARENT_WIZ16B4M4CS_MAIN_0_IP3_LN1_REFCLK | CLK_STATE_NOT_READY | 0 | | 288 | 2 | DEV_USB0_PIPE_REFCLK_PARENT_WIZ16B4M4CS_MAIN_3_IP3_LN1_REFCLK | CLK_STATE_READY | 0 | | 288 | 3 | DEV_USB0_CLK_LPM_CLK | CLK_STATE_READY | 24000000 | | 288 | 4 | DEV_USB0_BUF_CLK | CLK_STATE_READY | 250000000 | | 288 | 5 | DEV_USB0_USB2_APB_PCLK_CLK | CLK_STATE_READY | 125000000 | | 288 | 6 | DEV_USB0_PIPE_RXCLK | CLK_STATE_READY | 0 | | 288 | 7 | DEV_USB0_PIPE_RXCLK_PARENT_WIZ16B4M4CS_MAIN_0_IP3_LN1_RXCLK | CLK_STATE_NOT_READY | 0 | | 288 | 8 | DEV_USB0_PIPE_RXCLK_PARENT_WIZ16B4M4CS_MAIN_3_IP3_LN1_RXCLK | CLK_STATE_READY | 0 | | 288 | 9 | DEV_USB0_PIPE_TXMCLK | CLK_STATE_READY | 0 | | 288 | 10 | DEV_USB0_PIPE_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_0_IP3_LN1_TXMCLK | CLK_STATE_NOT_READY | 0 | | 288 | 11 | DEV_USB0_PIPE_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_3_IP3_LN1_TXMCLK | CLK_STATE_READY | 0 | | 288 | 12 | DEV_USB0_PIPE_RXFCLK | CLK_STATE_READY | 0 | | 288 | 13 | DEV_USB0_PIPE_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_0_IP3_LN1_RXFCLK | CLK_STATE_NOT_READY | 0 | | 288 | 14 | DEV_USB0_PIPE_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_3_IP3_LN1_RXFCLK | CLK_STATE_READY | 0 | | 288 | 15 | DEV_USB0_USB2_REFCLOCK_CLK | CLK_STATE_READY | 19200000 | | 288 | 16 | DEV_USB0_USB2_REFCLOCK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 288 | 17 | DEV_USB0_USB2_REFCLOCK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 288 | 18 | DEV_USB0_PCLK_CLK | CLK_STATE_READY | 125000000 | | 288 | 19 | DEV_USB0_ACLK_CLK | CLK_STATE_READY | 500000000 | | 288 | 20 | DEV_USB0_PIPE_TXFCLK | CLK_STATE_READY | 0 | | 288 | 21 | DEV_USB0_PIPE_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_0_IP3_LN1_TXFCLK | CLK_STATE_NOT_READY | 0 | | 288 | 22 | DEV_USB0_PIPE_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_3_IP3_LN1_TXFCLK | CLK_STATE_READY | 0 | | 288 | 23 | DEV_USB0_PIPE_TXCLK | CLK_STATE_READY | 0 | | 289 | 0 | DEV_USB1_PIPE_REFCLK | CLK_STATE_READY | 0 | | 289 | 1 | DEV_USB1_PIPE_REFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP3_LN1_REFCLK | CLK_STATE_READY | 0 | | 289 | 2 | DEV_USB1_PIPE_REFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP3_LN1_REFCLK | CLK_STATE_READY | 0 | | 289 | 3 | DEV_USB1_CLK_LPM_CLK | CLK_STATE_READY | 24000000 | | 289 | 4 | DEV_USB1_BUF_CLK | CLK_STATE_READY | 250000000 | | 289 | 5 | DEV_USB1_USB2_APB_PCLK_CLK | CLK_STATE_READY | 125000000 | | 289 | 6 | DEV_USB1_PIPE_RXCLK | CLK_STATE_READY | 0 | | 289 | 7 | DEV_USB1_PIPE_RXCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP3_LN1_RXCLK | CLK_STATE_READY | 0 | | 289 | 8 | DEV_USB1_PIPE_RXCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP3_LN1_RXCLK | CLK_STATE_READY | 0 | | 289 | 9 | DEV_USB1_PIPE_TXMCLK | CLK_STATE_READY | 0 | | 289 | 10 | DEV_USB1_PIPE_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP3_LN1_TXMCLK | CLK_STATE_READY | 0 | | 289 | 11 | DEV_USB1_PIPE_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP3_LN1_TXMCLK | CLK_STATE_READY | 0 | | 289 | 12 | DEV_USB1_PIPE_RXFCLK | CLK_STATE_READY | 0 | | 289 | 13 | DEV_USB1_PIPE_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP3_LN1_RXFCLK | CLK_STATE_READY | 0 | | 289 | 14 | DEV_USB1_PIPE_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP3_LN1_RXFCLK | CLK_STATE_READY | 0 | | 289 | 15 | DEV_USB1_USB2_REFCLOCK_CLK | CLK_STATE_READY | 19200000 | | 289 | 16 | DEV_USB1_USB2_REFCLOCK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 289 | 17 | DEV_USB1_USB2_REFCLOCK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 289 | 18 | DEV_USB1_PCLK_CLK | CLK_STATE_READY | 125000000 | | 289 | 19 | DEV_USB1_ACLK_CLK | CLK_STATE_READY | 500000000 | | 289 | 20 | DEV_USB1_PIPE_TXFCLK | CLK_STATE_READY | 0 | | 289 | 21 | DEV_USB1_PIPE_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP3_LN1_TXFCLK | CLK_STATE_READY | 0 | | 289 | 22 | DEV_USB1_PIPE_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP3_LN1_TXFCLK | CLK_STATE_READY | 0 | | 289 | 23 | DEV_USB1_PIPE_TXCLK | CLK_STATE_READY | 0 | | 290 | 0 | DEV_VPAC0_CLK | CLK_STATE_READY | 650000000 | | 290 | 1 | DEV_VPAC0_PLL_DCO_CLK | CLK_STATE_READY | 2600000000 | | 291 | 0 | DEV_VPFE0_CCD_PCLK_CLK | CLK_STATE_READY | 0 | | 291 | 1 | DEV_VPFE0_VPFE_CLK | CLK_STATE_READY | 333333333 | | 145 | 0 | DEV_WKUP_DDPA0_DDPA_CLK | CLK_STATE_READY | 166666666 | | 99 | 0 | DEV_WKUP_ESM0_CLK | CLK_STATE_READY | 166666666 | | 113 | 0 | DEV_WKUP_GPIO0_MMR_CLK | CLK_STATE_READY | 166666666 | | 114 | 0 | DEV_WKUP_GPIO1_MMR_CLK | CLK_STATE_READY | 166666666 | | 137 | 0 | DEV_WKUP_GPIOMUX_INTRTR0_INTR_CLK | CLK_STATE_READY | 166666666 | | 197 | 0 | DEV_WKUP_I2C0_PISYS_CLK | CLK_STATE_READY | 96000000 | | 197 | 1 | DEV_WKUP_I2C0_PISYS_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT3_CLK | CLK_STATE_READY | 96000000 | | 197 | 2 | DEV_WKUP_I2C0_PISYS_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 197 | 3 | DEV_WKUP_I2C0_PISCL | CLK_STATE_READY | 0 | | 197 | 4 | DEV_WKUP_I2C0_CLK | CLK_STATE_READY | 166666666 | | 197 | 5 | DEV_WKUP_I2C0_PORSCL | CLK_STATE_READY | 0 | | 132 | 0 | DEV_WKUP_PORZ_SYNC0_CLK_12M_RC_CLK | CLK_STATE_READY | 12500000 | | 138 | 0 | DEV_WKUP_PSC0_SLOW_CLK | CLK_STATE_READY | 41666666 | | 138 | 1 | DEV_WKUP_PSC0_CLK | CLK_STATE_READY | 166666666 | | 287 | 0 | DEV_WKUP_UART0_FCLK_CLK | CLK_STATE_READY | 96000000 | | 287 | 1 | DEV_WKUP_UART0_FCLK_CLK_PARENT_WKUPUSART_CLK_SEL_OUT0 | CLK_STATE_READY | 96000000 | | 287 | 2 | DEV_WKUP_UART0_FCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 287 | 3 | DEV_WKUP_UART0_VBUSP_CLK | CLK_STATE_READY | 166666666 | | 154 | 0 | DEV_WKUP_VTM0_FIX_REF2_CLK | CLK_STATE_READY | 12500000 | | 154 | 1 | DEV_WKUP_VTM0_VBUSP_CLK | CLK_STATE_READY | 166666666 | | 154 | 2 | DEV_WKUP_VTM0_FIX_REF_CLK | CLK_STATE_READY | 19200000 | |------------------------------------------------------------------------------------------------------------------------------------------------|