These tests typically are called from the file dra829_ddr_test.cmm

This is an AARCH32 memtester which can run on the TDA4's A72.  It is binary which runs on AM5.
To run here the MMU has been enabled to make the TDA4 and AM5 mappings appear similar.

the ddr4 version runs with both code and test data in the DDR.  The sram version puts the code
in sram and the test buffer in ddr.

The MMU has been setup to use virtual 0x40300000 for code.  This is either back by msmc-sram or
into ddr.  When it is mapped into DDR the test execution buffer needs to be placed higher in memory.

An example run for 'sram' would use a start address 0x80000000 and size > L3 cache.

An example run for 'ddr4' would use a start address of 0x81000000 and a size > L3 cache.



  
