/* * * Copyright (C) 2011-2013 Texas Instruments Incorporated - http://www.ti.com/ * * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ #ifndef __CSL_RL_K2H_H__ #define __CSL_RL_K2H_H__ #define _CSL_RL_TCI6636_H_ /* * Auto-generated CSL section */ #define CSL_EDMACC_0_NUM_DMACH (64) #define CSL_EDMACC_0_NUM_QDMACH (8) #define CSL_EDMACC_0_NUM_INTCH (64) #define CSL_EDMACC_0_NUM_PARAMSETS (512) #define CSL_EDMACC_0_NUM_EVQUE (2) #define CSL_EDMACC_0_NUM_TC (2) #define CSL_EDMACC_0_MEMPROTECT (1) #define CSL_EDMACC_0_NUM_REGIONS (8) #define CSL_EDMACC_0_CHMAPEXIST (1) /* * Auto-generated CSL section */ #define CSL_EDMACC_1_NUM_DMACH (64) #define CSL_EDMACC_1_NUM_QDMACH (8) #define CSL_EDMACC_1_NUM_INTCH (64) #define CSL_EDMACC_1_NUM_PARAMSETS (512) #define CSL_EDMACC_1_NUM_EVQUE (4) #define CSL_EDMACC_1_NUM_TC (4) #define CSL_EDMACC_1_MEMPROTECT (1) #define CSL_EDMACC_1_NUM_REGIONS (8) #define CSL_EDMACC_1_CHMAPEXIST (1) /* * Auto-generated CSL section */ #define CSL_EDMACC_2_NUM_DMACH (64) #define CSL_EDMACC_2_NUM_QDMACH (8) #define CSL_EDMACC_2_NUM_INTCH (64) #define CSL_EDMACC_2_NUM_PARAMSETS (512) #define CSL_EDMACC_2_NUM_EVQUE (4) #define CSL_EDMACC_2_NUM_TC (4) #define CSL_EDMACC_2_MEMPROTECT (1) #define CSL_EDMACC_2_NUM_REGIONS (8) #define CSL_EDMACC_2_CHMAPEXIST (1) /* * Auto-generated CSL section */ #define CSL_EDMACC_3_NUM_DMACH (64) #define CSL_EDMACC_3_NUM_QDMACH (8) #define CSL_EDMACC_3_NUM_INTCH (64) #define CSL_EDMACC_3_NUM_PARAMSETS (512) #define CSL_EDMACC_3_NUM_EVQUE (2) #define CSL_EDMACC_3_NUM_TC (2) #define CSL_EDMACC_3_MEMPROTECT (1) #define CSL_EDMACC_3_NUM_REGIONS (8) #define CSL_EDMACC_3_CHMAPEXIST (1) /* * Auto-generated CSL section */ #define CSL_EDMACC_4_NUM_DMACH (64) #define CSL_EDMACC_4_NUM_QDMACH (8) #define CSL_EDMACC_4_NUM_INTCH (64) #define CSL_EDMACC_4_NUM_PARAMSETS (512) #define CSL_EDMACC_4_NUM_EVQUE (2) #define CSL_EDMACC_4_NUM_TC (2) #define CSL_EDMACC_4_MEMPROTECT (1) #define CSL_EDMACC_4_NUM_REGIONS (8) #define CSL_EDMACC_4_CHMAPEXIST (1) /* * Auto-generated CSL section */ #define CSL_C66X_COREPAC_LOCAL_L2_SRAM_REGS (0x00800000) #define CSL_C66X_COREPAC_LOCAL_L1P_SRAM_REGS (0x00E00000) #define CSL_C66X_COREPAC_LOCAL_L1D_SRAM_REGS (0x00F00000) #define CSL_C66X_COREPAC_REG_BASE_ADDRESS_REGS (0x01800000) #define CSL_C66X_COREPAC_POWER_DOWN_CFG_REGS (0x01810000) #define CSL_C66X_COREPAC_SECURITY_ID_REGS (0x01811000) #define CSL_C66X_COREPAC_REVISION_ID_REGS (0x01812000) #define CSL_C66X_COREPAC_EMC_REGS (0x01820000) #define CSL_C66X_COREPAC_L1_L2_CFG_REGS (0x01840000) #define CSL_C66X_COREPAC_EMULATION_REGS (0x01BC0000) #define CSL_TRACER_0_REGS (0x01D00000) #define CSL_TRACER_1_REGS (0x01D08000) #define CSL_TRACER_2_REGS (0x01D10000) #define CSL_TRACER_3_REGS (0x01D18000) #define CSL_TRACER_23_REGS (0x01D20000) #define CSL_TRACER_8_REGS (0x01D28000) #define CSL_TRACER_20_REGS (0x01D30000) #define CSL_TRACER_21_REGS (0x01D38000) #define CSL_TRACER_25_REGS (0x01D40000) #define CSL_TRACER_9_REGS (0x01D48000) #define CSL_TRACER_10_REGS (0x01D50000) #define CSL_TRACER_11_REGS (0x01D58000) #define CSL_TRACER_12_REGS (0x01D60000) #define CSL_TRACER_13_REGS (0x01D68000) #define CSL_TRACER_14_REGS (0x01D70000) #define CSL_TRACER_15_REGS (0x01D78000) #define CSL_TRACER_16_REGS (0x01D80000) #define CSL_TRACER_26_REGS (0x01D88000) #define CSL_TRACER_27_REGS (0x01D90000) #define CSL_TRACER_28_REGS (0x01D98000) #define CSL_TRACER_22_REGS (0x01DA0000) #define CSL_TRACER_30_REGS (0x01DA8000) #define CSL_TRACER_31_REGS (0x01DB0000) #define CSL_TRACER_29_REGS (0x01DB8000) #define CSL_TRACER_17_REGS (0x01DC0000) #define CSL_TRACER_18_REGS (0x01DC8000) #define CSL_TRACER_19_REGS (0x01DD0000) #define CSL_TRACER_4_REGS (0x01DD8000) #define CSL_TRACER_5_REGS (0x01DE0000) #define CSL_TRACER_6_REGS (0x01DE0400) #define CSL_TRACER_7_REGS (0x01DE0800) #define CSL_TRACER_24_REGS (0x01DE8000) #define CSL_TETRIS_REGS (0x01E80000) #define CSL_MSMC_PBIST_REGS (0x01E84000) #define CSL_AIF_CFG_REGS (0x01F00000) #define CSL_AIF_CFG_PKTDMA_GLOBAL_CFG_REGS (0x01F00000 + 0x14000) #define CSL_AIF_CFG_PKTDMA_TX_CFG_REGS (0x01F00000 + 0x16000) #define CSL_AIF_CFG_PKTDMA_RX_CFG_REGS (0x01F00000 + 0x18000) #define CSL_AIF_CFG_PKTDMA_TX_SCHEDULER_CFG_REGS (0x01F00000 + 0x17000) #define CSL_AIF_CFG_PKTDMA_RX_FLOW_CFG_REGS (0x01F00000 + 0x1A000) #define CSL_RAC_1_FEI_CFG_REGS (0x01F80000) #define CSL_RAC_1_BEI_CFG_REGS (0x01F80000 + 0x10000) #define CSL_RAC_1_GCCP0_CFG_REGS (0x01F80000 + 0x20000) #define CSL_RAC_1_GCCP1_CFG_REGS (0x01F80000 + 0x40000) #define CSL_NETCP_CFG_REGS (0x02000000) #define CSL_NETCP_CFG_PKTDMA_GLOBAL_CFG_REGS (0x02000000 + 0x4000) #define CSL_NETCP_CFG_PKTDMA_TX_CFG_REGS (0x02000000 + 0x4400) #define CSL_NETCP_CFG_PKTDMA_RX_CFG_REGS (0x02000000 + 0x4800) #define CSL_NETCP_CFG_PKTDMA_TX_SCHEDULER_CFG_REGS (0x02000000 + 0x4C00) #define CSL_NETCP_CFG_PKTDMA_RX_FLOW_CFG_REGS (0x02000000 + 0x5000) #define CSL_NETCP_CFG_SA_CFG_REGS (0x02000000 + 0xC0000) #define CSL_RAC_0_FEI_CFG_REGS (0x02100000) #define CSL_RAC_0_BEI_CFG_REGS (0x02100000 + 0x10000) #define CSL_RAC_0_GCCP0_CFG_REGS (0x02100000 + 0x20000) #define CSL_RAC_0_GCCP1_CFG_REGS (0x02100000 + 0x40000) #define CSL_TCP3D_0_CFG_REGS (0x021C0000) #define CSL_TCP3D_2_CFG_REGS (0x021C4000) #define CSL_TCP3D_3_CFG_REGS (0x021C6000) #define CSL_TCP3D_1_CFG_REGS (0x021C8000) #define CSL_VCP_0_CFG_REGS (0x021D0000) #define CSL_VCP_1_CFG_REGS (0x021D4000) #define CSL_VCP_2_CFG_REGS (0x021D8000) #define CSL_VCP_3_CFG_REGS (0x021DC000) #define CSL_USIM_REGS (0x021DF000) #define CSL_OTP_REGS (0x021E0000) #define CSL_FFTC_0_CFG_REGS (0x021F0000) #define CSL_FFTC_0_CFG_PKTDMA_GLOBAL_CFG_REGS (0x021F0000 + 0x200) #define CSL_FFTC_0_CFG_PKTDMA_TX_CFG_REGS (0x021F0000 + 0x400) #define CSL_FFTC_0_CFG_PKTDMA_RX_CFG_REGS (0x021F0000 + 0x500) #define CSL_FFTC_0_CFG_PKTDMA_TX_SCHEDULER_CFG_REGS (0x021F0000 + 0x300) #define CSL_FFTC_0_CFG_PKTDMA_RX_FLOW_CFG_REGS (0x021F0000 + 0x600) #define CSL_FFTC_4_CFG_REGS (0x021F0800) #define CSL_FFTC_4_CFG_PKTDMA_GLOBAL_CFG_REGS (0x021F0800 + 0x200) #define CSL_FFTC_4_CFG_PKTDMA_TX_CFG_REGS (0x021F0800 + 0x400) #define CSL_FFTC_4_CFG_PKTDMA_RX_CFG_REGS (0x021F0800 + 0x500) #define CSL_FFTC_4_CFG_PKTDMA_TX_SCHEDULER_CFG_REGS (0x021F0800 + 0x300) #define CSL_FFTC_4_CFG_PKTDMA_RX_FLOW_CFG_REGS (0x021F0800 + 0x600) #define CSL_FFTC_5_CFG_REGS (0x021F1000) #define CSL_FFTC_5_CFG_PKTDMA_GLOBAL_CFG_REGS (0x021F1000 + 0x200) #define CSL_FFTC_5_CFG_PKTDMA_TX_CFG_REGS (0x021F1000 + 0x400) #define CSL_FFTC_5_CFG_PKTDMA_RX_CFG_REGS (0x021F1000 + 0x500) #define CSL_FFTC_5_CFG_PKTDMA_TX_SCHEDULER_CFG_REGS (0x021F1000 + 0x300) #define CSL_FFTC_5_CFG_PKTDMA_RX_FLOW_CFG_REGS (0x021F1000 + 0x600) #define CSL_FFTC_1_CFG_REGS (0x021F4000) #define CSL_FFTC_1_CFG_PKTDMA_GLOBAL_CFG_REGS (0x021F4000 + 0x200) #define CSL_FFTC_1_CFG_PKTDMA_TX_CFG_REGS (0x021F4000 + 0x400) #define CSL_FFTC_1_CFG_PKTDMA_RX_CFG_REGS (0x021F4000 + 0x500) #define CSL_FFTC_1_CFG_PKTDMA_TX_SCHEDULER_CFG_REGS (0x021F4000 + 0x300) #define CSL_FFTC_1_CFG_PKTDMA_RX_FLOW_CFG_REGS (0x021F4000 + 0x600) #define CSL_FFTC_2_CFG_REGS (0x021F8000) #define CSL_FFTC_2_CFG_PKTDMA_GLOBAL_CFG_REGS (0x021F8000 + 0x200) #define CSL_FFTC_2_CFG_PKTDMA_TX_CFG_REGS (0x021F8000 + 0x400) #define CSL_FFTC_2_CFG_PKTDMA_RX_CFG_REGS (0x021F8000 + 0x500) #define CSL_FFTC_2_CFG_PKTDMA_TX_SCHEDULER_CFG_REGS (0x021F8000 + 0x300) #define CSL_FFTC_2_CFG_PKTDMA_RX_FLOW_CFG_REGS (0x021F8000 + 0x600) #define CSL_FFTC_3_CFG_REGS (0x021FC000) #define CSL_FFTC_3_CFG_PKTDMA_GLOBAL_CFG_REGS (0x021FC000 + 0x200) #define CSL_FFTC_3_CFG_PKTDMA_TX_CFG_REGS (0x021FC000 + 0x400) #define CSL_FFTC_3_CFG_PKTDMA_RX_CFG_REGS (0x021FC000 + 0x500) #define CSL_FFTC_3_CFG_PKTDMA_TX_SCHEDULER_CFG_REGS (0x021FC000 + 0x300) #define CSL_FFTC_3_CFG_PKTDMA_RX_FLOW_CFG_REGS (0x021FC000 + 0x600) #define CSL_TIMER_0_REGS (0x02200000) #define CSL_TIMER_1_REGS (0x02210000) #define CSL_TIMER_2_REGS (0x02220000) #define CSL_TIMER_3_REGS (0x02230000) #define CSL_TIMER_4_REGS (0x02240000) #define CSL_TIMER_5_REGS (0x02250000) #define CSL_TIMER_6_REGS (0x02260000) #define CSL_TIMER_7_REGS (0x02270000) #define CSL_TIMER_8_REGS (0x02280000) #define CSL_TIMER_9_REGS (0x02290000) #define CSL_TIMER_10_REGS (0x022A0000) #define CSL_TIMER_11_REGS (0x022B0000) #define CSL_TIMER_12_REGS (0x022C0000) #define CSL_TIMER_13_REGS (0x022D0000) #define CSL_TIMER_14_REGS (0x022E0000) #define CSL_TIMER_15_REGS (0x022F0000) #define CSL_TIMER_16_REGS (0x022F0080) #define CSL_TIMER_17_REGS (0x022F0100) #define CSL_TIMER_18_REGS (0x022F0180) #define CSL_TIMER_19_REGS (0x022F0200) #define CSL_PLLC_REGS (0x02310000) #define CSL_HYPERLINK_0_SERDES_CFG_REGS (0x0231A000) #define CSL_HYPERLINK_1_SERDES_CFG_REGS (0x0231C000) #define CSL_XGE_SERDES_CFG_REGS (0x0231E000) #define CSL_PCIE_SERDES_CFG_REGS (0x02320000) #define CSL_AIF_SERDES_B4_CFG_REGS (0x02324000) #define CSL_AIF_SERDES_B8_CFG_REGS (0x02326000) #define CSL_DDR3_1_PHY_CFG_REGS (0x02328000) #define CSL_DDR3_0_PHY_CFG_REGS (0x02329000) #define CSL_NETCP_SERDES_CFG_REGS (0x0232A000) #define CSL_SRIO_SERDES_CFG_REGS (0x0232C000) #define CSL_SR_0_PID_PLUS_REGS (0x02330000) #define CSL_SR_0_VPRM_REGS (0x02330000 + 0x80) #define CSL_SR_0_SENSOR0_REGS (0x02330000 + 0x100) #define CSL_SR_0_SENSOR1_REGS (0x02330000 + 0x180) #define CSL_SR_0_SENSOR2_REGS (0x02330000 + 0x200) #define CSL_SR_0_SENSOR3_REGS (0x02330000 + 0x280) #define CSL_SR_0_VP_REGS (0x02330000 + 0x300) #define CSL_SR_0_VOLCON_REGS (0x02330000 + 0x380) #define CSL_SR_1_PID_PLUS_REGS (0x02330400) #define CSL_SR_1_VPRM_REGS (0x02330400 + 0x80) #define CSL_SR_1_SENSOR0_REGS (0x02330400 + 0x100) #define CSL_SR_1_SENSOR1_REGS (0x02330400 + 0x180) #define CSL_SR_1_SENSOR2_REGS (0x02330400 + 0x200) #define CSL_SR_1_SENSOR3_REGS (0x02330400 + 0x280) #define CSL_SR_1_VP_REGS (0x02330400 + 0x300) #define CSL_SR_1_VOLCON_REGS (0x02330400 + 0x380) #define CSL_VCP_4_CFG_REGS (0x02340000) #define CSL_VCP_5_CFG_REGS (0x02344000) #define CSL_VCP_6_CFG_REGS (0x02348000) #define CSL_VCP_7_CFG_REGS (0x0234C000) #define CSL_PSC_REGS (0x02350000) #define CSL_MPU_0_REGS (0x02360000) #define CSL_MPU_1_REGS (0x02368000) #define CSL_MPU_2_REGS (0x02370000) #define CSL_MPU_3_REGS (0x02378000) #define CSL_MPU_4_REGS (0x02380000) #define CSL_MPU_5_REGS (0x02388000) #define CSL_MPU_6_REGS (0x02388400) #define CSL_MPU_7_REGS (0x02388800) #define CSL_MPU_8_REGS (0x02388C00) #define CSL_MPU_9_REGS (0x02389000) #define CSL_MPU_10_REGS (0x02389400) #define CSL_MPU_11_REGS (0x02389800) #define CSL_MPU_12_REGS (0x02389C00) #define CSL_MPU_13_REGS (0x0238A000) #define CSL_MPU_14_REGS (0x0238A400) #define CSL_DBG_ADTF_0_REGS (0x02440000) #define CSL_DBG_ADTF_1_REGS (0x02450000) #define CSL_DBG_ADTF_2_REGS (0x02460000) #define CSL_DBG_ADTF_3_REGS (0x02470000) #define CSL_DBG_ADTF_4_REGS (0x02480000) #define CSL_DBG_ADTF_5_REGS (0x02490000) #define CSL_DBG_ADTF_6_REGS (0x024A0000) #define CSL_DBG_ADTF_7_REGS (0x024B0000) #define CSL_PBIST_CMB_CFG_REGS (0x024C0000) #define CSL_PBIST_CTL_0_CFG_REGS (0x024C0400) #define CSL_PBIST_CTL_1_CFG_REGS (0x024C0800) #define CSL_PBIST_CTL_2_CFG_REGS (0x024C0C00) #define CSL_SEC_CTL_REGS (0x02500000) #define CSL_I2C_0_DATA_CFG_REGS (0x02530000) #define CSL_I2C_1_DATA_CFG_REGS (0x02530400) #define CSL_I2C_2_DATA_CFG_REGS (0x02530800) #define CSL_UART_0_REGS (0x02530C00) #define CSL_UART_1_REGS (0x02531000) #define CSL_BCP_CFG_REGS (0x02540000) #define CSL_BCP_CFG_PKTDMA_GLOBAL_CFG_REGS (0x02540000 + 0x14000) #define CSL_BCP_CFG_PKTDMA_TX_CFG_REGS (0x02540000 + 0x16000) #define CSL_BCP_CFG_PKTDMA_RX_CFG_REGS (0x02540000 + 0x18000) #define CSL_BCP_CFG_PKTDMA_TX_SCHEDULER_CFG_REGS (0x02540000 + 0x1A000) #define CSL_BCP_CFG_PKTDMA_RX_FLOW_CFG_REGS (0x02540000 + 0x1C000) #define CSL_ARM_GIC_CFG_REGS (0x02560000) #define CSL_TAC_FEI_CFG_REGS (0x02580000) #define CSL_TAC_FEI_0_CFG_REGS (0x02580000) #define CSL_TAC_FEI_1_CFG_REGS (0x02580000 + 0x1000) #define CSL_TAC_FEI_2_CFG_REGS (0x02580000 + 0x2000) #define CSL_TAC_BEI_CFG_REGS (0x02580000 + 0x8000) #define CSL_TAC_SGCCP_0_CFG_REGS (0x02580000 + 0x10000) #define CSL_TAC_SGCCP_1_CFG_REGS (0x02580000 + 0x20000) #define CSL_TAC_SGCCP_2_CFG_REGS (0x02580000 + 0x30000) #define CSL_TAC_SGCCP_3_CFG_REGS (0x02580000 + 0x40000) #define CSL_TAC_SGCCP_4_CFG_REGS (0x02580000 + 0x50000) #define CSL_TAC_SGCCP_5_CFG_REGS (0x02580000 + 0x60000) #define CSL_CIC_0_REGS (0x02600000) #define CSL_CIC_1_REGS (0x02604000) #define CSL_CIC_2_REGS (0x02608000) #define CSL_GPIO_CFG_REGS (0x0260BF00) #define CSL_BOOT_CFG_REGS (0x02620000) #define CSL_USB_SERDES_CFG_REGS (0x02630000) #define CSL_SEMAPHORE_REGS (0x02640000) #define CSL_USB_CFG_REGS (0x02680000) #define CSL_EDMACC_0_REGS (0x02700000) #define CSL_EDMACC_4_REGS (0x02708000) #define CSL_EDMACC_1_REGS (0x02720000) #define CSL_EDMACC_3_REGS (0x02728000) #define CSL_EDMACC_2_REGS (0x02740000) #define CSL_EDMACC_0_TC_0_REGS (0x02760000) #define CSL_EDMACC_0_TC_1_REGS (0x02768000) #define CSL_EDMACC_1_TC_0_REGS (0x02770000) #define CSL_EDMACC_1_TC_1_REGS (0x02778000) #define CSL_EDMACC_1_TC_2_REGS (0x02780000) #define CSL_EDMACC_1_TC_3_REGS (0x02788000) #define CSL_EDMACC_2_TC_0_REGS (0x02790000) #define CSL_EDMACC_2_TC_1_REGS (0x02798000) #define CSL_EDMACC_2_TC_2_REGS (0x027A0000) #define CSL_EDMACC_2_TC_3_REGS (0x027A8000) #define CSL_EDMACC_3_TC_0_REGS (0x027B0000) #define CSL_EDMACC_3_TC_1_REGS (0x027B8000) #define CSL_EDMACC_4_TC_0_REGS (0x027B8400) #define CSL_EDMACC_4_TC_1_REGS (0x027B8800) #define CSL_BCR_CFG_REGS (0x027C0000) #define CSL_TETB_0_REGS (0x027D0000) #define CSL_DBG_TBR_TETRIS_REGS (0x027D4000) #define CSL_TETB_1_REGS (0x027E0000) #define CSL_TETB_2_REGS (0x027F0000) #define CSL_TETB_3_REGS (0x02800000) #define CSL_TETB_4_REGS (0x02810000) #define CSL_TETB_5_REGS (0x02820000) #define CSL_TETB_6_REGS (0x02830000) #define CSL_TETB_7_REGS (0x02840000) #define CSL_DBG_TBR_SYS_REGS (0x02850000) #define CSL_SRIO_CFG_REGS (0x02900000) #define CSL_SRIO_CFG_PKTDMA_GLOBAL_CFG_REGS (0x02900000 + 0x1000) #define CSL_SRIO_CFG_PKTDMA_TX_CFG_REGS (0x02900000 + 0x1400) #define CSL_SRIO_CFG_PKTDMA_RX_CFG_REGS (0x02900000 + 0x1800) #define CSL_SRIO_CFG_PKTDMA_TX_SCHEDULER_CFG_REGS (0x02900000 + 0x1C00) #define CSL_SRIO_CFG_PKTDMA_RX_FLOW_CFG_REGS (0x02900000 + 0x2000) #define CSL_QMSS_CFG_BASE (0x02A00000) #define CSL_QMSS_CFG_QM_1_CFG_REGS (0x02A02000) #define CSL_QMSS_CFG_QM_1_DESCRIPTOR_REGS (0x02A02000 + 0x1000) #define CSL_QMSS_CFG_QM_2_CFG_REGS (0x02A04000) #define CSL_QMSS_CFG_QM_2_DESCRIPTOR_REGS (0x02A04000 + 0x1000) #define CSL_QMSS_CFG_QM_1_STATUS_RAM (0x02A06000) #define CSL_QMSS_CFG_QM_2_STATUS_RAM (0x02A06400) #define CSL_QMSS_CFG_PKTDMA_1 (0x02A08000) #define CSL_QMSS_CFG_PKTDMA_1_GLOBAL_CFG_REGS (0x02A08000) #define CSL_QMSS_CFG_PKTDMA_1_TX_CFG_REGS (0x02A08000 + 0x400) #define CSL_QMSS_CFG_PKTDMA_1_RX_CFG_REGS (0x02A08000 + 0x800) #define CSL_QMSS_CFG_PKTDMA_1_TX_SCHEDULER_CFG_REGS (0x02A08000 + 0xC00) #define CSL_QMSS_CFG_PKTDMA_1_RX_FLOW_CFG_REGS (0x02A08000 + 0x1000) #define CSL_QMSS_CFG_PKTDMA_2 (0x02A0A000) #define CSL_QMSS_CFG_PKTDMA_2_GLOBAL_CFG_REGS (0x02A0A000) #define CSL_QMSS_CFG_PKTDMA_2_TX_CFG_REGS (0x02A0A000 + 0x400) #define CSL_QMSS_CFG_PKTDMA_2_RX_CFG_REGS (0x02A0A000 + 0x800) #define CSL_QMSS_CFG_PKTDMA_2_TX_SCHEDULER_CFG_REGS (0x02A0A000 + 0xC00) #define CSL_QMSS_CFG_PKTDMA_2_RX_FLOW_CFG_REGS (0x02A0A000 + 0x1000) #define CSL_QMSS_CFG_INTD_1_REGS (0x02A0C000) #define CSL_QMSS_CFG_INTD_2_REGS (0x02A0D000) #define CSL_QMSS_CFG_PDSP1_REGS (0x02A0F000) #define CSL_QMSS_CFG_PDSP2_REGS (0x02A0F000 + 0x100) #define CSL_QMSS_CFG_PDSP3_REGS (0x02A0F000 + 0x200) #define CSL_QMSS_CFG_PDSP4_REGS (0x02A0F000 + 0x300) #define CSL_QMSS_CFG_PDSP5_REGS (0x02A0F000 + 0x400) #define CSL_QMSS_CFG_PDSP6_REGS (0x02A0F000 + 0x500) #define CSL_QMSS_CFG_PDSP7_REGS (0x02A0F000 + 0x600) #define CSL_QMSS_CFG_PDSP8_REGS (0x02A0F000 + 0x700) #define CSL_QMSS_CFG_PDSP1_IRAM (0x02A10000) #define CSL_QMSS_CFG_PDSP2_IRAM (0x02A10000 + 0x1000) #define CSL_QMSS_CFG_PDSP3_IRAM (0x02A10000 + 0x2000) #define CSL_QMSS_CFG_PDSP4_IRAM (0x02A10000 + 0x3000) #define CSL_QMSS_CFG_PDSP5_IRAM (0x02A10000 + 0x4000) #define CSL_QMSS_CFG_PDSP6_IRAM (0x02A10000 + 0x5000) #define CSL_QMSS_CFG_PDSP7_IRAM (0x02A10000 + 0x6000) #define CSL_QMSS_CFG_PDSP8_IRAM (0x02A10000 + 0x7000) #define CSL_QMSS_CFG_PDSP1_SRAM (0x02A20000) #define CSL_QMSS_CFG_PDSP2_SRAM (0x02A20000 + 0x4000) #define CSL_QMSS_CFG_PDSP3_SRAM (0x02A20000 + 0x8000) #define CSL_QMSS_CFG_PDSP4_SRAM (0x02A20000 + 0xC000) #define CSL_QMSS_CFG_PDSP5_SRAM (0x02A20000 + 0x10000) #define CSL_QMSS_CFG_PDSP6_SRAM (0x02A20000 + 0x14000) #define CSL_QMSS_CFG_PDSP7_SRAM (0x02A20000 + 0x18000) #define CSL_QMSS_CFG_PDSP8_SRAM (0x02A20000 + 0x1C000) #define CSL_QMSS_CFG_QM_1_QUEUE_PEEK_REGS (0x02A40000) #define CSL_QMSS_CFG_QM_2_QUEUE_PEEK_REGS (0x02A60000) #define CSL_QMSS_CFG_QM_1_QUEUE_MANAGEMENT_REGS (0x02A80000) #define CSL_QMSS_CFG_QM_2_QUEUE_MANAGEMENT_REGS (0x02AA0000) #define CSL_QMSS_CFG_QM_1_QUEUE_PROXY_REGS (0x02AC0000) #define CSL_QMSS_CFG_QM_2_QUEUE_PROXY_REGS (0x02AE0000) #define CSL_QMSS_LINKING_RAM (0x02B00000) #define CSL_RAC_2_FEI_CFG_REGS (0x02C00000) #define CSL_RAC_2_BEI_CFG_REGS (0x02C00000 + 0x10000) #define CSL_RAC_2_GCCP0_CFG_REGS (0x02C00000 + 0x20000) #define CSL_RAC_2_GCCP1_CFG_REGS (0x02C00000 + 0x40000) #define CSL_RAC_3_FEI_CFG_REGS (0x02C80000) #define CSL_RAC_3_BEI_CFG_REGS (0x02C80000 + 0x10000) #define CSL_RAC_3_GCCP0_CFG_REGS (0x02C80000 + 0x20000) #define CSL_RAC_3_GCCP1_CFG_REGS (0x02C80000 + 0x40000) #define CSL_XGE_CFG_REGS (0x02F00000) #define CSL_XGE_CFG_CPPI_DMA_GLOBAL_CFG_REGS (0x02F00000 + 0xA1000) #define CSL_XGE_CFG_CPPI_DMA_TX_CFG_REGS (0x02F00000 + 0xA1400) #define CSL_XGE_CFG_CPPI_DMA_RX_CFG_REGS (0x02F00000 + 0xA1800) #define CSL_XGE_CFG_CPPI_DMA_TX_SCHEDULER_CFG_REGS (0x02F00000 + 0xA1C00) #define CSL_XGE_CFG_CPPI_DMA_RX_FLOW_CFG_REGS (0x02F00000 + 0xA2000) #define CSL_DBG_CFG_REGS (0x03000000) #define CSL_XMC_CFG_REGS (0x08000000) #define CSL_MSMC_CFG_REGS (0x0BC00000) #define CSL_MSMC_SRAM_REGS (0x0C000000) #define CSL_C66X_COREPAC_0_L2_SRAM_REGS (0x10800000) #define CSL_C66X_COREPAC_0_L1P_SRAM_REGS (0x10E00000) #define CSL_C66X_COREPAC_0_L1D_SRAM_REGS (0x10F00000) #define CSL_C66X_COREPAC_1_L2_SRAM_REGS (0x11800000) #define CSL_C66X_COREPAC_1_L1P_SRAM_REGS (0x11E00000) #define CSL_C66X_COREPAC_1_L1D_SRAM_REGS (0x11F00000) #define CSL_C66X_COREPAC_2_L2_SRAM_REGS (0x12800000) #define CSL_C66X_COREPAC_2_L1P_SRAM_REGS (0x12E00000) #define CSL_C66X_COREPAC_2_L1D_SRAM_REGS (0x12F00000) #define CSL_C66X_COREPAC_3_L2_SRAM_REGS (0x13800000) #define CSL_C66X_COREPAC_3_L1P_SRAM_REGS (0x13E00000) #define CSL_C66X_COREPAC_3_L1D_SRAM_REGS (0x13F00000) #define CSL_C66X_COREPAC_4_L2_SRAM_REGS (0x14800000) #define CSL_C66X_COREPAC_4_L1P_SRAM_REGS (0x14E00000) #define CSL_C66X_COREPAC_4_L1D_SRAM_REGS (0x14F00000) #define CSL_C66X_COREPAC_5_L2_SRAM_REGS (0x15800000) #define CSL_C66X_COREPAC_5_L1P_SRAM_REGS (0x15E00000) #define CSL_C66X_COREPAC_5_L1D_SRAM_REGS (0x15F00000) #define CSL_C66X_COREPAC_6_L2_SRAM_REGS (0x16800000) #define CSL_C66X_COREPAC_6_L1P_SRAM_REGS (0x16E00000) #define CSL_C66X_COREPAC_6_L1D_SRAM_REGS (0x16F00000) #define CSL_C66X_COREPAC_7_L2_SRAM_REGS (0x17800000) #define CSL_C66X_COREPAC_7_L1P_SRAM_REGS (0x17E00000) #define CSL_C66X_COREPAC_7_L1D_SRAM_REGS (0x17F00000) #define CSL_DBG_STM_REGS (0x20000000) #define CSL_TCP3D_1_DATA_REGS (0x20600000) #define CSL_TCP3D_2_DATA_REGS (0x20700000) #define CSL_TCP3D_0_DATA_REGS (0x20800000) #define CSL_TCP3D_3_DATA_REGS (0x20900000) #define CSL_BOOT_ROM_REGS (0x20B00000) #define CSL_SPI_0_SLV_REGS (0x21000400) #define CSL_SPI_1_SLV_REGS (0x21000600) #define CSL_SPI_2_SLV_REGS (0x21000800) #define CSL_AEMIF_SLV_CFG_REGS (0x21000A00) #define CSL_DDR3_0_SLV_CFG_REGS (0x21010000) #define CSL_DDR3_1_SLV_CFG_REGS (0x21020000) #define CSL_HYPERLINK_0_SLV_CFG_REGS (0x21400000) #define CSL_HYPERLINK_1_SLV_CFG_REGS (0x21400100) #define CSL_PCIE_SLV_CFG_REGS (0x21800000) #define CSL_VCP_0_DATA_REGS (0x22A00000) #define CSL_VCP_1_DATA_REGS (0x22B00000) #define CSL_VCP_2_DATA_REGS (0x22C00000) #define CSL_VCP_3_DATA_REGS (0x22D00000) #define CSL_VCP_4_DATA_REGS (0x22E00000) #define CSL_VCP_5_DATA_REGS (0x22F00000) #define CSL_VCP_6_DATA_REGS (0x23000000) #define CSL_VCP_7_DATA_REGS (0x23100000) #define CSL_TAC_DATA_BEI_REGS (0x23200000) #define CSL_QMSS_DATA_BASE (0x23A00000) #define CSL_QMSS_DATA_QM1_QUEUE_MANAGEMENT_REGS (0x23A00000 + 0x80000) #define CSL_QMSS_DATA_QM2_QUEUE_MANAGEMENT_REGS (0x23A00000 + 0xA0000) #define CSL_QMSS_DATA_PDSP1_IRAM (0x23A00000 + 0x10000) #define CSL_QMSS_DATA_PDSP2_IRAM (0x23A00000 + 0x11000) #define CSL_QMSS_DATA_PDSP3_IRAM (0x23A00000 + 0x12000) #define CSL_QMSS_DATA_PDSP4_IRAM (0x23A00000 + 0x13000) #define CSL_QMSS_DATA_PDSP5_IRAM (0x23A00000 + 0x14000) #define CSL_QMSS_DATA_PDSP6_IRAM (0x23A00000 + 0x15000) #define CSL_QMSS_DATA_PDSP7_IRAM (0x23A00000 + 0x16000) #define CSL_QMSS_DATA_PDSP8_IRAM (0x23A00000 + 0x17000) #define CSL_BCR_RAC_FEI_RAC_DATA_REGS (0x23C00000) #define CSL_DXB_SLV_REGS (0x24000000) #define CSL_HYPERLINK_1_SLV_DATA (0x28000000) #define CSL_AEMIF_SLV_AS1_EMIF16_CS_DATA (0x30000000) #define CSL_AEMIF_SLV_AS2_EMIF16_CS_DATA (0x34000000) #define CSL_AEMIF_SLV_AS3_EMIF16_CS_DATA (0x38000000) #define CSL_AEMIF_SLV_AS4_EMIF16_CS_DATA (0x3C000000) #define CSL_HYPERLINK_0_SLV_DATA (0x40000000) #define CSL_PCIE_SLV_DATA (0x50000000) #define CSL_DDR3_1_DATA (0x60000000) #define CSL_DDR3_0_DATA (0x80000000) /* * Auto-generated CSL section */ #define CSL_AEMIF (0) #define CSL_AIF (0) #define CSL_ARM_GIC (0) #define CSL_BCP (0) #define CSL_BCR (0) #define CSL_BOOT (0) #define CSL_BOOT_CFG (0) #define CSL_C66X_COREPAC_0_GLOBAL (0) #define CSL_C66X_COREPAC_1_GLOBAL (1) #define CSL_C66X_COREPAC_2_GLOBAL (2) #define CSL_C66X_COREPAC_3_GLOBAL (3) #define CSL_C66X_COREPAC_4_GLOBAL (4) #define CSL_C66X_COREPAC_5_GLOBAL (5) #define CSL_C66X_COREPAC_6_GLOBAL (6) #define CSL_C66X_COREPAC_7_GLOBAL (7) #define CSL_C66X_COREPAC_LOCAL_REGISTERS (0) #define CSL_CIC_0 (0) #define CSL_CIC_1 (1) #define CSL_CIC_2 (2) #define CSL_DBG (0) #define CSL_DDR3_0 (0) #define CSL_DDR3_1 (1) #define CSL_DEBUG (0) #define CSL_EDMACC_0 (0) #define CSL_EDMACC_0_TC_0 (0) #define CSL_EDMACC_0_TC_1 (1) #define CSL_EDMACC_1 (1) #define CSL_EDMACC_1_TC_0 (0) #define CSL_EDMACC_1_TC_1 (1) #define CSL_EDMACC_1_TC_2 (2) #define CSL_EDMACC_1_TC_3 (3) #define CSL_EDMACC_2 (2) #define CSL_EDMACC_2_TC_0 (0) #define CSL_EDMACC_2_TC_1 (1) #define CSL_EDMACC_2_TC_2 (2) #define CSL_EDMACC_2_TC_3 (3) #define CSL_EDMACC_3 (3) #define CSL_EDMACC_3_TC_0 (0) #define CSL_EDMACC_3_TC_1 (1) #define CSL_EDMACC_4 (4) #define CSL_EDMACC_4_TC_0 (0) #define CSL_EDMACC_4_TC_1 (1) #define CSL_FFTC_0 (0) #define CSL_FFTC_1 (1) #define CSL_FFTC_2 (2) #define CSL_FFTC_3 (3) #define CSL_FFTC_4 (4) #define CSL_FFTC_5 (5) #define CSL_GPIO (0) #define CSL_HYPERLINK_0 (0) #define CSL_HYPERLINK_1 (1) #define CSL_I2C_0 (0) #define CSL_I2C_1 (1) #define CSL_I2C_2 (2) #define CSL_INTERNAL_RAM (0) #define CSL_MPU_0 (0) #define CSL_MPU_1 (1) #define CSL_MPU_10 (10) #define CSL_MPU_11 (11) #define CSL_MPU_12 (12) #define CSL_MPU_13 (13) #define CSL_MPU_14 (14) #define CSL_MPU_2 (2) #define CSL_MPU_3 (3) #define CSL_MPU_4 (4) #define CSL_MPU_5 (5) #define CSL_MPU_6 (6) #define CSL_MPU_7 (7) #define CSL_MPU_8 (8) #define CSL_MPU_9 (9) #define CSL_MSMC (0) #define CSL_NETCP (0) #define CSL_OTP (0) #define CSL_PCIE (0) #define CSL_PLLC (0) #define CSL_PSC (0) #define CSL_QMSS (0) #define CSL_RAC_0 (0) #define CSL_RAC_1 (1) #define CSL_RAC_2 (2) #define CSL_RAC_3 (3) #define CSL_SEC_CTL (0) #define CSL_SEMAPHORE (0) #define CSL_SPI_0 (0) #define CSL_SPI_1 (1) #define CSL_SPI_2 (2) #define CSL_SR_0 (0) #define CSL_SR_1 (1) #define CSL_SRIO (0) #define CSL_TAC (0) #define CSL_TCP3D_0 (0) #define CSL_TCP3D_1 (1) #define CSL_TCP3D_2 (2) #define CSL_TCP3D_3 (3) #define CSL_TIMER_0 (0) #define CSL_TIMER_1 (1) #define CSL_TIMER_10 (10) #define CSL_TIMER_11 (11) #define CSL_TIMER_12 (12) #define CSL_TIMER_13 (13) #define CSL_TIMER_14 (14) #define CSL_TIMER_15 (15) #define CSL_TIMER_16 (16) #define CSL_TIMER_17 (17) #define CSL_TIMER_18 (18) #define CSL_TIMER_19 (19) #define CSL_TIMER_2 (2) #define CSL_TIMER_3 (3) #define CSL_TIMER_4 (4) #define CSL_TIMER_5 (5) #define CSL_TIMER_6 (6) #define CSL_TIMER_7 (7) #define CSL_TIMER_8 (8) #define CSL_TIMER_9 (9) #define CSL_TRACER_0 (0) #define CSL_TRACER_1 (1) #define CSL_TRACER_10 (10) #define CSL_TRACER_11 (11) #define CSL_TRACER_12 (12) #define CSL_TRACER_13 (13) #define CSL_TRACER_14 (14) #define CSL_TRACER_15 (15) #define CSL_TRACER_16 (16) #define CSL_TRACER_17 (17) #define CSL_TRACER_18 (18) #define CSL_TRACER_19 (19) #define CSL_TRACER_2 (2) #define CSL_TRACER_20 (20) #define CSL_TRACER_21 (21) #define CSL_TRACER_22 (22) #define CSL_TRACER_23 (23) #define CSL_TRACER_24 (24) #define CSL_TRACER_25 (25) #define CSL_TRACER_26 (26) #define CSL_TRACER_27 (27) #define CSL_TRACER_28 (28) #define CSL_TRACER_29 (29) #define CSL_TRACER_3 (3) #define CSL_TRACER_30 (30) #define CSL_TRACER_31 (31) #define CSL_TRACER_4 (4) #define CSL_TRACER_5 (5) #define CSL_TRACER_6 (6) #define CSL_TRACER_7 (7) #define CSL_TRACER_8 (8) #define CSL_TRACER_9 (9) #define CSL_UART_0 (0) #define CSL_UART_1 (1) #define CSL_USB (0) #define CSL_USIM (0) #define CSL_VCP_0 (0) #define CSL_VCP_1 (1) #define CSL_VCP_2 (2) #define CSL_VCP_3 (3) #define CSL_VCP_4 (4) #define CSL_VCP_5 (5) #define CSL_VCP_6 (6) #define CSL_VCP_7 (7) #define CSL_XGE (0) /* * Auto-generated CSL section */ #define CSL_C66X_COREPAC_LOCAL_REGISTERS_PER_CNT (1) #define CSL_TRACER_PER_CNT (32) #define CSL_AIF_PER_CNT (1) #define CSL_RAC_PER_CNT (4) #define CSL_NETCP_PER_CNT (1) #define CSL_TCP3D_PER_CNT (4) #define CSL_VCP_PER_CNT (8) #define CSL_USIM_PER_CNT (1) #define CSL_OTP_PER_CNT (1) #define CSL_FFTC_PER_CNT (6) #define CSL_TIMER_PER_CNT (20) #define CSL_PLLC_PER_CNT (1) #define CSL_SR_PER_CNT (2) #define CSL_PSC_PER_CNT (1) #define CSL_MPU_PER_CNT (15) #define CSL_SEC_CTL_PER_CNT (1) #define CSL_I2C_PER_CNT (3) #define CSL_UART_PER_CNT (2) #define CSL_BCP_PER_CNT (1) #define CSL_ARM_GIC_PER_CNT (1) #define CSL_TAC_PER_CNT (1) #define CSL_CIC_PER_CNT (3) #define CSL_GPIO_PER_CNT (1) #define CSL_BOOT_CFG_PER_CNT (1) #define CSL_SEMAPHORE_PER_CNT (1) #define CSL_USB_PER_CNT (1) #define CSL_EDMACC_PER_CNT (5) #define CSL_EDMACC_0_TC_PER_CNT (2) #define CSL_EDMACC_1_TC_PER_CNT (4) #define CSL_EDMACC_2_TC_PER_CNT (4) #define CSL_EDMACC_3_TC_PER_CNT (2) #define CSL_EDMACC_4_TC_PER_CNT (2) #define CSL_BCR_PER_CNT (1) #define CSL_SRIO_PER_CNT (1) #define CSL_QMSS_PER_CNT (1) #define CSL_XGE_PER_CNT (1) #define CSL_DBG_PER_CNT (1) #define CSL_MSMC_PER_CNT (1) #define CSL_INTERNAL_RAM_PER_CNT (1) #define CSL_C66X_COREPAC_0_GLOBAL_PER_CNT (1) #define CSL_C66X_COREPAC_1_GLOBAL_PER_CNT (1) #define CSL_C66X_COREPAC_2_GLOBAL_PER_CNT (1) #define CSL_C66X_COREPAC_3_GLOBAL_PER_CNT (1) #define CSL_C66X_COREPAC_4_GLOBAL_PER_CNT (1) #define CSL_C66X_COREPAC_5_GLOBAL_PER_CNT (1) #define CSL_C66X_COREPAC_6_GLOBAL_PER_CNT (1) #define CSL_C66X_COREPAC_7_GLOBAL_PER_CNT (1) #define CSL_DEBUG_PER_CNT (1) #define CSL_BOOT_PER_CNT (1) #define CSL_SPI_PER_CNT (3) #define CSL_AEMIF_PER_CNT (1) #define CSL_DDR3_PER_CNT (2) #define CSL_HYPERLINK_PER_CNT (2) #define CSL_PCIE_PER_CNT (1) /* * Auto-generated CSL section */ #define CSL_PSC_PD_ALWAYSON 0 #define CSL_PSC_PD_DEBUG_TRC 1 #define CSL_PSC_PD_NETCP 2 #define CSL_PSC_PD_PCIE 3 #define CSL_PSC_PD_SRIO 4 #define CSL_PSC_PD_HYPERLINK_0 5 #define CSL_PSC_PD_SR 6 #define CSL_PSC_PD_MSMCSRAM 7 #define CSL_PSC_PD_C66X_COREPAC_0 8 #define CSL_PSC_PD_C66X_COREPAC_1 9 #define CSL_PSC_PD_C66X_COREPAC_2 10 #define CSL_PSC_PD_C66X_COREPAC_3 11 #define CSL_PSC_PD_C66X_COREPAC_4 12 #define CSL_PSC_PD_C66X_COREPAC_5 13 #define CSL_PSC_PD_C66X_COREPAC_6 14 #define CSL_PSC_PD_C66X_COREPAC_7 15 #define CSL_PSC_PD_DDR 16 #define CSL_PSC_PD_TAC_RAC_01 17 #define CSL_PSC_PD_RAC_23 18 #define CSL_PSC_PD_FFTC_01 19 #define CSL_PSC_PD_FFTC_2345 20 #define CSL_PSC_PD_AIF 21 #define CSL_PSC_PD_TCP3D_01 22 #define CSL_PSC_PD_TCP3D_23 23 #define CSL_PSC_PD_VCP_0123 24 #define CSL_PSC_PD_VCP_4567 25 #define CSL_PSC_PD_BCP 26 #define CSL_PSC_PD_DXB 27 #define CSL_PSC_PD_HYPERLINK_1 28 #define CSL_PSC_PD_XGE 29 #define CSL_PSC_PD_ARM 31 /* * Auto-generated CSL section */ #define CSL_PSC_LPSC_MODRST0 0 #define CSL_PSC_LPSC_DUMMY1 1 #define CSL_PSC_LPSC_USB 2 #define CSL_PSC_LPSC_AEMIF_SPI 3 #define CSL_PSC_LPSC_TSIP 4 #define CSL_PSC_LPSC_DEBUGSS_TRC 5 #define CSL_PSC_LPSC_TETB_TRC 6 #define CSL_PSC_LPSC_PA 7 #define CSL_PSC_LPSC_CPGMAC 8 #define CSL_PSC_LPSC_SA 9 #define CSL_PSC_LPSC_PCIE 10 #define CSL_PSC_LPSC_SRIO 11 #define CSL_PSC_LPSC_HYPERLINK_0 12 #define CSL_PSC_LPSC_SR 13 #define CSL_PSC_LPSC_MSMCSRAM 14 #define CSL_PSC_LPSC_C66X_COREPAC_0 15 #define CSL_PSC_LPSC_C66X_COREPAC_1 16 #define CSL_PSC_LPSC_C66X_COREPAC_2 17 #define CSL_PSC_LPSC_C66X_COREPAC_3 18 #define CSL_PSC_LPSC_C66X_COREPAC_4 19 #define CSL_PSC_LPSC_C66X_COREPAC_5 20 #define CSL_PSC_LPSC_C66X_COREPAC_6 21 #define CSL_PSC_LPSC_C66X_COREPAC_7 22 #define CSL_PSC_LPSC_DDR3_0 23 #define CSL_PSC_LPSC_DDR3_1 24 #define CSL_PSC_LPSC_TAC 25 #define CSL_PSC_LPSC_RAC_01 26 #define CSL_PSC_LPSC_RAC_23 27 #define CSL_PSC_LPSC_FFTC_0 28 #define CSL_PSC_LPSC_FFTC_1 29 #define CSL_PSC_LPSC_FFTC_2 30 #define CSL_PSC_LPSC_FFTC_3 31 #define CSL_PSC_LPSC_FFTC_4 32 #define CSL_PSC_LPSC_FFTC_5 33 #define CSL_PSC_LPSC_AIF 34 #define CSL_PSC_LPSC_TCP3D_0 35 #define CSL_PSC_LPSC_TCP3D_1 36 #define CSL_PSC_LPSC_TCP3D_2 37 #define CSL_PSC_LPSC_TCP3D_3 38 #define CSL_PSC_LPSC_VCP_0 39 #define CSL_PSC_LPSC_VCP_1 40 #define CSL_PSC_LPSC_VCP_2 41 #define CSL_PSC_LPSC_VCP_3 42 #define CSL_PSC_LPSC_VCP_4 43 #define CSL_PSC_LPSC_VCP_5 44 #define CSL_PSC_LPSC_VCP_6 45 #define CSL_PSC_LPSC_VCP_7 46 #define CSL_PSC_LPSC_BCP 47 #define CSL_PSC_LPSC_DXB 48 #define CSL_PSC_LPSC_HYPERLINK_1 49 #define CSL_PSC_LPSC_XGE 50 #define CSL_PSC_LPSC_ARM 52 #endif /* __CSL_RL_K2H_H__ */