C66xx_24: GEL Output: ******************************************************** C66xx_24: GEL Output: PLL Control Register (PLLCR) C66xx_24: GEL Output: DDR3A_PLLCR: 0x0001C000 (Address: 0x02329018) C66xx_24: GEL Output: FRQSEL[19:18]: PLL Reference clock ranges from 335MHz to 533MHz (0) C66xx_24: GEL Output: Note: PLL Reference Clock should be 1/4 of DDR data rate. (i.e. 400MHz -> 1600MTs) C66xx_24: GEL Output: ******************************************************** C66xx_24: GEL Output: ******************************************************** C66xx_24: GEL Output: DRAM Timing Parameters Register 0 (DTPR0) C66xx_24: GEL Output: DDR3A_DTPR0: 0x9D9CBB66 (Address: 0x02329048) C66xx_24: GEL Output: tRFC[31:26]: Activate to Activate command delay (same bank) is 39 cycles C66xx_24: GEL Output: tRRD[25:22]: Activate to Activate command delay (diff banks) is 6 cycles C66xx_24: GEL Output: tRAS[21:16]: Activate to Precharge command delay is 28 cycles C66xx_24: GEL Output: tRCD[15:12]: Activate to Read/Write (on activated row) command delay is 11 cycles C66xx_24: GEL Output: tRP[11:8]: Precharge command period is 11 cycles C66xx_24: GEL Output: tWTR[7:4]: Internal write to read command delay is 6 cycles C66xx_24: GEL Output: tRTP[3:0]: Internal read to precharge command delay is 6 cycles C66xx_24: GEL Output: ******************************************************** C66xx_24: GEL Output: ******************************************************** C66xx_24: GEL Output: DRAM Timing Parameters Register 1 (DTPR1) C66xx_24: GEL Output: DDR3A_DTPR1: 0x32868400 (Address: 0x0232904C) C66xx_24: GEL Output: tWLO[29:26]: Write leveling output delay is 12 cycles C66xx_24: GEL Output: tWLMRD[25:20]: Min delay from write leveling mode to first DQS edge is 40 cycles C66xx_24: GEL Output: tRFC[19:11]: Refresh to Refresh command delay is 208 cycles C66xx_24: GEL Output: tFAW[10:5]: 4-bank activate period is 32 cycles C66xx_24: GEL Output: tMOD[4:2]: Load mode update delay is 12 cycles (0) C66xx_24: GEL Output: tMRD[1:0]: Load mode cycle time is 0 cycles C66xx_24: GEL Output: ******************************************************** C66xx_24: GEL Output: ******************************************************** C66xx_24: GEL Output: DRAM Timing Parameters Register 2 (DTPR2) C66xx_24: GEL Output: DDR3A_DTPR2: 0x5002D200 (Address: 0x02329050) C66xx_24: GEL Output: tCCD[31]: Read to read and write to write command delay is 4 cycles (0) C66xx_24: GEL Output: tRTW[30]: Read to write command delay is standard bus turn around delay +1 clock (1) C66xx_24: GEL Output: tRTODT[29]: Read to ODT delay is 0, may come immediately after read post-amble (0) C66xx_24: GEL Output: tDLLK[28:19]: DLL locking time is 512 cycles C66xx_24: GEL Output: tCKE[28:19]: CKE minimum pulse width (tCKESR) is 5 cycles C66xx_24: GEL Output: tXP[14:10]: Power down exit delay is 20 cycles C66xx_24: GEL Output: tXS[9:0]: Self refresh exit delay is 512 cycles C66xx_24: GEL Output: ******************************************************** C66xx_24: GEL Output: Mode Register 0 (MR0) C66xx_24: GEL Output: DDR3A_MR0: 0x00001C70 (Address: 0x02329054) C66xx_24: GEL Output: PD[12]: Fast power down exit (DLL on) (1) C66xx_24: GEL Output: WR[11:9]: Write Recovery is 12 cycles (6) C66xx_24: GEL Output: CL[6:4,2]: 11 cycles (14) C66xx_24: GEL Output: ******************************************************** C66xx_24: GEL Output: ******************************************************** C66xx_24: GEL Output: Mode Register 1 (MR1) C66xx_24: GEL Output: DDR3A_MR1: 0x00000006 (Address: 0x02329058) C66xx_24: GEL Output: AL[4:3]: AL Disabled (0) C66xx_24: GEL Output: RTT[9,6,2]: ODT is RZQ/4 on SDRAM (1) C66xx_24: GEL Output: DIC[5,1]: Output Drive is RZQ/7 on SDRAM (1) C66xx_24: GEL Output: DE[0]: DLL Enabled on SDRAM (0) C66xx_24: GEL Output: ******************************************************** C66xx_24: GEL Output: ******************************************************** C66xx_24: GEL Output: Mode Register 2 (MR2) C66xx_24: GEL Output: DDR3A_MR2: 0x00000098 (Address: 0x0232905C) C66xx_24: GEL Output: RTTWR[10:9]: Dynamic ODT is Disabled (0) C66xx_24: GEL Output: CWL[5:3]: CAS Write Latency is 8 cycles (3) C66xx_24: GEL Output: SRT[7]: Extended Operating Temperature Range (128) C66xx_24: GEL Output: ASR[6]: Auto Self-Refresh Power Management Disabled (0) C66xx_24: GEL Output: PASR[2:0]: Partial Array Self-Refresh is set to Full Array (0) C66xx_24: GEL Output: ******************************************************** C66xx_24: GEL Output: ******************************************************** C66xx_24: GEL Output: Impedance Control Register 1 (Address/Command/Control signals) (ZQ0CR1) C66xx_24: GEL Output: DDR3A_ZQ0CR1: 0x0001005D (Address: 0x02329184) C66xx_24: GEL Output: ZPROG-ODT[7:4]: On-Die Termination is set to N/A (5) C66xx_24: GEL Output: ZPROG-ZO[3:0]: Output Impedance is set to 34ohms (13) C66xx_24: GEL Output: ******************************************************** C66xx_24: GEL Output: ******************************************************** C66xx_24: GEL Output: Impedance Control Register 1 (Data Lanes 0-3) (ZQ1CR1) C66xx_24: GEL Output: DDR3A_ZQ1CR1: 0x0001005B (Address: 0x02329194) C66xx_24: GEL Output: ZPROG-ODT[7:4]: On-Die Termination is set to 60ohms (5) C66xx_24: GEL Output: ZPROG-ZO[3:0]: Output Impedance is set to 40ohms (11) C66xx_24: GEL Output: ******************************************************** C66xx_24: GEL Output: ******************************************************** C66xx_24: GEL Output: Impedance Control Register 1 (Data Lanes 4-7) (ZQ2CR1) C66xx_24: GEL Output: DDR3A_ZQ2CR1: 0x0001005B (Address: 0x023291A4) C66xx_24: GEL Output: ZPROG-ODT[7:4]: On-Die Termination is set to 60ohms (5) C66xx_24: GEL Output: ZPROG-ZO[3:0]: Output Impedance is set to 40ohms (11) C66xx_24: GEL Output: ********************************************************