<?xml version="1.0"?>
<!-- VPAC CTSET2                                                             -->
<!-- This file defines properties required to support core features in CCS --> 

<?CTOOLS version="1.1.0.0" Copyright="Copyright (c) 2020 Texas Instruments"?>
<AET>
    <JOB_MAJOR_V>1</JOB_MAJOR_V>
    <JOB_MINOR_V>0</JOB_MINOR_V>

<!--*****************************************************************************-->
<!--                       FIRST LEVEL OF FUNCTION LIST                          -->
<!-- This property presents all the supported functions to UBM and has a default -->
<!-- value of Count Event. Every time UBM creates a operation and calls          -->
<!-- Operation::GetProperties()this property will be returned.                   -->
<!-- The menu item showed by UBM will be look like:                              -->
<!--                                                                             -->
<!--     Type | Count Event                 |                                    -->
<!--                                                                             -->
<!-- For different device different set of functions will be listed              -->
<!-- Mapping of The Fields:                                                      -->
<!--    NAME         - IProperty::GetName()                                      -->
<!--    DESCRIPTION  - IProperty::GetDescription()                               -->
<!--    ALLOWEDLIST  - IStringProperty::GetAllowedValues()                       -->
<!-- Other definitions:                                                          -->
<!--    ALLOWEDITEM  - defines an item of allowed values                         -->
<!--    ALLOWED_KEY  - defines the child key when this allowed value is selected -->
<!--    ALLOWED_HALT - defines if the function halts CPU                         -->
<!--    ALLOWED_STRING - allowed string value                                    -->
<!-- Every time a allowed value is selected as the value of StringProperty, the  -->
<!-- CHILDKEY will be changed. The new CHILDKEY will be used to update the child -->
<!-- property of the StringProperty                                              -->
<!--*****************************************************************************-->
    <PROPERTY_STRING>                                           
    <NAME>Type</NAME>                                         
    <DESCRIPTION>Display all the AET functions</DESCRIPTION>    
      <ALLOWEDLIST>
          <ALLOWEDITEM>
            <ALLOWED_KEY>COUNT EVT</ALLOWED_KEY>
            <ALLOWED_STRING>Count Event</ALLOWED_STRING>
          </ALLOWEDITEM>
      </ALLOWEDLIST>
    </PROPERTY_STRING>

<!--=============================================================================-->
<!--                      VPAC CTSET2 Counters                                   -->
<!--=============================================================================-->

<!--=============================================================================-->
<!--                      Not Editable Counter Value                             -->
<!--=============================================================================-->
	<PROPERTY_INTEGER>
	  <NAME>Current Count</NAME>	
 	  <DESCRIPTION>Value of the count</DESCRIPTION>		
	  <KEYITEM>
		  <KEYNAME>COUNT EVT</KEYNAME>	      <!-- Key of sub property for Count Event -->
		  <KEYNUMBER>6</KEYNUMBER>	
	  </KEYITEM>
  	  <VALUE>0</VALUE>
	  <DISPLAYTYPE>DEC</DISPLAYTYPE>
	  <RANGELO>0</RANGELO>
	  <RANGEHI>0xFFFFFFFFFFFFFFFF</RANGEHI>
	  <EDITABLE>FALSE</EDITABLE>	
	  <ENUMVALUE>0x80070010</ENUMVALUE>
	</PROPERTY_INTEGER>

<!--=============================================================================-->
<!--                      Not Editable Overflow Flag                             -->
<!--=============================================================================-->
    <PROPERTY_STRING>
      <NAME>Overflow</NAME>    
       <DESCRIPTION>Counter Overflow status</DESCRIPTION>        
      <KEYITEM>
		  <KEYNAME>COUNT EVT</KEYNAME>	      <!-- Key of sub property for Count Event -->
		  <KEYNUMBER>7</KEYNUMBER>	
      </KEYITEM>
      <VALUE>no overflow</VALUE>
      <EDITABLE>FALSE</EDITABLE>    
    </PROPERTY_STRING>

<!--=============================================================================-->
<!--                      Other Editable Optioins                                -->
<!--=============================================================================-->
	<PROPERTY_STRING>
	  <NAME>Counter Size</NAME>	
 	  <DESCRIPTION>Size of the counter. This will be ignored if Timer Interval is non-zero.</DESCRIPTION>	
	  <KEYITEM>
		  <KEYNAME>COUNT EVT</KEYNAME>	
		  <KEYNUMBER>5</KEYNUMBER>	
	  </KEYITEM>
	  <ALLOWEDLIST>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80070002</ALLOWED_ENUM>
			<ALLOWED_STRING>32 Bit</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80070003</ALLOWED_ENUM>
			<ALLOWED_STRING>64 Bit</ALLOWED_STRING>
		  </ALLOWEDITEM>
	  </ALLOWEDLIST>
	</PROPERTY_STRING>

	<PROPERTY_STRING>
	  <NAME>Event Detection Type</NAME>	
 	  <DESCRIPTION>Edge or level detection. With the Edge type, counter will increment when a rising edge is detected. With the level type, counter will increment every time a clock cycle is seen while the input event signal is high.</DESCRIPTION>	
	  <KEYITEM>
		  <KEYNAME>COUNT EVT</KEYNAME>	
		  <KEYNUMBER>2</KEYNUMBER>	
	  </KEYITEM>
	  <ALLOWEDLIST>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80070007</ALLOWED_ENUM>
			<ALLOWED_STRING>Edge</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80070008</ALLOWED_ENUM>
			<ALLOWED_STRING>Level</ALLOWED_STRING>
		  </ALLOWEDITEM>
	  </ALLOWEDLIST>
	</PROPERTY_STRING>

	<PROPERTY_INTEGER>
	  <NAME>Timer Interval</NAME>	
 	  <DESCRIPTION>Timer interval match value. When a zero value is provided here, CTSET will function as Counter. When a non-zero value is provided here, CTSET will function as Timer and a debug event will be generated on timer interval match causing VPAC to halt.</DESCRIPTION>		
	  <KEYITEM>
		  <KEYNAME>COUNT EVT</KEYNAME>	      <!-- Key of sub property for Count Event -->
		  <KEYNUMBER>3</KEYNUMBER>	
	  </KEYITEM>
  	  <VALUE>0</VALUE>
	  <DISPLAYTYPE>DEC</DISPLAYTYPE>
	  <RANGELO>0</RANGELO>
	  <RANGEHI>0xFFFFFFFF</RANGEHI>
	  <EDITABLE>TRUE</EDITABLE>	
	  <ENUMVALUE>0x80070004</ENUMVALUE>
	</PROPERTY_INTEGER>

	<PROPERTY_STRING>
	  <NAME>Timer Mode</NAME>	
 	  <DESCRIPTION>This specifies the timer operation mode. This will be ignored if Timer Interval is zero. 
      1)Run Once Mode: The timer stops after the first interval match and is not re-enabled until the timer is reset. 
      2)Restart Mode: The timer automatically resets to the initial value (0) each time the designated interval is reached.</DESCRIPTION>	
	  <KEYITEM>
		  <KEYNAME>COUNT EVT</KEYNAME>	
		  <KEYNUMBER>4</KEYNUMBER>	
	  </KEYITEM>
	  <ALLOWEDLIST>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80070005</ALLOWED_ENUM>
			<ALLOWED_STRING>Run Once</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80070006</ALLOWED_ENUM>
			<ALLOWED_STRING>Restart</ALLOWED_STRING>
		  </ALLOWEDITEM>
	  </ALLOWEDLIST>
	</PROPERTY_STRING>
    
	<PROPERTY_STRING>
	  <NAME>Event to Count</NAME>	
 	  <DESCRIPTION>Selecting event input to count</DESCRIPTION>	
	  <KEYITEM>
		  <KEYNAME>COUNT EVT</KEYNAME>	
		  <KEYNUMBER>1</KEYNUMBER>	
	  </KEYITEM>
	  <ALLOWEDLIST>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071000</ALLOWED_ENUM>
			<ALLOWED_STRING>VISS Related Error message (config, ovf, sync, blank, access, vp)</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071001</ALLOWED_ENUM>
			<ALLOWED_STRING>h3a interrupt</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071002</ALLOWED_ENUM>
			<ALLOWED_STRING>verticle start in the beginning of the rawfe pipeline</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071003</ALLOWED_ENUM>
			<ALLOWED_STRING>verticle end in the beginning of the rawfe pipeline</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071004</ALLOWED_ENUM>
			<ALLOWED_STRING>horizontal start in the beginning of the rawfe pipeline</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071005</ALLOWED_ENUM>
			<ALLOWED_STRING>horizaontal end in the beginning of the rawfe pipeline</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071006</ALLOWED_ENUM>
			<ALLOWED_STRING>rawfe is stalling lse slave interface due to FCP or mtc stall</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071007</ALLOWED_ENUM>
			<ALLOWED_STRING>H3A master interface to LSE is stalled</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071008</ALLOWED_ENUM>
			<ALLOWED_STRING>within a frame (VS to VE at RFE i/p) lse is not sending data to RFE</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071009</ALLOWED_ENUM>
			<ALLOWED_STRING>x,y pixel position has reached the start of rawfe pipeline</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x8007100A</ALLOWED_ENUM>
			<ALLOWED_STRING>dpc otf corrected a pixel position</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x8007100B</ALLOWED_ENUM>
			<ALLOWED_STRING>active pipeline advancement</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x8007100C</ALLOWED_ENUM>
			<ALLOWED_STRING>Start of Active Line at NSF4V input</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x8007100D</ALLOWED_ENUM>
			<ALLOWED_STRING>Start of Active Frame at NSF4V input</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x8007100E</ALLOWED_ENUM>
			<ALLOWED_STRING>End of Active Line at NSF4V output</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x8007100F</ALLOWED_ENUM>
			<ALLOWED_STRING>End of Active Frame at NSF4V output</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071010</ALLOWED_ENUM>
			<ALLOWED_STRING>GLBCE filtering start ( generated at the rising edge of filtering signal)</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071011</ALLOWED_ENUM>
			<ALLOWED_STRING>GLBCE filtering done  (generated at falling edge of filtering signal)</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071012</ALLOWED_ENUM>
			<ALLOWED_STRING>Start of Active Line at GLBCE input</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071013</ALLOWED_ENUM>
			<ALLOWED_STRING>Start of Active Frame at GLBCE input</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071014</ALLOWED_ENUM>
			<ALLOWED_STRING>End of Active Line at GLBCE output</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071015</ALLOWED_ENUM>
			<ALLOWED_STRING>End of Active Frame at GLBCE output</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071016</ALLOWED_ENUM>
			<ALLOWED_STRING>Start of line processing for CFA input</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071017</ALLOWED_ENUM>
			<ALLOWED_STRING>Start of frame processing for CFA input</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071018</ALLOWED_ENUM>
			<ALLOWED_STRING>Stall has occurred on any one of the output lse interfaces</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071019</ALLOWED_ENUM>
			<ALLOWED_STRING>End of line on Y12 LSE I/f (only generated for valid lines)</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x8007101A</ALLOWED_ENUM>
			<ALLOWED_STRING>End of frame on Y12 LSE I/f</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x8007101B</ALLOWED_ENUM>
			<ALLOWED_STRING>End of line on UV12 LSE I/f (only generated for valid lines)</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x8007101C</ALLOWED_ENUM>
			<ALLOWED_STRING>End of frame on UV12 LSE I/f</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x8007101D</ALLOWED_ENUM>
			<ALLOWED_STRING>End of line on Y8R8 LSE I/f (only generated for valid lines)</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x8007101E</ALLOWED_ENUM>
			<ALLOWED_STRING>End of frame on Y8R8 LSE I/f</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x8007101F</ALLOWED_ENUM>
			<ALLOWED_STRING>End of line on C8G8 LSE I/f (only generated for valid lines)</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071020</ALLOWED_ENUM>
			<ALLOWED_STRING>End of frame on C8G8 LSE I/f</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071021</ALLOWED_ENUM>
			<ALLOWED_STRING>End of line on S8B8 LSE I/f (only generated for valid lines)</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071022</ALLOWED_ENUM>
			<ALLOWED_STRING>End of frame on S8B8 LSE I/f</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071023</ALLOWED_ENUM>
			<ALLOWED_STRING>End of processing for FlexCC</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071024</ALLOWED_ENUM>
			<ALLOWED_STRING>Frame processing done event</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071025</ALLOWED_ENUM>
			<ALLOWED_STRING>Travelled Frame Start from Core</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071027</ALLOWED_ENUM>
			<ALLOWED_STRING>ldc processing Error</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071028</ALLOWED_ENUM>
			<ALLOWED_STRING>Input mesh block fetch start event</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071029</ALLOWED_ENUM>
			<ALLOWED_STRING>Input mesh block fetch completion event</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x8007102A</ALLOWED_ENUM>
			<ALLOWED_STRING>Input pixel block fetch start event (Active for both Y and C)</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x8007102B</ALLOWED_ENUM>
			<ALLOWED_STRING>Input pixel block fetch done event (Active for both Y and C)</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x8007102C</ALLOWED_ENUM>
			<ALLOWED_STRING>Frame processing start event</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x8007102D</ALLOWED_ENUM>
			<ALLOWED_STRING>LSE write stall event</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x8007102E</ALLOWED_ENUM>
			<ALLOWED_STRING>LDC Core Block processing done</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x8007102F</ALLOWED_ENUM>
			<ALLOWED_STRING>LDC Core block write complete on C12 channel</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071030</ALLOWED_ENUM>
			<ALLOWED_STRING>LDC Core block write complete on Y12 channel</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071031</ALLOWED_ENUM>
			<ALLOWED_STRING>Frame processing done event</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071033</ALLOWED_ENUM>
			<ALLOWED_STRING>Error Response for VBUSM read/Write SL2 access (msc_lse_sl2_rd_err_intr || msc_lse_sl2_wr_err_intr) </ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071034</ALLOWED_ENUM>
			<ALLOWED_STRING>Frame processing done event for MSC Thread0</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071035</ALLOWED_ENUM>
			<ALLOWED_STRING>Frame processing done event for MSC Thread1</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071037</ALLOWED_ENUM>
			<ALLOWED_STRING>Error Response for VBUSM read/Write SL2 access (vpac_nf_sl2_wr_err_intr || vpac_nf_sl2_rd_err_intr)</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071038</ALLOWED_ENUM>
			<ALLOWED_STRING>Frame processing Done event</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x8007103A</ALLOWED_ENUM>
			<ALLOWED_STRING>CAL VP stall</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x8007103C</ALLOWED_ENUM>
			<ALLOWED_STRING>HWA-0 (task start)</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x8007103D</ALLOWED_ENUM>
			<ALLOWED_STRING>HWA-0 (task done)</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x8007103E</ALLOWED_ENUM>
			<ALLOWED_STRING>HWA-0 (init)</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x8007103F</ALLOWED_ENUM>
			<ALLOWED_STRING>HWA-0 (eop)</ALLOWED_STRING>
		  </ALLOWEDITEM>      
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071040</ALLOWED_ENUM>
			<ALLOWED_STRING>HWA-0-ch0-done</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071041</ALLOWED_ENUM>
			<ALLOWED_STRING>HWA-0-ch1-done</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071042</ALLOWED_ENUM>
			<ALLOWED_STRING>HWA-0-ch2-done</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071043</ALLOWED_ENUM>
			<ALLOWED_STRING>HWA-0-ch3-done</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071044</ALLOWED_ENUM>
			<ALLOWED_STRING>HWA-0-ch4-done</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071045</ALLOWED_ENUM>
			<ALLOWED_STRING>HWA-0-ch5-done</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071046</ALLOWED_ENUM>
			<ALLOWED_STRING>HWA-2 (task start)</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071047</ALLOWED_ENUM>
			<ALLOWED_STRING>HWA-2 (task done)</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071048</ALLOWED_ENUM>
			<ALLOWED_STRING>HWA-2 (init)</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071049</ALLOWED_ENUM>
			<ALLOWED_STRING>HWA-2 (eop)</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x8007104A</ALLOWED_ENUM>
			<ALLOWED_STRING>HWA-2-ch0-done</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x8007104B</ALLOWED_ENUM>
			<ALLOWED_STRING>HWA-2-ch1-done</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x8007104C</ALLOWED_ENUM>
			<ALLOWED_STRING>HWA-2-ch2-done</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x8007104D</ALLOWED_ENUM>
			<ALLOWED_STRING>HWA-2-ch3-done</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x8007104E</ALLOWED_ENUM>
			<ALLOWED_STRING>HWA-4 (task start)</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x8007104F</ALLOWED_ENUM>
			<ALLOWED_STRING>HWA-4 (task done)</ALLOWED_STRING>
		  </ALLOWEDITEM>      
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071050</ALLOWED_ENUM>
			<ALLOWED_STRING>HWA-4 (init)</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071051</ALLOWED_ENUM>
			<ALLOWED_STRING>HWA-4 (eop)</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071052</ALLOWED_ENUM>
			<ALLOWED_STRING>HWA-5 (task start)</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071053</ALLOWED_ENUM>
			<ALLOWED_STRING>HWA-5 (task done)</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071054</ALLOWED_ENUM>
			<ALLOWED_STRING>HWA-5 (init)</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071055</ALLOWED_ENUM>
			<ALLOWED_STRING>HWA-5 (eop)</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071056</ALLOWED_ENUM>
			<ALLOWED_STRING>HWA-4-5-ch0-done</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071057</ALLOWED_ENUM>
			<ALLOWED_STRING>HWA-4-5-ch1-done</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071058</ALLOWED_ENUM>
			<ALLOWED_STRING>HWA-4-5-ch2-done</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071059</ALLOWED_ENUM>
			<ALLOWED_STRING>HWA-4-5-ch3-done</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x8007105A</ALLOWED_ENUM>
			<ALLOWED_STRING>HWA-4-5-ch4-done</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x8007105B</ALLOWED_ENUM>
			<ALLOWED_STRING>HWA-4-5-ch5-done</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x8007105C</ALLOWED_ENUM>
			<ALLOWED_STRING>HWA-4-5-ch6-done</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x8007105D</ALLOWED_ENUM>
			<ALLOWED_STRING>HWA-4-5-ch7-done</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x8007105E</ALLOWED_ENUM>
			<ALLOWED_STRING>HWA-4-5-ch8-done</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x8007105F</ALLOWED_ENUM>
			<ALLOWED_STRING>HWA-4-5-ch9-done</ALLOWED_STRING>
		  </ALLOWEDITEM>      
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071060</ALLOWED_ENUM>
			<ALLOWED_STRING>HWA-6 (task start)</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071061</ALLOWED_ENUM>
			<ALLOWED_STRING>HWA-6 (task done)</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071062</ALLOWED_ENUM>
			<ALLOWED_STRING>HWA-6 (init)</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071063</ALLOWED_ENUM>
			<ALLOWED_STRING>HWA-6 (eop)</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071064</ALLOWED_ENUM>
			<ALLOWED_STRING>pipeline-0 Done</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071065</ALLOWED_ENUM>
			<ALLOWED_STRING>pipeline-1 Done</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071066</ALLOWED_ENUM>
			<ALLOWED_STRING>pipeline-2 Done</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071067</ALLOWED_ENUM>
			<ALLOWED_STRING>pipeline-3 Done</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071068</ALLOWED_ENUM>
			<ALLOWED_STRING>pipeline-4 Done</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071069</ALLOWED_ENUM>
			<ALLOWED_STRING>pipeline-5 Done</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x8007106A</ALLOWED_ENUM>
			<ALLOWED_STRING>pipeline-6 Done</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x8007106B</ALLOWED_ENUM>
			<ALLOWED_STRING>Spare 0 sch decrement pulse (ehost mode)</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x8007106C</ALLOWED_ENUM>
			<ALLOWED_STRING>Spare 1 sch decrement pulse (ehost mode)</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x8007106D</ALLOWED_ENUM>
			<ALLOWED_STRING>Spare 0 sch pend assertion (ehost mode)</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x8007106E</ALLOWED_ENUM>
			<ALLOWED_STRING>Spare 1 sch pend assertion (ehost mode)</ALLOWED_STRING>
		  </ALLOWEDITEM>      
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x8007106F</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_channel_start[0] when CTSET_HWA_SL2_DBG='0'; hwa_master_sl2_perf[0] when CTSET_HWA_SL2_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071070</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_channel_start[1] when CTSET_HWA_SL2_DBG='0'; hwa_master_sl2_perf[1] when CTSET_HWA_SL2_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071071</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_channel_start[2] when CTSET_HWA_SL2_DBG='0'; hwa_master_sl2_perf[2] when CTSET_HWA_SL2_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071072</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_channel_start[3] when CTSET_HWA_SL2_DBG='0'; hwa_master_sl2_perf[3] when CTSET_HWA_SL2_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071073</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_channel_start[4] when CTSET_HWA_SL2_DBG='0'; hwa_master_sl2_perf[4] when CTSET_HWA_SL2_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071074</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_channel_start[5] when CTSET_HWA_SL2_DBG='0'; hwa_master_sl2_perf[5] when CTSET_HWA_SL2_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071075</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_channel_start[6] when CTSET_HWA_SL2_DBG='0'; hwa_master_sl2_perf[6] when CTSET_HWA_SL2_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071076</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_channel_start[7] when CTSET_HWA_SL2_DBG='0'; hwa_master_sl2_perf[7] when CTSET_HWA_SL2_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071077</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_channel_start[8] when CTSET_HWA_SL2_DBG='0'; hwa_master_sl2_perf[8] when CTSET_HWA_SL2_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071078</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_channel_start[9] when CTSET_HWA_SL2_DBG='0'; hwa_master_sl2_perf[9] when CTSET_HWA_SL2_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071079</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_channel_start[10] when CTSET_HWA_SL2_DBG='0'; hwa_master_sl2_perf[10] when CTSET_HWA_SL2_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x8007107A</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_channel_start[11] when CTSET_HWA_SL2_DBG='0'; hwa_master_sl2_perf[11] when CTSET_HWA_SL2_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x8007107B</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_channel_start[12] when CTSET_HWA_SL2_DBG='0'; hwa_master_sl2_perf[12] when CTSET_HWA_SL2_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x8007107C</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_channel_start[13] when CTSET_HWA_SL2_DBG='0'; hwa_master_sl2_perf[13] when CTSET_HWA_SL2_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x8007107D</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_channel_start[14] when CTSET_HWA_SL2_DBG='0'; hwa_master_sl2_perf[14] when CTSET_HWA_SL2_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x8007107E</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_channel_start[15] when CTSET_HWA_SL2_DBG='0'; hwa_master_sl2_perf[15] when CTSET_HWA_SL2_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x8007107F</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_channel_start[16] when CTSET_HWA_SL2_DBG='0'; hwa_master_sl2_perf[16] when CTSET_HWA_SL2_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071080</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_channel_start[17] when CTSET_HWA_SL2_DBG='0'; hwa_master_sl2_perf[17] when CTSET_HWA_SL2_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071081</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_channel_start[18] when CTSET_HWA_SL2_DBG='0'; hwa_master_sl2_perf[18] when CTSET_HWA_SL2_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071082</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_channel_start[19] when CTSET_HWA_SL2_DBG='0'; hwa_master_sl2_perf[19] when CTSET_HWA_SL2_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071083</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_channel_start[20] when CTSET_HWA_SL2_DBG='0'; hwa_master_sl2_perf[20] when CTSET_HWA_SL2_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071084</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_channel_start[21] when CTSET_HWA_SL2_DBG='0'; hwa_master_sl2_perf[21] when CTSET_HWA_SL2_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071085</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_channel_start[22] when CTSET_HWA_SL2_DBG='0'; hwa_master_sl2_perf[22] when CTSET_HWA_SL2_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071086</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_channel_start[23] when CTSET_HWA_SL2_DBG='0'; hwa_master_sl2_perf[23] when CTSET_HWA_SL2_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071087</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_channel_start[24] when CTSET_HWA_SL2_DBG='0'; hwa_master_sl2_perf[24] when CTSET_HWA_SL2_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071088</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_channel_start[25] when CTSET_HWA_SL2_DBG='0'; hwa_master_sl2_perf[25] when CTSET_HWA_SL2_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071089</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_channel_start[26] when CTSET_HWA_SL2_DBG='0'; hwa_master_sl2_perf[26] when CTSET_HWA_SL2_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x8007108A</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_channel_start[27] when CTSET_HWA_SL2_DBG='0'; hwa_master_sl2_perf[27] when CTSET_HWA_SL2_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x8007108B</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_channel_start[28] when CTSET_HWA_SL2_DBG='0'; hwa_master_sl2_perf[28] when CTSET_HWA_SL2_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x8007108C</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_channel_start[29] when CTSET_HWA_SL2_DBG='0'; hwa_master_sl2_perf[29] when CTSET_HWA_SL2_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x8007108D</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_channel_start[30] when CTSET_HWA_SL2_DBG='0'; hwa_master_sl2_perf[30] when CTSET_HWA_SL2_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x8007108E</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_channel_start[31] when CTSET_HWA_SL2_DBG='0'; hwa_master_sl2_perf[31] when CTSET_HWA_SL2_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x8007108F</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_channel_start[32] when CTSET_RT_UTC_IN='0'; utc0_channel_start[0] when CTSET_RT_UTC_IN='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071090</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_channel_start[33] when CTSET_RT_UTC_IN='0'; utc0_channel_start[1] when CTSET_RT_UTC_IN='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071091</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_channel_start[34] when CTSET_RT_UTC_IN='0'; utc0_channel_start[2] when CTSET_RT_UTC_IN='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071092</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_channel_start[35] when CTSET_RT_UTC_IN='0'; utc0_channel_start[3] when CTSET_RT_UTC_IN='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071093</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_channel_start[36] when CTSET_RT_UTC_IN='0'; utc0_channel_start[4] when CTSET_RT_UTC_IN='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071094</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_channel_start[37] when CTSET_RT_UTC_IN='0'; utc0_channel_start[5] when CTSET_RT_UTC_IN='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071095</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_channel_start[38] when CTSET_RT_UTC_IN='0'; utc0_channel_start[6] when CTSET_RT_UTC_IN='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071096</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_channel_start[39] when CTSET_RT_UTC_IN='0'; utc0_channel_start[7] when CTSET_RT_UTC_IN='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071097</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_channel_start[40] when CTSET_RT_UTC_IN='0'; utc0_channel_start[8] when CTSET_RT_UTC_IN='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071098</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_channel_start[41] when CTSET_RT_UTC_IN='0'; utc0_channel_start[9] when CTSET_RT_UTC_IN='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x80071099</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_channel_start[42] when CTSET_RT_UTC_IN='0'; utc0_channel_start[10] when CTSET_RT_UTC_IN='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x8007109A</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_channel_start[43] when CTSET_RT_UTC_IN='0'; utc0_channel_start[11] when CTSET_RT_UTC_IN='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x8007109B</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_channel_start[44] when CTSET_RT_UTC_IN='0'; utc0_channel_start[12] when CTSET_RT_UTC_IN='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x8007109C</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_channel_start[45] when CTSET_RT_UTC_IN='0'; utc0_channel_start[13] when CTSET_RT_UTC_IN='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x8007109D</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_channel_start[46] when CTSET_RT_UTC_IN='0'; utc0_channel_start[14] when CTSET_RT_UTC_IN='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x8007109E</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_channel_start[47] when CTSET_RT_UTC_IN='0'; utc0_channel_start[15] when CTSET_RT_UTC_IN='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x8007109F</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_channel_start[48] when CTSET_RT_UTC_IN='0'; utc0_channel_start[16] when CTSET_RT_UTC_IN='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710A0</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_channel_start[49] when CTSET_RT_UTC_IN='0'; utc0_channel_start[17] when CTSET_RT_UTC_IN='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710A1</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_channel_start[50] when CTSET_RT_UTC_IN='0'; utc0_channel_start[18] when CTSET_RT_UTC_IN='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710A2</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_channel_start[51] when CTSET_RT_UTC_IN='0'; utc0_channel_start[19] when CTSET_RT_UTC_IN='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710A3</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_channel_start[52] when CTSET_RT_UTC_IN='0'; utc0_channel_start[20] when CTSET_RT_UTC_IN='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710A4</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_channel_start[53] when CTSET_RT_UTC_IN='0'; utc0_channel_start[21] when CTSET_RT_UTC_IN='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710A5</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_channel_start[54] when CTSET_RT_UTC_IN='0'; utc0_channel_start[22] when CTSET_RT_UTC_IN='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710A6</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_channel_start[55] when CTSET_RT_UTC_IN='0'; utc0_channel_start[23] when CTSET_RT_UTC_IN='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710A7</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_channel_start[56] when CTSET_RT_UTC_IN='0'; utc0_channel_start[24] when CTSET_RT_UTC_IN='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710A8</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_channel_start[57] when CTSET_RT_UTC_IN='0'; utc0_channel_start[25] when CTSET_RT_UTC_IN='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710A9</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_channel_start[58] when CTSET_RT_UTC_IN='0'; utc0_channel_start[26] when CTSET_RT_UTC_IN='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710AA</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_channel_start[59] when CTSET_RT_UTC_IN='0'; utc0_channel_start[27] when CTSET_RT_UTC_IN='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710AB</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_channel_start[60] when CTSET_RT_UTC_IN='0'; utc0_channel_start[28] when CTSET_RT_UTC_IN='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710AC</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_channel_start[61] when CTSET_RT_UTC_IN='0'; utc0_channel_start[29] when CTSET_RT_UTC_IN='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710AD</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_channel_start[62] when CTSET_RT_UTC_IN='0'; utc0_channel_start[30] when CTSET_RT_UTC_IN='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710AE</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_channel_start[63] when CTSET_RT_UTC_IN='0'; utc0_channel_start[31] when CTSET_RT_UTC_IN='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>      
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710AF</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_ctset_intr[0] when CTSET_DMA_SOC_DBG='0'; ext_master_ddr_perf[0] when CTSET_DMA_SOC_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710B0</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_ctset_intr[1] when CTSET_DMA_SOC_DBG='0'; ext_master_ddr_perf[1] when CTSET_DMA_SOC_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710B1</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_ctset_intr[2] when CTSET_DMA_SOC_DBG='0'; ext_master_ddr_perf[2] when CTSET_DMA_SOC_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710B2</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_ctset_intr[3] when CTSET_DMA_SOC_DBG='0'; ext_master_ddr_perf[3] when CTSET_DMA_SOC_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710B3</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_ctset_intr[4] when CTSET_DMA_SOC_DBG='0'; ext_master_ddr_perf[4] when CTSET_DMA_SOC_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710B4</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_ctset_intr[5] when CTSET_DMA_SOC_DBG='0'; ext_master_ddr_perf[5] when CTSET_DMA_SOC_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710B5</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_ctset_intr[6] when CTSET_DMA_SOC_DBG='0'; ext_master_ddr_perf[6] when CTSET_DMA_SOC_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710B6</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_ctset_intr[7] when CTSET_DMA_SOC_DBG='0'; ext_master_ddr_perf[7] when CTSET_DMA_SOC_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710B7</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_ctset_intr[8] when CTSET_DMA_SOC_DBG='0'; ext_master_ddr_perf[8] when CTSET_DMA_SOC_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710B8</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_ctset_intr[9] when CTSET_DMA_SOC_DBG='0'; ext_master_ddr_perf[9] when CTSET_DMA_SOC_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710B9</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_ctset_intr[10] when CTSET_DMA_SOC_DBG='0'; ext_master_ddr_perf[10] when CTSET_DMA_SOC_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710BA</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_ctset_intr[11] when CTSET_DMA_SOC_DBG='0'; ext_master_ddr_perf[11] when CTSET_DMA_SOC_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710BB</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_ctset_intr[12] when CTSET_DMA_SOC_DBG='0'; ext_master_ddr_perf[12] when CTSET_DMA_SOC_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710BC</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_ctset_intr[13] when CTSET_DMA_SOC_DBG='0'; ext_master_ddr_perf[13] when CTSET_DMA_SOC_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710BD</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_ctset_intr[14] when CTSET_DMA_SOC_DBG='0'; ext_master_ddr_perf[14] when CTSET_DMA_SOC_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710BE</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_ctset_intr[15] when CTSET_DMA_SOC_DBG='0'; ext_master_ddr_perf[15] when CTSET_DMA_SOC_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710BF</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_ctset_intr[16] when CTSET_DMA_SOC_DBG='0'; ext_master_ddr_perf[16] when CTSET_DMA_SOC_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710C0</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_ctset_intr[17] when CTSET_DMA_SOC_DBG='0'; ext_master_ddr_perf[17] when CTSET_DMA_SOC_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710C1</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_ctset_intr[18] when CTSET_DMA_SOC_DBG='0'; ext_master_ddr_perf[18] when CTSET_DMA_SOC_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710C2</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_ctset_intr[19] when CTSET_DMA_SOC_DBG='0'; ext_master_ddr_perf[19] when CTSET_DMA_SOC_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710C3</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_ctset_intr[20] when CTSET_DMA_SOC_DBG='0'; ext_master_ddr_perf[20] when CTSET_DMA_SOC_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710C4</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_ctset_intr[21] when CTSET_DMA_SOC_DBG='0'; ext_master_ddr_perf[21] when CTSET_DMA_SOC_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710C5</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_ctset_intr[22] when CTSET_DMA_SOC_DBG='0'; ext_master_ddr_perf[22] when CTSET_DMA_SOC_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710C6</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_ctset_intr[23] when CTSET_DMA_SOC_DBG='0'; ext_master_ddr_perf[23] when CTSET_DMA_SOC_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710C7</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_ctset_intr[24] when CTSET_DMA_SOC_DBG='0'; ext_master_ddr_perf[24] when CTSET_DMA_SOC_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710C8</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_ctset_intr[25] when CTSET_DMA_SOC_DBG='0'; ext_master_ddr_perf[25] when CTSET_DMA_SOC_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710C9</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_ctset_intr[26] when CTSET_DMA_SOC_DBG='0'; ext_master_ddr_perf[26] when CTSET_DMA_SOC_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710CA</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_ctset_intr[27] when CTSET_DMA_SOC_DBG='0'; ext_master_ddr_perf[27] when CTSET_DMA_SOC_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710CB</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_ctset_intr[28] when CTSET_DMA_SOC_DBG='0'; ext_master_ddr_perf[28] when CTSET_DMA_SOC_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710CC</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_ctset_intr[29] when CTSET_DMA_SOC_DBG='0'; ext_master_ddr_perf[29] when CTSET_DMA_SOC_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710CD</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_ctset_intr[30] when CTSET_DMA_SOC_DBG='0'; ext_master_ddr_perf[30] when CTSET_DMA_SOC_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710CE</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_ctset_intr[31] when CTSET_DMA_SOC_DBG='0'; ext_master_ddr_perf[31] when CTSET_DMA_SOC_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710CF</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_ctset_intr[32] when CTSET_RT_UTC_OUT='0'; utc0_ctset_intr[0] when CTSET_RT_UTC_OUT='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710D0</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_ctset_intr[33] when CTSET_RT_UTC_OUT='0'; utc0_ctset_intr[1] when CTSET_RT_UTC_OUT='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710D1</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_ctset_intr[34] when CTSET_RT_UTC_OUT='0'; utc0_ctset_intr[2] when CTSET_RT_UTC_OUT='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710D2</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_ctset_intr[35] when CTSET_RT_UTC_OUT='0'; utc0_ctset_intr[3] when CTSET_RT_UTC_OUT='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710D3</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_ctset_intr[36] when CTSET_RT_UTC_OUT='0'; utc0_ctset_intr[4] when CTSET_RT_UTC_OUT='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710D4</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_ctset_intr[37] when CTSET_RT_UTC_OUT='0'; utc0_ctset_intr[5] when CTSET_RT_UTC_OUT='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710D5</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_ctset_intr[38] when CTSET_RT_UTC_OUT='0'; utc0_ctset_intr[6] when CTSET_RT_UTC_OUT='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710D6</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_ctset_intr[39] when CTSET_RT_UTC_OUT='0'; utc0_ctset_intr[7] when CTSET_RT_UTC_OUT='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710D7</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_ctset_intr[40] when CTSET_RT_UTC_OUT='0'; utc0_ctset_intr[8] when CTSET_RT_UTC_OUT='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710D8</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_ctset_intr[41] when CTSET_RT_UTC_OUT='0'; utc0_ctset_intr[9] when CTSET_RT_UTC_OUT='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710D9</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_ctset_intr[42] when CTSET_RT_UTC_OUT='0'; utc0_ctset_intr[10] when CTSET_RT_UTC_OUT='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710DA</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_ctset_intr[43] when CTSET_RT_UTC_OUT='0'; utc0_ctset_intr[11] when CTSET_RT_UTC_OUT='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710DB</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_ctset_intr[44] when CTSET_RT_UTC_OUT='0'; utc0_ctset_intr[12] when CTSET_RT_UTC_OUT='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710DC</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_ctset_intr[45] when CTSET_RT_UTC_OUT='0'; utc0_ctset_intr[13] when CTSET_RT_UTC_OUT='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710DD</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_ctset_intr[46] when CTSET_RT_UTC_OUT='0'; utc0_ctset_intr[14] when CTSET_RT_UTC_OUT='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710DE</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_ctset_intr[47] when CTSET_RT_UTC_OUT='0'; utc0_ctset_intr[15] when CTSET_RT_UTC_OUT='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710DF</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_ctset_intr[48] when CTSET_RT_UTC_OUT='0'; utc0_ctset_intr[16] when CTSET_RT_UTC_OUT='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710E0</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_ctset_intr[49] when CTSET_RT_UTC_OUT='0'; utc0_ctset_intr[17] when CTSET_RT_UTC_OUT='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710E1</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_ctset_intr[50] when CTSET_RT_UTC_OUT='0'; utc0_ctset_intr[18] when CTSET_RT_UTC_OUT='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710E2</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_ctset_intr[51] when CTSET_RT_UTC_OUT='0'; utc0_ctset_intr[19] when CTSET_RT_UTC_OUT='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710E3</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_ctset_intr[52] when CTSET_RT_UTC_OUT='0'; utc0_ctset_intr[20] when CTSET_RT_UTC_OUT='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710E4</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_ctset_intr[53] when CTSET_RT_UTC_OUT='0'; utc0_ctset_intr[21] when CTSET_RT_UTC_OUT='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710E5</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_ctset_intr[54] when CTSET_RT_UTC_OUT='0'; utc0_ctset_intr[22] when CTSET_RT_UTC_OUT='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710E6</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_ctset_intr[55] when CTSET_RT_UTC_OUT='0'; utc0_ctset_intr[23] when CTSET_RT_UTC_OUT='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710E7</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_ctset_intr[56] when CTSET_RT_UTC_OUT='0'; utc0_ctset_intr[24] when CTSET_RT_UTC_OUT='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710E8</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_ctset_intr[57] when CTSET_RT_UTC_OUT='0'; utc0_ctset_intr[25] when CTSET_RT_UTC_OUT='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710E9</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_ctset_intr[58] when CTSET_RT_UTC_OUT='0'; utc0_ctset_intr[26] when CTSET_RT_UTC_OUT='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710EA</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_ctset_intr[59] when CTSET_RT_UTC_OUT='0'; utc0_ctset_intr[27] when CTSET_RT_UTC_OUT='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710EB</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_ctset_intr[60] when CTSET_RT_UTC_OUT='0'; utc0_ctset_intr[28] when CTSET_RT_UTC_OUT='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710EC</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_ctset_intr[61] when CTSET_RT_UTC_OUT='0'; utc0_ctset_intr[29] when CTSET_RT_UTC_OUT='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710ED</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_ctset_intr[62] when CTSET_RT_UTC_OUT='0'; utc0_ctset_intr[30] when CTSET_RT_UTC_OUT='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710EE</ALLOWED_ENUM>
			<ALLOWED_STRING>utc1_ctset_intr[63] when CTSET_RT_UTC_OUT='0'; utc0_ctset_intr[31] when CTSET_RT_UTC_OUT='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710EF</ALLOWED_ENUM>
			<ALLOWED_STRING>ext_ctset_event[0] when CTSET_UTC_SL2_DBG='0'; dma_master_sl2_perf[0] when CTSET_UTC_SL2_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710F0</ALLOWED_ENUM>
			<ALLOWED_STRING>ext_ctset_event[1] when CTSET_UTC_SL2_DBG='0'; dma_master_sl2_perf[1] when CTSET_UTC_SL2_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710F1</ALLOWED_ENUM>
			<ALLOWED_STRING>ext_ctset_event[2] when CTSET_UTC_SL2_DBG='0'; dma_master_sl2_perf[2] when CTSET_UTC_SL2_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710F2</ALLOWED_ENUM>
			<ALLOWED_STRING>ext_ctset_event[3] when CTSET_UTC_SL2_DBG='0'; dma_master_sl2_perf[3] when CTSET_UTC_SL2_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710F3</ALLOWED_ENUM>
			<ALLOWED_STRING>ext_ctset_event[4] when CTSET_UTC_SL2_DBG='0'; dma_master_sl2_perf[4] when CTSET_UTC_SL2_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710F4</ALLOWED_ENUM>
			<ALLOWED_STRING>ext_ctset_event[5] when CTSET_UTC_SL2_DBG='0'; dma_master_sl2_perf[5] when CTSET_UTC_SL2_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710F5</ALLOWED_ENUM>
			<ALLOWED_STRING>ext_ctset_event[6] when CTSET_UTC_SL2_DBG='0'; dma_master_sl2_perf[6] when CTSET_UTC_SL2_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710F6</ALLOWED_ENUM>
			<ALLOWED_STRING>ext_ctset_event[7] when CTSET_UTC_SL2_DBG='0'; dma_master_sl2_perf[7] when CTSET_UTC_SL2_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710F7</ALLOWED_ENUM>
			<ALLOWED_STRING>ext_ctset_event[8] when CTSET_UTC_SL2_DBG='0'; dma_master_sl2_perf[8] when CTSET_UTC_SL2_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710F8</ALLOWED_ENUM>
			<ALLOWED_STRING>ext_ctset_event[9] when CTSET_UTC_SL2_DBG='0'; dma_master_sl2_perf[9] when CTSET_UTC_SL2_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710F9</ALLOWED_ENUM>
			<ALLOWED_STRING>ext_ctset_event[10] when CTSET_UTC_SL2_DBG='0'; dma_master_sl2_perf[10] when CTSET_UTC_SL2_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710FA</ALLOWED_ENUM>
			<ALLOWED_STRING>ext_ctset_event[11] when CTSET_UTC_SL2_DBG='0'; dma_master_sl2_perf[11] when CTSET_UTC_SL2_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710FB</ALLOWED_ENUM>
			<ALLOWED_STRING>ext_ctset_event[12] when CTSET_UTC_SL2_DBG='0'; dma_master_sl2_perf[12] when CTSET_UTC_SL2_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710FC</ALLOWED_ENUM>
			<ALLOWED_STRING>ext_ctset_event[13] when CTSET_UTC_SL2_DBG='0'; dma_master_sl2_perf[13] when CTSET_UTC_SL2_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710FD</ALLOWED_ENUM>
			<ALLOWED_STRING>ext_ctset_event[14] when CTSET_UTC_SL2_DBG='0'; dma_master_sl2_perf[14] when CTSET_UTC_SL2_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
		  <ALLOWEDITEM>
			<ALLOWED_ENUM>0x800710FE</ALLOWED_ENUM>
			<ALLOWED_STRING>ext_ctset_event[15] when CTSET_UTC_SL2_DBG='0'; dma_master_sl2_perf[15] when CTSET_UTC_SL2_DBG='1'</ALLOWED_STRING>
		  </ALLOWEDITEM>
	  </ALLOWEDLIST>	
    </PROPERTY_STRING>

</AET>
