From 3c285f252f7f282f01469acd33eaf34ac6ea3d2b Mon Sep 17 00:00:00 2001
From: Gokul S <g-s@ti.com>
Date: Fri, 26 Sep 2025 14:34:58 +0530
Subject: [PATCH 2/2] final

---
 platform/j784s4/rtos/common/app_init.c        | 14 ++++-----
 utils/dss/include/app_dctrl.h                 |  7 ++++-
 utils/dss/src/app_dss_dual_display_defaults.c |  2 +-
 utils/dss/src/app_dss_soc.c                   | 30 ++++++++-----------
 4 files changed, 27 insertions(+), 26 deletions(-)

diff --git a/platform/j784s4/rtos/common/app_init.c b/platform/j784s4/rtos/common/app_init.c
index a34015c..bfa647d 100755
--- a/platform/j784s4/rtos/common/app_init.c
+++ b/platform/j784s4/rtos/common/app_init.c
@@ -815,13 +815,13 @@ int32_t appInit()
                 prm.display[i].display_type = APP_DSS_DEFAULT_DISPLAY_TYPE_DSI;
                 prm.display[i].timings.width        = 1920U;
                 prm.display[i].timings.height       = 1080U;
-                prm.display[i].timings.hFrontPorch  = 8U;
-                prm.display[i].timings.hBackPorch   = 40U;
-                prm.display[i].timings.hSyncLen     = 32U;
-                prm.display[i].timings.vFrontPorch  = 17U;
-                prm.display[i].timings.vBackPorch   = 6U;
-                prm.display[i].timings.vSyncLen     = 8U;
-                prm.display[i].timings.pixelClock   = 133320000U;
+                prm.display[i].timings.hFrontPorch  = 60U;
+                prm.display[i].timings.hBackPorch   = 70U;
+                prm.display[i].timings.hSyncLen     = 62U;
+                prm.display[i].timings.vFrontPorch  = 55U;
+                prm.display[i].timings.vBackPorch   = 60U;
+                prm.display[i].timings.vSyncLen     = 55U;
+                prm.display[i].timings.pixelClock   = 158400000ULL;
             }
         }
 
diff --git a/utils/dss/include/app_dctrl.h b/utils/dss/include/app_dctrl.h
index 79a7dc9..5ce56ed 100755
--- a/utils/dss/include/app_dctrl.h
+++ b/utils/dss/include/app_dctrl.h
@@ -122,7 +122,12 @@ extern "C" {
 #define APP_DCTRL_NODE_EDP_DPI1               (0x10U)
 #define APP_DCTRL_NODE_EDP_DPI2               (0x11U)
 #define APP_DCTRL_NODE_EDP_DPI3               (0x12U)
-#define APP_DCTRL_NODE_DSI_DPI2               (0x13U)
+#define APP_DCTRL_NODE_DSI_DPI1               (0x13U)
+#define APP_DCTRL_NODE_DSI_DPI2               (0x14U)
+#define APP_DCTRL_NODE_DSI_DPI3               (0x15U)
+#define APP_DCTRL_NODE_DISCSYNC0              (0x16U)
+#define APP_DCTRL_NODE_DISCSYNC1              (0x17U)
+#define APP_DCTRL_NODE_WB                     (0x18U)
 /* @} */
 
 /** \brief Defines maximum number of edges for allocation. This is derived by
diff --git a/utils/dss/src/app_dss_dual_display_defaults.c b/utils/dss/src/app_dss_dual_display_defaults.c
index 552485e..49188e9 100755
--- a/utils/dss/src/app_dss_dual_display_defaults.c
+++ b/utils/dss/src/app_dss_dual_display_defaults.c
@@ -433,7 +433,7 @@ int32_t appDctrlDualDisplayDefaultInit(app_dss_dual_display_default_obj_t *dual_
              * With 2 lanes, the DSITX clock will be high enough for the DSI to DP bridge to break;
              */
             dsiParams.num_lanes = 4u;
-            dsiParams.lane_speed_in_kbps = 799920u;
+            dsiParams.lane_speed_in_kbps = 950400u;
             retVal+= appRemoteServiceRun(cpuId, APP_DCTRL_REMOTE_SERVICE_NAME, APP_DCTRL_CMD_SET_DSI_PARAMS, &dsiParams, sizeof(app_dctrl_dsi_params_t), 0U);
         }
         retVal+= appRemoteServiceRun(cpuId, APP_DCTRL_REMOTE_SERVICE_NAME, APP_DCTRL_CMD_SET_VP_PARAMS, &vpParams[i], sizeof(vpParams[i]), 0U);
diff --git a/utils/dss/src/app_dss_soc.c b/utils/dss/src/app_dss_soc.c
index d5671ba..aeb5446 100755
--- a/utils/dss/src/app_dss_soc.c
+++ b/utils/dss/src/app_dss_soc.c
@@ -327,18 +327,7 @@ void appDssConfigureBoard(app_dss_default_prm_t *prm)
 #if defined(SOC_J721S2) || defined(SOC_J784S4) || defined(SOC_J742S2)
     if(prm->display_type == APP_DSS_DEFAULT_DISPLAY_TYPE_DSI)
     {
-        if ((prm->timings.width       == 1920U  &&
-            prm->timings.height       == 1080U   &&
-            prm->timings.hFrontPorch  == 8U    &&
-            prm->timings.hBackPorch   == 40U    &&
-            prm->timings.hSyncLen     == 32U    &&
-            prm->timings.vFrontPorch  == 17U     &&
-            prm->timings.vBackPorch   == 6U    &&
-            prm->timings.vSyncLen     == 8U) 
-        )
-        {
-            appDssDsiConfigureSN65(VX_DSI_RESO_1080P);
-        }
+        appDssDsiConfigureSN65(VX_DSI_RESO_1080P);
     }
 #endif
 
@@ -580,39 +569,46 @@ void appDssPrepareSN65I2cConfig(uint32_t resolution)
                 gI2cDsiBridgeCfg[i][1] = 0x4;
             }
         }
+        else if (gI2cDsiBridgeCfg[i][0] == 0x2C)
+        {
+            if (resolution == VX_DSI_RESO_1080P)
+            {
+                gI2cDsiBridgeCfg[i][1] = 0x3E;
+            }
+        }
         else if (gI2cDsiBridgeCfg[i][0] == 0x30)
         {
             if (resolution == VX_DSI_RESO_1080P)
             {
-                gI2cDsiBridgeCfg[i][1] = 0x08;
+                gI2cDsiBridgeCfg[i][1] = 0x37;
             }
         }
         else if (gI2cDsiBridgeCfg[i][0] == 0x34)
         {
             if (resolution == VX_DSI_RESO_1080P)
             {
-                gI2cDsiBridgeCfg[i][1] = 0x28;
+                gI2cDsiBridgeCfg[i][1] = 0x46;
             }
         }
         else if (gI2cDsiBridgeCfg[i][0] == 0x36)
         {
             if (resolution == VX_DSI_RESO_1080P)
             {
-                gI2cDsiBridgeCfg[i][1] = 0x06;
+                gI2cDsiBridgeCfg[i][1] = 0x3c;
             }
         }
         else if (gI2cDsiBridgeCfg[i][0] == 0x38)
         {
             if (resolution == VX_DSI_RESO_1080P)
             {
-                gI2cDsiBridgeCfg[i][1] = 0x08;
+                gI2cDsiBridgeCfg[i][1] = 0x3c;
             }
         }
         else if (gI2cDsiBridgeCfg[i][0] == 0x3a)
         {
             if (resolution == VX_DSI_RESO_1080P)
             {
-                gI2cDsiBridgeCfg[i][1] = 0x10;
+                gI2cDsiBridgeCfg[i][1] = 0x37;
             }
         }
     }
-- 
2.34.1

