diff --git a/psdkla/board-support/linux-5.10.120+gitAUTOINC+95b90aa828-g95b90aa828/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/psdkla/board-support/linux-5.10.120+gitAUTOINC+95b90aa828-g95b90aa828/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
index b4a462959..a4ad4ca1d 100644
--- a/psdkla/board-support/linux-5.10.120+gitAUTOINC+95b90aa828-g95b90aa828/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
+++ b/psdkla/board-support/linux-5.10.120+gitAUTOINC+95b90aa828-g95b90aa828/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
@@ -94,9 +94,9 @@
 	};
 
 	sound0: sound@0 {
+		status = "disabled";
 		compatible = "ti,j721e-cpb-audio";
 		model = "j721e-cpb";
-
 		ti,cpb-mcasp = <&mcasp10>;
 		ti,cpb-codec = <&pcm3168a_1>;
 
@@ -139,7 +139,7 @@
 		compatible = "ti,j721e-cpsw-virt-mac";
 		dma-coherent;
 		ti,psil-base = <0x4a00>;
-		ti,remote-name = "mpu_1_0_ethmac-device-1";
+		ti,remote-name = "mpu_1_0_ethmac-device-6";
 
 		dmas = <&main_udmap 0xca00>,
 		       <&main_udmap 0xca01>,
@@ -161,6 +161,7 @@
 	};
 
 	transceiver1: can-phy0 {
+		status = "disabled";
 		compatible = "ti,tcan1043";
 		#phy-cells = <0>;
 		max-bitrate = <5000000>;
@@ -171,6 +172,7 @@
 	};
 
 	transceiver2: can-phy1 {
+		status = "disabled";
 		compatible = "ti,tcan1042";
 		#phy-cells = <0>;
 		max-bitrate = <5000000>;
@@ -180,6 +182,7 @@
 	};
 
 	transceiver3: can-phy2 {
+		status = "disabled";
 		compatible = "ti,tcan1043";
 		#phy-cells = <0>;
 		max-bitrate = <5000000>;
@@ -188,6 +191,7 @@
 	};
 
 	transceiver4: can-phy3 {
+		status = "disabled";
 		compatible = "ti,tcan1042";
 		#phy-cells = <0>;
 		max-bitrate = <5000000>;
@@ -252,7 +256,6 @@
 	main_usbss0_pins_default: main-usbss0-pins-default {
 		pinctrl-single,pins = <
 			J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
-			J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
 		>;
 	};
 
@@ -311,11 +314,8 @@
 
 	mcasp10_pins_default: mcasp10-pins-default {
 		pinctrl-single,pins = <
-			J721E_IOPAD(0x158, PIN_OUTPUT_PULLDOWN, 12) /* (U23) RGMII5_TX_CTL.MCASP10_ACLKX */
 			J721E_IOPAD(0x15c, PIN_OUTPUT_PULLDOWN, 12) /* (U26) RGMII5_RX_CTL.MCASP10_AFSX */
 			J721E_IOPAD(0x160, PIN_OUTPUT_PULLDOWN, 12) /* (V28) RGMII5_TD3.MCASP10_AXR0 */
-			J721E_IOPAD(0x164, PIN_OUTPUT_PULLDOWN, 12) /* (V29) RGMII5_TD2.MCASP10_AXR1 */
-			J721E_IOPAD(0x170, PIN_OUTPUT_PULLDOWN, 12) /* (U29) RGMII5_TXC.MCASP10_AXR2 */
 			J721E_IOPAD(0x174, PIN_OUTPUT_PULLDOWN, 12) /* (U25) RGMII5_RXC.MCASP10_AXR3 */
 			J721E_IOPAD(0x198, PIN_INPUT_PULLDOWN, 12) /* (V25) RGMII6_TD1.MCASP10_AXR4 */
 			J721E_IOPAD(0x19c, PIN_INPUT_PULLDOWN, 12) /* (W27) RGMII6_TD0.MCASP10_AXR5 */
@@ -494,7 +494,7 @@
 	non-removable;
 	ti,driver-strength-ohm = <50>;
 	disable-wp;
-	mmc-hs400-1_8v;
+	mmc-hs200-1_8v;
 };
 
 &main_sdhci1 {
@@ -527,7 +527,7 @@
 };
 
 &serdes_wiz3 {
-	typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>;
+	typec-dir-gpios = <&main_gpio1 29 GPIO_ACTIVE_HIGH>;
 	typec-dir-debounce-ms = <700>;	/* TUSB321, tCCB_DEFAULT 133 ms */
 };
 
@@ -544,11 +544,12 @@
 &usbss0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&main_usbss0_pins_default>;
-	ti,vbus-divider;
+	/*ti,vbus-divider;*/
+	/*ti,usb2-only;*/
 };
 
 &usb0 {
-	dr_mode = "otg";
+	dr_mode = "host";
 	maximum-speed = "super-speed";
 	phys = <&serdes3_usb_link>;
 	phy-names = "cdns3,usb3-phy";
@@ -781,6 +782,7 @@
 	};
 
 	pcm3168a_1: audio-codec@44 {
+					status = "disabled";
 		compatible = "ti,pcm3168a";
 		reg = <0x44>;
 
@@ -846,7 +848,7 @@
 	 * VP2 - DSI
 	 * VP3 - DPI1
 	 */
-
+	status = "disabled";
 	assigned-clocks = <&k3_clks 152 1>,
 			  <&k3_clks 152 4>,
 			  <&k3_clks 152 9>,
@@ -858,6 +860,7 @@
 };
 
 &dss_ports {
+	status = "disabled";
 	port@0 {
 		reg = <0>;
 
@@ -932,6 +935,7 @@
 };
 
 &mcasp10 {
+	status = "disabled";
 	#sound-dai-cells = <0>;
 
 	pinctrl-names = "default";
diff --git a/psdkra/ethfw/utils/board/src/j721e/board_j721e_evm.c b/psdkra/ethfw/utils/board/src/j721e/board_j721e_evm.c
old mode 100644
new mode 100755
index d547a8773..ba7a915fa
--- a/psdkra/ethfw/utils/board/src/j721e/board_j721e_evm.c
+++ b/psdkra/ethfw/utils/board/src/j721e/board_j721e_evm.c
@@ -191,8 +191,8 @@ extern pinmuxBoardCfg_t gEthFwPinmuxData[];
 /* GPIO Driver board specific pin configuration structure */
 GPIO_PinConfig gEthFw_gpioPinCfgs[] =
 {
-    GPIO_DEVICE_CONFIG(0, 61) | GPIO_CFG_OUTPUT,
-    GPIO_DEVICE_CONFIG(0, 62) | GPIO_CFG_OUTPUT,
+    GPIO_DEVICE_CONFIG(0, 41) | GPIO_CFG_OUTPUT,
+    GPIO_DEVICE_CONFIG(0, 44) | GPIO_CFG_OUTPUT,
 };
 
 /* GPIO Driver callback functions */
@@ -235,7 +235,7 @@ static const Dp83867_Cfg gEnetGesiBoard_dp83867PhyCfg =
 /* 4 x RGMII ports in GESI expansion board */
 static EthFwBoard_MacPortCfg gEthFw_gesiMacPortCfg[] =
 {
-    {   /* "PRG1_RGMII1_B" */
+    /*{   [> "PRG1_RGMII1_B" <]
         .macPort   = ENET_MAC_PORT_1,
         .mii       = { ENET_MAC_LAYER_GMII, ENET_MAC_SUBLAYER_REDUCED },
         .phyCfg    =
@@ -248,8 +248,8 @@ static EthFwBoard_MacPortCfg gEthFw_gesiMacPortCfg[] =
         },
         .sgmiiMode = ENET_MAC_SGMIIMODE_INVALID,
         .linkCfg   = { ENET_SPEED_AUTO, ENET_DUPLEX_AUTO },
-    },
-    {   /* "PRG1_RGMII2_T" */
+    },*/
+    /*{   [> "PRG1_RGMII2_T" <]
         .macPort   = ENET_MAC_PORT_8,
         .mii       = { ENET_MAC_LAYER_GMII, ENET_MAC_SUBLAYER_REDUCED },
         .phyCfg    =
@@ -262,8 +262,8 @@ static EthFwBoard_MacPortCfg gEthFw_gesiMacPortCfg[] =
         },
         .sgmiiMode = ENET_MAC_SGMIIMODE_INVALID,
         .linkCfg   = { ENET_SPEED_AUTO, ENET_DUPLEX_AUTO },
-    },
-    {   /* "PRG0_RGMII1_B" */
+    },*/
+    /*{   [> "PRG0_RGMII1_B" <]
         .macPort   = ENET_MAC_PORT_3,
         .mii       = { ENET_MAC_LAYER_GMII, ENET_MAC_SUBLAYER_REDUCED },
         .phyCfg    =
@@ -276,20 +276,22 @@ static EthFwBoard_MacPortCfg gEthFw_gesiMacPortCfg[] =
         },
         .sgmiiMode = ENET_MAC_SGMIIMODE_INVALID,
         .linkCfg   = { ENET_SPEED_AUTO, ENET_DUPLEX_AUTO },
-    },
+    },*/
     {   /* "PRG0_RGMII02_T" */
-        .macPort   = ENET_MAC_PORT_4,
+        .macPort   = ENET_MAC_PORT_6,
         .mii       = { ENET_MAC_LAYER_GMII, ENET_MAC_SUBLAYER_REDUCED },
         .phyCfg    =
         {
-            .phyAddr         = 3U,
+            .phyAddr         = 7U,
             .isStrapped      = false,
             .skipExtendedCfg = false,
-            .extendedCfg     = &gEnetGesiBoard_dp83867PhyCfg,
-            .extendedCfgSize = sizeof(gEnetGesiBoard_dp83867PhyCfg),
+            //.extendedCfg     = &gEnetGesiBoard_dp83867PhyCfg,
+            //.extendedCfgSize = sizeof(gEnetGesiBoard_dp83867PhyCfg),
+            .extendedCfg     = NULL,
+            .extendedCfgSize = 0U,
         },
-        .sgmiiMode = ENET_MAC_SGMIIMODE_INVALID,
-        .linkCfg   = { ENET_SPEED_AUTO, ENET_DUPLEX_AUTO },
+        //.sgmiiMode = ENET_MAC_SGMIIMODE_INVALID,
+		.linkCfg   = { ENET_SPEED_AUTO, ENET_DUPLEX_AUTO },
     },
 };
 
@@ -581,7 +583,7 @@ static void EthFwBoard_configPinmux(void)
     Board_pinmuxUpdate(gEthFwPinmuxData, BOARD_SOC_DOMAIN_MAIN);
 
     /* Configure pinmux settings for Ethernet ports and MDIO */
-    Board_pinmuxUpdate(gJ721E_MainPinmuxDataGesiCpsw9gQsgmii, BOARD_SOC_DOMAIN_MAIN);
+    Board_pinmuxUpdate( gJ721E_MainPinmuxDataGesiCpsw9g, BOARD_SOC_DOMAIN_MAIN);
 
     /* REVISIT - Configure CPSW9G pins for ports on the GESI board */
     Board_pinmuxGetCfg(&pinmuxCfg);
@@ -604,7 +606,7 @@ static void EthFwBoard_detectDBs(void)
     {
         /* Assume expansion boards are present if detection not allowed */
         gEthFwBoard.gesiDetected  = true;
-        gEthFwBoard.qenetDetected = true;
+        gEthFwBoard.qenetDetected = false;
     }
 }
 
@@ -621,12 +623,16 @@ static void EthFwBoard_configUart(void)
 
 static void EthFwBoard_configGesi(void)
 {
-    if (gEthFwBoard.gpioAllowed)
-    {
+	int i=0;
+	/*if (gEthFwBoard.gpioAllowed)
+	{*/
         GPIO_init();
-        GPIO_write(0, 1);
-        GPIO_write(1, 1);
-    }
+		GPIO_write(0, 0);
+		appLogWaitMsecs(200);
+		GPIO_write(0, 1);
+		appLogWaitMsecs(50);
+		GPIO_write(1, 1);
+	/*}*/
 }
 
 static void EthFwBoard_configQenet(void)
diff --git a/psdkra/pdk_jacinto_08_04_00_21/packages/ti/board/src/j721e_evm/J721E_pinmux_data.c b/psdkra/pdk_jacinto_08_04_00_21/packages/ti/board/src/j721e_evm/J721E_pinmux_data.c
index 72f864696..d9487c674 100755
--- a/psdkra/pdk_jacinto_08_04_00_21/packages/ti/board/src/j721e_evm/J721E_pinmux_data.c
+++ b/psdkra/pdk_jacinto_08_04_00_21/packages/ti/board/src/j721e_evm/J721E_pinmux_data.c
@@ -80,6 +80,11 @@ static pinmuxPerCfg_t gGpio0PinCfg[] =
     {
         PIN_RGMII6_RX_CTL, PIN_MODE(7) | \
         ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+	/* MyGPIO1 -> GPIO0_45 -> AE27 */
+    {
+        PIN_PRG0_PRU0_GPO2, PIN_MODE(7) | \
+        ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))
     },
     /* MyGPIO0 -> GPIO0_117 -> W4 */
     {
@@ -458,10 +463,10 @@ static pinmuxPerCfg_t gMcu_fss0_ospi0PinCfg[] =
 static pinmuxPerCfg_t gMcu_fss0_ospi1PinCfg[] =
 {
     /* MyMCU_OSPI1 -> MCU_OSPI1_CLK -> F22 */
-    {
+    /*{
         PIN_MCU_OSPI1_CLK, PIN_MODE(0) | \
         ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
-    },
+    },*/
     /* MyMCU_OSPI1 -> MCU_OSPI1_CSn0 -> C22 */
     {
         PIN_MCU_OSPI1_CSN0, PIN_MODE(0) | \
@@ -503,7 +508,7 @@ static pinmuxPerCfg_t gMcu_fss0_ospi1PinCfg[] =
 static pinmuxModuleCfg_t gMcu_fss0_ospiPinCfg[] =
 {
     {0, TRUE, gMcu_fss0_ospi0PinCfg},
-    {1, TRUE, gMcu_fss0_ospi1PinCfg},
+    {1, FALSE, gMcu_fss0_ospi1PinCfg},
     {PINMUX_END}
 };
 
diff --git a/psdkra/pdk_jacinto_08_04_00_21/packages/ti/board/src/j721e_evm/J721E_pinmux_data_gesi_cpsw9g.c b/psdkra/pdk_jacinto_08_04_00_21/packages/ti/board/src/j721e_evm/J721E_pinmux_data_gesi_cpsw9g.c
index 28c803502..3226cbf4d 100755
--- a/psdkra/pdk_jacinto_08_04_00_21/packages/ti/board/src/j721e_evm/J721E_pinmux_data_gesi_cpsw9g.c
+++ b/psdkra/pdk_jacinto_08_04_00_21/packages/ti/board/src/j721e_evm/J721E_pinmux_data_gesi_cpsw9g.c
@@ -39,14 +39,15 @@ static pinmuxModuleCfg_t gCpsw9gPinCfg[] =
 
 static pinmuxPerCfg_t gGpio0PinCfg[] =
 {
-    /* MyGPIO0 -> GPIO0_96 -> T23 */
+    /* MyGPIO1 -> GPIO0_41 -> AD19 */
     {
-        PIN_RGMII5_RD0, PIN_MODE(7) | \
+        PIN_PRG1_MDIO0_MDIO, PIN_MODE(7) | \
         ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
     },
-    /* MyGPIO0 -> GPIO0_104 -> W26 */
+
+	/* MyGPIO1 -> GPIO0_44 -> AE28 */
     {
-        PIN_RGMII6_RXC, PIN_MODE(7) | \
+        PIN_PRG0_PRU0_GPO1, PIN_MODE(7) | \
         ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
     },
     {PINMUX_END}
@@ -61,16 +62,16 @@ static pinmuxModuleCfg_t gGpioPinCfg[] =
 
 static pinmuxPerCfg_t gMdio0PinCfg[] =
 {
-    /* MyMDIO1 -> MDIO0_MDC -> V24 */
-    {
-        PIN_MDIO0_MDC, PIN_MODE(0) | \
-        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
-    },
     /* MyMDIO1 -> MDIO0_MDIO -> V26 */
     {
         PIN_MDIO0_MDIO, PIN_MODE(0) | \
         ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
     },
+    /* MyMDIO1 -> MDIO0_MDC -> V24 */
+    {
+        PIN_MDIO0_MDC, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
     {PINMUX_END}
 };
 
@@ -471,15 +472,88 @@ static pinmuxPerCfg_t gRgmii8PinCfg[] =
     {PINMUX_END}
 };
 
-static pinmuxModuleCfg_t gRgmiiPinCfg[] =
+static pinmuxPerCfg_t gRgmii6PinCfg[] =
+{
+    /* MyRGMII1 -> RGMII6_RD0 -> W25 */
+    {
+        PIN_RGMII6_RD0, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyRGMII1 -> RGMII6_RD1 -> W24 */
+    {
+        PIN_RGMII6_RD1, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyRGMII1 -> RGMII6_RD2 -> Y27 */
+    {
+        PIN_RGMII6_RD2, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyRGMII1 -> RGMII6_RD3 -> Y29 */
+    {
+        PIN_RGMII6_RD3, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyRGMII1 -> RGMII6_RXC -> W26 */
+    {
+        PIN_RGMII6_RXC, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyRGMII1 -> RGMII6_RX_CTL -> V23 */
+    {
+        PIN_RGMII6_RX_CTL, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyRGMII1 -> RGMII6_TD0 -> W27 */
+    {
+        PIN_RGMII6_TD0, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+    /* MyRGMII1 -> RGMII6_TD1 -> V25 */
+    {
+        PIN_RGMII6_TD1, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+    /* MyRGMII1 -> RGMII6_TD2 -> W28 */
+    {
+        PIN_RGMII6_TD2, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+    /* MyRGMII1 -> RGMII6_TD3 -> W23 */
+    {
+        PIN_RGMII6_TD3, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+    /* MyRGMII1 -> RGMII6_TXC -> W29 */
+    {
+        PIN_RGMII6_TXC, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+    /* MyRGMII1 -> RGMII6_TX_CTL -> Y28 */
+    {
+        PIN_RGMII6_TX_CTL, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+    {PINMUX_END}
+};
+
+
+/*static pinmuxModuleCfg_t gRgmiiPinCfg[] =
 {
     {3, TRUE, gRgmii3PinCfg},
     {4, TRUE, gRgmii4PinCfg},
     {1, TRUE, gRgmii1PinCfg},
     {2, TRUE, gRgmii2PinCfg},
     {PINMUX_END}
-};
+};*/
 
+static pinmuxModuleCfg_t g_MtRgmiiPinCfg[] =
+{
+	{3, FALSE, gRgmii3PinCfg},
+	{6, TRUE, gRgmii6PinCfg},
+	{2, FALSE, gRgmii2PinCfg},
+    {PINMUX_END}
+};
 
 static pinmuxModuleCfg_t gSgmiiPinCfg[] =
 {
@@ -563,7 +637,8 @@ pinmuxBoardCfg_t gJ721E_MainPinmuxDataGesiCpsw9g[] =
     {0, gCpsw9gPinCfg},
     {1, gGpioPinCfg},
     {2, gMdioPinCfg},
-    {3, gRgmiiPinCfg},
+    /*{3, gRgmiiPinCfg},*/
+	{3,  g_MtRgmiiPinCfg},
     {4, gRmiiPinCfg},
     {PINMUX_END}
 };
diff --git a/psdkra/pdk_jacinto_08_04_00_21/packages/ti/board/src/j721e_evm/board_ethernet_config.c b/psdkra/pdk_jacinto_08_04_00_21/packages/ti/board/src/j721e_evm/board_ethernet_config.c
index 575b2e2db..0a3812e52 100755
--- a/psdkra/pdk_jacinto_08_04_00_21/packages/ti/board/src/j721e_evm/board_ethernet_config.c
+++ b/psdkra/pdk_jacinto_08_04_00_21/packages/ti/board/src/j721e_evm/board_ethernet_config.c
@@ -709,11 +709,12 @@ Board_STATUS Board_ethConfigCpsw9g(void)
     /* Configures the CPSW9G RGMII ports */
     for(portNum=0; portNum < BOARD_CPSW9G_PORT_MAX; portNum++)
     {
-        if ( 0U == portNum ||
-             2U == portNum ||
-             3U == portNum ||
-             7U == portNum )
+        if ( 0U == portNum )
         {
+            status = Board_cpsw9gEthConfig(portNum, RMII);
+        }
+		else if( 7u == portNum)
+		{
             status = Board_cpsw9gEthConfig(portNum, RGMII);
         }
         else
diff --git a/psdkra/pdk_jacinto_08_04_00_21/packages/ti/drv/enet/enet_cfg.h b/psdkra/pdk_jacinto_08_04_00_21/packages/ti/drv/enet/enet_cfg.h
old mode 100644
new mode 100755
index 4e0528f98..276fe85f5
--- a/psdkra/pdk_jacinto_08_04_00_21/packages/ti/drv/enet/enet_cfg.h
+++ b/psdkra/pdk_jacinto_08_04_00_21/packages/ti/drv/enet/enet_cfg.h
@@ -89,7 +89,7 @@ extern "C" {
 /* --------------------------------------------------------------------------*/
 
 /*! \brief CPSW Q/SGMII support (requires #ENET_CFG_CPSW_MACPORT_SGMII). */
-#define ENET_CFG_CPSW_SGMII                         (ENET_ON)
+//#define ENET_CFG_CPSW_SGMII                         (ENET_ON)
 
 /*! \brief CPSW interVLAN support support (requires #ENET_CFG_CPSW_MACPORT_INTERVLAN). */
 #define ENET_CFG_CPSW_INTERVLAN                     (ENET_ON)
diff --git a/psdkra/pdk_jacinto_08_04_00_21/packages/ti/drv/enet/include/phy/dummy.h b/psdkra/pdk_jacinto_08_04_00_21/packages/ti/drv/enet/include/phy/dummy.h
new file mode 100755
index 000000000..0305d7072
--- /dev/null
+++ b/psdkra/pdk_jacinto_08_04_00_21/packages/ti/drv/enet/include/phy/dummy.h
@@ -0,0 +1,104 @@
+/*
+ *  Copyright (c) Texas Instruments Incorporated 2020
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*!
+ * \file  tja1101.h
+ *
+ * \brief This file contains the type definitions and helper macros for the
+ *        TJA1101 Ethernet PHY.
+ */
+
+/*!
+ * \ingroup  DRV_ENETPHY
+ * \defgroup ENETPHY_TJA1101 TI TJA1101 PHY
+ *
+ * TI TJA1101 RMII Ethernet PHY.
+ *
+ * @{
+ */
+
+#ifndef DUMMY_H_
+#define DUMMY_H_
+
+/* ========================================================================== */
+/*                             Include Files                                  */
+/* ========================================================================== */
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ========================================================================== */
+/*                                 Macros                                     */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/*                         Structures and Enums                               */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/*                         Global Variables Declarations                      */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/*                          Function Declarations                             */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/*                        Deprecated Function Declarations                    */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/*                       Static Function Definitions                          */
+/* ========================================================================== */
+
+/* None */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* TJA1101_H_ */
+
+/* @} */
diff --git a/psdkra/pdk_jacinto_08_04_00_21/packages/ti/drv/enet/src/phy/dummy.c b/psdkra/pdk_jacinto_08_04_00_21/packages/ti/drv/enet/src/phy/dummy.c
new file mode 100755
index 000000000..24ef8b622
--- /dev/null
+++ b/psdkra/pdk_jacinto_08_04_00_21/packages/ti/drv/enet/src/phy/dummy.c
@@ -0,0 +1,215 @@
+/*
+ *  Copyright (c) Texas Instruments Incorporated 2020
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*!
+ * \file  Dummy.c
+ *
+ * \brief This file contains the implementation of the Dummy PHY.
+ */
+
+/* ========================================================================== */
+/*                             Include Files                                  */
+/* ========================================================================== */
+
+#include <stdint.h>
+#include <ti/drv/enet/include/core/enet_utils.h>
+#include <ti/drv/enet/priv/core/enet_trace_priv.h>
+#include <ti/drv/enet/include/phy/enetphy.h>
+#include <ti/drv/enet/include/phy/dummy.h>
+#include "enetphy_priv.h"
+#include "generic_phy.h"
+/*#include "Dummy_priv.h"*/
+
+/* ========================================================================== */
+/*                           Macros & Typedefs                                */
+/* ========================================================================== */
+
+#define Dummy_OUI                           (0x6037U)
+#define Dummy_MODEL                         (0x10U)
+#define Dummy_REV                           (0x2U)
+
+/* ========================================================================== */
+/*                         Structure Declarations                             */
+/* ========================================================================== */
+
+static bool Dummy_isPhyDevSupported(EnetPhy_Handle hPhy,
+                                      const EnetPhy_Version *version);
+
+static bool Dummy_isMacModeSupported(EnetPhy_Handle hPhy,
+                                       EnetPhy_Mii mii);
+
+static int32_t Dummy_config(EnetPhy_Handle hPhy,
+                              const EnetPhy_Cfg *cfg,
+                              EnetPhy_Mii mii);
+
+void Dummy_reset(EnetPhy_Handle hPhy);
+
+bool Dummy_isResetComplete(EnetPhy_Handle hPhy);
+
+static void Dummy_printRegs(EnetPhy_Handle hPhy);
+
+/* ========================================================================== */
+/*                          Function Declarations                             */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/*                            Global Variables                                */
+/* ========================================================================== */
+
+EnetPhy_Drv gEnetPhyDrvDummy =
+{
+    .name               = "Dummy",
+    .isPhyDevSupported  = Dummy_isPhyDevSupported,
+    .isMacModeSupported = Dummy_isMacModeSupported,
+    .config             = Dummy_config,
+    .reset              = Dummy_reset,
+    .isResetComplete    = Dummy_isResetComplete,
+    .readExtReg         = GenericPhy_readExtReg,
+    .writeExtReg        = GenericPhy_writeExtReg,
+    .printRegs          = Dummy_printRegs,
+};
+
+/* ========================================================================== */
+/*                          Function Definitions                              */
+/* ========================================================================== */
+
+static bool Dummy_isPhyDevSupported(EnetPhy_Handle hPhy,
+                                      const EnetPhy_Version *version)
+{
+    /*bool supported = false;*/
+    bool supported = true;
+
+    /*if ((version->oui == Dummy_OUI) &&
+        (version->model == Dummy_MODEL) &&
+        (version->revision == Dummy_REV))
+    {
+        supported = true;
+    }*/
+
+    return supported;
+}
+
+static bool Dummy_isMacModeSupported(EnetPhy_Handle hPhy,
+                                       EnetPhy_Mii mii)
+{
+    bool supported = true;
+
+    /*switch (mii)
+    {
+        case ENETPHY_MAC_MII_RMII:
+            supported = true;
+            break;
+
+        [> This driver doesn't support MII and RGMII interfaces,
+         * but the Dummy PHY does support them <]
+        case ENETPHY_MAC_MII_MII:
+        case ENETPHY_MAC_MII_RGMII:
+        default:
+            supported = false;
+            break;
+    }*/
+
+    return supported;
+}
+
+static int32_t Dummy_config(EnetPhy_Handle hPhy,
+                              const EnetPhy_Cfg *cfg,
+                              EnetPhy_Mii mii)
+{
+	uint16_t i;
+    int32_t status = ENETPHY_SOK;
+	uint16_t val;
+	return status;
+
+#if 1
+	if(hPhy->addr == 4)
+    {
+    	/* enable the register RW */
+        EnetPhy_writeReg(hPhy, 17, 0x9804);
+		
+    	/* RMII mode enabled (50 MHz input on REF_CLK) */
+        EnetPhy_writeReg(hPhy, 18, 0xDE05);
+
+		/* 50 MHz input at REF_CLK; RMII mode only; no XTAL; no clock at CLK_IN_OUT */
+		EnetPhy_readReg(hPhy, 27, &val);
+		val &= ~(3 << 12);
+        EnetPhy_writeReg(hPhy, 27, val);
+    }
+#else
+	// not do anything
+#endif
+	/*if( hPhy->addr == 4 )
+	{
+		for(i = 0; i <= 28; i++)
+		{
+			EnetPhy_readReg(hPhy, i, &val);
+			[>ENETTRACE_DBG("PHY %u: register%u	  = 0x%04x\n", hPhy->addr, i, val);<]
+			EnetUtils_printf("PHY %u: register%u	  = 0x%04x\n", hPhy->addr, i, val);
+		}
+	}*/
+
+	return status;
+}
+
+void Dummy_reset(EnetPhy_Handle hPhy)
+{
+	ENETTRACE_DBG("PHY %u: reset\n", hPhy->addr);
+	/*EnetPhy_writeReg(hPhy, 17, 0x9804);*/
+	/* Reset the PHY */
+	/*EnetPhy_rmwReg(hPhy, PHY_BMCR, BMCR_RESET, BMCR_RESET);*/
+}
+
+bool Dummy_isResetComplete(EnetPhy_Handle hPhy)
+{
+    bool complete = true;
+
+    ENETTRACE_DBG("PHY %u: reset is %scomplete\n", hPhy->addr, complete ? "" : "not");
+
+    return complete;
+}
+
+static void Dummy_printRegs(EnetPhy_Handle hPhy)
+{
+    uint32_t phyAddr = hPhy->addr;
+    uint16_t val = 0;
+    EnetUtils_printf("PHY %u: BMCR    = 0x%04x\n", phyAddr, 1);
+    /*EnetPhy_readReg(hPhy, PHY_BMCR, &val);
+    EnetUtils_printf("PHY %u: BMCR    = 0x%04x\n", phyAddr, val);
+    EnetPhy_readReg(hPhy, PHY_BMSR, &val);
+    EnetUtils_printf("PHY %u: BMSR    = 0x%04x\n", phyAddr, val);
+    EnetPhy_readReg(hPhy, PHY_PHYIDR1, &val);
+    EnetUtils_printf("PHY %u: PHYIDR1 = 0x%04x\n", phyAddr, val);
+    EnetPhy_readReg(hPhy, PHY_PHYIDR2, &val);
+    EnetUtils_printf("PHY %u: PHYIDR2 = 0x%04x\n", phyAddr, val);*/
+}
diff --git a/psdkra/pdk_jacinto_08_04_00_21/packages/ti/drv/enet/src/phy/enetphy.c b/psdkra/pdk_jacinto_08_04_00_21/packages/ti/drv/enet/src/phy/enetphy.c
old mode 100644
new mode 100755
index 43a70bc5b..f9ec88328
--- a/psdkra/pdk_jacinto_08_04_00_21/packages/ti/drv/enet/src/phy/enetphy.c
+++ b/psdkra/pdk_jacinto_08_04_00_21/packages/ti/drv/enet/src/phy/enetphy.c
@@ -179,10 +179,12 @@ extern EnetPhy_Drv gEnetPhyDrvGeneric;
 extern EnetPhy_Drv gEnetPhyDrvDp83822;
 extern EnetPhy_Drv gEnetPhyDrvDp83867;
 extern EnetPhy_Drv gEnetPhyDrvVsc8514;
+extern EnetPhy_Drv gEnetPhyDrvDummy;
 
 /*! \brief All the registered PHY specific drivers. */
 static EnetPhyDrv_Handle gEnetPhyDrvs[] =
 {
+    &gEnetPhyDrvDummy,   /*Dummy */
     &gEnetPhyDrvVsc8514,   /* VSC8514 */
     &gEnetPhyDrvDp83822,   /* DP83822 */
     &gEnetPhyDrvDp83867,   /* DP83867 */
@@ -311,7 +313,10 @@ EnetPhy_Handle EnetPhy_open(const EnetPhy_Cfg *phyCfg,
         /* Take a shortcut to FOUND state if PHY is already alive, will save some
          * hundreds of msecs.  Take a shorter shortcut to LINK_WAIT state if PHY
          * is strap configured */
-        alive = EnetPhy_isAlive(hPhy);
+		if(hPhy->addr == 7)
+			alive = true;
+		else
+			alive = EnetPhy_isAlive(hPhy);
         if (alive)
         {
             EnetPhy_initState(hPhy);
@@ -506,13 +511,22 @@ bool EnetPhy_isAlive(EnetPhy_Handle hPhy)
     /* Get PHY alive status */
     if (hMdio->isAlive != NULL)
     {
-        /* Get alive status from MDIO driver (i.e. hardware assisted) */
-        status = hMdio->isAlive(phyAddr, &isAlive, hPhy->mdioArgs);
-        ENETTRACE_ERR_IF(status != ENETPHY_SOK,
-                         "PHY %u: Failed to get alive status: %d\n", phyAddr, status);
+		ENETTRACE_ERR_IF(true,"jinmin----- in 1\n");
+		if(hPhy->addr == 7)
+			return true;
+		else
+		{
+			/* Get alive status from MDIO driver (i.e. hardware assisted) */
+			status = hMdio->isAlive(phyAddr, &isAlive, hPhy->mdioArgs);
+			ENETTRACE_ERR_IF(status != ENETPHY_SOK,
+					"PHY %u: Failed to get alive status: %d\n", phyAddr, status);
+		}
     }
     else
     {
+		ENETTRACE_ERR_IF(true,"jinmin----- in 2\n");
+		if(hPhy->addr == 7)
+			return true;
         /* Alternatively, read BMSR - PHY is alive if transaction is successful */
         status = hMdio->readC22(phyGroup, phyAddr, PHY_BMSR, &val, hPhy->mdioArgs);
         ENETTRACE_ERR_IF(status != ENETPHY_SOK,
@@ -541,21 +555,21 @@ int32_t EnetPhy_getId(EnetPhy_Handle hPhy,
         status = ENETPHY_EFAIL;
     }
 
-    if (status == ENETPHY_SOK)
+    if (status == ENETPHY_SOK && hPhy->addr !=7)
     {
         status = EnetPhy_readReg(hPhy, PHY_PHYIDR1, &id1);
         ENETTRACE_ERR_IF(status != ENETPHY_SOK,
                          "PHY %u: Failed to read ID1 register: %d\n", phyAddr, status);
     }
 
-    if (status == ENETPHY_SOK)
+    if (status == ENETPHY_SOK && hPhy->addr !=7)
     {
         status = EnetPhy_readReg(hPhy, PHY_PHYIDR2, &id2);
         ENETTRACE_ERR_IF(status != ENETPHY_SOK,
                          "PHY %u: Failed to read ID2 register: %d\n", phyAddr, status);
     }
 
-    if (status == ENETPHY_SOK)
+    if (status == ENETPHY_SOK && hPhy->addr !=7)
     {
         version->oui      = ((uint32_t)id1 << PHYIDR1_OUI_OFFSET);
         version->oui     |= (id2 & PHYIDR2_OUI_MASK)  >> PHYIDR2_OUI_OFFSET;
@@ -563,6 +577,13 @@ int32_t EnetPhy_getId(EnetPhy_Handle hPhy,
         version->revision = (id2 & PHYIDR2_VREV_MASK) >> PHYIDR2_VREV_OFFSET;
     }
 
+	if(hPhy->addr == 7)
+	{
+		version->oui=0x6038;
+		version->model=0x11;
+		version->revision=0x2;
+	}
+
     return status;
 }
 
@@ -943,9 +964,18 @@ static void EnetPhy_initState(EnetPhy_Handle hPhy)
 {
     EnetPhy_State *state = &hPhy->state;
 
-    state->speed = ENETPHY_SPEED_10MBIT;
-    state->duplexity = ENETPHY_DUPLEX_HALF;
-    state->phyLinkCaps = 0U;
+	if(hPhy->addr == 7)
+	{
+		state->speed = ENETPHY_SPEED_1GBIT;
+		state->duplexity = ENETPHY_DUPLEX_FULL;
+		state->phyLinkCaps = 0U;
+	}
+	else
+	{
+		state->speed = ENETPHY_SPEED_10MBIT;
+		state->duplexity = ENETPHY_DUPLEX_HALF;
+		state->phyLinkCaps = 0U;
+	}
 
     if (hPhy->phyCfg.isStrapped)
     {
@@ -1069,8 +1099,9 @@ static void EnetPhy_enableState(EnetPhy_Handle hPhy)
 
     /* Enable PHY (resetting it if applicable) can be done only when
      * entering the ENABLE state for the first time */
-    if (state->needsNwayCfg ||
-        state->needsManualCfg)
+    if ((state->needsNwayCfg ||
+        state->needsManualCfg) && 
+		(hPhy->addr != 7))
     {
         /* Set PHY in normal mode */
         ENETTRACE_DBG("PHY %u: enable\n", hPhy->addr);
@@ -1088,7 +1119,12 @@ static void EnetPhy_enableState(EnetPhy_Handle hPhy)
     ENETTRACE_DBG("PHY %u: req caps: %s\n",
                   hPhy->addr, EnetPhy_getCapsString(hPhy->reqLinkCaps));
 
-    state->phyLinkCaps = EnetPhy_getLocalCaps(hPhy);
+
+	if (hPhy->addr == 7)
+		state->phyLinkCaps =  ENETPHY_LINK_CAP_FD1000;
+	else
+		state->phyLinkCaps = EnetPhy_getLocalCaps(hPhy);
+	ENETTRACE_DBG("jinmin-------- 1\n");
     ENETTRACE_DBG("PHY %u: PHY caps: %s\n",
                   hPhy->addr, EnetPhy_getCapsString(state->phyLinkCaps));
 
@@ -1108,7 +1144,11 @@ static void EnetPhy_enableState(EnetPhy_Handle hPhy)
 
         /* Enable NWAY if requested by app (via auto-speed or auto-duplex) and
          * supported by PHY */
+		if(hPhy->addr!=7)
         state->isNwayCapable = EnetPhy_isNwayCapable(hPhy);
+		else
+			state->isNwayCapable = false;
+
         ENETTRACE_DBG("PHY %u: PHY is %sNWAY-capable\n",
                       hPhy->addr, state->isNwayCapable ? "" : "not ");
 
@@ -1268,6 +1308,7 @@ static void EnetPhy_setupManual(EnetPhy_Handle hPhy,
             val |= BMCR_LOOPBACK;
         }
 
+		if(hPhy->addr !=7 )
         EnetPhy_rmwReg(hPhy, PHY_BMCR,
                        BMCR_LOOPBACK | BMCR_SPEED1000 | BMCR_SPEED100 | BMCR_FD,
                        val);
@@ -1393,8 +1434,10 @@ static void EnetPhy_linkWaitState(EnetPhy_Handle hPhy)
     EnetPhy_State *state = &hPhy->state;
     uint32_t nwayCaps;
     uint16_t status;
-
-    EnetPhy_readReg(hPhy, PHY_BMSR, &status);
+	
+	if(hPhy->addr != 7)
+	{
+		EnetPhy_readReg(hPhy, PHY_BMSR, &status);
 
     if ((status & BMSR_LINKSTS) != 0U)
     {
@@ -1425,6 +1468,9 @@ static void EnetPhy_linkWaitState(EnetPhy_Handle hPhy)
             EnetPhy_phyTimeout(hPhy);
         }
     }
+	}
+	else
+        EnetPhy_setNextState(hPhy, ENETPHY_FSM_STATE_LINKED);
 }
 
 static void EnetPhy_linkedState(EnetPhy_Handle hPhy)
@@ -1648,7 +1694,8 @@ static bool EnetPhy_isPhyLinked(EnetPhy_Handle hPhy)
     bool isLinked = false;
     uint16_t val = 0U;
     int32_t status;
-
+	if(hPhy->addr==7)
+		return true;
     /* Get PHY link status */
     if (hMdio->isLinked != NULL)
     {
diff --git a/psdkra/pdk_jacinto_08_04_00_21/packages/ti/drv/enet/src/phy/makefile b/psdkra/pdk_jacinto_08_04_00_21/packages/ti/drv/enet/src/phy/makefile
old mode 100644
new mode 100755
index f4c3b7233..adc42cc39
--- a/psdkra/pdk_jacinto_08_04_00_21/packages/ti/drv/enet/src/phy/makefile
+++ b/psdkra/pdk_jacinto_08_04_00_21/packages/ti/drv/enet/src/phy/makefile
@@ -19,7 +19,7 @@ INCLUDE_INTERNAL_INTERFACES =
 
 # Common source files and CFLAGS across all platforms and cores
 SRCS_COMMON += enetphy.c generic_phy.c
-SRCS_COMMON += dp83867.c dp83822.c vsc8514.c
+SRCS_COMMON += dp83867.c dp83822.c vsc8514.c  dummy.c
 
 PACKAGE_SRCS_COMMON = $(SRCDIR)
 CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS) $(ENET_CFLAGS)
diff --git a/psdkra/vision_apps/tja_dummy.diff b/psdkra/vision_apps/tja_dummy.diff
new file mode 100644
index 000000000..070b5ce58
--- /dev/null
+++ b/psdkra/vision_apps/tja_dummy.diff
@@ -0,0 +1,50 @@
+diff --git a/psdkra/vision_apps/utils/ethfw/src/app_ethfw_freertos.c b/psdkra/vision_apps/utils/ethfw/src/app_ethfw_freertos.c
+index cc484978a..796a24a0b 100644
+--- a/psdkra/vision_apps/utils/ethfw/src/app_ethfw_freertos.c
++++ b/psdkra/vision_apps/utils/ethfw/src/app_ethfw_freertos.c
+@@ -129,10 +129,11 @@ static Enet_MacPort gEthAppPorts[] =
+ #if defined(SOC_J721E)
+     /* On J721E EVM to use all 8 ports simultaneously, we use below configuration
+        RGMII Ports - 1,3,4,8. QSGMII ports - 2,5,6,7 */
+-    ENET_MAC_PORT_1, /* RGMII */
+-    ENET_MAC_PORT_3, /* RGMII */
+-    ENET_MAC_PORT_4, /* RGMII */
+-    ENET_MAC_PORT_8, /* RGMII */
++    /*ENET_MAC_PORT_1, [> RGMII <]
++    ENET_MAC_PORT_3, [> RGMII <]
++    ENET_MAC_PORT_4, [> RGMII <]
++    ENET_MAC_PORT_8, [> RGMII <]*/
++    ENET_MAC_PORT_6,
+ #if defined(ENABLE_QSGMII_PORTS)
+     ENET_MAC_PORT_2, /* QSGMII main */
+     ENET_MAC_PORT_5, /* QSGMII sub */
+@@ -149,22 +150,22 @@ static Enet_MacPort gEthAppPorts[] =
+ 
+ static EthFw_VirtPortCfg gEthApp_virtPortCfg[] =
+ {
+-    {
++    /*{
+         .remoteCoreId = IPC_MPU1_0,
+         .portId       = ETHREMOTECFG_SWITCH_PORT_0,
+-    },
+-    {
++    },*/
++    /*{
+         .remoteCoreId = IPC_MCU2_1,
+         .portId       = ETHREMOTECFG_SWITCH_PORT_1,
+-    },
++    },*/
+     {
+         .remoteCoreId = IPC_MPU1_0,
+-        .portId       = ETHREMOTECFG_MAC_PORT_1,
++        .portId       = ETHREMOTECFG_MAC_PORT_6,
+     },
+-    {
++    /*{
+         .remoteCoreId = IPC_MCU2_1,
+         .portId       = ETHREMOTECFG_MAC_PORT_4,
+-    },
++    },*/
+ };
+ 
+ static EthFw_VirtPortCfg gEthApp_autosarVirtPortCfg[] =
diff --git a/psdkra/vision_apps/utils/ethfw/src/app_ethfw_freertos.c b/psdkra/vision_apps/utils/ethfw/src/app_ethfw_freertos.c
index cc484978a..796a24a0b 100644
--- a/psdkra/vision_apps/utils/ethfw/src/app_ethfw_freertos.c
+++ b/psdkra/vision_apps/utils/ethfw/src/app_ethfw_freertos.c
@@ -129,10 +129,11 @@ static Enet_MacPort gEthAppPorts[] =
 #if defined(SOC_J721E)
     /* On J721E EVM to use all 8 ports simultaneously, we use below configuration
        RGMII Ports - 1,3,4,8. QSGMII ports - 2,5,6,7 */
-    ENET_MAC_PORT_1, /* RGMII */
-    ENET_MAC_PORT_3, /* RGMII */
-    ENET_MAC_PORT_4, /* RGMII */
-    ENET_MAC_PORT_8, /* RGMII */
+    /*ENET_MAC_PORT_1, [> RGMII <]
+    ENET_MAC_PORT_3, [> RGMII <]
+    ENET_MAC_PORT_4, [> RGMII <]
+    ENET_MAC_PORT_8, [> RGMII <]*/
+    ENET_MAC_PORT_6,
 #if defined(ENABLE_QSGMII_PORTS)
     ENET_MAC_PORT_2, /* QSGMII main */
     ENET_MAC_PORT_5, /* QSGMII sub */
@@ -149,22 +150,22 @@ static Enet_MacPort gEthAppPorts[] =
 
 static EthFw_VirtPortCfg gEthApp_virtPortCfg[] =
 {
-    {
+    /*{
         .remoteCoreId = IPC_MPU1_0,
         .portId       = ETHREMOTECFG_SWITCH_PORT_0,
-    },
-    {
+    },*/
+    /*{
         .remoteCoreId = IPC_MCU2_1,
         .portId       = ETHREMOTECFG_SWITCH_PORT_1,
-    },
+    },*/
     {
         .remoteCoreId = IPC_MPU1_0,
-        .portId       = ETHREMOTECFG_MAC_PORT_1,
+        .portId       = ETHREMOTECFG_MAC_PORT_6,
     },
-    {
+    /*{
         .remoteCoreId = IPC_MCU2_1,
         .portId       = ETHREMOTECFG_MAC_PORT_4,
-    },
+    },*/
 };
 
 static EthFw_VirtPortCfg gEthApp_autosarVirtPortCfg[] =
