Starting MMC/SD memory card driver... eMMC Starting MMC/SD memory card driver... SD Setting environment variables... done.. CMD 0, flgs 0x1, arg 0x0, blks 0, blksz 0, timeout 1000ms CMD 0 cmplt status SUCCESS (1) CMD 8, flgs 0x152, arg 0x1aa, blks 0, blksz 0, timeout 1000ms CMD 8 cmplt status SUCCESS (1) CMD 55, flgs 0x151, arg 0x0, blks 0, blksz 0, timeout 1000ms CMD 55 cmplt status SUCCESS (1) CMD 41, flgs 0x812, arg 0x0, blks 0, blksz 0, timeout 1000ms CMD 0, flgs 0x1, arg 0x0, blks 0, blksz 0, timeout 1000ms CMD 0 cmplt status SUCCESS (1) CMD 1, flgs 0x12, arg 0x0, blks 0, blksz 0, timeout 1000ms CMD 41 cmplt status SUCCESS (1) CMD 8, flgs 0x152, arg 0x1aa, blks 0, blksz 0, timeout 1000ms CMD 1 cmplt status SUCCESS (1) CMD 0, flgs 0x1, arg 0x0, blks 0, blksz 0, timeout 1000ms CMD 8 cmplt status SUCCESS (1) CMD 0, flgs 0x1, arg 0x0, blks 0, blksz 0, timeout 1000ms CMD 0 cmplt status SUCCESS (1) CMD 1, flgs 0x12, arg 0x40000080, blks 0, blksz 0, timeout 1000ms CMD 0 cmplt status SUCCESS (1) CMD 8, flgs 0x152, arg 0x1aa, blks 0, blksz 0, timeout 1000ms CMD 1 cmplt status SUCCESS (1) CMD 8 cmplt status SUCCESS (1) CMD 55, flgs 0x151, arg 0x0, blks 0, blksz 0, timeout 1000ms CMD 55 cmplt status SUCCESS (1) CMD 41, flgs 0x812, arg 0x40100000, blks 0, blksz 0, timeout 1000ms CMD 41 cmplt status SUCCESS (1) CMD 55, flgs 0x151, arg 0x0, blks 0, blksz 0, timeout 1000ms CMD 1, flgs 0x12, arg 0x40000080, blks 0, blksz 0, timeout 1000ms CMD 55 cmplt status SUCCESS (1) CMD 1 cmplt status SUCCESS (1) CMD 41, flgs 0x812, arg 0x40100000, blks 0, blksz 0, timeout 1000ms CMD 2, flgs 0x72, arg 0x0, blks 0, blksz 0, timeout 1000ms CMD 41 cmplt status SUCCESS (1) CMD 2, flgs 0x72, arg 0x0, blks 0, blksz 0, timeout 1000ms CMD 2 cmplt status SUCCESS (1) CMD 3, flgs 0x154, arg 0x10000, blks 0, blksz 0, timeout 1000ms CMD 2 cmplt status SUCCESS (1) CMD 3 cmplt status SUCCESS (1) CMD 3, flgs 0x152, arg 0x0, blks 0, blksz 0, timeout 1000ms CMD 9, flgs 0x74, arg 0x10000, blks 0, blksz 0, timeout 1000ms CMD 3 cmplt status SUCCESS (1) CMD 9, flgs 0x74, arg 0x59b40000, blks 0, blksz 0, timeout 1000ms CMD 9 cmplt status SUCCESS (1) CMD 7, flgs 0x154, arg 0x10000, blks 0, blksz 0, timeout 1000ms CMD 9 cmplt status SUCCESS (1) CMD 7, flgs 0x154, arg 0x59b40000, blks 0, blksz 0, timeout 1000ms CMD 7 cmplt status SUCCESS (1) CMD 8, flgs 0x358, arg 0x0, blks 1, blksz 512, timeout 1000ms CMD 7 cmplt status SUCCESS (1) CMD 55, flgs 0x152, arg 0x59b40000, blks 0, blksz 0, timeout 1000ms CMD 55 cmplt status SUCCESS (1) CMD 51, flgs 0xb58, arg 0x0, blks 1, blksz 8, timeout 1000ms CMD 51 cmplt status SUCCESS (1) CMD 55, flgs 0x152, arg 0x59b40000, blks 0, blksz 0, timeout 1000ms CMD 55 cmplt status SUCCESS (1) CMD 13, flgs 0xb58, arg 0x0, blks 1, blksz 64, timeout 1000ms CMD 13 cmplt status SUCCESS (1) CMD 6, flgs 0x358, arg 0xffffff, blks 1, blksz 64, timeout 1000ms CMD 6 cmplt status SUCCESS (1) CMD 6, flgs 0x358, arg 0x80fffff1, blks 1, blksz 64, timeout 1000ms CMD 6 cmplt status SUCCESS (1) CMD 55, flgs 0x152, arg 0x59b40000, blks 0, blksz 0, timeout 1000ms CMD 55 cmplt status SUCCESS (1) CMD 6, flgs 0x954, arg 0x2, blks 0, blksz 0, timeout 1000ms CMD 6 cmplt status SUCCESS (1) CMD 16, flgs 0x154, arg 0x200, blks 0, blksz 0, timeout 1000ms CMD 16 cmplt status SUCCESS (1) CMD 17, flgs 0x358, arg 0x0, blks 1, blksz 512, timeout 60000ms CMD 17 cmplt status SUCCESS (1) CMD 8 cmplt status SUCCESS (1) CMD 18, flgs 0x2000358, arg 0x0, blks 8, blksz 512, timeout 10000ms CMD 6, flgs 0x1d4, arg 0x3af0101, blks 0, blksz 0, timeout 1000ms CMD 6 cmplt status SUCCESS (1) CMD 18 cmplt status SUCCESS (1) CMD 13, flgs 0x154, arg 0x10000, blks 0, blksz 0, timeout 1000ms CMD 13 cmplt status SUCCESS (1) CMD 6, flgs 0x1d4, arg 0x3a10101, blks 0, blksz 0, timeout 1000ms CMD 6 cmplt status SUCCESS (1) CMD 13, flgs 0x154, arg 0x10000, blks 0, blksz 0, timeout 1000ms CMD 13 cmplt status SUCCESS (1) Ruifeng Set LS mode SDMMC_SS_PHY_CTRL4 & SDMMC_SS_PHY_CTRL5. Ruifeng Set SDMMC_SS_PHY_CTRL4 to 0x110 Ruifeng Set SDMMC_SS_PHY_CTRL5 to 0x10007 Ruifeng Begin to set HS200... SDMMC_SS_PHY_CTRL4 physical address = 0x4f8810c SDMMC_SS_PHY_CTRL5 physical address = 0x4f88110 MMCSD0_SS_CFG_base address = 0x4c184ca000 SDMMC_SS_PHY_CTRL1(0x100) = 0x10000 SDMMC_SS_PHY_CTRL4(0x10c) = 0x110 SDMMC_SS_PHY_CTRL5(0x110) = 0x10007 Dump MMCSD0_SS_CFG... [0x000] | 00 4a 41 68 00 00 00 00 | 00 00 00 00 00 00 00 00 | c8 30 10 20 01 c8 ec 64 | 07 04 00 98 00 00 00 00 [0x020] | 00 00 00 00 00 01 00 00 | 04 00 00 00 02 00 00 00 | 04 00 00 00 02 00 00 00 | 01 00 00 00 00 00 00 00 [0x040] | 02 00 00 00 01 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 [0x060] | 00 00 00 80 10 00 00 00 | 00 00 00 00 00 00 00 00 | 08 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 [0x080] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 [0x0a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 [0x0c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 [0x0e0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 [0x100] | 00 00 01 00 00 00 00 00 | ff 10 ff 10 10 01 00 00 | 07 00 01 00 00 00 00 00 | 00 00 00 00 00 00 00 00 [0x120] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | e0 00 00 00 00 00 00 00 MMCSD0_HOST_CONTROL1 physical address = 0x4f80028 MMCSD0_HOST_CONTROL2 physical address = 0x4f8003e MMCSD0_CTL_CFG_base = 0x4c184cb000 MMCSD0_HOST_CONTROL1(0x28) = 0x18 HIGH_SPEED_ENA(0x28 bit[2]) = 0 MMCSD0_HOST_CONTROL2(0x3e) = 0x0 Dump MMCSD0_CTL_CFG... [0x000] | 00 00 00 00 00 72 01 00 | 00 00 01 00 00 00 1a 0d | 00 09 00 00 ff db f6 ff | 03 59 0f 32 01 27 d0 00 [0x020] | 00 00 00 00 f0 00 ff 01 | 18 0b 80 00 07 fa 0e 00 | 00 00 00 00 01 00 0f 03 | ff 07 ff 33 00 00 00 00 [0x040] | 01 c8 ec 7c 07 04 00 98 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 0c 20 04 80 00 00 00 00 [0x060] | 00 01 04 00 02 00 04 00 | 02 00 01 00 00 00 02 00 | 00 00 01 00 00 00 00 00 | 00 00 00 00 00 00 00 00 [0x080] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 [0x0a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 [0x0c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 [0x0e0] | 00 01 10 01 20 01 30 01 | 40 01 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 20 4e 00 00 00 00 04 10 [0x100] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 11 4f 04 00 00 00 11 00 | 00 01 00 20 81 00 00 00 [0x120] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 [0x140] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 [0x160] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 [0x180] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 [0x1a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 [0x1c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 [0x1e0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 [0x200] | 10 05 00 00 c8 30 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 [0x220] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 [0x240] | 00 10 01 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 80 a0 f9 fd 00 00 00 00 | 00 00 00 00 00 00 00 00 [0x260] | 00 00 00 00 00 00 00 00 Ruifeng mmc_init_hs200 1073 Skip set the voltage to 1.8V. Ruifeng End to set HS200. SDMMC_SS_PHY_CTRL4 physical address = 0x4f8810c SDMMC_SS_PHY_CTRL5 physical address = 0x4f88110 MMCSD0_SS_CFG_base address = 0x4c184ca000 SDMMC_SS_PHY_CTRL1(0x100) = 0x10000 SDMMC_SS_PHY_CTRL4(0x10c) = 0x110 SDMMC_SS_PHY_CTRL5(0x110) = 0x10007 Dump MMCSD0_SS_CFG... [0x000] | 00 4a 41 68 00 00 00 00 | 00 00 00 00 00 00 00 00 | c8 30 10 20 01 c8 ec 64 | 07 04 00 98 00 00 00 00 [0x020] | 00 00 00 00 00 01 00 00 | 04 00 00 00 02 00 00 00 | 04 00 00 00 02 00 00 00 | 01 00 00 00 00 00 00 00 [0x040] | 02 00 00 00 01 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 [0x060] | 00 00 00 80 10 00 00 00 | 00 00 00 00 00 00 00 00 | 08 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 [0x080] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 [0x0a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 [0x0c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 [0x0e0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 [0x100] | 00 00 01 00 00 00 00 00 | ff 10 ff 10 10 01 00 00 | 07 00 01 00 00 00 00 00 | 00 00 00 00 00 00 00 00 [0x120] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | e0 00 00 00 00 00 00 00 MMCSD0_HOST_CONTROL1 physical address = 0x4f80028 MMCSD0_HOST_CONTROL2 physical address = 0x4f8003e MMCSD0_CTL_CFG_base = 0x4c184cb000 MMCSD0_HOST_CONTROL1(0x28) = 0x18 HIGH_SPEED_ENA(0x28 bit[2]) = 0 MMCSD0_HOST_CONTROL2(0x3e) = 0x0 Dump MMCSD0_CTL_CFG... [0x000] | 00 00 00 00 00 72 01 00 | 00 00 01 00 00 00 1a 0d | 00 09 00 00 ff db f6 ff | 03 59 0f 32 01 27 d0 00 [0x020] | 00 00 00 00 f0 00 ff 01 | 18 0b 80 00 07 fa 0e 00 | 00 00 00 00 01 00 0f 03 | ff 07 ff 33 00 00 00 00 [0x040] | 01 c8 ec 7c 07 04 00 98 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 0c 20 04 80 00 00 00 00 [0x060] | 00 01 04 00 02 00 04 00 | 02 00 01 00 00 00 02 00 | 00 00 01 00 00 00 00 00 | 00 00 00 00 00 00 00 00 [0x080] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 [0x0a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 [0x0c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 [0x0e0] | 00 01 10 01 20 01 30 01 | 40 01 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 20 4e 00 00 00 00 04 10 [0x100] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 11 4f 04 00 00 00 11 00 | 00 01 00 20 81 00 00 00 [0x120] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 [0x140] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 [0x160] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 [0x180] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 [0x1a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 [0x1c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 [0x1e0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 [0x200] | 10 05 00 00 c8 30 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 [0x220] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 [0x240] | 00 10 01 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 80 a0 f9 fd 00 00 00 00 | 00 00 00 00 00 00 00 00 [0x260] | 00 00 00 00 00 00 00 00 Ruifeng Set DR_TY to 4, Instead 40 Ohms. Ruifeng Set SDMMC_SS_PHY_CTRL4 to 0x10610f Ruifeng Set SDMMC_SS_PHY_CTRL5 to 0x7 Ruifeng Changed HS200. SDMMC_SS_PHY_CTRL4 physical address = 0x4f8810c SDMMC_SS_PHY_CTRL5 physical address = 0x4f88110 MMCSD0_SS_CFG_base address = 0x4c184ca000 SDMMC_SS_PHY_CTRL1(0x100) = 0x410000 SDMMC_SS_PHY_CTRL4(0x10c) = 0x10610f SDMMC_SS_PHY_CTRL5(0x110) = 0x7 Dump MMCSD0_SS_CFG... [0x000] | 00 4a 41 68 00 00 00 00 | 00 00 00 00 00 00 00 00 | c8 30 10 20 01 c8 ec 64 | 07 04 00 98 00 00 00 00 [0x020] | 00 00 00 00 00 01 00 00 | 04 00 00 00 02 00 00 00 | 04 00 00 00 02 00 00 00 | 01 00 00 00 00 00 00 00 [0x040] | 02 00 00 00 01 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 [0x060] | 00 00 00 80 10 00 00 00 | 00 00 00 00 00 00 00 00 | 08 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 [0x080] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 [0x0a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 [0x0c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 [0x0e0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 [0x100] | 00 00 41 00 00 00 00 00 | ff 10 ff 10 0f 61 10 00 | 07 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 [0x120] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | e0 00 00 00 00 00 00 00 MMCSD0_HOST_CONTROL1 physical address = 0x4f80028 UnaMMCSD0_HOST_CONTROL2 physical address = 0x4f8003e bleMMCSD0_CTL_CFG_base = 0x4c184cb000 MMCSD0_HOST_CONTROL1(0x28) = 0x18 HIGH_SPEED_ENA(0x28 bit[2]) = 0 MMCSD0_HOST_CONTROL2(0x3e) = 0x0 Dump MMCSD0_CTL_CFG... t o acces[0x000] | 00 00 00 00 00 72 01 00 | 00 00 01 00 00 00 1a 0d | 00 09 00 00 ff db f6 ff | 03 59 0f 32 01 27 d0 00 s /dev/emmc0t179 [0x020] | 00 00 00 00 f0 00 ff 01 | 18 0b 80 00 07 fa 0e 00 | 00 00 00 00 01 00 0f 03 | ff 07 ff 33 00 00 00 00 [0x040] | 01 c8 ec 7c 07 04 00 98 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 0c 20 04 80 00 00 00 00 [0x060] | 00 01 04 00 02 00 04 00 | 02 00 01 00 00 00 02 00 | 00 00 01 00 00 00 00 00 | 00 00 00 00 00 00 00 00 [0x080] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 [0x0a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 [0x0c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 [0x0e0] | 00 01 10 01 20 01 30 01 | 40 01 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 20 4e 00 00 00 00 04 10 [0x100] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 11 4f 04 00 00 00 11 00 | 00 01 00 20 81 00 00 00 [0x120] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 [0x140] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 [0x160] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 Mounting the sd .. [0x180] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 [0x1a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 [0x1c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 [0x1e0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 [0x200] | 10 05 00 00 c8 30 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 [0x220] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 [0x240] | 00 10 01 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 80 a0 f9 fd 00 00 00 00 | 00 00 00 00 00 00 00 00 [0x260] | 00 00 00 00 00 00 00 00 CMD 6, flgs 0x1d4, arg 0x3b90101, blks 0, blksz 0, timeout 1000ms CMD 6 cmplt status CMD TO ERR (5) cmd->opcode = 6 status = 5 ====== FLIP GPIO 126 Ruifeng =======================================gpio_high============================= Ruifeng GPIO_OUT_DATA67 addr: 0x0060008Ch = 0x200000 Ruifeng GPIO_OUT_DATA67 addr: 0x0060008Ch = 0x40200000 J7EVM@QNX:/# slog2info Jan 01 00:00:00.035 random.5 low* 0 qcrypto: loading configuration file '/etc/qcrypto.conf' [qcrypto_common.c(190)] Jan 01 00:00:00.036 random.5..0 slog* 700 Random is using the Fortuna PRNG Jan 01 00:00:00.040 random.5 low 0 qcrypto: 'openssl' plugin loaded [qcrypto_plugins.c(354)] Jan 01 00:00:00.040 random.5..0 slog 700 Selecting timer as an entropy source Jan 01 00:00:00.040 random.5..0 slog 700 Registered path names Jan 01 00:00:00.040 random.5..0 slog 700 random: starting resmgr Jan 01 00:00:00.041 random.5..0 slog 700 random: Daemonizing the process Jan 01 00:00:00.054 devb_sdmmc_am65x.9 slog* 1800 devb-sdmmc-am65x 1.00A (May 23 2022 15:56:44) Jan 01 00:00:00.054 devb_sdmmc_am65x.9 slog 0 libcam.so (Sep 3 2021 11:57:38) bver 7010004 Jan 01 00:00:00.055 devb_sdmmc_am65x.9 slog 1800 sdio_cd: insertion path 0, cd state 0x1 Jan 01 00:00:00.056 devb_sdmmc_am65x.10 slog* 1800 devb-sdmmc-am65x 1.00A (May 23 2022 15:56:44) Jan 01 00:00:00.057 devb_sdmmc_am65x.10 slog 0 libcam.so (Sep 3 2021 11:57:38) bver 7010004 Jan 01 00:00:00.057 devb_sdmmc_am65x.10 slog 1800 sdio_cd: insertion path 0, cd state 0x1 Jan 01 00:00:00.059 iopkt.11 main_buffer* 0 tcpip starting Jan 01 00:00:00.060 iopkt.11 main_buffer 0 smmu support is disabled Jan 01 00:00:00.061 iopkt.11 main_buffer 0 initializing IPsec... Jan 01 00:00:00.061 iopkt.11 main_buffer 0 done Jan 01 00:00:00.061 iopkt.11 main_buffer 0 IPsec: Initialized Security Association Processing. Jan 01 00:00:00.245 devb_sdmmc_am65x.10 slog 1800 SD CID: Jan 01 00:00:00.245 devb_sdmmc_am65x.10 slog 1800 MID 0x1d, OID 0x4144, PNM USD Jan 01 00:00:00.245 devb_sdmmc_am65x.10 slog 1800 PRV 0x0, PSN 0x5ea8, MDT 12-2020 Jan 01 00:00:00.245 devb_sdmmc_am65x.10 slog 1800 SD CSD: Jan 01 00:00:00.245 devb_sdmmc_am65x.10 slog 1800 CSD_STRUCTURE 1, SPEC_VERS 0, CCC 0x5b5 Jan 01 00:00:00.245 devb_sdmmc_am65x.10 slog 1800 TAAC 14, NSAC 0, TRAN_SPEED 50 Jan 01 00:00:00.245 devb_sdmmc_am65x.10 slog 1800 C_SIZE 30719, C_SIZE_MULT 0 Jan 01 00:00:00.245 devb_sdmmc_am65x.10 slog 1800 READ_BL_LEN 9, WRITE_BL_LEN 9 Jan 01 00:00:00.245 devb_sdmmc_am65x.10 slog 1800 ERASE GRP_SIZE 0, GRP_MULT 0, SIZE 127 Jan 01 00:00:00.245 devb_sdmmc_am65x.10 slog 1800 blksz 512, sectors 31457280, dtr 25000000 Jan 01 00:00:00.245 devb_sdmmc_am65x.10 slog 1800 SD SW CAPS: Jan 01 00:00:00.245 devb_sdmmc_am65x.10 slog 1800 bus mode 0x3, cmd sys 0x1 Jan 01 00:00:00.245 devb_sdmmc_am65x.10 slog 1800 drv type 0x1, curr limit 0x1 Jan 01 00:00:00.245 devb_sdmmc_am65x.10 slog 1800 dtr 50000000 Jan 01 00:00:00.245 devb_sdmmc_am65x.10 slog 1800 CFG: Timing HS, DTR 50000000, Bus Width 4 bit Jan 01 00:00:00.245 devb_sdmmc_am65x.10 slog 100 cam-disk.so (Sep 3 2021 11:57:42) Jan 01 00:00:02.334 devb_sdmmc_am65x.9 slog 1800 sdio_wait_cmd: TIMEOUT 1000ms (errno 260) CMD 6, flgs 0x1d4, arg 0x3b90101, blks 0, blksz 0 Jan 01 00:00:02.334 devb_sdmmc_am65x.9 slog 1800 mmc_init_hs: switch ECSD_HS_TIMING HS Jan 01 00:00:03.449 devb_sdmmc_am65x.9 slog 1800 sdio_wait_cmd: TIMEOUT 1000ms (errno 260) CMD 16, flgs 0x154, arg 0x200, blks 0, blksz 0 Jan 01 00:00:03.449 devb_sdmmc_am65x.9 slog 1800 mmc_init_bus: sdio_set_block_length Jan 01 00:00:03.582 tisci_mgr.36877 slog* 55 SYSFW Firmware Version 21.5.0--v2021.05 (Terrific Llam Jan 01 00:00:03.582 tisci_mgr.36877 slog 55 SYSFW Firmware revision 0x15 Jan 01 00:00:03.582 tisci_mgr.36877 slog 55 SYSFW ABI revision 3.1 Jan 01 00:00:03.590 shmemallocator.49166 slog* 0 SharedMemoryAllocator: BaseAddress: 0xb8000000 Size: 0x20000000 (536870912) Jan 01 00:00:03.590 shmemallocator.49166 slog 0 SharedMemoryAllocator: BaseAddress: 0x00000000 Size: 0x00000000 (0) Jan 01 00:00:03.761 tiipc_mgr.53263 slog* 0 [IPC] Jan 01 00:00:03.761 tiipc_mgr.53263 slog 0 Mailbox_plugInterrupt: interrupt Number 489, arg 0xAA3CC738 Jan 01 00:00:03.776 tiipc_mgr.53263 slog 0 [IPC] Jan 01 00:00:03.776 tiipc_mgr.53263 slog 0 Mailbox_plugInterrupt: interrupt Number 490, arg 0xAA3CC8D8 Jan 01 00:00:03.792 tiipc_mgr.53263 slog 0 [IPC] Jan 01 00:00:03.792 tiipc_mgr.53263 slog 0 Mailbox_plugInterrupt: interrupt Number 491, arg 0xAA3CCA78 Jan 01 00:00:03.807 tiipc_mgr.53263 slog 0 [IPC] Jan 01 00:00:03.807 tiipc_mgr.53263 slog 0 Mailbox_plugInterrupt: interrupt Number 492, arg 0xAA3CCC18 Jan 01 00:00:03.822 tiipc_mgr.53263 slog 0 [IPC] Jan 01 00:00:03.822 tiipc_mgr.53263 slog 0 Mailbox_plugInterrupt: interrupt Number 493, arg 0xAA3CCDB8 Jan 01 00:00:04.157 screen.61457 slog* 300 screen: starting up... Jan 01 00:00:04.159 screen.61457 slog 300 screen: Configuration file: /ti_fs/usr/lib/graphics/jacinto7/graphics.conf.dss_on_r5 Jan 01 00:00:04.305 screen.61457 slog 300 screen: slog2 context created with 1 pages Jan 01 00:00:04.305 screen.61457 slog 300 screen: loading alloc module stdbuf... Jan 01 00:00:04.307 screen.61457 slog 300 screen: display 1 returned invalid value 0 for WFD_PORT_MODE_ROTATION_SUPPORT Jan 01 00:00:04.309 screen.61457 slog 300 screen: loading libhiddi.so... Jan 01 00:00:04.309 screen.61457 slog 300 screen: server is ready Jan 01 00:00:04.571 devb_sdmmc_am65x.9 slog 1800 sdio_wait_cmd: TIMEOUT 1000ms (errno 260) CMD 0, flgs 0x1, arg 0x0, blks 0, blksz 0 Jan 01 00:00:05.586 devb_sdmmc_am65x.9 slog 1800 sdio_wait_cmd: TIMEOUT 1000ms (errno 260) CMD 0, flgs 0x1, arg 0x0, blks 0, blksz 0 Jan 01 00:00:06.601 devb_sdmmc_am65x.9 slog 1800 sdio_wait_cmd: TIMEOUT 1000ms (errno 260) CMD 0, flgs 0x1, arg 0x0, blks 0, blksz 0 Jan 01 00:00:06.601 devb_sdmmc_am65x.9 slog 1800 sdio_cd: Unsupported card inserted