Modules | Data Structures | Macros | Typedefs | Enumerations | Functions
Ethernet PHY Driver

Modules

 TI DP83822 PHY
 
 TI DP83867 PHY
 
 Generic PHY
 
 VSC8514 PHY
 

Data Structures

struct  EnetPhy_MacCfg_s
 MAC port parameters: MII interface, capabilities. More...
 
struct  EnetPhy_Version_s
 PHY version (ID). More...
 
struct  EnetPhy_LinkCfg_s
 Link speed and duplexity configuration. More...
 
struct  EnetPhy_FsmTimeoutCfg_s
 PHY State-Machine time-out values. More...
 
struct  EnetPhy_Cfg_s
 PHY configuration parameters. More...
 
struct  EnetPhy_Mdio_s
 MDIO driver. More...
 

Macros

#define ENETPHY_EXTENDED_CFG_SIZE_MAX   (128U)
 Max extended configuration size, arbitrarily chosen.
 
#define ENETPHY_FSM_TICK_PERIOD_MS   (100U)
 Enet PHY State Machine tick period.
 
#define ENETPHY_INVALID_PHYADDR   (~0U)
 Invalid PHY address indicator.
 

Typedefs

typedef enum EnetPhy_Mii_e EnetPhy_Mii
 MAC Media-Independent Interface (MII).
 
typedef struct EnetPhy_MacCfg_s EnetPhy_MacCfg
 MAC port parameters: MII interface, capabilities.
 
typedef enum EnetPhy_Speed_e EnetPhy_Speed
 MAC interface speed.
 
typedef enum EnetPhy_Duplexity_e EnetPhy_Duplexity
 MAC interface duplexity.
 
typedef struct EnetPhy_Version_s EnetPhy_Version
 PHY version (ID).
 
typedef enum EnetPhy_LinkStatus_e EnetPhy_LinkStatus
 PHY link status.
 
typedef struct EnetPhy_LinkCfg_s EnetPhy_LinkCfg
 Link speed and duplexity configuration.
 
typedef struct
EnetPhy_FsmTimeoutCfg_s 
EnetPhy_FsmTimeoutCfg
 PHY State-Machine time-out values.
 
typedef struct EnetPhy_Cfg_s EnetPhy_Cfg
 PHY configuration parameters.
 
typedef struct EnetPhy_Mdio_s EnetPhy_Mdio
 MDIO driver.
 
typedef EnetPhy_MdioEnetPhy_MdioHandle
 MDIO driver handle.
 
typedef struct EnetPhy_Obj_s * EnetPhy_Handle
 PHY driver object handle. More...
 

Enumerations

enum  EnetPhy_Mii_e {
  ENETPHY_MAC_MII_MII = 0U, ENETPHY_MAC_MII_RMII, ENETPHY_MAC_MII_GMII, ENETPHY_MAC_MII_RGMII,
  ENETPHY_MAC_MII_SGMII, ENETPHY_MAC_MII_QSGMII
}
 MAC Media-Independent Interface (MII). More...
 
enum  EnetPhy_Speed_e { ENETPHY_SPEED_10MBIT = 0U, ENETPHY_SPEED_100MBIT, ENETPHY_SPEED_1GBIT, ENETPHY_SPEED_AUTO }
 MAC interface speed. More...
 
enum  EnetPhy_Duplexity_e { ENETPHY_DUPLEX_HALF = 0U, ENETPHY_DUPLEX_FULL, ENETPHY_DUPLEX_AUTO }
 MAC interface duplexity. More...
 
enum  EnetPhy_LinkStatus_e { ENETPHY_GOT_LINK = 0U, ENETPHY_LINK_UP, ENETPHY_LOST_LINK, ENETPHY_LINK_DOWN }
 PHY link status. More...
 

Functions

void EnetPhy_initParams (EnetPhy_Cfg *phyCfg)
 Initialize PHY config params. More...
 
void EnetPhy_setExtendedParams (EnetPhy_Cfg *phyCfg, const void *extendedCfg, uint32_t extendedCfgSize)
 Set PHY extended parameters. More...
 
EnetPhy_Handle EnetPhy_open (EnetPhy_MdioHandle hMdio, const EnetPhy_MacCfg *macCfg, const EnetPhy_Cfg *phyCfg, const EnetPhy_LinkCfg *linkCfg)
 Open the PHY driver. More...
 
void EnetPhy_close (EnetPhy_Handle hPhy)
 Close the PHY driver. More...
 
EnetPhy_LinkStatus EnetPhy_tick (EnetPhy_Handle hPhy)
 Run PHY state machine. More...
 
bool EnetPhy_isLinked (EnetPhy_Handle hPhy)
 Get link status. More...
 
int32_t EnetPhy_getLinkCfg (EnetPhy_Handle hPhy, EnetPhy_LinkCfg *linkCfg)
 Get link configuration. More...
 
int32_t EnetPhy_readReg (EnetPhy_Handle hPhy, uint32_t reg, uint16_t *val)
 Read PHY register. More...
 
int32_t EnetPhy_writeReg (EnetPhy_Handle hPhy, uint32_t reg, uint16_t val)
 Write PHY register. More...
 
int32_t EnetPhy_rmwReg (EnetPhy_Handle hPhy, uint32_t reg, uint16_t mask, uint16_t val)
 Read-modify-write PHY register. More...
 
int32_t EnetPhy_readExtReg (EnetPhy_Handle hPhy, uint32_t reg, uint16_t *val)
 Read PHY extended register. More...
 
int32_t EnetPhy_writeExtReg (EnetPhy_Handle hPhy, uint32_t reg, uint16_t val)
 Write PHY extended register. More...
 
int32_t EnetPhy_rmwExtReg (EnetPhy_Handle hPhy, uint32_t reg, uint16_t mask, uint16_t val)
 Read-modify-write PHY extended register. More...
 
int32_t EnetPhy_readC45Reg (EnetPhy_Handle hPhy, uint8_t mmd, uint32_t reg, uint16_t *val)
 Read PHY register using Clause-45 frame. More...
 
int32_t EnetPhy_writeC45Reg (EnetPhy_Handle hPhy, uint8_t mmd, uint32_t reg, uint16_t val)
 Write PHY register using Clause-45 frame. More...
 
int32_t EnetPhy_rmwC45Reg (EnetPhy_Handle hPhy, uint8_t mmd, uint32_t reg, uint16_t mask, uint16_t val)
 Read-modify-write PHY register using Clause-45 frame. More...
 
void EnetPhy_printRegs (EnetPhy_Handle hPhy)
 Print all PHY registers. More...
 

Ethernet PHY driver error codes

Error codes returned by the Ethernet PHY driver APIs.

#define ENETPHY_SOK   (CSL_PASS)
 Success.
 
#define ENETPHY_EFAIL   (CSL_EFAIL)
 Generic failure error condition (typically caused by hardware).
 
#define ENETPHY_EBADARGS   (CSL_EBADARGS)
 Bad arguments (i.e. NULL pointer).
 
#define ENETPHY_EINVALIDPARAMS   (CSL_EINVALID_PARAMS)
 Invalid parameters (i.e. value out-of-range).
 
#define ENETPHY_ETIMEOUT   (CSL_ETIMEOUT)
 Time out while waiting for a given condition to happen.
 
#define ENETPHY_EALLOC   (CSL_EALLOC)
 Allocation failure.
 
#define ENETPHY_EPERM   (CSL_EALLOC - 4)
 Operation not permitted.
 
#define ENETPHY_ENOTSUPPORTED   (CSL_EALLOC - 5)
 Operation not supported.
 

Ethernet PHY link capability masks

Error codes returned by the Ethernet PHY driver APIs.

#define ENETPHY_LINK_CAP_HD10   ENETPHY_BIT(1)
 10-Mbps, half-duplex capability mask.
 
#define ENETPHY_LINK_CAP_FD10   ENETPHY_BIT(2)
 10-Mbps, full-duplex capability mask.
 
#define ENETPHY_LINK_CAP_HD100   ENETPHY_BIT(3)
 100-Mbps, half-duplex capability mask.
 
#define ENETPHY_LINK_CAP_FD100   ENETPHY_BIT(4)
 100-Mbps, full-duplex capability mask.
 
#define ENETPHY_LINK_CAP_HD1000   ENETPHY_BIT(5)
 1-Gbps, half-duplex capability mask.
 
#define ENETPHY_LINK_CAP_FD1000   ENETPHY_BIT(6)
 1-Gbps, full-duplex capability mask.
 
#define ENETPHY_LINK_CAP_10
 10-Mbps, full and half-duplex capability mask. More...
 
#define ENETPHY_LINK_CAP_100
 100-Mbps, full and half-duplex capability mask. More...
 
#define ENETPHY_LINK_CAP_1000
 1-Gbps, full and half-duplex capability mask. More...
 
#define ENETPHY_LINK_CAP_ALL
 Auto-negotiation mask with all duplexity and speed values set. More...
 

Detailed Description

The Ethernet PHY driver supports auto-negotiation and manual modes. The PHY driver uses an MDIO abstraction to perform register reads and writes. The MDIO abstraction can be implemented using Enet LLD's ENET_MDIO_API or any other MDIO driver.

Macro Definition Documentation

#define ENETPHY_LINK_CAP_10
Value:
#define ENETPHY_LINK_CAP_HD10
10-Mbps, half-duplex capability mask.
Definition: enetphy.h:125
#define ENETPHY_LINK_CAP_FD10
10-Mbps, full-duplex capability mask.
Definition: enetphy.h:128

10-Mbps, full and half-duplex capability mask.

#define ENETPHY_LINK_CAP_100
Value:
#define ENETPHY_LINK_CAP_FD100
100-Mbps, full-duplex capability mask.
Definition: enetphy.h:134
#define ENETPHY_LINK_CAP_HD100
100-Mbps, half-duplex capability mask.
Definition: enetphy.h:131

100-Mbps, full and half-duplex capability mask.

#define ENETPHY_LINK_CAP_1000
Value:
#define ENETPHY_LINK_CAP_HD1000
1-Gbps, half-duplex capability mask.
Definition: enetphy.h:137
#define ENETPHY_LINK_CAP_FD1000
1-Gbps, full-duplex capability mask.
Definition: enetphy.h:140

1-Gbps, full and half-duplex capability mask.

#define ENETPHY_LINK_CAP_ALL
Value:
#define ENETPHY_LINK_CAP_FD100
100-Mbps, full-duplex capability mask.
Definition: enetphy.h:134
#define ENETPHY_LINK_CAP_HD10
10-Mbps, half-duplex capability mask.
Definition: enetphy.h:125
#define ENETPHY_LINK_CAP_HD1000
1-Gbps, half-duplex capability mask.
Definition: enetphy.h:137
#define ENETPHY_LINK_CAP_FD10
10-Mbps, full-duplex capability mask.
Definition: enetphy.h:128
#define ENETPHY_LINK_CAP_HD100
100-Mbps, half-duplex capability mask.
Definition: enetphy.h:131
#define ENETPHY_LINK_CAP_FD1000
1-Gbps, full-duplex capability mask.
Definition: enetphy.h:140

Auto-negotiation mask with all duplexity and speed values set.

Typedef Documentation

typedef struct EnetPhy_Obj_s* EnetPhy_Handle

PHY driver object handle.

PHY driver opaque handle used to call any PHY related APIs.

Enumeration Type Documentation

MAC interface duplexity.

Enumerator
ENETPHY_DUPLEX_HALF 

Half duplex

ENETPHY_DUPLEX_FULL 

Full duplex

ENETPHY_DUPLEX_AUTO 

Duplexity determined automatically

PHY link status.

Enumerator
ENETPHY_GOT_LINK 

PHY got link up

ENETPHY_LINK_UP 

PHY link is still up

ENETPHY_LOST_LINK 

PHY lost link

ENETPHY_LINK_DOWN 

PHY link is still down

MAC Media-Independent Interface (MII).

Enumerator
ENETPHY_MAC_MII_MII 

MII interface.

ENETPHY_MAC_MII_RMII 

RMII interface.

ENETPHY_MAC_MII_GMII 

GMII interface.

ENETPHY_MAC_MII_RGMII 

RGMII interface.

ENETPHY_MAC_MII_SGMII 

SGMII interface.

ENETPHY_MAC_MII_QSGMII 

QSGMII interface.

MAC interface speed.

Enumerator
ENETPHY_SPEED_10MBIT 

10 Mbps

ENETPHY_SPEED_100MBIT 

100 Mbps

ENETPHY_SPEED_1GBIT 

1 Gbps

ENETPHY_SPEED_AUTO 

Speed determined automatically

Function Documentation

void EnetPhy_close ( EnetPhy_Handle  hPhy)

Close the PHY driver.

Closes the Ethernet PHY driver.

Parameters
hPhyPHY device handle
int32_t EnetPhy_getLinkCfg ( EnetPhy_Handle  hPhy,
EnetPhy_LinkCfg linkCfg 
)

Get link configuration.

Gets the link configuration, that is, the configuration that the PHY has negotiated with the link partner or the manual link configuration it was set to.

Parameters
hPhyPHY device handle
linkCfgLink configuration
Returns
EnetPhy_ErrorCodes
void EnetPhy_initParams ( EnetPhy_Cfg phyCfg)

Initialize PHY config params.

Initializes PHY driver configuration parameters.

Parameters
phyCfgPHY configuration params
bool EnetPhy_isLinked ( EnetPhy_Handle  hPhy)

Get link status.

Gets the link status: linked or not, based on driver's state machine. The PHY driver state machine can take a little longer to detect link up because it runs on tick period intervals and need to traverse few states to reach link up FSM state.

Parameters
hPhyPHY device handle
Returns
true if PHY is linked, false otherwise
EnetPhy_Handle EnetPhy_open ( EnetPhy_MdioHandle  hMdio,
const EnetPhy_MacCfg macCfg,
const EnetPhy_Cfg phyCfg,
const EnetPhy_LinkCfg linkCfg 
)

Open the PHY driver.

Open the Ethernet PHY driver for the given MAC port number. The PHY driver takes PHY specific configuration parameters, the MAC port type connection and the desired link configuration (auto or manual).

Parameters
hMdioMDIO driver to be used for PHY register read/write
macCfgMAC port parameters (MII interface, speed/duplex capabilities)
phyCfgPHY configuration params
linkCfgLink configuration (auto or manual)
Returns
EnetPhy_Handle if success, NULL otherwise
void EnetPhy_printRegs ( EnetPhy_Handle  hPhy)

Print all PHY registers.

Prints all registers of a PHY.

Parameters
hPhyPHY device handle
int32_t EnetPhy_readC45Reg ( EnetPhy_Handle  hPhy,
uint8_t  mmd,
uint32_t  reg,
uint16_t *  val 
)

Read PHY register using Clause-45 frame.

Reads a PHY register using Clause-45 frame.

Parameters
hPhyPHY device handle
mmdMMD
regRegister number
valPointer to the read value
Returns
EnetPhy_ErrorCodes
int32_t EnetPhy_readExtReg ( EnetPhy_Handle  hPhy,
uint32_t  reg,
uint16_t *  val 
)

Read PHY extended register.

Reads a PHY extended register.

Parameters
hPhyPHY device handle
regRegister number
valPointer to the read value
Returns
EnetPhy_ErrorCodes
int32_t EnetPhy_readReg ( EnetPhy_Handle  hPhy,
uint32_t  reg,
uint16_t *  val 
)

Read PHY register.

Reads a PHY register. It's not meant for extended registers.

Parameters
hPhyPHY device handle
regRegister number
valPointer to the read value
Returns
EnetPhy_ErrorCodes
int32_t EnetPhy_rmwC45Reg ( EnetPhy_Handle  hPhy,
uint8_t  mmd,
uint32_t  reg,
uint16_t  mask,
uint16_t  val 
)

Read-modify-write PHY register using Clause-45 frame.

Read-modify-write a PHY register using Clause-45 frame.

Parameters
hPhyPHY device handle
mmdMMD
regRegister number
maskBitmask to be applied on read value and value to be written
valValue to be written
Returns
EnetPhy_ErrorCodes
int32_t EnetPhy_rmwExtReg ( EnetPhy_Handle  hPhy,
uint32_t  reg,
uint16_t  mask,
uint16_t  val 
)

Read-modify-write PHY extended register.

Read-modify-write a PHY extended register.

Parameters
hPhyPHY device handle
regRegister number
maskBitmask to be applied on read value and value to be written
valValue to be written
Returns
EnetPhy_ErrorCodes
int32_t EnetPhy_rmwReg ( EnetPhy_Handle  hPhy,
uint32_t  reg,
uint16_t  mask,
uint16_t  val 
)

Read-modify-write PHY register.

Read-modify-write a PHY register. It's not meant for extended registers.

Parameters
hPhyPHY device handle
regRegister number
maskBitmask to be applied on read value and value to be written
valValue to be written
Returns
EnetPhy_ErrorCodes
void EnetPhy_setExtendedParams ( EnetPhy_Cfg phyCfg,
const void *  extendedCfg,
uint32_t  extendedCfgSize 
)

Set PHY extended parameters.

Sets the PHY-specific extended parameters to the PHY config structure.

Parameters
phyCfgPointer to the PHY config
extendedCfgPointer to the PHY extended config
extendedCfgSizeSize of the PHY extended config
EnetPhy_LinkStatus EnetPhy_tick ( EnetPhy_Handle  hPhy)

Run PHY state machine.

Runs the PHY FSM.

Parameters
hPhyPHY device handle
Returns
Whether PHY got or lost link, or no change.
int32_t EnetPhy_writeC45Reg ( EnetPhy_Handle  hPhy,
uint8_t  mmd,
uint32_t  reg,
uint16_t  val 
)

Write PHY register using Clause-45 frame.

Writes a PHY register using Clause-45 frame.

Parameters
hPhyPHY device handle
mmdMMD
regRegister number
valValue to be written
Returns
EnetPhy_ErrorCodes
int32_t EnetPhy_writeExtReg ( EnetPhy_Handle  hPhy,
uint32_t  reg,
uint16_t  val 
)

Write PHY extended register.

Writes a PHY extended register.

Parameters
hPhyPHY device handle
regRegister number
valValue to be written
Returns
EnetPhy_ErrorCodes
int32_t EnetPhy_writeReg ( EnetPhy_Handle  hPhy,
uint32_t  reg,
uint16_t  val 
)

Write PHY register.

Writes a PHY register. It's not meant for extended registers.

Parameters
hPhyPHY device handle
regRegister number
valValue to be written
Returns
EnetPhy_ErrorCodes

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