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Modules | |
TI DP83822 PHY | |
TI DP83867 PHY | |
Generic PHY | |
VSC8514 PHY | |
Data Structures | |
struct | EnetPhy_MacCfg_s |
MAC port parameters: MII interface, capabilities. More... | |
struct | EnetPhy_Version_s |
PHY version (ID). More... | |
struct | EnetPhy_LinkCfg_s |
Link speed and duplexity configuration. More... | |
struct | EnetPhy_FsmTimeoutCfg_s |
PHY State-Machine time-out values. More... | |
struct | EnetPhy_Cfg_s |
PHY configuration parameters. More... | |
struct | EnetPhy_Mdio_s |
MDIO driver. More... | |
Macros | |
#define | ENETPHY_EXTENDED_CFG_SIZE_MAX (128U) |
Max extended configuration size, arbitrarily chosen. | |
#define | ENETPHY_FSM_TICK_PERIOD_MS (100U) |
Enet PHY State Machine tick period. | |
#define | ENETPHY_INVALID_PHYADDR (~0U) |
Invalid PHY address indicator. | |
Typedefs | |
typedef enum EnetPhy_Mii_e | EnetPhy_Mii |
MAC Media-Independent Interface (MII). | |
typedef struct EnetPhy_MacCfg_s | EnetPhy_MacCfg |
MAC port parameters: MII interface, capabilities. | |
typedef enum EnetPhy_Speed_e | EnetPhy_Speed |
MAC interface speed. | |
typedef enum EnetPhy_Duplexity_e | EnetPhy_Duplexity |
MAC interface duplexity. | |
typedef struct EnetPhy_Version_s | EnetPhy_Version |
PHY version (ID). | |
typedef enum EnetPhy_LinkStatus_e | EnetPhy_LinkStatus |
PHY link status. | |
typedef struct EnetPhy_LinkCfg_s | EnetPhy_LinkCfg |
Link speed and duplexity configuration. | |
typedef struct EnetPhy_FsmTimeoutCfg_s | EnetPhy_FsmTimeoutCfg |
PHY State-Machine time-out values. | |
typedef struct EnetPhy_Cfg_s | EnetPhy_Cfg |
PHY configuration parameters. | |
typedef struct EnetPhy_Mdio_s | EnetPhy_Mdio |
MDIO driver. | |
typedef EnetPhy_Mdio * | EnetPhy_MdioHandle |
MDIO driver handle. | |
typedef struct EnetPhy_Obj_s * | EnetPhy_Handle |
PHY driver object handle. More... | |
Enumerations | |
enum | EnetPhy_Mii_e { ENETPHY_MAC_MII_MII = 0U, ENETPHY_MAC_MII_RMII, ENETPHY_MAC_MII_GMII, ENETPHY_MAC_MII_RGMII, ENETPHY_MAC_MII_SGMII, ENETPHY_MAC_MII_QSGMII } |
MAC Media-Independent Interface (MII). More... | |
enum | EnetPhy_Speed_e { ENETPHY_SPEED_10MBIT = 0U, ENETPHY_SPEED_100MBIT, ENETPHY_SPEED_1GBIT, ENETPHY_SPEED_AUTO } |
MAC interface speed. More... | |
enum | EnetPhy_Duplexity_e { ENETPHY_DUPLEX_HALF = 0U, ENETPHY_DUPLEX_FULL, ENETPHY_DUPLEX_AUTO } |
MAC interface duplexity. More... | |
enum | EnetPhy_LinkStatus_e { ENETPHY_GOT_LINK = 0U, ENETPHY_LINK_UP, ENETPHY_LOST_LINK, ENETPHY_LINK_DOWN } |
PHY link status. More... | |
Functions | |
void | EnetPhy_initParams (EnetPhy_Cfg *phyCfg) |
Initialize PHY config params. More... | |
void | EnetPhy_setExtendedParams (EnetPhy_Cfg *phyCfg, const void *extendedCfg, uint32_t extendedCfgSize) |
Set PHY extended parameters. More... | |
EnetPhy_Handle | EnetPhy_open (EnetPhy_MdioHandle hMdio, const EnetPhy_MacCfg *macCfg, const EnetPhy_Cfg *phyCfg, const EnetPhy_LinkCfg *linkCfg) |
Open the PHY driver. More... | |
void | EnetPhy_close (EnetPhy_Handle hPhy) |
Close the PHY driver. More... | |
EnetPhy_LinkStatus | EnetPhy_tick (EnetPhy_Handle hPhy) |
Run PHY state machine. More... | |
bool | EnetPhy_isLinked (EnetPhy_Handle hPhy) |
Get link status. More... | |
int32_t | EnetPhy_getLinkCfg (EnetPhy_Handle hPhy, EnetPhy_LinkCfg *linkCfg) |
Get link configuration. More... | |
int32_t | EnetPhy_readReg (EnetPhy_Handle hPhy, uint32_t reg, uint16_t *val) |
Read PHY register. More... | |
int32_t | EnetPhy_writeReg (EnetPhy_Handle hPhy, uint32_t reg, uint16_t val) |
Write PHY register. More... | |
int32_t | EnetPhy_rmwReg (EnetPhy_Handle hPhy, uint32_t reg, uint16_t mask, uint16_t val) |
Read-modify-write PHY register. More... | |
int32_t | EnetPhy_readExtReg (EnetPhy_Handle hPhy, uint32_t reg, uint16_t *val) |
Read PHY extended register. More... | |
int32_t | EnetPhy_writeExtReg (EnetPhy_Handle hPhy, uint32_t reg, uint16_t val) |
Write PHY extended register. More... | |
int32_t | EnetPhy_rmwExtReg (EnetPhy_Handle hPhy, uint32_t reg, uint16_t mask, uint16_t val) |
Read-modify-write PHY extended register. More... | |
int32_t | EnetPhy_readC45Reg (EnetPhy_Handle hPhy, uint8_t mmd, uint32_t reg, uint16_t *val) |
Read PHY register using Clause-45 frame. More... | |
int32_t | EnetPhy_writeC45Reg (EnetPhy_Handle hPhy, uint8_t mmd, uint32_t reg, uint16_t val) |
Write PHY register using Clause-45 frame. More... | |
int32_t | EnetPhy_rmwC45Reg (EnetPhy_Handle hPhy, uint8_t mmd, uint32_t reg, uint16_t mask, uint16_t val) |
Read-modify-write PHY register using Clause-45 frame. More... | |
void | EnetPhy_printRegs (EnetPhy_Handle hPhy) |
Print all PHY registers. More... | |
Ethernet PHY driver error codes | |
Error codes returned by the Ethernet PHY driver APIs. | |
#define | ENETPHY_SOK (CSL_PASS) |
Success. | |
#define | ENETPHY_EFAIL (CSL_EFAIL) |
Generic failure error condition (typically caused by hardware). | |
#define | ENETPHY_EBADARGS (CSL_EBADARGS) |
Bad arguments (i.e. NULL pointer). | |
#define | ENETPHY_EINVALIDPARAMS (CSL_EINVALID_PARAMS) |
Invalid parameters (i.e. value out-of-range). | |
#define | ENETPHY_ETIMEOUT (CSL_ETIMEOUT) |
Time out while waiting for a given condition to happen. | |
#define | ENETPHY_EALLOC (CSL_EALLOC) |
Allocation failure. | |
#define | ENETPHY_EPERM (CSL_EALLOC - 4) |
Operation not permitted. | |
#define | ENETPHY_ENOTSUPPORTED (CSL_EALLOC - 5) |
Operation not supported. | |
Ethernet PHY link capability masks | |
Error codes returned by the Ethernet PHY driver APIs. | |
#define | ENETPHY_LINK_CAP_HD10 ENETPHY_BIT(1) |
10-Mbps, half-duplex capability mask. | |
#define | ENETPHY_LINK_CAP_FD10 ENETPHY_BIT(2) |
10-Mbps, full-duplex capability mask. | |
#define | ENETPHY_LINK_CAP_HD100 ENETPHY_BIT(3) |
100-Mbps, half-duplex capability mask. | |
#define | ENETPHY_LINK_CAP_FD100 ENETPHY_BIT(4) |
100-Mbps, full-duplex capability mask. | |
#define | ENETPHY_LINK_CAP_HD1000 ENETPHY_BIT(5) |
1-Gbps, half-duplex capability mask. | |
#define | ENETPHY_LINK_CAP_FD1000 ENETPHY_BIT(6) |
1-Gbps, full-duplex capability mask. | |
#define | ENETPHY_LINK_CAP_10 |
10-Mbps, full and half-duplex capability mask. More... | |
#define | ENETPHY_LINK_CAP_100 |
100-Mbps, full and half-duplex capability mask. More... | |
#define | ENETPHY_LINK_CAP_1000 |
1-Gbps, full and half-duplex capability mask. More... | |
#define | ENETPHY_LINK_CAP_ALL |
Auto-negotiation mask with all duplexity and speed values set. More... | |
The Ethernet PHY driver supports auto-negotiation and manual modes. The PHY driver uses an MDIO abstraction to perform register reads and writes. The MDIO abstraction can be implemented using Enet LLD's ENET_MDIO_API or any other MDIO driver.
#define ENETPHY_LINK_CAP_10 |
10-Mbps, full and half-duplex capability mask.
#define ENETPHY_LINK_CAP_100 |
100-Mbps, full and half-duplex capability mask.
#define ENETPHY_LINK_CAP_1000 |
1-Gbps, full and half-duplex capability mask.
#define ENETPHY_LINK_CAP_ALL |
Auto-negotiation mask with all duplexity and speed values set.
typedef struct EnetPhy_Obj_s* EnetPhy_Handle |
PHY driver object handle.
PHY driver opaque handle used to call any PHY related APIs.
enum EnetPhy_Duplexity_e |
enum EnetPhy_LinkStatus_e |
enum EnetPhy_Mii_e |
enum EnetPhy_Speed_e |
void EnetPhy_close | ( | EnetPhy_Handle | hPhy | ) |
Close the PHY driver.
Closes the Ethernet PHY driver.
hPhy | PHY device handle |
int32_t EnetPhy_getLinkCfg | ( | EnetPhy_Handle | hPhy, |
EnetPhy_LinkCfg * | linkCfg | ||
) |
Get link configuration.
Gets the link configuration, that is, the configuration that the PHY has negotiated with the link partner or the manual link configuration it was set to.
hPhy | PHY device handle |
linkCfg | Link configuration |
void EnetPhy_initParams | ( | EnetPhy_Cfg * | phyCfg | ) |
Initialize PHY config params.
Initializes PHY driver configuration parameters.
phyCfg | PHY configuration params |
bool EnetPhy_isLinked | ( | EnetPhy_Handle | hPhy | ) |
Get link status.
Gets the link status: linked or not, based on driver's state machine. The PHY driver state machine can take a little longer to detect link up because it runs on tick period intervals and need to traverse few states to reach link up FSM state.
hPhy | PHY device handle |
EnetPhy_Handle EnetPhy_open | ( | EnetPhy_MdioHandle | hMdio, |
const EnetPhy_MacCfg * | macCfg, | ||
const EnetPhy_Cfg * | phyCfg, | ||
const EnetPhy_LinkCfg * | linkCfg | ||
) |
Open the PHY driver.
Open the Ethernet PHY driver for the given MAC port number. The PHY driver takes PHY specific configuration parameters, the MAC port type connection and the desired link configuration (auto or manual).
hMdio | MDIO driver to be used for PHY register read/write |
macCfg | MAC port parameters (MII interface, speed/duplex capabilities) |
phyCfg | PHY configuration params |
linkCfg | Link configuration (auto or manual) |
void EnetPhy_printRegs | ( | EnetPhy_Handle | hPhy | ) |
Print all PHY registers.
Prints all registers of a PHY.
hPhy | PHY device handle |
int32_t EnetPhy_readC45Reg | ( | EnetPhy_Handle | hPhy, |
uint8_t | mmd, | ||
uint32_t | reg, | ||
uint16_t * | val | ||
) |
Read PHY register using Clause-45 frame.
Reads a PHY register using Clause-45 frame.
hPhy | PHY device handle |
mmd | MMD |
reg | Register number |
val | Pointer to the read value |
int32_t EnetPhy_readExtReg | ( | EnetPhy_Handle | hPhy, |
uint32_t | reg, | ||
uint16_t * | val | ||
) |
Read PHY extended register.
Reads a PHY extended register.
hPhy | PHY device handle |
reg | Register number |
val | Pointer to the read value |
int32_t EnetPhy_readReg | ( | EnetPhy_Handle | hPhy, |
uint32_t | reg, | ||
uint16_t * | val | ||
) |
Read PHY register.
Reads a PHY register. It's not meant for extended registers.
hPhy | PHY device handle |
reg | Register number |
val | Pointer to the read value |
int32_t EnetPhy_rmwC45Reg | ( | EnetPhy_Handle | hPhy, |
uint8_t | mmd, | ||
uint32_t | reg, | ||
uint16_t | mask, | ||
uint16_t | val | ||
) |
Read-modify-write PHY register using Clause-45 frame.
Read-modify-write a PHY register using Clause-45 frame.
hPhy | PHY device handle |
mmd | MMD |
reg | Register number |
mask | Bitmask to be applied on read value and value to be written |
val | Value to be written |
int32_t EnetPhy_rmwExtReg | ( | EnetPhy_Handle | hPhy, |
uint32_t | reg, | ||
uint16_t | mask, | ||
uint16_t | val | ||
) |
Read-modify-write PHY extended register.
Read-modify-write a PHY extended register.
hPhy | PHY device handle |
reg | Register number |
mask | Bitmask to be applied on read value and value to be written |
val | Value to be written |
int32_t EnetPhy_rmwReg | ( | EnetPhy_Handle | hPhy, |
uint32_t | reg, | ||
uint16_t | mask, | ||
uint16_t | val | ||
) |
Read-modify-write PHY register.
Read-modify-write a PHY register. It's not meant for extended registers.
hPhy | PHY device handle |
reg | Register number |
mask | Bitmask to be applied on read value and value to be written |
val | Value to be written |
void EnetPhy_setExtendedParams | ( | EnetPhy_Cfg * | phyCfg, |
const void * | extendedCfg, | ||
uint32_t | extendedCfgSize | ||
) |
Set PHY extended parameters.
Sets the PHY-specific extended parameters to the PHY config structure.
phyCfg | Pointer to the PHY config |
extendedCfg | Pointer to the PHY extended config |
extendedCfgSize | Size of the PHY extended config |
EnetPhy_LinkStatus EnetPhy_tick | ( | EnetPhy_Handle | hPhy | ) |
Run PHY state machine.
Runs the PHY FSM.
hPhy | PHY device handle |
int32_t EnetPhy_writeC45Reg | ( | EnetPhy_Handle | hPhy, |
uint8_t | mmd, | ||
uint32_t | reg, | ||
uint16_t | val | ||
) |
Write PHY register using Clause-45 frame.
Writes a PHY register using Clause-45 frame.
hPhy | PHY device handle |
mmd | MMD |
reg | Register number |
val | Value to be written |
int32_t EnetPhy_writeExtReg | ( | EnetPhy_Handle | hPhy, |
uint32_t | reg, | ||
uint16_t | val | ||
) |
Write PHY extended register.
Writes a PHY extended register.
hPhy | PHY device handle |
reg | Register number |
val | Value to be written |
int32_t EnetPhy_writeReg | ( | EnetPhy_Handle | hPhy, |
uint32_t | reg, | ||
uint16_t | val | ||
) |
Write PHY register.
Writes a PHY register. It's not meant for extended registers.
hPhy | PHY device handle |
reg | Register number |
val | Value to be written |