/**
 * \file appl_cnfg.h
 * \brief Headerfile for Memory Mapping and Muxing
 *
 * \copyright Copyright (c) 2012 Texas Instruments Incorporated ALL RIGHTS RESERVED
 *
*/
#include "plat_mux.h"
#include "osdrv_mmu.h"

#ifndef _ECAT_APPL_CNFG_H
#define _ECAT_APPL_CNFG_H

#ifndef USE_CPSW_DRIVER

/**IDK Mux Config*/
MUX_CONFIG idkMux[] = {
    { 0x0820 , 4 , AM335X_PIN_OUTPUT },	//	ehrpwm2A_mux1	gpmc_ad8 ==> PWM C
    { 0x0824 , 4 , AM335X_PIN_OUTPUT },	//	ehrpwm2B_mux1	gpmc_ad9 ==> PWM D
    { 0x082C , 4 , AM335X_PIN_OUTPUT },	//	ehrpwm0_synco_mux1	gpmc_ad11 ==> PWM SyncOut
    { 0x0840 , 5 , AM335X_PIN_INPUT },	    //	pr1_mii_mt1_clk	gpmc_a0
    { 0x0844 , 5 , AM335X_PIN_OUTPUT },	//	pr1_mii1_txd3	gpmc_a1
    { 0x0848 , 5 , AM335X_PIN_OUTPUT },	//	pr1_mii1_txd2	gpmc_a2
    { 0x084C , 5 , AM335X_PIN_OUTPUT },	//	pr1_mii1_txd1	gpmc_a3
    { 0x0850 , 5 , AM335X_PIN_OUTPUT },	//	pr1_mii1_txd0	gpmc_a4
    { 0x0854 , 5 , AM335X_PIN_INPUT },	    //	pr1_mii1_rxd3	gpmc_a5
    { 0x0858 , 5 , AM335X_PIN_INPUT },	    //	pr1_mii1_rxd2	gpmc_a6
    { 0x085C , 5 , AM335X_PIN_INPUT },	    //	pr1_mii1_rxd1	gpmc_a7
    { 0x0860 , 5 , AM335X_PIN_INPUT },	    //	pr1_mii1_rxd0	gpmc_a8
    { 0x0864 , 5 , AM335X_PIN_INPUT },	    //	pr1_mii_mr1_clk	gpmc_a9
    { 0x0868 , 5 , AM335X_PIN_INPUT },	    //	pr1_mii1_rxdv	gpmc_a10
    { 0x086C , 5 , AM335X_PIN_INPUT },	    //	pr1_mii1_rxer	gpmc_a11
    { 0x0874 , 5 , AM335X_PIN_OUTPUT },	//	pr1_mii1_txen	gpmc_wpn
    { 0x0878 , 5 , AM335X_PIN_INPUT },	    //	pr1_mii1_rxlink	gpmc_be1n
    { 0x0888 , 5 , AM335X_PIN_INPUT_PULLUP },	//	pr1_mdio_data	gpmc_csn3
    { 0x088C , 5 , AM335X_PIN_OUTPUT_PULLUP },	//	pr1_mdio_mdclk	gpmc_clk
    { 0x08A0 , 2 , AM335X_PIN_INPUT },		//	pr1_mii_mt0_clk_mux1	lcd_data0
    { 0x08A4 , 2 , AM335X_PIN_OUTPUT },	//	pr1_mii0_txen_mux1	lcd_data1
    { 0x08A8 , 2 , AM335X_PIN_OUTPUT },	//	pr1_mii0_txd3_mux1	lcd_data2
    { 0x08AC , 2 , AM335X_PIN_OUTPUT },	//	pr1_mii0_txd2_mux1	lcd_data3
    { 0x08B0 , 2 , AM335X_PIN_OUTPUT },	//	pr1_mii0_txd1_mux1	lcd_data4
    { 0x08B4 , 2 , AM335X_PIN_OUTPUT },	//	pr1_mii0_txd0_mux1	lcd_data5
    { 0x08B8 , 7 , AM335X_PIN_OUTPUT },	//	gpio2[12]	lcd_data6  ==> ECAT RUNLED
    { 0x08D0 , 5 , AM335X_PIN_INPUT },	    //	pr1_mii0_rxlink	lcd_data12
    { 0x08D4 , 5 , AM335X_PIN_INPUT },	    //	pr1_mii0_rxer	lcd_data13
    { 0x08D8 , 5 , AM335X_PIN_INPUT },	    //	pr1_mii_mr0_clk	lcd_data14
    { 0x08DC , 5 , AM335X_PIN_INPUT },	    //	pr1_mii0_rxdv	lcd_data15
    { 0x08E0 , 6 , AM335X_PIN_INPUT },	    //	pr1_mii0_rxd_post[3]	lcd_vsync
    { 0x08E4 , 6 , AM335X_PIN_INPUT },	    //	pr1_mii0_rxd_post[2]	lcd_hsync
    { 0x08E8 , 6 , AM335X_PIN_INPUT },	    //	pr1_mii0_rxd_post[1]	lcd_pclk
    { 0x08EC , 6 , AM335X_PIN_INPUT },	    //	pr1_mii0_rxd_post[0]	lcd_ac_bias_en
    { 0x0944 , 7 , AM335X_PIN_OUTPUT },	//	gpio0[29]	rmii1_refclk  ==> ECAT LED ACT1
    { 0x0950 , 3 , AM335X_PIN_OUTPUT },	//	ehrpwm0A_mux1	spi0_sclk ==> PWM A
    { 0x0954 , 3 , AM335X_PIN_OUTPUT },	//	ehrpwm0B_mux1	spi0_d0   ==> PWM B
    { 0x0958 , 2 , AM335X_PIN_OUTPUT | AM335X_PIN_INPUT },	//	I2C1_SDA_mux3	spi0_d1
    { 0x095C , 2 , AM335X_PIN_OUTPUT | AM335X_PIN_INPUT },	//	I2C1_SCL_mux3	spi0_cs0
    { 0x0968 , 6 , AM335X_PIN_OUTPUT },	//	pr1_edc_sync0_out	uart0_ctsn

    { 0x096C , 7 , AM335X_PIN_OUTPUT },	//	gpio1[9]	uart0_rtsn 	{ 0x09b0 , 4 , AM335X_PIN_OUTPUT;	//	spi1_cs1_mux4/CS	XDMA_EVENT_INTR0 -- muxed in the CPLD!!
    // HVS882 pinmux
    { 0x097C , 7 , AM335X_PIN_OUTPUT },	//	gpio0[13]	uart1_rtsn -- INDUS_LDn (load pulse for HVS882)
    { 0x0980 , 5 , AM335X_PIN_INPUT },	    //	pr1_uart0_rxd_mux1	uart1_rxd
    { 0x0984 , 5 , AM335X_PIN_OUTPUT },	//	pr1_uart0_txd_mux1	uart1_txd
    // SPI pinmux
    { 0x0994 , 3 , AM335X_PIN_OUTPUT },	//	spi1_d0_mux2/SIMO	mcasp0_fsx
    { 0x0998 , 3 , AM335X_PIN_INPUT_PULLUP },	//	spi1_d1_mux2/SOMI	mcasp0_axr0
    { 0x0990 , 3 , AM335X_PIN_OUTPUT | AM335X_PIN_INPUT_PULLDOWN },	//	spi1_sclk_mux2/CLK	mcasp0_aclkx . 
    { 0x099c , 3 , AM335X_PIN_OUTPUT },	//	spi1_cs0_mux4/CS	mcasp0_ahclkr -- muxed in the CPLD!!
    { 0x09A4 , 5 , AM335X_PIN_OUTPUT },	//	pr1_pru0_pru_r30[5]	mcasp0_fsr
    { 0x09A8 , 7 , AM335X_PIN_OUTPUT },	//	gpio3[20]	mcasp0_axr1    ==> ECAT LED ERR
    { 0x09AC , 7 , AM335X_PIN_OUTPUT },	//	gpio3[21]	mcasp0_ahclkx  ==> ECAT LED ACT0
    { 0x09b0 , 7 , AM335X_PIN_OUTPUT },	//	spi1_cs1_mux4/CS	XDMA_EVENT_INTR0 -- muxed in the CPLD!!
    {0xFFFFFFFF,0,0}
};

/**ICE Mux Config*/
MUX_CONFIG iceMux[] = {
	    { 0x0840 , 5 , AM335X_PIN_INPUT },	    //	pr1_mii_mt1_clk	gpmc_a0
	    { 0x0844 , 5 , AM335X_PIN_OUTPUT },	//	pr1_mii1_txd3	gpmc_a1
	    { 0x0848 , 5 , AM335X_PIN_OUTPUT },	//	pr1_mii1_txd2	gpmc_a2
	    { 0x084C , 5 , AM335X_PIN_OUTPUT },	//	pr1_mii1_txd1	gpmc_a3
	    { 0x0850 , 5 , AM335X_PIN_OUTPUT },	//	pr1_mii1_txd0	gpmc_a4
	    { 0x0854 , 5 , AM335X_PIN_INPUT },	    //	pr1_mii1_rxd3	gpmc_a5
	    { 0x0858 , 5 , AM335X_PIN_INPUT },	    //	pr1_mii1_rxd2	gpmc_a6
	    { 0x085C , 5 , AM335X_PIN_INPUT },	    //	pr1_mii1_rxd1	gpmc_a7
	    { 0x0860 , 5 , AM335X_PIN_INPUT },	    //	pr1_mii1_rxd0	gpmc_a8
	    { 0x0864 , 5 , AM335X_PIN_INPUT },	    //	pr1_mii_mr1_clk	gpmc_a9
	    { 0x0868 , 5 , AM335X_PIN_INPUT },	    //	pr1_mii1_rxdv	gpmc_a10
	    { 0x086C , 5 , AM335X_PIN_INPUT },	    //	pr1_mii1_rxer	gpmc_a11
	    { 0x0874 , 5 , AM335X_PIN_OUTPUT },	//	pr1_mii1_txen	gpmc_wpn
	    { 0x0878 , 5 , AM335X_PIN_INPUT },	    //	pr1_mii1_rxlink	gpmc_be1n
	    { 0x0888 , 5 , AM335X_PIN_INPUT_PULLUP },	//	pr1_mdio_data	gpmc_csn3
	    { 0x088C , 5 , AM335X_PIN_OUTPUT_PULLUP },	//	pr1_mdio_mdclk	gpmc_clk
	    { 0x089C , 7 , AM335X_PIN_OUTPUT },	//	gpmc_be0n_cle	GPIO2[5] -> TLK110 Port0 Reset
	    { 0x08A0 , 2 , AM335X_PIN_INPUT },	//	pr1_mii_mt0_clk_mux1	lcd_data0
	    { 0x08A4 , 2 , AM335X_PIN_OUTPUT },	//	pr1_mii0_txen_mux1	lcd_data1
	    { 0x08A8 , 2 , AM335X_PIN_OUTPUT },	//	pr1_mii0_txd3_mux1	lcd_data2
	    { 0x08AC , 2 , AM335X_PIN_OUTPUT },	//	pr1_mii0_txd2_mux1	lcd_data3
	    { 0x08B0 , 2 , AM335X_PIN_OUTPUT },	//	pr1_mii0_txd1_mux1	lcd_data4
	    { 0x08B4 , 2 , AM335X_PIN_OUTPUT },	//	pr1_mii0_txd0_mux1	lcd_data5
	    { 0x08D0 , 5 , AM335X_PIN_INPUT },	//	pr1_mii0_rxlink	lcd_data12
	    { 0x08D4 , 5 , AM335X_PIN_INPUT },	//	pr1_mii0_rxer	lcd_data13
	    { 0x08D8 , 5 , AM335X_PIN_INPUT },	//	pr1_mii_mr0_clk	lcd_data14
	    { 0x08DC , 5 , AM335X_PIN_INPUT },	//	pr1_mii0_rxdv	lcd_data15
	    { 0x091C , 7 , AM335X_PIN_OUTPUT },	//	mii1_txd3
	    { 0x0920 , 7 , AM335X_PIN_OUTPUT },	//	mii1_txd2

	    {0xFFFFFFFF,0,0}
};
/**ICEv1 Mux Config*/
MUX_CONFIG icev1Mux[] = {
    { 0x0800 , 0 , AM335X_PIN_OUTPUT }, 	//	gpmc_ad0	gpmc_ad0
    { 0x0804 , 0 , AM335X_PIN_OUTPUT },	//	gpmc_ad1	gpmc_ad1
    { 0x0808 , 0 , AM335X_PIN_OUTPUT },	//	gpmc_ad2	gpmc_ad2
    { 0x080C , 0 , AM335X_PIN_OUTPUT },	//	gpmc_ad3	gpmc_ad3
    { 0x0810 , 0 , AM335X_PIN_OUTPUT },	//	gpmc_ad4	gpmc_ad4
    { 0x0814 , 0 , AM335X_PIN_OUTPUT },	//	gpmc_ad5	gpmc_ad5
    { 0x0818 , 0 , AM335X_PIN_OUTPUT },	//	gpmc_ad6	gpmc_ad6
    { 0x081C , 0 , AM335X_PIN_OUTPUT },	//	gpmc_ad7	gpmc_ad7
    { 0x0820 , 0 , AM335X_PIN_OUTPUT },	//  gpmc_ad8
    { 0x0824 , 0 , AM335X_PIN_OUTPUT },	//	gpmc_ad9
    { 0x0828 , 0 , AM335X_PIN_OUTPUT },	//	gpmc_ad10
    { 0x082C , 0 , AM335X_PIN_OUTPUT },	//	gpmc_ad11
    { 0x0830 , 0 , AM335X_PIN_OUTPUT },	//	gpmc_ad12
    { 0x0834 , 0 , AM335X_PIN_OUTPUT },	//	gpmc_ad13
    { 0x0838 , 0 , AM335X_PIN_OUTPUT },	//	gpmc_ad14
    { 0x083C , 0 , AM335X_PIN_OUTPUT },	//	gpmc_ad15
    { 0x0870 , 0 , AM335X_PIN_OUTPUT },	//	gpmc_wait0	gpmc_wait0
    { 0x087C , 0 , AM335X_PIN_OUTPUT },	//	gpmc_csn0
    { 0x0880 , 0 , AM335X_PIN_OUTPUT },	//	gpmc_csn1
    { 0x0884 , 7 , AM335X_PIN_OUTPUT },	//	gpmc_csn2 - GPIO1[31] -> TLK110 Port1 Reset
    { 0x0890 , 0 , AM335X_PIN_OUTPUT },	//	gpmc_advn_ale	gpmc_advn_ale
    { 0x0894 , 0 , AM335X_PIN_OUTPUT },	//	gpmc_oen_ren	gpmc_oen_ren
    { 0x0898 , 0 , AM335X_PIN_OUTPUT },	//	gpmc_wen	gpmc_wen
    { 0x08CC , 7 , AM335X_PIN_OUTPUT },	//	lcd_data11 GPIO2[17] -> LCD_power_enable
    { 0x08E0 , 6 , AM335X_PIN_INPUT },	//	pr1_mii0_rxd_post[3]	lcd_vsync
    { 0x08E4 , 6 , AM335X_PIN_INPUT },	//	pr1_mii0_rxd_post[2]	lcd_hsync
    { 0x08E8 , 6 , AM335X_PIN_INPUT },	//	pr1_mii0_rxd_post[1]	lcd_pclk
    { 0x08EC , 6 , AM335X_PIN_INPUT },	//	pr1_mii0_rxd_post[0]	lcd_ac_bias_en
    { 0x0908 ,  7 , AM335X_PIN_OUTPUT },	//	gpio3[0]	mii1_col	-> ECAT LED1
    { 0x090C ,  7 , AM335X_PIN_OUTPUT },	//	gpio3[1]	mii1_crs	-> ECAT LED2
    { 0x0910 ,  7 , AM335X_PIN_OUTPUT },	//	gpio3[2]	mii1_rxerr	-> ECAT LED3
    { 0x0914 ,  7 , AM335X_PIN_OUTPUT },	//	gpio3[3]	mii1_txen	-> ECAT LED4
    { 0x0944 , 7 , AM335X_PIN_OUTPUT },	//	gpio0[12] uart1_ctsn -> TLK_SYSBOOT_FET (Beta)
    { 0x0948 , 7 , AM335X_PIN_OUTPUT },	//	gpio0[0]	mdio_data -> LED 6a
    { 0x094C , 7 , AM335X_PIN_OUTPUT },	//	gpio0[1]	mdio_clk  -> LED 6b
    { 0x0950 , 0 , AM335X_PIN_OUTPUT | AM335X_PIN_INPUT },	//	spi0_sclk
    { 0x0954 , 7 , AM335X_PIN_INPUT },	//	spi0_DO
    { 0x0958 , 0 , AM335X_PIN_OUTPUT },	//	spi0_DI
    { 0x095C , 0 , AM335X_PIN_OUTPUT },	//	spi0_cs0
    // enable ECAT SYNC0 for DC Tests
    { 0x0968 , 7 , AM335X_PIN_OUTPUT },	//	pr1_edc_sync0_out -> DC mode - uart0_ctsn
    { 0x096C , 7 , AM335X_PIN_OUTPUT },	//	gpio1[9]	uart0_rtsn -> DC test GPIO
    { 0x097C , 7 , AM335X_PIN_OUTPUT },	//	gpio0[13] uart1_rtsn -> LED 6c Blue
    { 0x0988 ,  0 , AM335X_PIN_OUTPUT | AM335X_PIN_INPUT },	//	I2C0_SDA	-> config by boot code ?
    { 0x098C ,  0 , AM335X_PIN_OUTPUT | AM335X_PIN_INPUT },	//	I2C0_SCL
    // SPI pinmux
    { 0x0990 , 3 , AM335X_PIN_OUTPUT | AM335X_PIN_INPUT_PULLDOWN },	//	spi1_sclk_mux2/CLK	mcasp0_aclkx . IMPORTATN: You need to enable both, input and output. Input clock is feed back into the RX logic of SPI.
    { 0x0994 , 3 , AM335X_PIN_OUTPUT },	//	spi1_d0_mux2/SIMO	mcasp0_fsx
    { 0x0998 , 3 , AM335X_PIN_INPUT_PULLUP },	//	spi1_d1_mux2/SOMI	mcasp0_axr0
	{ 0x099c , 7 , AM335X_PIN_OUTPUT },	//	spi1_cs0_mux4: HVS SPI1 CS in GPIO mode
	{ 0x09A0 , 7 , AM335X_PIN_OUTPUT },	//	gpio3[18]	mcasp0_aclkr -> INDUS_LDn
    {0xFFFFFFFF,0,0}
};

/**Memory Mapping Entry*/
SYS_MMU_ENTRY applMmuEntries[] = {
    {(void*)0x08000000,SYS_MMU_CACHEABLE},  // Non bufferable| Cacheable
    {(void*)0x08100000,SYS_MMU_CACHEABLE},  // Non bufferable| Cacheable
    {(void*)0x08200000,SYS_MMU_CACHEABLE},  // Non bufferable| Cacheable
    {(void*)0x40300000,0},  // Non bufferable| Non Cacheable
    {(void*)0x48300000,0},  // Non bufferable| Non Cacheable
    {(void*)0x48200000,0},  // Non bufferable| Non Cacheable
    {(void*)0x48100000,0},  // Non bufferable| Non Cacheable
    {(void*)0x48000000,0},  // Non bufferable| Non Cacheable
    {(void*)0x44E00000,0},  // Non bufferable| Non Cacheable
    {(void*)0x4A300000,0},  // Non bufferable| Non Cacheable
    {(void*)0x49000000,0},   // Non bufferable| Non Cacheable
    {(void*)0x4A000000,0},  //L4 FAST CFG- Non bufferable| Non Cacheable    
    {(void*)0x4A100000,0},  //CPSW - Non bufferable| Non Cacheable
    {(void*)0xFFFFFFFF,0xFFFFFFFF}   
    
    
};

/**ICE2 Mux Config*/
MUX_CONFIG icev2Mux[] = {
    /* Pin Mux for MII 1 */
    { 0x0870 , 5 , AM335X_PIN_INPUT },	//	gpmc_wait0	gpmc_wait0
   // { 0x0824 , 5 , AM335X_PIN_INPUT },	//	gpmc_ad9
    { 0x0880 , 7 , AM335X_PIN_OUTPUT },	//	GPMC_CSN(1) -> LED_4
    { 0x08C0 , 5 , AM335X_PIN_INPUT },	//	pr1_mii0_rxdv	lcd_data15
    { 0x08C4 , 5 , AM335X_PIN_INPUT },	//	pr1_mii0_rxdv	lcd_data15
    { 0x08C8 , 5 , AM335X_PIN_INPUT },	//	pr1_mii0_rxdv	lcd_data15
    { 0x08CC , 5 , AM335X_PIN_INPUT },	//	pr1_mii0_rxdv	lcd_data15
    { 0x08EC , 2 , AM335X_PIN_INPUT },	//	pr1_mii0_rxd_post[0]	lcd_ac_bias_en
    { 0x08E8 , 2 , AM335X_PIN_INPUT },	//	pr1_mii0_rxd_post[1]	lcd_pclk
#ifdef ICE_V2_0
    { 0x09AC , 7 , AM335X_PIN_OUTPUT },
#else
    { 0x0918 , 7 , AM335X_PIN_OUTPUT },
#endif
    /* GPIO3_10 for MUX control configuration 0- PRU-MII1 , 1- RMII2 */
    { 0x092C , 7 , AM335X_PIN_OUTPUT }, //  MII1_TXCLK -> LED_3
    { 0x0930 , 7 , AM335X_PIN_OUTPUT },
    { 0x0964 , 7 , AM335X_PULL_UP },	/* GPIO0_7 for FET_nOE */
    { 0x096C , 7 , AM335X_PIN_OUTPUT },	//	gpio1[9]	uart0_rtsn -> DC test GPIO

    { 0x09B0 , 7 , AM335X_PIN_OUTPUT }, //  XDMA_EVENT_INTR(0) -> LED_5
    { 0x09B4 , 7 , AM335X_PIN_OUTPUT }, //  XDMA_EVENT_INTR(1) -> LED_6
    { 0x0A1C , 7 , AM335X_PULL_UP },	/* DDR_VTT_EN - GPIO0_18 */
    {0xFFFFFFFF,0,0}
};

#else

/**Memory Mapping Entry*/
SYS_MMU_ENTRY applMmuEntries[] = {
    {(void*)0x08000000,SYS_MMU_CACHEABLE},  // Non bufferable| Cacheable
    {(void*)0x08100000,SYS_MMU_CACHEABLE},  // Non bufferable| Cacheable
    {(void*)0x08200000,SYS_MMU_CACHEABLE},  // Non bufferable| Cacheable
    {(void*)0x40300000,0},  // Non bufferable| Non Cacheable
    {(void*)0x48300000,0},  // Non bufferable| Non Cacheable
    {(void*)0x48200000,0},  // Non bufferable| Non Cacheable
    {(void*)0x48100000,0},  // Non bufferable| Non Cacheable
    {(void*)0x48000000,0},  // Non bufferable| Non Cacheable
    {(void*)0x44E00000,0},  // Non bufferable| Non Cacheable
    {(void*)0x4A100000,0},   // Non bufferable| Non Cacheable
    {(void*)0x4A300000,0},  // Non bufferable| Non Cacheable
    {(void*)0x49000000,0},   // Non bufferable| Non Cacheable
    {(void*)0xFFFFFFFF,0xFFFFFFFF}
};

/**IDK Mux Config*/
MUX_CONFIG idkMux[] = {
	{ 0x0908 , 0 , AM335X_PIN_INPUT }, // GMII1_COL  	conf_mii1_col
	{ 0x090c , 0 , AM335X_PIN_INPUT }, // GMII1_CRS	 	conf_mii1_crs
	{ 0x0910 , 0 , AM335X_PIN_INPUT }, // GMII1_RXERR 	conf_mii1_rx_er
	{ 0x0914 , 0 , AM335X_PIN_OUTPUT}, // GMII1_TXEN  	conf_mii1_tx_en
	{ 0x0918 , 0 , AM335X_PIN_INPUT }, // GMII1_RXDV	conf_mii1_rx_dv
	{ 0x091c , 0 , AM335X_PIN_OUTPUT}, // GMII1_TXD3	conf_mii1_txd3
	{ 0x0920 , 0 , AM335X_PIN_OUTPUT}, // GMII1_TXD2	conf_mii1_txd2
	{ 0x0924 , 0 , AM335X_PIN_OUTPUT}, // GMII1_TXD1	conf_mii1_txd1
	{ 0x0928 , 0 , AM335X_PIN_OUTPUT}, // GMII1_TXD0	conf_mii1_txd0
	{ 0x092c , 0 , AM335X_PIN_INPUT }, // GMII1_TXCLK	conf_mii1_tx_clk
	{ 0x0930 , 0 , AM335X_PIN_INPUT }, // GMII1_RXCLK	conf_mii1_rx_clk
	{ 0x0934 , 0 , AM335X_PIN_INPUT }, // GMII1_RXD3	conf_mii1_rxd3
	{ 0x0938 , 0 , AM335X_PIN_INPUT }, // GMII1_RXD2	conf_mii1_rxd2
	{ 0x093c , 0 , AM335X_PIN_INPUT }, // GMII1_RXD1	conf_mii1_rxd1
	{ 0x0940 , 0 , AM335X_PIN_INPUT }, // GMII1_RXD0	conf_mii1_rxd0
	{ 0x0944 , 0 , AM335X_PIN_INPUT }, // RMII1_REFCLK	conf_rmii1_ref_clk
	{ 0x0948 , 0 , AM335X_PIN_INPUT_PULLUP }, // MDIO_DATA	conf_mdio
	{ 0x094c , 0 , AM335X_PIN_OUTPUT_PULLUP}, // MDIO_CLK	conf_mdc
	{0xFFFFFFFF,0,0}
};
/**ICE2 Mux Config*/
MUX_CONFIG icev2Mux[] = {
	{ 0x0948 , 0 , AM335X_PIN_INPUT_PULLUP }, 	// 		conf_mdio
	{ 0x094c , 0 , AM335X_PIN_OUTPUT_PULLUP}, 	// 		conf_mdc
	{ 0x090c , 1 , AM335X_PIN_INPUT }, 			// 	 	conf_mii1_crs
	{ 0x0914 , 1 , AM335X_PIN_OUTPUT}, 			//   	conf_mii1_tx_en
	{ 0x0924 , 1 , AM335X_PIN_OUTPUT}, 			// 		conf_mii1_txd1
	{ 0x0928 , 1 , AM335X_PIN_OUTPUT}, 			// 		conf_mii1_txd0
	{ 0x092c , 0 , AM335X_PIN_INPUT }, 			// 		conf_mii1_tx_clk
	{ 0x0930 , 0 , AM335X_PIN_INPUT }, 			// 		conf_mii1_rx_clk
	{ 0x0910 , 1 , AM335X_PIN_INPUT }, 			// 	 	conf_mii1_rx_er
	{ 0x093c , 1 , AM335X_PIN_INPUT }, 			// 		conf_mii1_rxd1
	{ 0x0940 , 1 , AM335X_PIN_INPUT }, 			// 		conf_mii1_rxd0
	{ 0x0944 , 0 , AM335X_PIN_INPUT_PULLUP }, 	// 		conf_rmii1_ref_clk
	{ 0x0840 , 3 , AM335X_PIN_OUTPUT },	    	//		gpmc_a0
	{ 0x0850 , 3 , AM335X_PIN_OUTPUT },			//		gpmc_a4
	{ 0x0854 , 3 , AM335X_PIN_OUTPUT },	   	 	//		gpmc_a5
	{ 0x0868 , 3 , AM335X_PIN_INPUT },	    	//		gpmc_a10
	{ 0x086C , 3 , AM335X_PIN_INPUT },	    	//		gpmc_a11
	{ 0x0870 , 3 , AM335X_PIN_INPUT },			//		gpmc_wait0
	{ 0x0874 , 3 , AM335X_PIN_INPUT },			//		gpmc_wpn
	{ 0x0908 , 1 , AM335X_PIN_INPUT_PULLUP }, 	// 	  	conf_mii1_col
	{ 0x089C , 7 , AM335X_PIN_OUTPUT },			//		gpmc_be0n_cle
	{ 0x09AC , 7 , AM335X_PIN_OUTPUT },			//		conf_mcasp0_ahclkx
	{ 0x0930 , 7 , AM335X_PIN_OUTPUT }, 		// 		conf_mii1_rx_clk
	{ 0x0964 , 7 , AM335X_PULL_DISA },			//		conf_ecap0_in_pwm0_out
	{ 0x0A1C , 7 , AM335X_PULL_DISA },			//		conf_usb0_drvvbus
	{ 0x0918 , 7 , AM335X_PIN_OUTPUT }, 		// 		conf_mii1_rx_dv
	{0xFFFFFFFF,0,0}
};
#endif

#endif
