/dts-v1/;

/ {
	#address-cells = <0x1>;
	#size-cells = <0x1>;
	compatible = "ti,am5718", "ti,dra722", "ti,dra72", "ti,dra7";
	interrupt-parent = <0x1>;
	model = "TI AM5718 VAHM GE9X";

	chosen {
	};

	aliases {
		i2c0 = "/ocp/i2c@48070000";
		i2c1 = "/ocp/i2c@48072000";
		i2c2 = "/ocp/i2c@48060000";
		i2c3 = "/ocp/i2c@4807a000";
		i2c4 = "/ocp/i2c@4807c000";
		serial0 = "/ocp/serial@4806a000";
		serial1 = "/ocp/serial@4806c000";
		serial2 = "/ocp/serial@48020000";
		serial3 = "/ocp/serial@4806e000";
		serial4 = "/ocp/serial@48066000";
		serial5 = "/ocp/serial@48068000";
		serial6 = "/ocp/serial@48420000";
		serial7 = "/ocp/serial@48422000";
		serial8 = "/ocp/serial@48424000";
		serial9 = "/ocp/serial@4ae2b000";
		ethernet0 = "/ocp/ethernet@48484000/slave@48480200";
		ethernet1 = "/ocp/ethernet@48484000/slave@48480300";
		d_can0 = "/ocp/can@481cc000";
		d_can1 = "/ocp/can@481d0000";
		rproc0 = "/ocp/ipu@58820000";
		rproc1 = "/ocp/ipu@55020000";
		rproc2 = "/ocp/dsp@40800000";
	};

	memory {
		device_type = "memory";
		reg = <0x80000000 0x20000000>;
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <0x1 0xd 0x308 0x1 0xe 0x308 0x1 0xb 0x308 0x1 0xa 0x308>;
		interrupt-parent = <0x2>;
	};

	interrupt-controller@48211000 {
		compatible = "arm,cortex-a15-gic";
		interrupt-controller;
		#interrupt-cells = <0x3>;
		reg = <0x48211000 0x1000 0x48212000 0x1000 0x48214000 0x2000 0x48216000 0x2000>;
		interrupts = <0x1 0x9 0x304>;
		interrupt-parent = <0x2>;
		linux,phandle = <0x2>;
		phandle = <0x2>;
	};

	interrupt-controller@48281000 {
		compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
		interrupt-controller;
		#interrupt-cells = <0x3>;
		reg = <0x48281000 0x1000>;
		interrupt-parent = <0x2>;
		linux,phandle = <0x3>;
		phandle = <0x3>;
	};

	soc {
		compatible = "ti,omap-infra";

		mpu {
			compatible = "ti,omap5-mpu";
			ti,hwmods = "mpu";
		};
	};

	ocp {
		compatible = "ti,dra7-l3-noc", "simple-bus";
		#address-cells = <0x1>;
		#size-cells = <0x1>;
		ranges;
		ti,hwmods = "l3_main_1", "l3_main_2";
		reg = <0x44000000 0x1000000 0x45000000 0x1000>;
		interrupts-extended = <0x1 0x0 0x4 0x4 0x3 0x0 0xa 0x4>;

		l4@4a000000 {
			compatible = "ti,dra7-l4-cfg", "simple-bus";
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			ranges = <0x0 0x4a000000 0x22c000>;

			scm@2000 {
				compatible = "ti,dra7-scm-core", "simple-bus";
				reg = <0x2000 0x2000>;
				#address-cells = <0x1>;
				#size-cells = <0x1>;
				ranges = <0x0 0x2000 0x2000>;

				scm_conf@0 {
					compatible = "syscon", "simple-bus";
					reg = <0x0 0x1400>;
					#address-cells = <0x1>;
					#size-cells = <0x1>;
					linux,phandle = <0x4>;
					phandle = <0x4>;

					pbias_regulator {
						compatible = "ti,pbias-omap";
						reg = <0xe00 0x4>;
						syscon = <0x4>;

						pbias_mmc_omap5 {
							regulator-name = "pbias_mmc_omap5";
							regulator-min-microvolt = <0x1b7740>;
							regulator-max-microvolt = <0x2dc6c0>;
							linux,phandle = <0xb7>;
							phandle = <0xb7>;
						};
					};

					clocks {
						#address-cells = <0x1>;
						#size-cells = <0x0>;

						dss_deshdcp_clk {
							#clock-cells = <0x0>;
							compatible = "ti,gate-clock";
							clocks = <0x5>;
							ti,bit-shift = <0x0>;
							reg = <0x558>;
						};

						ehrpwm0_tbclk {
							#clock-cells = <0x0>;
							compatible = "ti,gate-clock";
							clocks = <0x6>;
							ti,bit-shift = <0x14>;
							reg = <0x558>;
						};

						ehrpwm1_tbclk {
							#clock-cells = <0x0>;
							compatible = "ti,gate-clock";
							clocks = <0x6>;
							ti,bit-shift = <0x15>;
							reg = <0x558>;
						};

						ehrpwm2_tbclk {
							#clock-cells = <0x0>;
							compatible = "ti,gate-clock";
							clocks = <0x6>;
							ti,bit-shift = <0x16>;
							reg = <0x558>;
						};
					};
				};

				pinmux@1400 {
					compatible = "ti,dra7-padconf", "pinctrl-single";
					reg = <0x1400 0x464>;
					#address-cells = <0x1>;
					#size-cells = <0x0>;
					#interrupt-cells = <0x1>;
					interrupt-controller;
					pinctrl-single,register-width = <0x20>;
					pinctrl-single,function-mask = <0x3fffffff>;

					i2c1_pins_default {
						pinctrl-single,pins = <0x404 0x50000 0x400 0x50000>;
					};

					i2c2_pins_default {
						pinctrl-single,pins = <0x40c 0x50000 0x408 0x50000>;
					};

					uart1_pins_default {
						pinctrl-single,pins = <0x3e0 0x50000 0x3e4 0x10000>;
					};

					uart3_pins_default {
						pinctrl-single,pins = <0x3f8 0x50002 0x3fc 0x10001>;
					};

					pruss1_uart_pins_default {
						pinctrl-single,pins = <0x168 0x5000b 0x16c 0x1000b>;
					};

					spi_pins_default {
						pinctrl-single,pins = <0x394 0x10001 0x39c 0x10001 0x398 0x50001 0x3a0 0x10001 0x3a4 0x50000 0x3b0 0x50000 0x3ac 0x50000>;
					};

					mcspi3_pins {
						pinctrl-single,pins = <0x380 0x50001 0x388 0x10001 0x384 0x50001 0x38c 0x50001>;
						linux,phandle = <0xbd>;
						phandle = <0xbd>;
					};

					gpio_pins_default {
						pinctrl-single,pins = <0x158 0x5000e 0x164 0x5000e 0x170 0x5000e 0x174 0x5000e 0x178 0x5000e 0x17c 0x5000e 0x184 0x5000e 0x190 0x5000e 0x198 0x5000e 0x19c 0x5000e 0x1a0 0x5000e 0x1ac 0x5000e 0x1b0 0x5000e 0x1b4 0x5000e>;
					};

					gpio_pins_virtual {
						pinctrl-single,pins = <0x154 0x501be 0x15c 0x501be 0x160 0x5019e 0x188 0x5019e 0x194 0x5019e>;
					};

					int_pins_default {
						pinctrl-single,pins = <0x424 0x50001 0x418 0x5000e>;
					};

					mdio_pins_default {
						pinctrl-single,pins = <0x3b8 0x10005 0x3bc 0x50005>;
					};

					gpmc_pins_default {
						pinctrl-single,pins = <0x1c 0x50000 0x18 0x50000 0x14 0x50000 0x10 0x50000 0xc 0x50000 0x8 0x50000 0x4 0x50000 0x0 0x50000 0xd8 0x50000 0xc0 0x50003 0xb4 0x10000 0xb0 0x10000 0xc4 0x10000 0xc8 0x10000 0xcc 0x10000 0xd0 0x10000>;
						linux,phandle = <0xd6>;
						phandle = <0xd6>;
					};

					gpmc_pins_virtual {
						pinctrl-single,pins = <0x1c 0x501d0 0x18 0x501d0 0x14 0x501d0 0x10 0x501d0 0xc 0x501d0 0x8 0x501d0 0x4 0x501d0 0x0 0x501d0 0xd8 0x501f0 0xc0 0x501f3 0xb4 0x101f0 0xb0 0x101f0 0xc4 0x101f0 0xc8 0x101f0 0xcc 0x101f0 0xd0 0x101f0>;
					};

					qspi1_pins_default {
						pinctrl-single,pins = <0x88 0x10001 0x74 0x50001 0xb8 0x10001 0xbc 0x10001 0x80 0x50001 0x84 0x50001 0x7c 0x50001 0x78 0x50001>;
					};

					qspi1_pins_manual {
						pinctrl-single,pins = <0x88 0x10001 0x74 0x50001 0xb8 0x10001 0xbc 0x10001 0x80 0x50001 0x84 0x50001 0x7c 0x50001 0x78 0x50001>;
					};

					qspi1_pins_virtual1 {
						pinctrl-single,pins = <0x88 0x101e1 0x74 0x501e1 0xb8 0x101e1 0xbc 0x101d1 0x7c 0x501e1 0x78 0x501e1>;
					};

					qspi1_pins_virtual2 {
						pinctrl-single,pins = <0x88 0x101d1 0x74 0x501d1 0xb8 0x101d1 0xbc 0x101c1 0x7c 0x501d1 0x78 0x501d1>;
					};

					debug_pins_trace {
						pinctrl-single,pins = <0x430 0x50000 0x434 0x50000 0x438 0x10000 0x43c 0x50000 0x440 0x50000 0x444 0x10000 0x448 0x50000 0x44c 0x50000 0x1e4 0x10002 0x204 0x10002 0x224 0x10002 0x1e8 0x10002 0x1ec 0x10002 0x1f0 0x10002 0x1f4 0x10002 0x1f8 0x10002 0x208 0x10002 0x20c 0x10002 0x210 0x10002 0x214 0x10002 0x218 0x10002 0x228 0x10002 0x22c 0x10002 0x230 0x10002>;
					};
				};
			};

			cm_core_aon@5000 {
				compatible = "ti,dra7-cm-core-aon";
				reg = <0x5000 0x2000>;

				clocks {
					#address-cells = <0x1>;
					#size-cells = <0x0>;

					atl_clkin0_ck {
						#clock-cells = <0x0>;
						compatible = "ti,dra7-atl-clock";
						clocks = <0x7>;
						linux,phandle = <0x41>;
						phandle = <0x41>;
					};

					atl_clkin1_ck {
						#clock-cells = <0x0>;
						compatible = "ti,dra7-atl-clock";
						clocks = <0x7>;
						linux,phandle = <0x40>;
						phandle = <0x40>;
					};

					atl_clkin2_ck {
						#clock-cells = <0x0>;
						compatible = "ti,dra7-atl-clock";
						clocks = <0x7>;
						linux,phandle = <0x3f>;
						phandle = <0x3f>;
					};

					atl_clkin3_ck {
						#clock-cells = <0x0>;
						compatible = "ti,dra7-atl-clock";
						clocks = <0x7>;
						linux,phandle = <0x3e>;
						phandle = <0x3e>;
					};

					hdmi_clkin_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x0>;
						linux,phandle = <0x2c>;
						phandle = <0x2c>;
					};

					mlb_clkin_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x0>;
						linux,phandle = <0xa3>;
						phandle = <0xa3>;
					};

					mlbp_clkin_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x0>;
						linux,phandle = <0xa4>;
						phandle = <0xa4>;
					};

					pciesref_acs_clk_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x5f5e100>;
						linux,phandle = <0x59>;
						phandle = <0x59>;
					};

					ref_clkin0_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x0>;
						linux,phandle = <0x43>;
						phandle = <0x43>;
					};

					ref_clkin1_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x0>;
						linux,phandle = <0x44>;
						phandle = <0x44>;
					};

					ref_clkin2_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x0>;
						linux,phandle = <0x45>;
						phandle = <0x45>;
					};

					ref_clkin3_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x0>;
						linux,phandle = <0x46>;
						phandle = <0x46>;
					};

					rmii_clk_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x0>;
					};

					sdvenc_clkin_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x0>;
					};

					secure_32k_clk_src_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x8000>;
						linux,phandle = <0x8c>;
						phandle = <0x8c>;
					};

					sys_32k_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x8000>;
						linux,phandle = <0x4e>;
						phandle = <0x4e>;
					};

					virt_12000000_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0xb71b00>;
						linux,phandle = <0x7e>;
						phandle = <0x7e>;
					};

					virt_13000000_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0xc65d40>;
					};

					virt_16800000_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x1005900>;
						linux,phandle = <0x80>;
						phandle = <0x80>;
					};

					virt_19200000_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x124f800>;
						linux,phandle = <0x81>;
						phandle = <0x81>;
					};

					virt_20000000_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x1312d00>;
						linux,phandle = <0x7f>;
						phandle = <0x7f>;
					};

					virt_26000000_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x18cba80>;
						linux,phandle = <0x82>;
						phandle = <0x82>;
					};

					virt_27000000_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x19bfcc0>;
						linux,phandle = <0x83>;
						phandle = <0x83>;
					};

					virt_38400000_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x249f000>;
						linux,phandle = <0x84>;
						phandle = <0x84>;
					};

					sys_clkin2 {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x1588800>;
						linux,phandle = <0x42>;
						phandle = <0x42>;
					};

					usb_otg_clkin_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x0>;
						linux,phandle = <0x89>;
						phandle = <0x89>;
					};

					video1_clkin_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x0>;
						linux,phandle = <0x37>;
						phandle = <0x37>;
					};

					video1_m2_clkin_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x0>;
						linux,phandle = <0x2b>;
						phandle = <0x2b>;
					};

					video2_clkin_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x0>;
						linux,phandle = <0x38>;
						phandle = <0x38>;
					};

					video2_m2_clkin_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x0>;
						linux,phandle = <0x2a>;
						phandle = <0x2a>;
					};

					dpll_abe_ck {
						#clock-cells = <0x0>;
						compatible = "ti,omap4-dpll-m4xen-clock";
						clocks = <0x8 0x9>;
						reg = <0x1e0 0x1e4 0x1ec 0x1e8>;
						ti,sink-clkdm = <0xa>;
						linux,phandle = <0xb>;
						phandle = <0xb>;
					};

					dpll_abe_x2_ck {
						#clock-cells = <0x0>;
						compatible = "ti,omap4-dpll-x2-clock";
						clocks = <0xb>;
						linux,phandle = <0xc>;
						phandle = <0xc>;
					};

					dpll_abe_m2x2_ck {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0xc>;
						ti,max-div = <0x1f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x1f0>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						linux,phandle = <0xd>;
						phandle = <0xd>;
					};

					abe_clk {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0xd>;
						ti,max-div = <0x4>;
						reg = <0x108>;
						ti,index-power-of-two;
						linux,phandle = <0x86>;
						phandle = <0x86>;
					};

					dpll_abe_m2_ck {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0xb>;
						ti,max-div = <0x1f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x1f0>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						linux,phandle = <0x6f>;
						phandle = <0x6f>;
					};

					dpll_abe_m3x2_ck {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0xc>;
						ti,max-div = <0x1f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x1f4>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						linux,phandle = <0xf>;
						phandle = <0xf>;
					};

					dpll_core_byp_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0xe 0xf>;
						ti,bit-shift = <0x17>;
						reg = <0x12c>;
						linux,phandle = <0x10>;
						phandle = <0x10>;
					};

					dpll_core_ck {
						#clock-cells = <0x0>;
						compatible = "ti,omap4-dpll-core-clock";
						clocks = <0xe 0x10>;
						reg = <0x120 0x124 0x12c 0x128>;
						linux,phandle = <0x11>;
						phandle = <0x11>;
					};

					dpll_core_x2_ck {
						#clock-cells = <0x0>;
						compatible = "ti,omap4-dpll-x2-clock";
						clocks = <0x11>;
						linux,phandle = <0x12>;
						phandle = <0x12>;
					};

					dpll_core_h12x2_ck {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x12>;
						ti,max-div = <0x3f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x13c>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						linux,phandle = <0x13>;
						phandle = <0x13>;
					};

					mpu_dpll_hs_clk_div {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x13>;
						clock-mult = <0x1>;
						clock-div = <0x1>;
						linux,phandle = <0x14>;
						phandle = <0x14>;
					};

					dpll_mpu_ck {
						#clock-cells = <0x0>;
						compatible = "ti,omap5-mpu-dpll-clock";
						clocks = <0xe 0x14>;
						reg = <0x160 0x164 0x16c 0x168>;
						linux,phandle = <0x15>;
						phandle = <0x15>;
					};

					dpll_mpu_m2_ck {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x15>;
						ti,max-div = <0x1f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x170>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						linux,phandle = <0x16>;
						phandle = <0x16>;
					};

					mpu_dclk_div {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x16>;
						clock-mult = <0x1>;
						clock-div = <0x1>;
						linux,phandle = <0x90>;
						phandle = <0x90>;
					};

					dsp_dpll_hs_clk_div {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x13>;
						clock-mult = <0x1>;
						clock-div = <0x1>;
						linux,phandle = <0x17>;
						phandle = <0x17>;
					};

					dpll_dsp_byp_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0xe 0x17>;
						ti,bit-shift = <0x17>;
						reg = <0x240>;
						linux,phandle = <0x18>;
						phandle = <0x18>;
					};

					dpll_dsp_ck {
						#clock-cells = <0x0>;
						compatible = "ti,omap4-dpll-clock";
						clocks = <0xe 0x18>;
						reg = <0x234 0x238 0x240 0x23c>;
						ti,sink-clkdm = <0x19>;
						assigned-clocks = <0x1a>;
						assigned-clock-rates = <0x29b92700>;
						linux,phandle = <0x1a>;
						phandle = <0x1a>;
					};

					dpll_dsp_m2_ck {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x1a>;
						ti,max-div = <0x1f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x244>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						assigned-clocks = <0x1b>;
						assigned-clock-rates = <0x29b92700>;
						linux,phandle = <0x1b>;
						phandle = <0x1b>;
					};

					iva_dpll_hs_clk_div {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x13>;
						clock-mult = <0x1>;
						clock-div = <0x1>;
						linux,phandle = <0x1c>;
						phandle = <0x1c>;
					};

					dpll_iva_byp_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0xe 0x1c>;
						ti,bit-shift = <0x17>;
						reg = <0x1ac>;
						linux,phandle = <0x1d>;
						phandle = <0x1d>;
					};

					dpll_iva_ck {
						#clock-cells = <0x0>;
						compatible = "ti,omap4-dpll-clock";
						clocks = <0xe 0x1d>;
						reg = <0x1a0 0x1a4 0x1ac 0x1a8>;
						ti,sink-clkdm = <0x1e>;
						assigned-clocks = <0x1f>;
						assigned-clock-rates = <0x45707d40>;
						linux,phandle = <0x1f>;
						phandle = <0x1f>;
					};

					dpll_iva_m2_ck {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x1f>;
						ti,max-div = <0x1f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x1b0>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						assigned-clocks = <0x20>;
						assigned-clock-rates = <0x17257f16>;
						linux,phandle = <0x20>;
						phandle = <0x20>;
					};

					iva_dclk {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x20>;
						clock-mult = <0x1>;
						clock-div = <0x1>;
						linux,phandle = <0x92>;
						phandle = <0x92>;
					};

					dpll_gpu_byp_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0xe 0xf>;
						ti,bit-shift = <0x17>;
						reg = <0x2e4>;
						linux,phandle = <0x21>;
						phandle = <0x21>;
					};

					dpll_gpu_ck {
						#clock-cells = <0x0>;
						compatible = "ti,omap4-dpll-clock";
						clocks = <0xe 0x21>;
						reg = <0x2d8 0x2dc 0x2e4 0x2e0>;
						ti,sink-clkdm = <0x22>;
						linux,phandle = <0x23>;
						phandle = <0x23>;
					};

					dpll_gpu_m2_ck {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x23>;
						ti,max-div = <0x1f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x2e8>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						linux,phandle = <0x74>;
						phandle = <0x74>;
					};

					dpll_core_m2_ck {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x11>;
						ti,max-div = <0x1f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x130>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						linux,phandle = <0x24>;
						phandle = <0x24>;
					};

					core_dpll_out_dclk_div {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x24>;
						clock-mult = <0x1>;
						clock-div = <0x1>;
						linux,phandle = <0x94>;
						phandle = <0x94>;
					};

					dpll_ddr_byp_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0xe 0xf>;
						ti,bit-shift = <0x17>;
						reg = <0x21c>;
						linux,phandle = <0x25>;
						phandle = <0x25>;
					};

					dpll_ddr_ck {
						#clock-cells = <0x0>;
						compatible = "ti,omap4-dpll-clock";
						clocks = <0xe 0x25>;
						reg = <0x210 0x214 0x21c 0x218>;
						linux,phandle = <0x26>;
						phandle = <0x26>;
					};

					dpll_ddr_m2_ck {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x26>;
						ti,max-div = <0x1f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x220>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						linux,phandle = <0x88>;
						phandle = <0x88>;
					};

					dpll_gmac_byp_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0xe 0xf>;
						ti,bit-shift = <0x17>;
						reg = <0x2b4>;
						linux,phandle = <0x27>;
						phandle = <0x27>;
					};

					dpll_gmac_ck {
						#clock-cells = <0x0>;
						compatible = "ti,omap4-dpll-clock";
						clocks = <0xe 0x27>;
						reg = <0x2a8 0x2ac 0x2b4 0x2b0>;
						ti,sink-clkdm = <0x28>;
						linux,phandle = <0x29>;
						phandle = <0x29>;
					};

					dpll_gmac_m2_ck {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x29>;
						ti,max-div = <0x1f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x2b8>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						linux,phandle = <0x71>;
						phandle = <0x71>;
					};

					video2_dclk_div {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x2a>;
						clock-mult = <0x1>;
						clock-div = <0x1>;
						linux,phandle = <0x97>;
						phandle = <0x97>;
					};

					video1_dclk_div {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x2b>;
						clock-mult = <0x1>;
						clock-div = <0x1>;
						linux,phandle = <0x98>;
						phandle = <0x98>;
					};

					hdmi_dclk_div {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x2c>;
						clock-mult = <0x1>;
						clock-div = <0x1>;
						linux,phandle = <0x99>;
						phandle = <0x99>;
					};

					per_dpll_hs_clk_div {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0xf>;
						clock-mult = <0x1>;
						clock-div = <0x2>;
						linux,phandle = <0x5d>;
						phandle = <0x5d>;
					};

					usb_dpll_hs_clk_div {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0xf>;
						clock-mult = <0x1>;
						clock-div = <0x3>;
						linux,phandle = <0x61>;
						phandle = <0x61>;
					};

					eve_dpll_hs_clk_div {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x13>;
						clock-mult = <0x1>;
						clock-div = <0x1>;
						linux,phandle = <0x2d>;
						phandle = <0x2d>;
					};

					dpll_eve_byp_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0xe 0x2d>;
						ti,bit-shift = <0x17>;
						reg = <0x290>;
						linux,phandle = <0x2e>;
						phandle = <0x2e>;
					};

					dpll_eve_ck {
						#clock-cells = <0x0>;
						compatible = "ti,omap4-dpll-clock";
						clocks = <0xe 0x2e>;
						reg = <0x284 0x288 0x290 0x28c>;
						ti,sink-clkdm = <0x2f>;
						linux,phandle = <0x30>;
						phandle = <0x30>;
					};

					dpll_eve_m2_ck {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x30>;
						ti,max-div = <0x1f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x294>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						linux,phandle = <0x31>;
						phandle = <0x31>;
					};

					eve_dclk_div {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x31>;
						clock-mult = <0x1>;
						clock-div = <0x1>;
						linux,phandle = <0xa2>;
						phandle = <0xa2>;
					};

					dpll_core_h13x2_ck {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x12>;
						ti,max-div = <0x3f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x140>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
					};

					dpll_core_h14x2_ck {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x12>;
						ti,max-div = <0x3f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x144>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						linux,phandle = <0x72>;
						phandle = <0x72>;
					};

					dpll_core_h22x2_ck {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x12>;
						ti,max-div = <0x3f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x154>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						linux,phandle = <0x39>;
						phandle = <0x39>;
					};

					dpll_core_h23x2_ck {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x12>;
						ti,max-div = <0x3f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x158>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						linux,phandle = <0x7d>;
						phandle = <0x7d>;
					};

					dpll_core_h24x2_ck {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x12>;
						ti,max-div = <0x3f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x15c>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
					};

					dpll_ddr_x2_ck {
						#clock-cells = <0x0>;
						compatible = "ti,omap4-dpll-x2-clock";
						clocks = <0x26>;
						linux,phandle = <0x32>;
						phandle = <0x32>;
					};

					dpll_ddr_h11x2_ck {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x32>;
						ti,max-div = <0x3f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x228>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
					};

					dpll_dsp_x2_ck {
						#clock-cells = <0x0>;
						compatible = "ti,omap4-dpll-x2-clock";
						clocks = <0x1a>;
						linux,phandle = <0x33>;
						phandle = <0x33>;
					};

					dpll_dsp_m3x2_ck {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x33>;
						ti,max-div = <0x1f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x248>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						assigned-clocks = <0x34>;
						assigned-clock-rates = <0x1bd0c4ab>;
						linux,phandle = <0x34>;
						phandle = <0x34>;
					};

					dpll_gmac_x2_ck {
						#clock-cells = <0x0>;
						compatible = "ti,omap4-dpll-x2-clock";
						clocks = <0x29>;
						linux,phandle = <0x35>;
						phandle = <0x35>;
					};

					dpll_gmac_h11x2_ck {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x35>;
						ti,max-div = <0x3f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x2c0>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						linux,phandle = <0x36>;
						phandle = <0x36>;
					};

					dpll_gmac_h12x2_ck {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x35>;
						ti,max-div = <0x3f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x2c4>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
					};

					dpll_gmac_h13x2_ck {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x35>;
						ti,max-div = <0x3f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x2c8>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
					};

					dpll_gmac_m3x2_ck {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x35>;
						ti,max-div = <0x1f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x2bc>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
					};

					gmii_m_clk_div {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x36>;
						clock-mult = <0x1>;
						clock-div = <0x2>;
					};

					hdmi_clk2_div {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x2c>;
						clock-mult = <0x1>;
						clock-div = <0x1>;
						linux,phandle = <0x4c>;
						phandle = <0x4c>;
					};

					hdmi_div_clk {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x2c>;
						clock-mult = <0x1>;
						clock-div = <0x1>;
						linux,phandle = <0x52>;
						phandle = <0x52>;
					};

					l3_iclk_div {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						ti,max-div = <0x2>;
						ti,bit-shift = <0x4>;
						reg = <0x100>;
						clocks = <0x13>;
						ti,index-power-of-two;
						linux,phandle = <0x5>;
						phandle = <0x5>;
					};

					l4_root_clk_div {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x5>;
						clock-mult = <0x1>;
						clock-div = <0x2>;
						linux,phandle = <0x6>;
						phandle = <0x6>;
					};

					video1_clk2_div {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x37>;
						clock-mult = <0x1>;
						clock-div = <0x1>;
						linux,phandle = <0x4a>;
						phandle = <0x4a>;
					};

					video1_div_clk {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x37>;
						clock-mult = <0x1>;
						clock-div = <0x1>;
						linux,phandle = <0x50>;
						phandle = <0x50>;
					};

					video2_clk2_div {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x38>;
						clock-mult = <0x1>;
						clock-div = <0x1>;
						linux,phandle = <0x4b>;
						phandle = <0x4b>;
					};

					video2_div_clk {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x38>;
						clock-mult = <0x1>;
						clock-div = <0x1>;
						linux,phandle = <0x51>;
						phandle = <0x51>;
					};

					ipu1_gfclk_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0xd 0x39>;
						ti,bit-shift = <0x18>;
						reg = <0x520>;
						assigned-clocks = <0x3a>;
						assigned-clock-parents = <0x39>;
						linux,phandle = <0x3a>;
						phandle = <0x3a>;
					};

					mcasp1_ahclkr_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x3b 0x3c 0x3d 0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48>;
						ti,bit-shift = <0x1c>;
						reg = <0x550>;
					};

					mcasp1_ahclkx_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x3b 0x3c 0x3d 0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48>;
						ti,bit-shift = <0x18>;
						reg = <0x550>;
					};

					mcasp1_aux_gfclk_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x49 0x4a 0x4b 0x4c>;
						ti,bit-shift = <0x16>;
						reg = <0x550>;
					};

					timer5_gfclk_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x4d 0x4e 0x42 0x43 0x44 0x45 0x46 0x4f 0x50 0x51 0x52 0x53>;
						ti,bit-shift = <0x18>;
						reg = <0x558>;
					};

					timer6_gfclk_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x4d 0x4e 0x42 0x43 0x44 0x45 0x46 0x4f 0x50 0x51 0x52 0x53>;
						ti,bit-shift = <0x18>;
						reg = <0x560>;
					};

					timer7_gfclk_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x4d 0x4e 0x42 0x43 0x44 0x45 0x46 0x4f 0x50 0x51 0x52 0x53>;
						ti,bit-shift = <0x18>;
						reg = <0x568>;
					};

					timer8_gfclk_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x4d 0x4e 0x42 0x43 0x44 0x45 0x46 0x4f 0x50 0x51 0x52 0x53>;
						ti,bit-shift = <0x18>;
						reg = <0x570>;
					};

					uart6_gfclk_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x54 0x55>;
						ti,bit-shift = <0x18>;
						reg = <0x580>;
					};

					dummy_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x0>;
					};
				};

				clockdomains {
				};
			};

			cm_core@8000 {
				compatible = "ti,dra7-cm-core";
				reg = <0x8000 0x3000>;

				clocks {
					#address-cells = <0x1>;
					#size-cells = <0x0>;

					dpll_pcie_ref_ck {
						#clock-cells = <0x0>;
						compatible = "ti,omap4-dpll-clock";
						clocks = <0xe 0xe>;
						reg = <0x200 0x204 0x20c 0x208>;
						ti,sink-clkdm = <0x56>;
						linux,phandle = <0x57>;
						phandle = <0x57>;
					};

					dpll_pcie_ref_m2ldo_ck {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x57>;
						ti,max-div = <0x1f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x210>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						linux,phandle = <0x58>;
						phandle = <0x58>;
					};

					apll_pcie_in_clk_mux@4ae06118 {
						compatible = "ti,mux-clock";
						clocks = <0x58 0x59>;
						#clock-cells = <0x0>;
						reg = <0x21c 0x4>;
						ti,bit-shift = <0x7>;
						linux,phandle = <0x5a>;
						phandle = <0x5a>;
					};

					apll_pcie_ck {
						#clock-cells = <0x0>;
						compatible = "ti,dra7-apll-clock";
						clocks = <0x5a 0x57>;
						reg = <0x21c 0x220>;
						linux,phandle = <0x5b>;
						phandle = <0x5b>;
					};

					optfclk_pciephy1_32khz@4a0093b0 {
						compatible = "ti,gate-clock";
						clocks = <0x4e>;
						#clock-cells = <0x0>;
						reg = <0x13b0>;
						ti,bit-shift = <0x8>;
						linux,phandle = <0xc3>;
						phandle = <0xc3>;
					};

					optfclk_pciephy2_32khz@4a0093b8 {
						compatible = "ti,gate-clock";
						clocks = <0x4e>;
						#clock-cells = <0x0>;
						reg = <0x13b8>;
						ti,bit-shift = <0x8>;
						linux,phandle = <0xc7>;
						phandle = <0xc7>;
					};

					optfclk_pciephy_div@4a00821c {
						compatible = "ti,divider-clock";
						clocks = <0x5b>;
						#clock-cells = <0x0>;
						reg = <0x21c>;
						ti,dividers = <0x2 0x1>;
						ti,bit-shift = <0x8>;
						ti,max-div = <0x2>;
						linux,phandle = <0x5c>;
						phandle = <0x5c>;
					};

					optfclk_pciephy1_clk@4a0093b0 {
						compatible = "ti,gate-clock";
						clocks = <0x5b>;
						#clock-cells = <0x0>;
						reg = <0x13b0>;
						ti,bit-shift = <0x9>;
						linux,phandle = <0xc4>;
						phandle = <0xc4>;
					};

					optfclk_pciephy2_clk@4a0093b8 {
						compatible = "ti,gate-clock";
						clocks = <0x5b>;
						#clock-cells = <0x0>;
						reg = <0x13b8>;
						ti,bit-shift = <0x9>;
						linux,phandle = <0xc8>;
						phandle = <0xc8>;
					};

					optfclk_pciephy1_div_clk@4a0093b0 {
						compatible = "ti,gate-clock";
						clocks = <0x5c>;
						#clock-cells = <0x0>;
						reg = <0x13b0>;
						ti,bit-shift = <0xa>;
						linux,phandle = <0xc5>;
						phandle = <0xc5>;
					};

					optfclk_pciephy2_div_clk@4a0093b8 {
						compatible = "ti,gate-clock";
						clocks = <0x5c>;
						#clock-cells = <0x0>;
						reg = <0x13b8>;
						ti,bit-shift = <0xa>;
						linux,phandle = <0xc9>;
						phandle = <0xc9>;
					};

					apll_pcie_clkvcoldo {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x5b>;
						clock-mult = <0x1>;
						clock-div = <0x1>;
					};

					apll_pcie_clkvcoldo_div {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x5b>;
						clock-mult = <0x1>;
						clock-div = <0x1>;
					};

					apll_pcie_m2_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x5b>;
						clock-mult = <0x1>;
						clock-div = <0x1>;
						linux,phandle = <0x8b>;
						phandle = <0x8b>;
					};

					dpll_per_byp_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0xe 0x5d>;
						ti,bit-shift = <0x17>;
						reg = <0x14c>;
						linux,phandle = <0x5e>;
						phandle = <0x5e>;
					};

					dpll_per_ck {
						#clock-cells = <0x0>;
						compatible = "ti,omap4-dpll-clock";
						clocks = <0xe 0x5e>;
						reg = <0x140 0x144 0x14c 0x148>;
						linux,phandle = <0x5f>;
						phandle = <0x5f>;
					};

					dpll_per_m2_ck {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x5f>;
						ti,max-div = <0x1f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x150>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						linux,phandle = <0x60>;
						phandle = <0x60>;
					};

					func_96m_aon_dclk_div {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x60>;
						clock-mult = <0x1>;
						clock-div = <0x1>;
						linux,phandle = <0x9a>;
						phandle = <0x9a>;
					};

					dpll_usb_byp_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0xe 0x61>;
						ti,bit-shift = <0x17>;
						reg = <0x18c>;
						linux,phandle = <0x62>;
						phandle = <0x62>;
					};

					dpll_usb_ck {
						#clock-cells = <0x0>;
						compatible = "ti,omap4-dpll-j-type-clock";
						clocks = <0xe 0x62>;
						reg = <0x180 0x184 0x18c 0x188>;
						ti,sink-clkdm = <0x63>;
						linux,phandle = <0x64>;
						phandle = <0x64>;
					};

					dpll_usb_m2_ck {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x64>;
						ti,max-div = <0x7f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x190>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						linux,phandle = <0x67>;
						phandle = <0x67>;
					};

					dpll_pcie_ref_m2_ck {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x57>;
						ti,max-div = <0x7f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x210>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						linux,phandle = <0x8a>;
						phandle = <0x8a>;
					};

					dpll_per_x2_ck {
						#clock-cells = <0x0>;
						compatible = "ti,omap4-dpll-x2-clock";
						clocks = <0x5f>;
						linux,phandle = <0x65>;
						phandle = <0x65>;
					};

					dpll_per_h11x2_ck {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x65>;
						ti,max-div = <0x3f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x158>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						linux,phandle = <0x66>;
						phandle = <0x66>;
					};

					dpll_per_h12x2_ck {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x65>;
						ti,max-div = <0x3f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x15c>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						linux,phandle = <0x6a>;
						phandle = <0x6a>;
					};

					dpll_per_h13x2_ck {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x65>;
						ti,max-div = <0x3f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x160>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						linux,phandle = <0x7b>;
						phandle = <0x7b>;
					};

					dpll_per_h14x2_ck {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x65>;
						ti,max-div = <0x3f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x164>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						linux,phandle = <0x73>;
						phandle = <0x73>;
					};

					dpll_per_m2x2_ck {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x65>;
						ti,max-div = <0x1f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x150>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						linux,phandle = <0x55>;
						phandle = <0x55>;
					};

					dpll_usb_clkdcoldo {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x64>;
						clock-mult = <0x1>;
						clock-div = <0x1>;
						linux,phandle = <0x69>;
						phandle = <0x69>;
					};

					func_128m_clk {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x66>;
						clock-mult = <0x1>;
						clock-div = <0x2>;
						linux,phandle = <0x76>;
						phandle = <0x76>;
					};

					func_12m_fclk {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x55>;
						clock-mult = <0x1>;
						clock-div = <0x10>;
					};

					func_24m_clk {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x60>;
						clock-mult = <0x1>;
						clock-div = <0x4>;
						linux,phandle = <0x3d>;
						phandle = <0x3d>;
					};

					func_48m_fclk {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x55>;
						clock-mult = <0x1>;
						clock-div = <0x4>;
						linux,phandle = <0x54>;
						phandle = <0x54>;
					};

					func_96m_fclk {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x55>;
						clock-mult = <0x1>;
						clock-div = <0x2>;
					};

					l3init_60m_fclk {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x67>;
						reg = <0x104>;
						ti,dividers = <0x1 0x8>;
					};

					clkout2_clk {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x68>;
						ti,bit-shift = <0x8>;
						reg = <0x6b0>;
					};

					l3init_960m_gfclk {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x69>;
						ti,bit-shift = <0x8>;
						reg = <0x6c0>;
						linux,phandle = <0x6e>;
						phandle = <0x6e>;
					};

					dss_32khz_clk {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x4e>;
						ti,bit-shift = <0xb>;
						reg = <0x1120>;
					};

					dss_48mhz_clk {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x54>;
						ti,bit-shift = <0x9>;
						reg = <0x1120>;
						linux,phandle = <0xe0>;
						phandle = <0xe0>;
					};

					dss_dss_clk {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x6a>;
						ti,bit-shift = <0x8>;
						reg = <0x1120>;
						ti,set-rate-parent;
						linux,phandle = <0xde>;
						phandle = <0xde>;
					};

					dss_hdmi_clk {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x6b>;
						ti,bit-shift = <0xa>;
						reg = <0x1120>;
						linux,phandle = <0xe1>;
						phandle = <0xe1>;
					};

					dss_video1_clk {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x6c>;
						ti,bit-shift = <0xc>;
						reg = <0x1120>;
						linux,phandle = <0xdf>;
						phandle = <0xdf>;
					};

					dss_video2_clk {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x6d>;
						ti,bit-shift = <0xd>;
						reg = <0x1120>;
					};

					gpio2_dbclk {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x4e>;
						ti,bit-shift = <0x8>;
						reg = <0x1760>;
					};

					gpio3_dbclk {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x4e>;
						ti,bit-shift = <0x8>;
						reg = <0x1768>;
					};

					gpio4_dbclk {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x4e>;
						ti,bit-shift = <0x8>;
						reg = <0x1770>;
					};

					gpio5_dbclk {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x4e>;
						ti,bit-shift = <0x8>;
						reg = <0x1778>;
					};

					gpio6_dbclk {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x4e>;
						ti,bit-shift = <0x8>;
						reg = <0x1780>;
					};

					gpio7_dbclk {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x4e>;
						ti,bit-shift = <0x8>;
						reg = <0x1810>;
					};

					gpio8_dbclk {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x4e>;
						ti,bit-shift = <0x8>;
						reg = <0x1818>;
					};

					mmc1_clk32k {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x4e>;
						ti,bit-shift = <0x8>;
						reg = <0x1328>;
					};

					mmc2_clk32k {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x4e>;
						ti,bit-shift = <0x8>;
						reg = <0x1330>;
					};

					mmc3_clk32k {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x4e>;
						ti,bit-shift = <0x8>;
						reg = <0x1820>;
					};

					mmc4_clk32k {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x4e>;
						ti,bit-shift = <0x8>;
						reg = <0x1828>;
					};

					sata_ref_clk {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0xe>;
						ti,bit-shift = <0x8>;
						reg = <0x1388>;
						linux,phandle = <0xc0>;
						phandle = <0xc0>;
					};

					usb_otg_ss1_refclk960m {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x6e>;
						ti,bit-shift = <0x8>;
						reg = <0x13f0>;
						linux,phandle = <0xcd>;
						phandle = <0xcd>;
					};

					usb_otg_ss2_refclk960m {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x6e>;
						ti,bit-shift = <0x8>;
						reg = <0x1340>;
						linux,phandle = <0xd0>;
						phandle = <0xd0>;
					};

					usb_phy1_always_on_clk32k {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x4e>;
						ti,bit-shift = <0x8>;
						reg = <0x640>;
						linux,phandle = <0xcc>;
						phandle = <0xcc>;
					};

					usb_phy2_always_on_clk32k {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x4e>;
						ti,bit-shift = <0x8>;
						reg = <0x688>;
						linux,phandle = <0xcf>;
						phandle = <0xcf>;
					};

					usb_phy3_always_on_clk32k {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x4e>;
						ti,bit-shift = <0x8>;
						reg = <0x698>;
						linux,phandle = <0xd2>;
						phandle = <0xd2>;
					};

					atl_dpll_clk_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x4e 0x37 0x38 0x2c>;
						ti,bit-shift = <0x18>;
						reg = <0xc00>;
						linux,phandle = <0x70>;
						phandle = <0x70>;
					};

					atl_gfclk_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x5 0x6f 0x70>;
						ti,bit-shift = <0x1a>;
						reg = <0xc00>;
						linux,phandle = <0x7>;
						phandle = <0x7>;
					};

					gmac_gmii_ref_clk_div {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x71>;
						ti,bit-shift = <0x18>;
						reg = <0x13d0>;
						ti,dividers = <0x2>;
						linux,phandle = <0xdc>;
						phandle = <0xdc>;
					};

					gmac_rft_clk_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x37 0x38 0x6f 0x2c 0x5>;
						ti,bit-shift = <0x19>;
						reg = <0x13d0>;
					};

					gpu_core_gclk_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x72 0x73 0x74>;
						ti,bit-shift = <0x18>;
						reg = <0x1220>;
						linux,phandle = <0xb5>;
						phandle = <0xb5>;
					};

					gpu_hyd_gclk_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x72 0x73 0x74>;
						ti,bit-shift = <0x1a>;
						reg = <0x1220>;
						linux,phandle = <0xb6>;
						phandle = <0xb6>;
					};

					l3instr_ts_gclk_div {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x75>;
						ti,bit-shift = <0x18>;
						reg = <0xe50>;
						ti,dividers = <0x8 0x10 0x20>;
					};

					mcasp2_ahclkr_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x3b 0x3c 0x3d 0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48>;
						ti,bit-shift = <0x1c>;
						reg = <0x1860>;
					};

					mcasp2_ahclkx_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x3b 0x3c 0x3d 0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48>;
						ti,bit-shift = <0x18>;
						reg = <0x1860>;
					};

					mcasp2_aux_gfclk_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x49 0x4a 0x4b 0x4c>;
						ti,bit-shift = <0x16>;
						reg = <0x1860>;
					};

					mcasp3_ahclkx_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x3b 0x3c 0x3d 0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48>;
						ti,bit-shift = <0x18>;
						reg = <0x1868>;
						linux,phandle = <0xda>;
						phandle = <0xda>;
					};

					mcasp3_aux_gfclk_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x49 0x4a 0x4b 0x4c>;
						ti,bit-shift = <0x16>;
						reg = <0x1868>;
					};

					mcasp4_ahclkx_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x3b 0x3c 0x3d 0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48>;
						ti,bit-shift = <0x18>;
						reg = <0x1898>;
					};

					mcasp4_aux_gfclk_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x49 0x4a 0x4b 0x4c>;
						ti,bit-shift = <0x16>;
						reg = <0x1898>;
					};

					mcasp5_ahclkx_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x3b 0x3c 0x3d 0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48>;
						ti,bit-shift = <0x18>;
						reg = <0x1878>;
					};

					mcasp5_aux_gfclk_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x49 0x4a 0x4b 0x4c>;
						ti,bit-shift = <0x16>;
						reg = <0x1878>;
					};

					mcasp6_ahclkx_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x3b 0x3c 0x3d 0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48>;
						ti,bit-shift = <0x18>;
						reg = <0x1904>;
					};

					mcasp6_aux_gfclk_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x49 0x4a 0x4b 0x4c>;
						ti,bit-shift = <0x16>;
						reg = <0x1904>;
					};

					mcasp7_ahclkx_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x3b 0x3c 0x3d 0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48>;
						ti,bit-shift = <0x18>;
						reg = <0x1908>;
					};

					mcasp7_aux_gfclk_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x49 0x4a 0x4b 0x4c>;
						ti,bit-shift = <0x16>;
						reg = <0x1908>;
					};

					mcasp8_ahclkx_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x3b 0x3c 0x3d 0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48>;
						ti,bit-shift = <0x16>;
						reg = <0x1890>;
						linux,phandle = <0xdb>;
						phandle = <0xdb>;
					};

					mcasp8_aux_gfclk_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x49 0x4a 0x4b 0x4c>;
						ti,bit-shift = <0x18>;
						reg = <0x1890>;
					};

					mmc1_fclk_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x76 0x55>;
						ti,bit-shift = <0x18>;
						reg = <0x1328>;
						linux,phandle = <0x77>;
						phandle = <0x77>;
					};

					mmc1_fclk_div {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x77>;
						ti,bit-shift = <0x19>;
						ti,max-div = <0x4>;
						reg = <0x1328>;
						ti,index-power-of-two;
					};

					mmc2_fclk_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x76 0x55>;
						ti,bit-shift = <0x18>;
						reg = <0x1330>;
						linux,phandle = <0x78>;
						phandle = <0x78>;
					};

					mmc2_fclk_div {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x78>;
						ti,bit-shift = <0x19>;
						ti,max-div = <0x4>;
						reg = <0x1330>;
						ti,index-power-of-two;
					};

					mmc3_gfclk_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x54 0x55>;
						ti,bit-shift = <0x18>;
						reg = <0x1820>;
						linux,phandle = <0x79>;
						phandle = <0x79>;
					};

					mmc3_gfclk_div {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x79>;
						ti,bit-shift = <0x19>;
						ti,max-div = <0x4>;
						reg = <0x1820>;
						ti,index-power-of-two;
					};

					mmc4_gfclk_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x54 0x55>;
						ti,bit-shift = <0x18>;
						reg = <0x1828>;
						linux,phandle = <0x7a>;
						phandle = <0x7a>;
					};

					mmc4_gfclk_div {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x7a>;
						ti,bit-shift = <0x19>;
						ti,max-div = <0x4>;
						reg = <0x1828>;
						ti,index-power-of-two;
					};

					qspi_gfclk_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x76 0x7b>;
						ti,bit-shift = <0x18>;
						reg = <0x1838>;
						linux,phandle = <0x7c>;
						phandle = <0x7c>;
					};

					qspi_gfclk_div {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x7c>;
						ti,bit-shift = <0x19>;
						ti,max-div = <0x4>;
						reg = <0x1838>;
						ti,index-power-of-two;
						linux,phandle = <0xbe>;
						phandle = <0xbe>;
					};

					timer10_gfclk_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x4d 0x4e 0x42 0x43 0x44 0x45 0x46 0x4f 0x50 0x51 0x52>;
						ti,bit-shift = <0x18>;
						reg = <0x1728>;
					};

					timer11_gfclk_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x4d 0x4e 0x42 0x43 0x44 0x45 0x46 0x4f 0x50 0x51 0x52>;
						ti,bit-shift = <0x18>;
						reg = <0x1730>;
					};

					timer13_gfclk_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x4d 0x4e 0x42 0x43 0x44 0x45 0x46 0x4f 0x50 0x51 0x52>;
						ti,bit-shift = <0x18>;
						reg = <0x17c8>;
					};

					timer14_gfclk_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x4d 0x4e 0x42 0x43 0x44 0x45 0x46 0x4f 0x50 0x51 0x52>;
						ti,bit-shift = <0x18>;
						reg = <0x17d0>;
					};

					timer15_gfclk_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x4d 0x4e 0x42 0x43 0x44 0x45 0x46 0x4f 0x50 0x51 0x52>;
						ti,bit-shift = <0x18>;
						reg = <0x17d8>;
					};

					timer16_gfclk_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x4d 0x4e 0x42 0x43 0x44 0x45 0x46 0x4f 0x50 0x51 0x52>;
						ti,bit-shift = <0x18>;
						reg = <0x1830>;
					};

					timer2_gfclk_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x4d 0x4e 0x42 0x43 0x44 0x45 0x46 0x4f 0x50 0x51 0x52>;
						ti,bit-shift = <0x18>;
						reg = <0x1738>;
					};

					timer3_gfclk_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x4d 0x4e 0x42 0x43 0x44 0x45 0x46 0x4f 0x50 0x51 0x52>;
						ti,bit-shift = <0x18>;
						reg = <0x1740>;
					};

					timer4_gfclk_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x4d 0x4e 0x42 0x43 0x44 0x45 0x46 0x4f 0x50 0x51 0x52>;
						ti,bit-shift = <0x18>;
						reg = <0x1748>;
					};

					timer9_gfclk_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x4d 0x4e 0x42 0x43 0x44 0x45 0x46 0x4f 0x50 0x51 0x52>;
						ti,bit-shift = <0x18>;
						reg = <0x1750>;
					};

					uart1_gfclk_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x54 0x55>;
						ti,bit-shift = <0x18>;
						reg = <0x1840>;
					};

					uart2_gfclk_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x54 0x55>;
						ti,bit-shift = <0x18>;
						reg = <0x1848>;
					};

					uart3_gfclk_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x54 0x55>;
						ti,bit-shift = <0x18>;
						reg = <0x1850>;
					};

					uart4_gfclk_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x54 0x55>;
						ti,bit-shift = <0x18>;
						reg = <0x1858>;
					};

					uart5_gfclk_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x54 0x55>;
						ti,bit-shift = <0x18>;
						reg = <0x1870>;
					};

					uart7_gfclk_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x54 0x55>;
						ti,bit-shift = <0x18>;
						reg = <0x18d0>;
					};

					uart8_gfclk_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x54 0x55>;
						ti,bit-shift = <0x18>;
						reg = <0x18e0>;
					};

					uart9_gfclk_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x54 0x55>;
						ti,bit-shift = <0x18>;
						reg = <0x18e8>;
					};

					vip1_gclk_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x5 0x7d>;
						ti,bit-shift = <0x18>;
						reg = <0x1020>;
					};

					vip2_gclk_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x5 0x7d>;
						ti,bit-shift = <0x18>;
						reg = <0x1028>;
					};

					vip3_gclk_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x5 0x7d>;
						ti,bit-shift = <0x18>;
						reg = <0x1030>;
					};
				};

				clockdomains {

					coreaon_clkdm {
						compatible = "ti,clockdomain";
						clocks = <0x64>;
					};

					gpu_clkdm {
						compatible = "ti,clockdomain";
						linux,phandle = <0x22>;
						phandle = <0x22>;
					};

					pcie_clkdm {
						compatible = "ti,clockdomain";
						linux,phandle = <0x56>;
						phandle = <0x56>;
					};

					iva_clkdm {
						compatible = "ti,clockdomain";
						linux,phandle = <0x1e>;
						phandle = <0x1e>;
					};

					dsp1_clkdm {
						compatible = "ti,clockdomain";
						linux,phandle = <0x19>;
						phandle = <0x19>;
					};

					gmac_clkdm {
						compatible = "ti,clockdomain";
						linux,phandle = <0x28>;
						phandle = <0x28>;
					};

					l3init_clkdm {
						compatible = "ti,clockdomain";
						linux,phandle = <0x63>;
						phandle = <0x63>;
					};

					eve1_clkdm {
						compatible = "ti,clockdomain";
						linux,phandle = <0x2f>;
						phandle = <0x2f>;
					};

					atl_clkdm {
						compatible = "ti,clockdomain";
						linux,phandle = <0xa>;
						phandle = <0xa>;
					};
				};
			};
		};

		l4@4ae00000 {
			compatible = "ti,dra7-l4-wkup", "simple-bus";
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			ranges = <0x0 0x4ae00000 0x3f000>;

			counter@4000 {
				compatible = "ti,omap-counter32k";
				reg = <0x4000 0x40>;
				ti,hwmods = "counter_32k";
			};

			prm@6000 {
				compatible = "ti,dra7-prm";
				reg = <0x6000 0x3000>;
				interrupts = <0x0 0x6 0x4>;

				clocks {
					#address-cells = <0x1>;
					#size-cells = <0x0>;

					sys_clkin1 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x7e 0x7f 0x80 0x81 0x82 0x83 0x84>;
						reg = <0x110>;
						ti,index-starts-at-one;
						linux,phandle = <0xe>;
						phandle = <0xe>;
					};

					abe_dpll_sys_clk_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0xe 0x42>;
						reg = <0x118>;
						linux,phandle = <0x85>;
						phandle = <0x85>;
					};

					abe_dpll_bypass_clk_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x85 0x4e>;
						reg = <0x114>;
						linux,phandle = <0x9>;
						phandle = <0x9>;
					};

					abe_dpll_clk_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x85 0x4e>;
						reg = <0x10c>;
						linux,phandle = <0x8>;
						phandle = <0x8>;
					};

					abe_24m_fclk {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0xd>;
						reg = <0x11c>;
						ti,dividers = <0x8 0x10>;
						linux,phandle = <0x3b>;
						phandle = <0x3b>;
					};

					aess_fclk {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x86>;
						reg = <0x178>;
						ti,max-div = <0x2>;
						linux,phandle = <0x87>;
						phandle = <0x87>;
					};

					abe_giclk_div {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x87>;
						reg = <0x174>;
						ti,max-div = <0x2>;
						linux,phandle = <0x4f>;
						phandle = <0x4f>;
					};

					abe_lp_clk_div {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0xd>;
						reg = <0x1d8>;
						ti,dividers = <0x10 0x20>;
						linux,phandle = <0xa5>;
						phandle = <0xa5>;
					};

					abe_sys_clk_div {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0xe>;
						reg = <0x120>;
						ti,max-div = <0x2>;
						linux,phandle = <0x3c>;
						phandle = <0x3c>;
					};

					adc_gfclk_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0xe 0x42 0x4e>;
						reg = <0x1dc>;
					};

					sys_clk1_dclk_div {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0xe>;
						ti,max-div = <0x40>;
						reg = <0x1c8>;
						ti,index-power-of-two;
						linux,phandle = <0x8d>;
						phandle = <0x8d>;
					};

					sys_clk2_dclk_div {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x42>;
						ti,max-div = <0x40>;
						reg = <0x1cc>;
						ti,index-power-of-two;
						linux,phandle = <0x8e>;
						phandle = <0x8e>;
					};

					per_abe_x1_dclk_div {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x6f>;
						ti,max-div = <0x40>;
						reg = <0x1bc>;
						ti,index-power-of-two;
						linux,phandle = <0x8f>;
						phandle = <0x8f>;
					};

					dsp_gclk_div {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x1b>;
						ti,max-div = <0x40>;
						reg = <0x18c>;
						ti,index-power-of-two;
						linux,phandle = <0x91>;
						phandle = <0x91>;
					};

					gpu_dclk {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x74>;
						ti,max-div = <0x40>;
						reg = <0x1a0>;
						ti,index-power-of-two;
						linux,phandle = <0x93>;
						phandle = <0x93>;
					};

					emif_phy_dclk_div {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x88>;
						ti,max-div = <0x40>;
						reg = <0x190>;
						ti,index-power-of-two;
						linux,phandle = <0x95>;
						phandle = <0x95>;
					};

					gmac_250m_dclk_div {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x71>;
						ti,max-div = <0x40>;
						reg = <0x19c>;
						ti,index-power-of-two;
						linux,phandle = <0x96>;
						phandle = <0x96>;
					};

					l3init_480m_dclk_div {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x67>;
						ti,max-div = <0x40>;
						reg = <0x1ac>;
						ti,index-power-of-two;
						linux,phandle = <0x9b>;
						phandle = <0x9b>;
					};

					usb_otg_dclk_div {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x89>;
						ti,max-div = <0x40>;
						reg = <0x184>;
						ti,index-power-of-two;
						linux,phandle = <0x9c>;
						phandle = <0x9c>;
					};

					sata_dclk_div {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0xe>;
						ti,max-div = <0x40>;
						reg = <0x1c0>;
						ti,index-power-of-two;
						linux,phandle = <0x9d>;
						phandle = <0x9d>;
					};

					pcie2_dclk_div {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x8a>;
						ti,max-div = <0x40>;
						reg = <0x1b8>;
						ti,index-power-of-two;
						linux,phandle = <0x9e>;
						phandle = <0x9e>;
					};

					pcie_dclk_div {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x8b>;
						ti,max-div = <0x40>;
						reg = <0x1b4>;
						ti,index-power-of-two;
						linux,phandle = <0x9f>;
						phandle = <0x9f>;
					};

					emu_dclk_div {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0xe>;
						ti,max-div = <0x40>;
						reg = <0x194>;
						ti,index-power-of-two;
						linux,phandle = <0xa0>;
						phandle = <0xa0>;
					};

					secure_32k_dclk_div {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x8c>;
						ti,max-div = <0x40>;
						reg = <0x1c4>;
						ti,index-power-of-two;
						linux,phandle = <0xa1>;
						phandle = <0xa1>;
					};

					clkoutmux0_clk_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x8d 0x8e 0x8f 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9a 0x9b 0x9c 0x9d 0x9e 0x9f 0xa0 0xa1 0xa2>;
						reg = <0x158>;
						linux,phandle = <0x53>;
						phandle = <0x53>;
					};

					clkoutmux1_clk_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x8d 0x8e 0x8f 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9a 0x9b 0x9c 0x9d 0x9e 0x9f 0xa0 0xa1 0xa2>;
						reg = <0x15c>;
					};

					clkoutmux2_clk_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x8d 0x8e 0x8f 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9a 0x9b 0x9c 0x9d 0x9e 0x9f 0xa0 0xa1 0xa2>;
						reg = <0x160>;
						linux,phandle = <0x68>;
						phandle = <0x68>;
					};

					custefuse_sys_gfclk_div {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0xe>;
						clock-mult = <0x1>;
						clock-div = <0x2>;
					};

					eve_clk {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x31 0x34>;
						reg = <0x180>;
					};

					hdmi_dpll_clk_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0xe 0x42>;
						reg = <0x164>;
						linux,phandle = <0x6b>;
						phandle = <0x6b>;
					};

					mlb_clk {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0xa3>;
						ti,max-div = <0x40>;
						reg = <0x134>;
						ti,index-power-of-two;
						linux,phandle = <0x47>;
						phandle = <0x47>;
					};

					mlbp_clk {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0xa4>;
						ti,max-div = <0x40>;
						reg = <0x130>;
						ti,index-power-of-two;
						linux,phandle = <0x48>;
						phandle = <0x48>;
					};

					per_abe_x1_gfclk2_div {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x6f>;
						ti,max-div = <0x40>;
						reg = <0x138>;
						ti,index-power-of-two;
						linux,phandle = <0x49>;
						phandle = <0x49>;
					};

					timer_sys_clk_div {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0xe>;
						reg = <0x144>;
						ti,max-div = <0x2>;
						linux,phandle = <0x4d>;
						phandle = <0x4d>;
					};

					video1_dpll_clk_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0xe 0x42>;
						reg = <0x168>;
						linux,phandle = <0x6c>;
						phandle = <0x6c>;
					};

					video2_dpll_clk_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0xe 0x42>;
						reg = <0x16c>;
						linux,phandle = <0x6d>;
						phandle = <0x6d>;
					};

					wkupaon_iclk_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0xe 0xa5>;
						reg = <0x108>;
						linux,phandle = <0x75>;
						phandle = <0x75>;
					};

					gpio1_dbclk {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x4e>;
						ti,bit-shift = <0x8>;
						reg = <0x1838>;
					};

					dcan1_sys_clk_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0xe 0x42>;
						ti,bit-shift = <0x18>;
						reg = <0x1888>;
						linux,phandle = <0xdd>;
						phandle = <0xdd>;
					};

					timer1_gfclk_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x4d 0x4e 0x42 0x43 0x44 0x45 0x46 0x4f 0x50 0x51 0x52>;
						ti,bit-shift = <0x18>;
						reg = <0x1840>;
					};

					uart10_gfclk_mux {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x54 0x55>;
						ti,bit-shift = <0x18>;
						reg = <0x1880>;
					};
				};

				clockdomains {
				};
			};
		};

		axi@0 {
			compatible = "simple-bus";
			#size-cells = <0x1>;
			#address-cells = <0x1>;
			ranges = <0x51000000 0x51000000 0x3000 0x0 0x20000000 0x10000000>;

			pcie@51000000 {
				compatible = "ti,dra7-pcie";
				reg = <0x51000000 0x2000 0x51002000 0x14c 0x1000 0x2000>;
				reg-names = "rc_dbics", "ti_conf", "config";
				interrupts = <0x0 0xe8 0x4 0x0 0xe9 0x4>;
				#address-cells = <0x3>;
				#size-cells = <0x2>;
				device_type = "pci";
				ranges = <0x81000000 0x0 0x0 0x3000 0x0 0x10000 0x82000000 0x0 0x20013000 0x13000 0x0 0xffed000>;
				#interrupt-cells = <0x1>;
				num-lanes = <0x1>;
				ti,hwmods = "pcie1";
				phys = <0xa6>;
				phy-names = "pcie-phy0";
				interrupt-map-mask = <0x0 0x0 0x0 0x7>;
				interrupt-map = <0x0 0x0 0x0 0x1 0xa7 0x1 0x0 0x0 0x0 0x2 0xa7 0x2 0x0 0x0 0x0 0x3 0xa7 0x3 0x0 0x0 0x0 0x4 0xa7 0x4>;

				interrupt-controller {
					interrupt-controller;
					#address-cells = <0x0>;
					#interrupt-cells = <0x1>;
					linux,phandle = <0xa7>;
					phandle = <0xa7>;
				};
			};
		};

		axi@1 {
			compatible = "simple-bus";
			#size-cells = <0x1>;
			#address-cells = <0x1>;
			ranges = <0x51800000 0x51800000 0x3000 0x0 0x30000000 0x10000000>;
			status = "disabled";

			pcie@51000000 {
				compatible = "ti,dra7-pcie";
				reg = <0x51800000 0x2000 0x51802000 0x14c 0x1000 0x2000>;
				reg-names = "rc_dbics", "ti_conf", "config";
				interrupts = <0x0 0x163 0x4 0x0 0x164 0x4>;
				#address-cells = <0x3>;
				#size-cells = <0x2>;
				device_type = "pci";
				ranges = <0x81000000 0x0 0x0 0x3000 0x0 0x10000 0x82000000 0x0 0x30013000 0x13000 0x0 0xffed000>;
				#interrupt-cells = <0x1>;
				num-lanes = <0x1>;
				ti,hwmods = "pcie2";
				phys = <0xa8>;
				phy-names = "pcie-phy0";
				interrupt-map-mask = <0x0 0x0 0x0 0x7>;
				interrupt-map = <0x0 0x0 0x0 0x1 0xa9 0x1 0x0 0x0 0x0 0x2 0xa9 0x2 0x0 0x0 0x0 0x3 0xa9 0x3 0x0 0x0 0x0 0x4 0xa9 0x4>;

				interrupt-controller {
					interrupt-controller;
					#address-cells = <0x0>;
					#interrupt-cells = <0x1>;
					linux,phandle = <0xa9>;
					phandle = <0xa9>;
				};
			};
		};

		bandgap@4a0021e0 {
			reg = <0x4a0021e0 0xc 0x4a00232c 0xc 0x4a002380 0x2c 0x4a0023c0 0x3c 0x4a002564 0x8 0x4a002574 0x50>;
			compatible = "ti,dra752-bandgap";
			interrupts = <0x0 0x79 0x4>;
			#thermal-sensor-cells = <0x1>;
			linux,phandle = <0xe2>;
			phandle = <0xe2>;
		};

		ctrl_core@4a002000 {
			compatible = "syscon";
			reg = <0x4a002000 0x6d0>;
			linux,phandle = <0xc1>;
			phandle = <0xc1>;
		};

		tisyscon@4a002e00 {
			compatible = "syscon";
			reg = <0x4a002e00 0x7c>;
		};

		dsp_system@40d00000 {
			compatible = "syscon";
			reg = <0x40d00000 0x100>;
			linux,phandle = <0xb8>;
			phandle = <0xb8>;
		};

		padconf@4844a000 {
			compatible = "ti,dra7-iodelay";
			reg = <0x4844a000 0xd1c>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
		};

		dma-controller@4a056000 {
			compatible = "ti,omap4430-sdma";
			reg = <0x4a056000 0x1000>;
			interrupts = <0x0 0x7 0x4 0x0 0x8 0x4 0x0 0x9 0x4 0x0 0xa 0x4>;
			#dma-cells = <0x1>;
			dma-channels = <0x20>;
			dma-requests = <0x7f>;
			linux,phandle = <0xaa>;
			phandle = <0xaa>;
		};

		dma-router@4a002b78 {
			compatible = "ti,dra7-dma-crossbar";
			reg = <0x4a002b78 0xfc>;
			#dma-cells = <0x1>;
			dma-requests = <0xcd>;
			ti,dma-safe-map = <0x0>;
			dma-masters = <0xaa>;
			linux,phandle = <0xac>;
			phandle = <0xac>;
		};

		edma-controller@43300000 {
			compatible = "ti,edma3";
			reg = <0x43300000 0x801c>;
			interrupts = <0x0 0x169 0x4 0x0 0x168 0x4 0x0 0x167 0x4>;
			#dma-cells = <0x1>;
			ti,hwmods = "tpcc", "tptc0", "tptc1";
			dma-requests = <0x40>;
			linux,phandle = <0xab>;
			phandle = <0xab>;
		};

		dma-router@4a002c78 {
			compatible = "ti,dra7-dma-crossbar";
			reg = <0x4a002c78 0x7c>;
			#dma-cells = <0x1>;
			dma-requests = <0xcc>;
			ti,dma-safe-map = <0x0>;
			dma-masters = <0xab>;
			linux,phandle = <0xd9>;
			phandle = <0xd9>;
		};

		gpio@4ae10000 {
			compatible = "ti,omap4-gpio";
			reg = <0x4ae10000 0x200>;
			interrupts = <0x0 0x18 0x4>;
			ti,hwmods = "gpio1";
			gpio-controller;
			#gpio-cells = <0x2>;
			interrupt-controller;
			#interrupt-cells = <0x2>;
		};

		gpio@48055000 {
			compatible = "ti,omap4-gpio";
			reg = <0x48055000 0x200>;
			interrupts = <0x0 0x19 0x4>;
			ti,hwmods = "gpio2";
			gpio-controller;
			#gpio-cells = <0x2>;
			interrupt-controller;
			#interrupt-cells = <0x2>;
		};

		gpio@48057000 {
			compatible = "ti,omap4-gpio";
			reg = <0x48057000 0x200>;
			interrupts = <0x0 0x1a 0x4>;
			ti,hwmods = "gpio3";
			gpio-controller;
			#gpio-cells = <0x2>;
			interrupt-controller;
			#interrupt-cells = <0x2>;
		};

		gpio@48059000 {
			compatible = "ti,omap4-gpio";
			reg = <0x48059000 0x200>;
			interrupts = <0x0 0x1b 0x4>;
			ti,hwmods = "gpio4";
			gpio-controller;
			#gpio-cells = <0x2>;
			interrupt-controller;
			#interrupt-cells = <0x2>;
		};

		gpio@4805b000 {
			compatible = "ti,omap4-gpio";
			reg = <0x4805b000 0x200>;
			interrupts = <0x0 0x1c 0x4>;
			ti,hwmods = "gpio5";
			gpio-controller;
			#gpio-cells = <0x2>;
			interrupt-controller;
			#interrupt-cells = <0x2>;
		};

		gpio@4805d000 {
			compatible = "ti,omap4-gpio";
			reg = <0x4805d000 0x200>;
			interrupts = <0x0 0x1d 0x4>;
			ti,hwmods = "gpio6";
			gpio-controller;
			#gpio-cells = <0x2>;
			interrupt-controller;
			#interrupt-cells = <0x2>;
		};

		gpio@48051000 {
			compatible = "ti,omap4-gpio";
			reg = <0x48051000 0x200>;
			interrupts = <0x0 0x1e 0x4>;
			ti,hwmods = "gpio7";
			gpio-controller;
			#gpio-cells = <0x2>;
			interrupt-controller;
			#interrupt-cells = <0x2>;
		};

		gpio@48053000 {
			compatible = "ti,omap4-gpio";
			reg = <0x48053000 0x200>;
			interrupts = <0x0 0x74 0x4>;
			ti,hwmods = "gpio8";
			gpio-controller;
			#gpio-cells = <0x2>;
			interrupt-controller;
			#interrupt-cells = <0x2>;
		};

		serial@4806a000 {
			compatible = "ti,dra742-uart", "ti,omap4-uart";
			reg = <0x4806a000 0x100>;
			interrupts-extended = <0x1 0x0 0x43 0x4>;
			ti,hwmods = "uart1";
			clock-frequency = <0x2dc6c00>;
			status = "okay";
			dmas = <0xac 0x31 0xac 0x32>;
			dma-names = "tx", "rx";
		};

		serial@4806c000 {
			compatible = "ti,dra742-uart", "ti,omap4-uart";
			reg = <0x4806c000 0x100>;
			interrupts = <0x0 0x44 0x4>;
			ti,hwmods = "uart2";
			clock-frequency = <0x2dc6c00>;
			status = "disabled";
			dmas = <0xac 0x33 0xac 0x34>;
			dma-names = "tx", "rx";
		};

		serial@48020000 {
			compatible = "ti,dra742-uart", "ti,omap4-uart";
			reg = <0x48020000 0x100>;
			interrupts = <0x0 0x45 0x4>;
			ti,hwmods = "uart3";
			clock-frequency = <0x2dc6c00>;
			status = "okay";
			dmas = <0xac 0x35 0xac 0x36>;
			dma-names = "tx", "rx";
		};

		serial@4806e000 {
			compatible = "ti,dra742-uart", "ti,omap4-uart";
			reg = <0x4806e000 0x100>;
			interrupts = <0x0 0x41 0x4>;
			ti,hwmods = "uart4";
			clock-frequency = <0x2dc6c00>;
			status = "disabled";
			dmas = <0xac 0x37 0xac 0x38>;
			dma-names = "tx", "rx";
		};

		serial@48066000 {
			compatible = "ti,dra742-uart", "ti,omap4-uart";
			reg = <0x48066000 0x100>;
			interrupts = <0x0 0x64 0x4>;
			ti,hwmods = "uart5";
			clock-frequency = <0x2dc6c00>;
			status = "disabled";
			dmas = <0xac 0x3f 0xac 0x40>;
			dma-names = "tx", "rx";
		};

		serial@48068000 {
			compatible = "ti,dra742-uart", "ti,omap4-uart";
			reg = <0x48068000 0x100>;
			interrupts = <0x0 0x65 0x4>;
			ti,hwmods = "uart6";
			clock-frequency = <0x2dc6c00>;
			status = "disabled";
			dmas = <0xac 0x4f 0xac 0x50>;
			dma-names = "tx", "rx";
		};

		serial@48420000 {
			compatible = "ti,dra742-uart", "ti,omap4-uart";
			reg = <0x48420000 0x100>;
			interrupts = <0x0 0xda 0x4>;
			ti,hwmods = "uart7";
			clock-frequency = <0x2dc6c00>;
			status = "disabled";
		};

		serial@48422000 {
			compatible = "ti,dra742-uart", "ti,omap4-uart";
			reg = <0x48422000 0x100>;
			interrupts = <0x0 0xdb 0x4>;
			ti,hwmods = "uart8";
			clock-frequency = <0x2dc6c00>;
			status = "disabled";
		};

		serial@48424000 {
			compatible = "ti,dra742-uart", "ti,omap4-uart";
			reg = <0x48424000 0x100>;
			interrupts = <0x0 0xdc 0x4>;
			ti,hwmods = "uart9";
			clock-frequency = <0x2dc6c00>;
			status = "disabled";
		};

		serial@4ae2b000 {
			compatible = "ti,dra742-uart", "ti,omap4-uart";
			reg = <0x4ae2b000 0x100>;
			interrupts = <0x0 0xdd 0x4>;
			ti,hwmods = "uart10";
			clock-frequency = <0x2dc6c00>;
			status = "disabled";
		};

		mailbox@4a0f4000 {
			compatible = "ti,omap4-mailbox";
			reg = <0x4a0f4000 0x200>;
			interrupts = <0x0 0x15 0x4 0x0 0x87 0x4 0x0 0x86 0x4>;
			ti,hwmods = "mailbox1";
			#mbox-cells = <0x1>;
			ti,mbox-num-users = <0x3>;
			ti,mbox-num-fifos = <0x8>;
			status = "disabled";
		};

		mailbox@4883a000 {
			compatible = "ti,omap4-mailbox";
			reg = <0x4883a000 0x200>;
			interrupts = <0x0 0xed 0x4 0x0 0xee 0x4 0x0 0xef 0x4 0x0 0xf0 0x4>;
			ti,hwmods = "mailbox2";
			#mbox-cells = <0x1>;
			ti,mbox-num-users = <0x4>;
			ti,mbox-num-fifos = <0xc>;
			status = "disabled";
		};

		mailbox@4883c000 {
			compatible = "ti,omap4-mailbox";
			reg = <0x4883c000 0x200>;
			interrupts = <0x0 0xf1 0x4 0x0 0xf2 0x4 0x0 0xf3 0x4 0x0 0xf4 0x4>;
			ti,hwmods = "mailbox3";
			#mbox-cells = <0x1>;
			ti,mbox-num-users = <0x4>;
			ti,mbox-num-fifos = <0xc>;
			status = "disabled";
		};

		mailbox@4883e000 {
			compatible = "ti,omap4-mailbox";
			reg = <0x4883e000 0x200>;
			interrupts = <0x0 0xf5 0x4 0x0 0xf6 0x4 0x0 0xf7 0x4 0x0 0xf8 0x4>;
			ti,hwmods = "mailbox4";
			#mbox-cells = <0x1>;
			ti,mbox-num-users = <0x4>;
			ti,mbox-num-fifos = <0xc>;
			status = "disabled";
		};

		mailbox@48840000 {
			compatible = "ti,omap4-mailbox";
			reg = <0x48840000 0x200>;
			interrupts = <0x0 0xf9 0x4 0x0 0xfa 0x4 0x0 0xfb 0x4 0x0 0xfc 0x4>;
			ti,hwmods = "mailbox5";
			#mbox-cells = <0x1>;
			ti,mbox-num-users = <0x4>;
			ti,mbox-num-fifos = <0xc>;
			status = "okay";
			linux,phandle = <0xb2>;
			phandle = <0xb2>;

			mbox_ipu1_ipc3x {
				ti,mbox-tx = <0x6 0x2 0x2>;
				ti,mbox-rx = <0x4 0x2 0x2>;
				status = "disabled";
			};

			mbox_dsp1_ipc3x {
				ti,mbox-tx = <0x5 0x2 0x2>;
				ti,mbox-rx = <0x1 0x2 0x2>;
				status = "okay";
				linux,phandle = <0xb3>;
				phandle = <0xb3>;
			};
		};

		mailbox@48842000 {
			compatible = "ti,omap4-mailbox";
			reg = <0x48842000 0x200>;
			interrupts = <0x0 0xfd 0x4 0x0 0xfe 0x4 0x0 0xff 0x4 0x0 0x100 0x4>;
			ti,hwmods = "mailbox6";
			#mbox-cells = <0x1>;
			ti,mbox-num-users = <0x4>;
			ti,mbox-num-fifos = <0xc>;
			status = "disabled";

			mbox_ipu2_ipc3x {
				ti,mbox-tx = <0x6 0x2 0x2>;
				ti,mbox-rx = <0x4 0x2 0x2>;
				status = "disabled";
			};
		};

		mailbox@48844000 {
			compatible = "ti,omap4-mailbox";
			reg = <0x48844000 0x200>;
			interrupts = <0x0 0x101 0x4 0x0 0x102 0x4 0x0 0x103 0x4 0x0 0x104 0x4>;
			ti,hwmods = "mailbox7";
			#mbox-cells = <0x1>;
			ti,mbox-num-users = <0x4>;
			ti,mbox-num-fifos = <0xc>;
			status = "disabled";
		};

		mailbox@48846000 {
			compatible = "ti,omap4-mailbox";
			reg = <0x48846000 0x200>;
			interrupts = <0x0 0x105 0x4 0x0 0x106 0x4 0x0 0x107 0x4 0x0 0x108 0x4>;
			ti,hwmods = "mailbox8";
			#mbox-cells = <0x1>;
			ti,mbox-num-users = <0x4>;
			ti,mbox-num-fifos = <0xc>;
			status = "disabled";
		};

		mailbox@4885e000 {
			compatible = "ti,omap4-mailbox";
			reg = <0x4885e000 0x200>;
			interrupts = <0x0 0x109 0x4 0x0 0x10a 0x4 0x0 0x10b 0x4 0x0 0x10c 0x4>;
			ti,hwmods = "mailbox9";
			#mbox-cells = <0x1>;
			ti,mbox-num-users = <0x4>;
			ti,mbox-num-fifos = <0xc>;
			status = "disabled";
		};

		mailbox@48860000 {
			compatible = "ti,omap4-mailbox";
			reg = <0x48860000 0x200>;
			interrupts = <0x0 0x10d 0x4 0x0 0x10e 0x4 0x0 0x10f 0x4 0x0 0x110 0x4>;
			ti,hwmods = "mailbox10";
			#mbox-cells = <0x1>;
			ti,mbox-num-users = <0x4>;
			ti,mbox-num-fifos = <0xc>;
			status = "disabled";
		};

		mailbox@48862000 {
			compatible = "ti,omap4-mailbox";
			reg = <0x48862000 0x200>;
			interrupts = <0x0 0x111 0x4 0x0 0x112 0x4 0x0 0x113 0x4 0x0 0x114 0x4>;
			ti,hwmods = "mailbox11";
			#mbox-cells = <0x1>;
			ti,mbox-num-users = <0x4>;
			ti,mbox-num-fifos = <0xc>;
			status = "disabled";
		};

		mailbox@48864000 {
			compatible = "ti,omap4-mailbox";
			reg = <0x48864000 0x200>;
			interrupts = <0x0 0x115 0x4 0x0 0x116 0x4 0x0 0x117 0x4 0x0 0x118 0x4>;
			ti,hwmods = "mailbox12";
			#mbox-cells = <0x1>;
			ti,mbox-num-users = <0x4>;
			ti,mbox-num-fifos = <0xc>;
			status = "disabled";
		};

		mailbox@48802000 {
			compatible = "ti,omap4-mailbox";
			reg = <0x48802000 0x200>;
			interrupts = <0x0 0x17b 0x4 0x0 0x17c 0x4 0x0 0x17d 0x4 0x0 0x17e 0x4>;
			ti,hwmods = "mailbox13";
			#mbox-cells = <0x1>;
			ti,mbox-num-users = <0x4>;
			ti,mbox-num-fifos = <0xc>;
			status = "disabled";
		};

		timer@4ae18000 {
			compatible = "ti,omap5430-timer";
			reg = <0x4ae18000 0x80>;
			interrupts = <0x0 0x20 0x4>;
			ti,hwmods = "timer1";
			ti,timer-alwon;
		};

		timer@48032000 {
			compatible = "ti,omap5430-timer";
			reg = <0x48032000 0x80>;
			interrupts = <0x0 0x21 0x4>;
			ti,hwmods = "timer2";
		};

		timer@48034000 {
			compatible = "ti,omap5430-timer";
			reg = <0x48034000 0x80>;
			interrupts = <0x0 0x22 0x4>;
			ti,hwmods = "timer3";
		};

		timer@48036000 {
			compatible = "ti,omap5430-timer";
			reg = <0x48036000 0x80>;
			interrupts = <0x0 0x23 0x4>;
			ti,hwmods = "timer4";
		};

		timer@48820000 {
			compatible = "ti,omap5430-timer";
			reg = <0x48820000 0x80>;
			interrupts = <0x0 0x24 0x4>;
			ti,hwmods = "timer5";
			linux,phandle = <0xb4>;
			phandle = <0xb4>;
		};

		timer@48822000 {
			compatible = "ti,omap5430-timer";
			reg = <0x48822000 0x80>;
			interrupts = <0x0 0x25 0x4>;
			ti,hwmods = "timer6";
		};

		timer@48824000 {
			compatible = "ti,omap5430-timer";
			reg = <0x48824000 0x80>;
			interrupts = <0x0 0x26 0x4>;
			ti,hwmods = "timer7";
		};

		timer@48826000 {
			compatible = "ti,omap5430-timer";
			reg = <0x48826000 0x80>;
			interrupts = <0x0 0x27 0x4>;
			ti,hwmods = "timer8";
		};

		timer@4803e000 {
			compatible = "ti,omap5430-timer";
			reg = <0x4803e000 0x80>;
			interrupts = <0x0 0x28 0x4>;
			ti,hwmods = "timer9";
		};

		timer@48086000 {
			compatible = "ti,omap5430-timer";
			reg = <0x48086000 0x80>;
			interrupts = <0x0 0x29 0x4>;
			ti,hwmods = "timer10";
		};

		timer@48088000 {
			compatible = "ti,omap5430-timer";
			reg = <0x48088000 0x80>;
			interrupts = <0x0 0x2a 0x4>;
			ti,hwmods = "timer11";
		};

		timer@4ae20000 {
			compatible = "ti,omap5430-timer";
			reg = <0x4ae20000 0x80>;
			interrupts = <0x0 0x5a 0x4>;
			ti,hwmods = "timer12";
			ti,timer-alwon;
			ti,timer-secure;
			status = "disabled";
		};

		timer@48828000 {
			compatible = "ti,omap5430-timer";
			reg = <0x48828000 0x80>;
			interrupts = <0x0 0x153 0x4>;
			ti,hwmods = "timer13";
			status = "disabled";
		};

		timer@4882a000 {
			compatible = "ti,omap5430-timer";
			reg = <0x4882a000 0x80>;
			interrupts = <0x0 0x154 0x4>;
			ti,hwmods = "timer14";
			status = "disabled";
		};

		timer@4882c000 {
			compatible = "ti,omap5430-timer";
			reg = <0x4882c000 0x80>;
			interrupts = <0x0 0x155 0x4>;
			ti,hwmods = "timer15";
			status = "disabled";
		};

		timer@4882e000 {
			compatible = "ti,omap5430-timer";
			reg = <0x4882e000 0x80>;
			interrupts = <0x0 0x156 0x4>;
			ti,hwmods = "timer16";
			status = "disabled";
		};

		wdt@4ae14000 {
			compatible = "ti,omap3-wdt";
			reg = <0x4ae14000 0x80>;
			interrupts = <0x0 0x4b 0x4>;
			ti,hwmods = "wd_timer2";
		};

		spinlock@4a0f6000 {
			compatible = "ti,omap4-hwspinlock";
			reg = <0x4a0f6000 0x1000>;
			ti,hwmods = "spinlock";
			#hwlock-cells = <0x1>;
		};

		dmm@4e000000 {
			compatible = "ti,dra7-dmm", "ti,omap5-dmm";
			reg = <0x4e000000 0x800>;
			interrupts = <0x0 0x6c 0x4>;
			ti,hwmods = "dmm";
		};

		ipu@58820000 {
			compatible = "ti,dra7-rproc-ipu";
			reg = <0x58820000 0x10000>;
			reg-names = "l2ram";
			ti,hwmods = "ipu1";
			iommus = <0xad>;
			status = "disabled";
		};

		ipu@55020000 {
			compatible = "ti,dra7-rproc-ipu";
			reg = <0x55020000 0x10000>;
			reg-names = "l2ram";
			ti,hwmods = "ipu2";
			iommus = <0xae>;
			status = "disabled";
		};

		dsp@40800000 {
			compatible = "ti,dra7-rproc-dsp", "ti,dra7-dsp";
			reg = <0x40800000 0x48000>;
			reg-names = "l2ram";
			ti,hwmods = "dsp1";
			syscon-bootreg = <0x4 0x55c>;
			iommus = <0xaf 0xb0>;
			status = "okay";
			memory-region = <0xb1>;
			mboxes = <0xb2 0xb3>;
			timers = <0xb4>;
		};

		sgx@0x56000000 {
			compatible = "ti,dra7-sgx544", "img,sgx544";
			reg = <0x5600fe00 0x200>;
			reg-names = "gpu_wrapper";
			interrupts = <0x0 0x10 0x4>;
			ti,hwmods = "gpu";
			clocks = <0x5 0xb5 0xb6>;
			clock-names = "gpu_iclk", "gpu_fclk1", "gpu_fclk2";
		};

		i2c@48070000 {
			compatible = "ti,omap4-i2c";
			reg = <0x48070000 0x100>;
			interrupts = <0x0 0x33 0x4>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			ti,hwmods = "i2c1";
			status = "disabled";
		};

		i2c@48072000 {
			compatible = "ti,omap4-i2c";
			reg = <0x48072000 0x100>;
			interrupts = <0x0 0x34 0x4>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			ti,hwmods = "i2c2";
			status = "disabled";
		};

		i2c@48060000 {
			compatible = "ti,omap4-i2c";
			reg = <0x48060000 0x100>;
			interrupts = <0x0 0x38 0x4>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			ti,hwmods = "i2c3";
			status = "disabled";
		};

		i2c@4807a000 {
			compatible = "ti,omap4-i2c";
			reg = <0x4807a000 0x100>;
			interrupts = <0x0 0x39 0x4>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			ti,hwmods = "i2c4";
			status = "disabled";
		};

		i2c@4807c000 {
			compatible = "ti,omap4-i2c";
			reg = <0x4807c000 0x100>;
			interrupts = <0x0 0x37 0x4>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			ti,hwmods = "i2c5";
			status = "disabled";
		};

		mmc@4809c000 {
			compatible = "ti,omap4-hsmmc";
			reg = <0x4809c000 0x400>;
			interrupts = <0x0 0x4e 0x4>;
			ti,hwmods = "mmc1";
			ti,dual-volt;
			ti,needs-special-reset;
			dmas = <0xac 0x3d 0xac 0x3e>;
			dma-names = "tx", "rx";
			status = "disabled";
			pbias-supply = <0xb7>;
			sd-uhs-sdr104;
			sd-uhs-sdr50;
			sd-uhs-ddr50;
			sd-uhs-sdr25;
			sd-uhs-sdr12;
		};

		mmc@480b4000 {
			compatible = "ti,omap4-hsmmc";
			reg = <0x480b4000 0x400>;
			interrupts = <0x0 0x51 0x4>;
			ti,hwmods = "mmc2";
			ti,needs-special-reset;
			dmas = <0xac 0x2f 0xac 0x30>;
			dma-names = "tx", "rx";
			status = "disabled";
			sd-uhs-sdr25;
			sd-uhs-sdr12;
			mmc-hs200-1_8v;
			mmc-ddr-1_8v;
		};

		mmc@480ad000 {
			compatible = "ti,omap4-hsmmc";
			reg = <0x480ad000 0x400>;
			interrupts = <0x0 0x59 0x4>;
			ti,hwmods = "mmc3";
			ti,needs-special-reset;
			dmas = <0xac 0x4d 0xac 0x4e>;
			dma-names = "tx", "rx";
			status = "disabled";
			sd-uhs-sdr12;
			sd-uhs-sdr25;
			sd-uhs-sdr50;
		};

		mmc@480d1000 {
			compatible = "ti,omap4-hsmmc";
			reg = <0x480d1000 0x400>;
			interrupts = <0x0 0x5b 0x4>;
			ti,hwmods = "mmc4";
			ti,needs-special-reset;
			dmas = <0xac 0x39 0xac 0x3a>;
			dma-names = "tx", "rx";
			status = "disabled";
			sd-uhs-sdr12;
			sd-uhs-sdr25;
		};

		mmu@40d01000 {
			compatible = "ti,dra7-dsp-iommu";
			reg = <0x40d01000 0x100>;
			interrupts = <0x0 0x17 0x4>;
			ti,hwmods = "mmu0_dsp1";
			#iommu-cells = <0x0>;
			ti,syscon-mmuconfig = <0xb8 0x0>;
			status = "okay";
			linux,phandle = <0xaf>;
			phandle = <0xaf>;
		};

		mmu@40d02000 {
			compatible = "ti,dra7-dsp-iommu";
			reg = <0x40d02000 0x100>;
			interrupts = <0x0 0x91 0x4>;
			ti,hwmods = "mmu1_dsp1";
			#iommu-cells = <0x0>;
			ti,syscon-mmuconfig = <0xb8 0x1>;
			status = "okay";
			linux,phandle = <0xb0>;
			phandle = <0xb0>;
		};

		mmu@58882000 {
			compatible = "ti,dra7-iommu";
			reg = <0x58882000 0x100>;
			interrupts = <0x0 0x18b 0x4>;
			ti,hwmods = "mmu_ipu1";
			#iommu-cells = <0x0>;
			ti,iommu-bus-err-back;
			status = "disabled";
			linux,phandle = <0xad>;
			phandle = <0xad>;
		};

		mmu@55082000 {
			compatible = "ti,dra7-iommu";
			reg = <0x55082000 0x100>;
			interrupts = <0x0 0x18c 0x4>;
			ti,hwmods = "mmu_ipu2";
			#iommu-cells = <0x0>;
			ti,iommu-bus-err-back;
			status = "disabled";
			linux,phandle = <0xae>;
			phandle = <0xae>;
		};

		pruss@4b200000 {
			compatible = "ti,am5728-pruss";
			ti,hwmods = "pruss1";
			reg = <0x4b200000 0x2000 0x4b202000 0x2000 0x4b210000 0x8000 0x4b220000 0x2000 0x4b226000 0x2000>;
			reg-names = "dram0", "dram1", "shrdram2", "intc", "cfg";
			interrupts = <0x0 0xba 0x4 0x0 0xbb 0x4 0x0 0xbc 0x4 0x0 0xbd 0x4 0x0 0xbe 0x4 0x0 0xbf 0x4 0x0 0xc0 0x4 0x0 0xc1 0x4>;
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			ranges;
			status = "disabled";

			pru@4b234000 {
				compatible = "ti,am5728-pru-rproc";
				reg = <0x4b234000 0x3000 0x4b222000 0x400 0x4b222400 0x100>;
				reg-names = "iram", "control", "debug";
				status = "disabled";
			};

			pru@4b238000 {
				compatible = "ti,am5728-pru-rproc";
				reg = <0x4b238000 0x3000 0x4b224000 0x400 0x4b224400 0x100>;
				reg-names = "iram", "control", "debug";
				status = "disabled";
			};
		};

		pruss@4b280000 {
			compatible = "ti,am5728-pruss";
			ti,hwmods = "pruss2";
			reg = <0x4b280000 0x2000 0x4b282000 0x2000 0x4b290000 0x8000 0x4b2a0000 0x2000 0x4b2a6000 0x2000>;
			reg-names = "dram0", "dram1", "shrdram2", "intc", "cfg";
			interrupts = <0x0 0xc4 0x4 0x0 0xc5 0x4 0x0 0xc6 0x4 0x0 0xc7 0x4 0x0 0xc8 0x4 0x0 0xc9 0x4 0x0 0xca 0x4 0x0 0xcb 0x4>;
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			ranges;
			status = "disabled";

			pru@4b2b4000 {
				compatible = "ti,am5728-pru-rproc";
				reg = <0x4b2b4000 0x3000 0x4b2a2000 0x400 0x4b2a2400 0x100>;
				reg-names = "iram", "control", "debug";
				status = "disabled";
			};

			pru@4b2b8000 {
				compatible = "ti,am5728-pru-rproc";
				reg = <0x4b2b8000 0x3000 0x4b2a4000 0x400 0x4b2a4400 0x100>;
				reg-names = "iram", "control", "debug";
				status = "disabled";
			};
		};

		regulator-abb-mpu {
			compatible = "ti,abb-v3";
			regulator-name = "abb_mpu";
			#address-cells = <0x0>;
			#size-cells = <0x0>;
			clocks = <0xe>;
			ti,settling-time = <0x32>;
			ti,clock-cycles = <0x10>;
			reg = <0x4ae07ddc 0x4 0x4ae07de0 0x4 0x4ae06014 0x4 0x4a003b20 0xc 0x4ae0c158 0x4>;
			reg-names = "setup-address", "control-address", "int-address", "efuse-address", "ldo-address";
			ti,tranxdone-status-mask = <0x80>;
			ti,ldovbb-override-mask = <0x400>;
			ti,ldovbb-vset-mask = <0x1f>;
			ti,abb_info = <0x102ca0 0x0 0x0 0x0 0x2000000 0x1f00000 0x11b340 0x0 0x4 0x0 0x2000000 0x1f00000 0x127690 0x0 0x8 0x0 0x2000000 0x1f00000>;
			linux,phandle = <0xb9>;
			phandle = <0xb9>;
		};

		regulator-abb-ivahd {
			compatible = "ti,abb-v3";
			regulator-name = "abb_ivahd";
			#address-cells = <0x0>;
			#size-cells = <0x0>;
			clocks = <0xe>;
			ti,settling-time = <0x32>;
			ti,clock-cycles = <0x10>;
			reg = <0x4ae07e34 0x4 0x4ae07e24 0x4 0x4ae06010 0x4 0x4a0025cc 0xc 0x4a002470 0x4>;
			reg-names = "setup-address", "control-address", "int-address", "efuse-address", "ldo-address";
			ti,tranxdone-status-mask = <0x40000000>;
			ti,ldovbb-override-mask = <0x400>;
			ti,ldovbb-vset-mask = <0x1f>;
			ti,abb_info = <0x101918 0x0 0x0 0x0 0x2000000 0x1f00000 0x118c30 0x0 0x4 0x0 0x2000000 0x1f00000 0x1312d0 0x0 0x8 0x0 0x2000000 0x1f00000>;
			linux,phandle = <0xba>;
			phandle = <0xba>;
		};

		regulator-abb-dspeve {
			compatible = "ti,abb-v3";
			regulator-name = "abb_dspeve";
			#address-cells = <0x0>;
			#size-cells = <0x0>;
			clocks = <0xe>;
			ti,settling-time = <0x32>;
			ti,clock-cycles = <0x10>;
			reg = <0x4ae07e30 0x4 0x4ae07e20 0x4 0x4ae06010 0x4 0x4a0025e0 0xc 0x4a00246c 0x4>;
			reg-names = "setup-address", "control-address", "int-address", "efuse-address", "ldo-address";
			ti,tranxdone-status-mask = <0x20000000>;
			ti,ldovbb-override-mask = <0x400>;
			ti,ldovbb-vset-mask = <0x1f>;
			ti,abb_info = <0x101918 0x0 0x0 0x0 0x2000000 0x1f00000 0x118c30 0x0 0x4 0x0 0x2000000 0x1f00000 0x1312d0 0x0 0x8 0x0 0x2000000 0x1f00000>;
			linux,phandle = <0xbb>;
			phandle = <0xbb>;
		};

		regulator-abb-gpu {
			compatible = "ti,abb-v3";
			regulator-name = "abb_gpu";
			#address-cells = <0x0>;
			#size-cells = <0x0>;
			clocks = <0xe>;
			ti,settling-time = <0x32>;
			ti,clock-cycles = <0x10>;
			reg = <0x4ae07de4 0x4 0x4ae07de8 0x4 0x4ae06010 0x4 0x4a003b08 0xc 0x4ae0c154 0x4>;
			reg-names = "setup-address", "control-address", "int-address", "efuse-address", "ldo-address";
			ti,tranxdone-status-mask = <0x10000000>;
			ti,ldovbb-override-mask = <0x400>;
			ti,ldovbb-vset-mask = <0x1f>;
			ti,abb_info = <0x10a1d0 0x0 0x0 0x0 0x2000000 0x1f00000 0x127690 0x0 0x4 0x0 0x2000000 0x1f00000 0x138800 0x0 0x8 0x0 0x2000000 0x1f00000>;
			linux,phandle = <0xbc>;
			phandle = <0xbc>;
		};

		voltdm@4a003b20 {
			compatible = "ti,omap5-voltdm";
			#voltdm-cells = <0x0>;
			vbb-supply = <0xb9>;
			reg = <0x4a003b20 0xc>;
			ti,efuse-settings = <0x102ca0 0x0 0x11b340 0x4 0x127690 0x8>;
			ti,absolute-max-voltage-uv = <0x16e360>;
		};

		voltdm@4a0025cc {
			compatible = "ti,omap5-voltdm";
			#voltdm-cells = <0x0>;
			vbb-supply = <0xba>;
			reg = <0x4a0025cc 0xc>;
			ti,efuse-settings = <0x101918 0x0 0x118c30 0x4 0x1312d0 0x8>;
			ti,absolute-max-voltage-uv = <0x16e360>;
		};

		voltdm@4a0025e0 {
			compatible = "ti,omap5-voltdm";
			#voltdm-cells = <0x0>;
			vbb-supply = <0xbb>;
			reg = <0x4a0025e0 0xc>;
			ti,efuse-settings = <0x101918 0x0 0x118c30 0x4 0x1312d0 0x8>;
			ti,absolute-max-voltage-uv = <0x16e360>;
		};

		voltdm@4a003b08 {
			compatible = "ti,omap5-voltdm";
			#voltdm-cells = <0x0>;
			vbb-supply = <0xbc>;
			reg = <0x4a003b08 0xc>;
			ti,efuse-settings = <0x10a1d0 0x0 0x127690 0x4 0x138800 0x8>;
			ti,absolute-max-voltage-uv = <0x16e360>;
		};

		voltdm@4a0025f4 {
			compatible = "ti,omap5-core-voltdm";
			#voltdm-cells = <0x0>;
			reg = <0x4a0025f4 0x4>;
			ti,efuse-settings = <0x10a1d0 0x0>;
			ti,absolute-max-voltage-uv = <0x16e360>;
		};

		spi@48098000 {
			compatible = "ti,omap4-mcspi";
			reg = <0x48098000 0x200>;
			interrupts = <0x0 0x3c 0x4>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			ti,hwmods = "mcspi1";
			ti,spi-num-cs = <0x4>;
			dmas = <0xac 0x23 0xac 0x24 0xac 0x25 0xac 0x26 0xac 0x27 0xac 0x28 0xac 0x29 0xac 0x2a>;
			dma-names = "tx0", "rx0", "tx1", "rx1", "tx2", "rx2", "tx3", "rx3";
			status = "disabled";
		};

		spi@4809a000 {
			compatible = "ti,omap4-mcspi";
			reg = <0x4809a000 0x200>;
			interrupts = <0x0 0x3d 0x4>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			ti,hwmods = "mcspi2";
			ti,spi-num-cs = <0x2>;
			dmas = <0xac 0x2b 0xac 0x2c 0xac 0x2d 0xac 0x2e>;
			dma-names = "tx0", "rx0", "tx1", "rx1";
			status = "disabled";
		};

		spi@480b8000 {
			compatible = "ti,omap4-mcspi";
			reg = <0x480b8000 0x200>;
			interrupts = <0x0 0x56 0x4>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			ti,hwmods = "mcspi3";
			ti,spi-num-cs = <0x1>;
			dmas = <0xac 0xf 0xac 0x10>;
			dma-names = "tx0", "rx0";
			status = "okay";
			pinctrl-names = "default";
			pinctrl-0 = <0xbd>;

			divio@0 {
				compatible = "safran,divio";
				spi-max-frequency = <0x2dc6c00>;
				reg = <0x0>;
				status = "okay";
			};
		};

		spi@480ba000 {
			compatible = "ti,omap4-mcspi";
			reg = <0x480ba000 0x200>;
			interrupts = <0x0 0x2b 0x4>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			ti,hwmods = "mcspi4";
			ti,spi-num-cs = <0x1>;
			dmas = <0xac 0x46 0xac 0x47>;
			dma-names = "tx0", "rx0";
			status = "disabled";
		};

		qspi@4b300000 {
			compatible = "ti,dra7xxx-qspi";
			reg = <0x4b300000 0x100 0x4a002558 0x4 0x5c000000 0x3ffffff>;
			reg-names = "qspi_base", "qspi_ctrlmod", "qspi_mmap";
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			ti,hwmods = "qspi";
			clocks = <0xbe>;
			clock-names = "fck";
			num-cs = <0x4>;
			interrupts = <0x0 0x157 0x4>;
			status = "okay";
			spi-max-frequency = <0x2dc6c00>;

			n25q512a@0 {
				compatible = "micron,n25q512a";
				spi-max-frequency = <0x2dc6c00>;
				reg = <0x0>;
				spi-tx-bus-width = <0x1>;
				spi-rx-bus-width = <0x1>;
				spi-cpol;
				spi-cpha;
				#address-cells = <0x1>;
				#size-cells = <0x1>;

				partition@0 {
					label = "MLO";
					reg = <0x0 0x20000>;
				};

				partition@1 {
					label = "UBOOT";
					reg = <0x20000 0xd0000>;
				};

				partition@2 {
					label = "UBOOT.ENV";
					reg = <0xf0000 0x10000>;
				};

				partition@3 {
					label = "HMRS.ZIMAGE";
					reg = <0x100000 0x8c0000>;
				};

				partition@4 {
					label = "HMRS.DTB";
					reg = <0x9c0000 0x40000>;
				};

				partition@5 {
					label = "HMOS.ZIMAGE";
					reg = <0xa00000 0x31c0000>;
				};

				partition@6 {
					label = "HMOS.DTB";
					reg = <0x3bc0000 0x40000>;
				};

				partition@7 {
					label = "LOADS";
					reg = <0x3c00000 0x400000>;
				};
			};
		};

		control-phy@4a002374 {
			compatible = "ti,control-phy-pipe3";
			reg = <0x4a002374 0x4>;
			reg-names = "power";
			clocks = <0xe>;
			clock-names = "sysclk";
			linux,phandle = <0xbf>;
			phandle = <0xbf>;
		};

		ocp2scp@4a090000 {
			compatible = "ti,omap-ocp2scp";
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			ranges;
			reg = <0x4a090000 0x20>;
			ti,hwmods = "ocp2scp3";

			phy@4A096000 {
				compatible = "ti,phy-pipe3-sata";
				reg = <0x4a096000 0x80 0x4a096400 0x64 0x4a096800 0x40>;
				reg-names = "phy_rx", "phy_tx", "pll_ctrl";
				ctrl-module = <0xbf>;
				clocks = <0xe 0xc0>;
				clock-names = "sysclk", "refclk";
				syscon-pllreset = <0xc1 0x3fc>;
				#phy-cells = <0x0>;
				linux,phandle = <0xca>;
				phandle = <0xca>;
			};

			pciephy@4a094000 {
				compatible = "ti,phy-pipe3-pcie";
				reg = <0x4a094000 0x80 0x4a094400 0x64>;
				reg-names = "phy_rx", "phy_tx";
				ctrl-module = <0xc2>;
				clocks = <0x57 0x58 0xc3 0xc4 0xc5 0x5c>;
				clock-names = "dpll_ref", "dpll_ref_m2", "wkupclk", "refclk", "div-clk", "phy-div";
				#phy-cells = <0x0>;
				linux,phandle = <0xa6>;
				phandle = <0xa6>;
			};

			pciephy@4a095000 {
				compatible = "ti,phy-pipe3-pcie";
				reg = <0x4a095000 0x80 0x4a095400 0x64>;
				reg-names = "phy_rx", "phy_tx";
				ctrl-module = <0xc6>;
				clocks = <0x57 0x58 0xc7 0xc8 0xc9 0x5c>;
				clock-names = "dpll_ref", "dpll_ref_m2", "wkupclk", "refclk", "div-clk", "phy-div";
				#phy-cells = <0x0>;
				status = "disabled";
				linux,phandle = <0xa8>;
				phandle = <0xa8>;
			};
		};

		sata@4a141100 {
			compatible = "snps,dwc-ahci";
			reg = <0x4a140000 0x1100 0x4a141100 0x7>;
			interrupts = <0x0 0x31 0x4>;
			phys = <0xca>;
			phy-names = "sata-phy";
			clocks = <0xc0>;
			ti,hwmods = "sata";
		};

		control-phy@0x4a003c40 {
			compatible = "ti,control-phy-pcie";
			reg = <0x4a003c40 0x4 0x4a003c14 0x4 0x4a003c34 0x4>;
			reg-names = "power", "control_sma", "pcie_pcs";
			clocks = <0xe>;
			clock-names = "sysclk";
			linux,phandle = <0xc2>;
			phandle = <0xc2>;
		};

		control-pcie@0x4a003c44 {
			compatible = "ti,control-phy-pcie";
			reg = <0x4a003c44 0x4 0x4a003c14 0x4 0x4a003c34 0x4>;
			reg-names = "power", "control_sma", "pcie_pcs";
			clocks = <0xe>;
			clock-names = "sysclk";
			status = "disabled";
			linux,phandle = <0xc6>;
			phandle = <0xc6>;
		};

		rtc@48838000 {
			compatible = "ti,am3352-rtc";
			reg = <0x48838000 0x100>;
			interrupts = <0x0 0xd9 0x4 0x0 0xd9 0x4>;
			ti,hwmods = "rtcss";
			clocks = <0x4e>;
			status = "disabled";
		};

		control-phy@4a002300 {
			compatible = "ti,control-phy-usb2";
			reg = <0x4a002300 0x4>;
			reg-names = "power";
			linux,phandle = <0xcb>;
			phandle = <0xcb>;
		};

		control-phy@4a002370 {
			compatible = "ti,control-phy-pipe3";
			reg = <0x4a002370 0x4>;
			reg-names = "power";
			linux,phandle = <0xd1>;
			phandle = <0xd1>;
		};

		control-phy@0x4a002e74 {
			compatible = "ti,control-phy-usb2-dra7";
			reg = <0x4a002e74 0x4>;
			reg-names = "power";
			linux,phandle = <0xce>;
			phandle = <0xce>;
		};

		ocp2scp@4a080000 {
			compatible = "ti,omap-ocp2scp";
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			ranges;
			reg = <0x4a080000 0x20>;
			ti,hwmods = "ocp2scp1";

			phy@4a084000 {
				compatible = "ti,omap-usb2";
				reg = <0x4a084000 0x400>;
				ctrl-module = <0xcb>;
				clocks = <0xcc 0xcd>;
				clock-names = "wkupclk", "refclk";
				#phy-cells = <0x0>;
				linux,phandle = <0xd3>;
				phandle = <0xd3>;
			};

			phy@4a085000 {
				compatible = "ti,omap-usb2";
				reg = <0x4a085000 0x400>;
				ctrl-module = <0xce>;
				clocks = <0xcf 0xd0>;
				clock-names = "wkupclk", "refclk";
				#phy-cells = <0x0>;
				linux,phandle = <0xd5>;
				phandle = <0xd5>;
			};

			phy@4a084400 {
				compatible = "ti,omap-usb3";
				reg = <0x4a084400 0x80 0x4a084800 0x64 0x4a084c00 0x40>;
				reg-names = "phy_rx", "phy_tx", "pll_ctrl";
				ctrl-module = <0xd1>;
				clocks = <0xd2 0xe 0xcd>;
				clock-names = "wkupclk", "sysclk", "refclk";
				#phy-cells = <0x0>;
				linux,phandle = <0xd4>;
				phandle = <0xd4>;
			};
		};

		omap_dwc3_1@48880000 {
			compatible = "ti,dwc3";
			ti,hwmods = "usb_otg_ss1";
			reg = <0x48880000 0x10000>;
			interrupts = <0x0 0x48 0x4>;
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			utmi-mode = <0x2>;
			ranges;

			usb@48890000 {
				compatible = "snps,dwc3";
				reg = <0x48890000 0x17000>;
				interrupts = <0x0 0x47 0x4 0x0 0x47 0x4 0x0 0x48 0x4>;
				interrupt-names = "peripheral", "host", "otg";
				phys = <0xd3 0xd4>;
				phy-names = "usb2-phy", "usb3-phy";
				tx-fifo-resize;
				maximum-speed = "super-speed";
				dr_mode = "otg";
				snps,dis_u3_susphy_quirk;
				snps,dis_u2_susphy_quirk;
			};
		};

		omap_dwc3_2@488c0000 {
			compatible = "ti,dwc3";
			ti,hwmods = "usb_otg_ss2";
			reg = <0x488c0000 0x10000>;
			interrupts = <0x0 0x57 0x4>;
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			utmi-mode = <0x2>;
			ranges;

			usb@488d0000 {
				compatible = "snps,dwc3";
				reg = <0x488d0000 0x17000>;
				interrupts = <0x0 0x49 0x4 0x0 0x49 0x4 0x0 0x57 0x4>;
				interrupt-names = "peripheral", "host", "otg";
				phys = <0xd5>;
				phy-names = "usb2-phy";
				tx-fifo-resize;
				maximum-speed = "high-speed";
				dr_mode = "host";
				snps,dis_u3_susphy_quirk;
				snps,dis_u2_susphy_quirk;
			};
		};

		omap_dwc3_3@48900000 {
			compatible = "ti,dwc3";
			ti,hwmods = "usb_otg_ss3";
			reg = <0x48900000 0x10000>;
			interrupts = <0x0 0x158 0x4>;
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			utmi-mode = <0x2>;
			ranges;
			status = "disabled";

			usb@48910000 {
				compatible = "snps,dwc3";
				reg = <0x48910000 0x17000>;
				interrupts = <0x0 0x58 0x4 0x0 0x58 0x4 0x0 0x158 0x4>;
				interrupt-names = "peripheral", "host", "otg";
				tx-fifo-resize;
				maximum-speed = "high-speed";
				dr_mode = "otg";
				snps,dis_u3_susphy_quirk;
				snps,dis_u2_susphy_quirk;
			};
		};

		elm@48078000 {
			compatible = "ti,am3352-elm";
			reg = <0x48078000 0xfc0>;
			interrupts = <0x0 0x1 0x4>;
			ti,hwmods = "elm";
			status = "okay";
			linux,phandle = <0xd8>;
			phandle = <0xd8>;
		};

		gpmc@50000000 {
			compatible = "ti,am3352-gpmc";
			ti,hwmods = "gpmc";
			reg = <0x50000000 0x37c>;
			interrupts = <0x0 0xf 0x4>;
			gpmc,num-cs = <0x8>;
			gpmc,num-waitpins = <0x2>;
			#address-cells = <0x2>;
			#size-cells = <0x1>;
			gpio-controller;
			#gpio-cells = <0x2>;
			interrupt-controller;
			#interrupt-cells = <0x2>;
			status = "okay";
			ranges = <0x0 0x0 0x8000000 0x1000000>;
			pinctrl-names = "default";
			pinctrl-0 = <0xd6>;
			linux,phandle = <0xd7>;
			phandle = <0xd7>;

			nand@0,0 {
				compatible = "ti,omap2-nand";
				reg = <0x0 0x0 0x4>;
				ready-gpio = <0xd7 0x0 0x0>;
				ti,nand-ecc-opt = "bch8";
				ti,elm-id = <0xd8>;
				nand-bus-width = <0x8>;
				gpmc,device-width = <0x1>;
				gpmc,sync-clk-ps = <0x0>;
				gpmc,cs-on-ns = <0x0>;
				gpmc,cs-rd-off-ns = <0x64>;
				gpmc,cs-wr-off-ns = <0x64>;
				gpmc,adv-on-ns = <0x0>;
				gpmc,adv-rd-off-ns = <0x64>;
				gpmc,adv-wr-off-ns = <0x64>;
				gpmc,we-on-ns = <0xa>;
				gpmc,we-off-ns = <0x3c>;
				gpmc,oe-on-ns = <0x4>;
				gpmc,oe-off-ns = <0x3c>;
				gpmc,access-ns = <0x32>;
				gpmc,wr-access-ns = <0x50>;
				gpmc,rd-cycle-ns = <0x64>;
				gpmc,wr-cycle-ns = <0x64>;
				gpmc,bus-turnaround-ns = <0x0>;
				gpmc,cycle2cycle-delay-ns = <0x0>;
				gpmc,clk-activation-ns = <0x0>;
				gpmc,wait-monitoring-ns = <0x0>;
				gpmc,wr-data-mux-bus-ns = <0x0>;
				#address-cells = <0x1>;
				#size-cells = <0x2>;

				partition@8 {
					label = "NAND";
					reg = <0x0 0x1 0x0>;
				};
			};
		};

		atl@4843c000 {
			compatible = "ti,dra7-atl";
			reg = <0x4843c000 0x3ff>;
			ti,hwmods = "atl";
			ti,provided-clocks = <0x41 0x40 0x3f 0x3e>;
			clocks = <0x7>;
			clock-names = "fck";
			status = "disabled";
		};

		mcasp@48468000 {
			compatible = "ti,dra7-mcasp-audio";
			ti,hwmods = "mcasp3";
			reg = <0x48468000 0x2000 0x46000000 0x1000>;
			reg-names = "mpu", "dat";
			interrupts = <0x0 0x97 0x4 0x0 0x96 0x4>;
			interrupt-names = "tx", "rx";
			dmas = <0xd9 0x85 0xd9 0x84>;
			dma-names = "tx", "rx";
			clocks = <0xda>;
			clock-names = "fck";
			status = "enabled";
		};

		mcasp@4847c000 {
			compatible = "ti,dra7-mcasp-audio";
			ti,hwmods = "mcasp8";
			reg = <0x4847c000 0x2000 0x48454000 0x1000>;
			reg-names = "mpu", "dat";
			interrupts = <0x0 0xa1 0x4 0x0 0xa0 0x4>;
			interrupt-names = "tx", "rx";
			dmas = <0xac 0x8f 0xac 0x8e>;
			dma-names = "tx", "rx";
			clocks = <0xdb>;
			clock-names = "fck";
			status = "disabled";
		};

		crossbar@4a002a48 {
			compatible = "ti,irq-crossbar";
			reg = <0x4a002a48 0x130>;
			interrupt-controller;
			interrupt-parent = <0x3>;
			#interrupt-cells = <0x3>;
			ti,max-irqs = <0xa0>;
			ti,max-crossbar-sources = <0x190>;
			ti,reg-size = <0x2>;
			ti,irqs-reserved = <0x0 0x1 0x2 0x3 0x5 0x6 0x83 0x84>;
			ti,irqs-skip = <0xa 0x85 0x8b 0x8c>;
			ti,irqs-safe-map = <0x0>;
			linux,phandle = <0x1>;
			phandle = <0x1>;
		};

		ethernet@48484000 {
			compatible = "ti,dra7-cpsw", "ti,cpsw";
			ti,hwmods = "gmac";
			clocks = <0x29 0xdc>;
			clock-names = "fck", "cpts";
			cpdma_channels = <0x8>;
			ale_entries = <0x400>;
			bd_ram_size = <0x2000>;
			no_bd_ram = <0x0>;
			rx_descs = <0x40>;
			mac_control = <0x20>;
			slaves = <0x2>;
			active_slave = <0x0>;
			cpts_clock_mult = <0x80000000>;
			cpts_clock_shift = <0x1d>;
			reg = <0x48484000 0x1000 0x48485200 0x2e00>;
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			ti,no-idle;
			interrupts = <0x0 0x14e 0x4 0x0 0x14f 0x4 0x0 0x150 0x4 0x0 0x151 0x4>;
			ranges;
			status = "okay";
			dual_emac;

			mdio@48485000 {
				compatible = "ti,davinci_mdio";
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				ti,hwmods = "davinci_mdio";
				bus_freq = <0xf4240>;
				reg = <0x48485000 0x100>;
			};

			slave@48480200 {
				mac-address = [00 00 00 00 00 00];
				phy-mode = "rmii";
				dual_emac_res_vlan = <0x1>;

				fixed-link {
					speed = <0xa>;
					full-duplex;
				};
			};

			slave@48480300 {
				mac-address = [00 00 00 00 00 00];
				phy-mode = "rmii";
				dual_emac_res_vlan = <0x2>;

				fixed-link {
					speed = <0x64>;
					full-duplex;
				};
			};

			cpsw-phy-sel@4a002554 {
				compatible = "ti,dra7xx-cpsw-phy-sel";
				reg = <0x4a002554 0x4>;
				reg-names = "gmii-sel";
				rmii-clock-ext;
			};
		};

		can@481cc000 {
			compatible = "ti,dra7-d_can";
			ti,hwmods = "dcan1";
			reg = <0x4ae3c000 0x2000>;
			syscon-raminit = <0x4 0x558 0x0>;
			interrupts = <0x0 0xde 0x4>;
			clocks = <0xdd>;
			status = "disabled";
		};

		can@481d0000 {
			compatible = "ti,dra7-d_can";
			ti,hwmods = "dcan2";
			reg = <0x48480000 0x2000>;
			syscon-raminit = <0x4 0x558 0x1>;
			interrupts = <0x0 0xe1 0x4>;
			clocks = <0xe>;
			status = "disabled";
		};

		dss@58000000 {
			compatible = "ti,dra7-dss";
			status = "disabled";
			ti,hwmods = "dss_core";
			syscon-pll-ctrl = <0x4 0x538>;
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			ranges;
			reg = <0x58000000 0x80 0x58004054 0x4 0x58004300 0x20>;
			reg-names = "dss", "pll1_clkctrl", "pll1";
			clocks = <0xde 0xdf>;
			clock-names = "fck", "video1_clk";

			dispc@58001000 {
				compatible = "ti,dra7-dispc";
				reg = <0x58001000 0x1000>;
				interrupts = <0x0 0x14 0x4>;
				ti,hwmods = "dss_dispc";
				clocks = <0xde>;
				clock-names = "fck";
				syscon-pol = <0x4 0x534>;
			};

			encoder@58060000 {
				compatible = "ti,dra7-hdmi";
				reg = <0x58040000 0x200 0x58040200 0x80 0x58040300 0x80 0x58060000 0x19000>;
				reg-names = "wp", "pll", "phy", "core";
				interrupts = <0x0 0x60 0x4>;
				status = "disabled";
				ti,hwmods = "dss_hdmi";
				clocks = <0xe0 0xe1>;
				clock-names = "fck", "sys_clk";
				dmas = <0xac 0x4c>;
				dma-names = "audio_tx";
			};
		};

		epwmss@4843e000 {
			compatible = "ti,dra7xx-pwmss", "ti,am33xx-pwmss";
			reg = <0x4843e000 0x30>;
			ti,hwmods = "epwmss0";
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			status = "disabled";
			ranges = <0x4843e100 0x4843e100 0x80 0x4843e180 0x4843e180 0x80 0x4843e200 0x4843e200 0x80>;

			ehrpwm@4843e200 {
				compatible = "ti,dra7xx-ehrpwm", "ti,am33xx-ehrpwm";
				#pwm-cells = <0x3>;
				reg = <0x4843e200 0x80>;
				ti,hwmods = "ehrpwm0";
				status = "disabled";
			};
		};

		epwmss@48440000 {
			compatible = "ti,dra7xx-pwmss", "ti,am33xx-pwmss";
			reg = <0x48440000 0x30>;
			ti,hwmods = "epwmss1";
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			status = "disabled";
			ranges = <0x48440100 0x48440100 0x80 0x48440180 0x48440180 0x80 0x48440200 0x48440200 0x80>;

			ehrpwm@48440200 {
				compatible = "ti,dra7xx-ehrpwm", "ti,am33xx-ehrpwm";
				#pwm-cells = <0x3>;
				reg = <0x48440200 0x80>;
				ti,hwmods = "ehrpwm1";
				status = "disabled";
			};
		};

		epwmss@48442000 {
			compatible = "ti,dra7xx-pwmss", "ti,am33xx-pwmss";
			reg = <0x48442000 0x30>;
			ti,hwmods = "epwmss2";
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			status = "disabled";
			ranges = <0x48442100 0x48442100 0x80 0x48442180 0x48442180 0x80 0x48442200 0x48442200 0x80>;

			ehrpwm@48442200 {
				compatible = "ti,dra7xx-ehrpwm", "ti,am33xx-ehrpwm";
				#pwm-cells = <0x3>;
				reg = <0x48442200 0x80>;
				ti,hwmods = "ehrpwm2";
				status = "disabled";
			};
		};

		aes@4b500000 {
			compatible = "ti,omap4-aes";
			ti,hwmods = "aes1";
			reg = <0x4b500000 0xa0>;
			interrupts = <0x0 0x50 0x4>;
			dmas = <0xac 0x6f 0xac 0x6e>;
			dma-names = "tx", "rx";
			clocks = <0x5>;
			clock-names = "fck";
		};

		aes@4b700000 {
			compatible = "ti,omap4-aes";
			ti,hwmods = "aes2";
			reg = <0x4b700000 0xa0>;
			interrupts = <0x0 0x3b 0x4>;
			dmas = <0xac 0x72 0xac 0x71>;
			dma-names = "tx", "rx";
			clocks = <0x5>;
			clock-names = "fck";
		};

		des@480a5000 {
			compatible = "ti,omap4-des";
			ti,hwmods = "des";
			reg = <0x480a5000 0xa0>;
			interrupts = <0x0 0x4d 0x4>;
			dmas = <0xac 0x75 0xac 0x74>;
			dma-names = "tx", "rx";
			clocks = <0x5>;
			clock-names = "fck";
		};

		sham@53100000 {
			compatible = "ti,omap5-sham";
			ti,hwmods = "sham";
			reg = <0x4b101000 0x300>;
			interrupts = <0x0 0x2e 0x4>;
			dmas = <0xac 0x77>;
			dma-names = "rx";
			clocks = <0x5>;
			clock-names = "fck";
		};

		rng@48090000 {
			compatible = "ti,omap4-rng";
			ti,hwmods = "rng";
			reg = <0x48090000 0x2000>;
			interrupts = <0x0 0x2f 0x4>;
			clocks = <0x5>;
			clock-names = "fck";
		};

		vpe {
			compatible = "ti,vpe";
			ti,hwmods = "vpe";
			clocks = <0x7d>;
			clock-names = "fck";
			reg = <0x489d0000 0x120 0x489d0300 0x20 0x489d0400 0x20 0x489d0500 0x20 0x489d0600 0x3c 0x489d0700 0x80 0x489d5700 0x18 0x489dd000 0x400>;
			reg-names = "vpe_top", "vpe_chr_us0", "vpe_chr_us1", "vpe_chr_us2", "vpe_dei", "sc", "csc", "vpdma";
			interrupts = <0x0 0x162 0x4>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
		};

		vip@0x48970000 {
			compatible = "ti,vip1";
			reg = <0x48970000 0x10000 0x4897d000 0x1000>;
			reg-names = "vip", "vpdma";
			ti,hwmods = "vip1";
			interrupts = <0x0 0x15f 0x4 0x0 0x188 0x4>;
			syscon = <0xc1>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			status = "disabled";

			port@0 {
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				reg = <0x0>;
				status = "disabled";
			};

			port@1 {
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				reg = <0x1>;
				status = "disabled";
			};

			port@2 {
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				reg = <0x2>;
				status = "disabled";
			};

			port@3 {
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				reg = <0x3>;
				status = "disabled";
			};
		};

		vip@0x48990000 {
			compatible = "ti,vip2";
			reg = <0x48990000 0x10000 0x4899d000 0x1000>;
			reg-names = "vip", "vpdma";
			ti,hwmods = "vip2";
			interrupts = <0x0 0x160 0x4 0x0 0x189 0x4>;
			syscon = <0xc1>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			status = "disabled";

			port@0 {
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				reg = <0x0>;
				status = "disabled";
			};

			port@1 {
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				reg = <0x1>;
				status = "disabled";
			};

			port@2 {
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				reg = <0x2>;
				status = "disabled";
			};

			port@3 {
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				reg = <0x3>;
				status = "disabled";
			};
		};

		vip@0x489b0000 {
			compatible = "ti,vip3";
			reg = <0x489b0000 0x10000 0x489bd000 0x1000>;
			reg-names = "vip", "vpdma";
			ti,hwmods = "vip3";
			interrupts = <0x0 0x161 0x4 0x0 0x18a 0x4>;
			syscon = <0xc1>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			status = "disabled";

			port@0 {
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				reg = <0x0>;
				status = "disabled";
			};

			port@1 {
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				reg = <0x1>;
				status = "disabled";
			};
		};

		cal@4845b000 {
			compatible = "ti,cal";
			ti,hwmods = "cal";
			reg = <0x4845b000 0x400 0x4845b800 0x40 0x4845b900 0x40 0x4a002e94 0x4>;
			reg-names = "cal_top", "cal_rx_core0", "cal_rx_core1", "camerrx_control";
			interrupts = <0x0 0x77 0x4>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			status = "disabled";

			port@0 {
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				reg = <0x0>;
			};

			port@1 {
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				reg = <0x1>;
			};
		};

		debugss {
			compatible = "ti,dra7xx-debugss";
			clocks = <0xe>;
			clock-names = "sysclockin1";
		};
	};

	thermal-zones {

		cpu_thermal {
			polling-delay-passive = <0xfa>;
			polling-delay = <0x1f4>;
			thermal-sensors = <0xe2 0x0>;

			trips {

				cpu_alert {
					temperature = <0x186a0>;
					hysteresis = <0x7d0>;
					type = "passive";
					linux,phandle = <0xe3>;
					phandle = <0xe3>;
				};

				cpu_crit {
					temperature = <0x1e848>;
					hysteresis = <0x7d0>;
					type = "critical";
				};
			};

			cooling-maps {

				map0 {
					trip = <0xe3>;
					cooling-device = <0xe4 0xffffffff 0xffffffff>;
				};
			};
		};

		gpu_thermal {
			polling-delay-passive = <0xfa>;
			polling-delay = <0x1f4>;
			thermal-sensors = <0xe2 0x1>;

			trips {

				gpu_crit {
					temperature = <0x1e848>;
					hysteresis = <0x7d0>;
					type = "critical";
				};
			};
		};

		core_thermal {
			polling-delay-passive = <0xfa>;
			polling-delay = <0x1f4>;
			thermal-sensors = <0xe2 0x2>;

			trips {

				core_crit {
					temperature = <0x1e848>;
					hysteresis = <0x7d0>;
					type = "critical";
				};
			};
		};
	};

	cpus {
		#address-cells = <0x1>;
		#size-cells = <0x0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x0>;
			cooling-min-level = <0x0>;
			cooling-max-level = <0x2>;
			#cooling-cells = <0x2>;
			operating-points = <0xf4240 0x102ca0>;
			clocks = <0x15>;
			clock-names = "cpu";
			clock-latency = <0x493e0>;
			linux,phandle = <0xe4>;
			phandle = <0xe4>;
		};
	};

	pinmux@4a002e8c {
		compatible = "pinctrl-single";
		reg = <0x4a002e8c 0x4>;
		#address-cells = <0x1>;
		#size-cells = <0x0>;
		pinctrl-single,register-width = <0x20>;
		pinctrl-single,function-mask = <0x7f>;
	};

	pmu {
		compatible = "arm,cortex-a15-pmu";
		interrupt-parent = <0x3>;
		interrupts = <0x0 0x83 0x4>;
	};

	reserved-memory {
		#address-cells = <0x1>;
		#size-cells = <0x1>;
		ranges;

		dsp1_cma@99000000 {
			compatible = "shared-dma-pool";
			reg = <0x99000000 0x4000000>;
			reusable;
			status = "okay";
			linux,phandle = <0xb1>;
			phandle = <0xb1>;
		};

		cmem_block_mem@90000000 {
			reg = <0x90000000 0x5800000>;
			no-map;
			status = "okay";
			linux,phandle = <0xe5>;
			phandle = <0xe5>;
		};
	};

	cmem {
		compatible = "ti,cmem";
		#address-cells = <0x1>;
		#size-cells = <0x0>;
		#pool-size-cells = <0x2>;
		status = "okay";

		cmem_block@0 {
			reg = <0x0>;
			memory-region = <0xe5>;
			cmem-buf-pools = <0x1 0x0 0x5800000>;
		};
	};
};