--ram_model
-heap  0x20000
-stack 0x20000
--args 0x1000
--diag_suppress=10068 /* to suppress no matching section error */
--cinit_compression=off
-e _c_int00_secure

#define DDR0_ALLOCATED_START  0x80000000
#define C7X_ALLOCATED_START DDR0_ALLOCATED_START // + 0x19800000

#define C7X_RESOURCE_TABLE_BASE (C7X_ALLOCATED_START + 0x00100000)
#define C7X_BOOT_BASE           (C7X_ALLOCATED_START + 0x00200000)
#define C7X_VECTOR_BASE         (C7X_ALLOCATED_START + 0x00400000)
#define C7X_DDR_SPACE_BASE      (C7X_ALLOCATED_START + 0x00410000)

MEMORY
{
    L2SRAM_CINIT (RWX)  : org = 0x7E000000, len = 0x000100 //for 256byte init
 	L2SRAM (RWX)        : org = 0x7E000100, len = 0x0fff00 //for 1MBytes  EL2
  	L2SRAMAUX   (RWX): org = 0x7F000000, len = 0x040000   // for 256 KBytes AM62A
  	L1DSRAM  (RWX): org = 0x64E00000, len = 0x004000   // 16kB, for J7
//    DDR0_RESERVED: org = 0x80000000,          len = 0x19800000   /*  Reserved for A53 OS */
    C7X_IPC_D:     org = C7X_ALLOCATED_START, len = 0x00100000   /*  1MB DDR */
    C7X_BOOT_D:    org = C7X_BOOT_BASE,       len = 0x400        /*  1024B DDR */
    C7X_VECS_D:    org = C7X_VECTOR_BASE,     len = 0x4000       /*  16KB DDR */
    C7X_CIO_MEM:   org = C7X_DDR_SPACE_BASE,  len = 0x1000       /*  4KB DDR */


  	EXTMEM_STATIC   (RWX): org = C7X_DDR_SPACE_BASE+0x1000, len = 0x600000
  	EXTMEM_DATACN   (RWX): org = 0x80A11000, len = 0x200000
  	EXTMEM          (RWX): org = 0x80C11000, len = 0x200000
    C7X_DDR_SPACE: org = 0x80E11000, len = 0x19800000-0x1000  /*  27.9MB - 4KB DDR  */
}

SECTIONS
{

    boot:
    {
      boot.*<boot.oe71>(.text)
    } load > C7X_BOOT_D ALIGN(0x200000)
    .vecs       >       C7X_VECS_D ALIGN(0x400000)
    .secure_vecs    >   C7X_DDR_SPACE ALIGN(0x200000)
    .l1dmemory        > L2SRAM
  	.l2dmemory        > L2SRAM
	.text:            > EXTMEM
	.text:touch:      > EXTMEM
	.text:_c_int00:   > L2SRAM_CINIT
	.neardata:        > EXTMEM
  	.rodata:          > EXTMEM
  	.bss:             > EXTMEM
  	RUN_START(__BSS_START)
    RUN_END(__BSS_END)
  	.init_array:      > EXTMEM
  	.far:             > EXTMEM
  	.fardata:         > EXTMEM
  	.neardata         > EXTMEM
  	.rodata           > EXTMEM
  	.data:            > EXTMEM
  	.switch:          > EXTMEM
  	.stack:           > L2SRAM
  	.args:            > EXTMEM align = 0x4, fill = 0 {_argsize = 0x200; }
  	.sysmem:          > C7X_DDR_SPACE
  	.cinit:           > EXTMEM
  	.const:           > L2SRAM START(const_start) SIZE(const_size)
  	.pinit:           > L2SRAM
  	.cio:             > L2SRAM
  	.stack:           > EXTMEM
  	.ddrData          > EXTMEM_DATACN
  	.staticData       > EXTMEM_STATIC
  	.l2sramaux        > L2SRAMAUX
  	 GROUP:              >  C7X_DDR_SPACE
    {
        .data.Mmu_tableArray          : type=NOINIT
        .data.Mmu_tableArraySlot      : type=NOINIT
        .data.Mmu_level1Table         : type=NOINIT
        .data.gMmu_tableArray_NS       : type=NOINIT
        .data.Mmu_tableArraySlot_NS   : type=NOINIT
        .data.Mmu_level1Table_NS      : type=NOINIT
    }
  	xdc.meta:        > L2SRAM, type = COPY
}