/**
 *  \file   nandDma.c
 *
 *  \brief  This file contains the NAND DMA related functions definitions.
 *
 */

/*
* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ 
*/
/* 
*  Redistribution and use in source and binary forms, with or without 
*  modification, are permitted provided that the following conditions 
*  are met:
*
*    Redistributions of source code must retain the above copyright 
*    notice, this list of conditions and the following disclaimer.
*
*    Redistributions in binary form must reproduce the above copyright
*    notice, this list of conditions and the following disclaimer in the 
*    documentation and/or other materials provided with the   
*    distribution.
*
*    Neither the name of Texas Instruments Incorporated nor the names of
*    its contributors may be used to endorse or promote products derived
*    from this software without specific prior written permission.
*
*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/

#include <stdint.h>
#include <stddef.h>
#include <stdio.h>
#include <string.h>
#include <ti/csl/csl_gpmc.h>
#include <ti/csl/src/ip/gpmc/V1/gpmc.h>
#include <ti/boot/sbl_auto/nandflash/nand_flash.h>
#include <ti/boot/sbl_auto/nandflash/nand_gpmc.h>
#if defined (SOC_TDA2XX) || defined (SOC_TDA2EX)
#include <ti/csl/csl_wd_timer.h>
#endif

#include <ti/csl/soc.h>
#include <ti/drv/stw_lld/platform/platform.h>
#include <ti/csl/csl_types.h>
#include <ti/csl/src/ip/gpmc/V1/hw_gpmc.h>
#include <ti/csl/src/ip/elm/V0/elm.h>
#include "nandDma.h"
//#include <ti/csl/arch/a15/interrupt.h>
//#include <ti/csl/arch/m4/interrupt.h>
#include <ti/csl/csl_edma.h>
#include <ti/csl/arch/csl_arch.h>
/*
#include "hw_types.h"
#include "interrupt.h"
#include "gpmc.h"
#include "edma.h"
#include "soc_AM335x.h"
#include "nandlib.h"

*/
/*******************************************************************************
*                       INTERNAL MACRO DEFINITIONS
*******************************************************************************/
#define EDMA_TPCC_BASE_ADDR	SOC_EDMA_TPCC_BASE_VIRT//SOC_DSP1_EDMA_CC_BASE//SOC_EDMA_TPCC_BASE_VIRT

/*****************************************************************************/
/*
** Macros which defines the DMA related info like event Q num, TCC num, channel
** num etc.


#define EDMA3_CC_XFER_COMPLETION_INT            (34U)
#define XBAR_INST_CC_XFER_COMPLETION            (CSL_XBAR_INST_IPU1_IRQ_34)
#define XBAR_INTR_SOURCE_CC_XFER_COMPLETION     (CSL_XBAR_EDMA_TPCC_IRQ_REGION1)
*/
#define GPMC_EDMA_TCC_NUM                       (3)
#define REGION_NUMBER                           (0)
#define GPMC_NAND_PREFETCH_FIFO_THRLD           (64)
#define DMA_XBAR_INST        	CSL_XBAR_INST_DMA_EDMA_DREQ_3				
#define DMA_XBAR_INST_SRC  	CSL_XBAR_DMA_GPMC_DREQ
/* EDMA3 Event queue number. */
#define EVTNT_QUEUE_NUM                       (0U)

#define SYS_INT_EDMACOMPINT 46//12
//#define SYS_INT_EDMAERRINT 47//14
//#define EDMA3CC_CCERR_TCCERR_SHIFT 0x10

#define GPMC_IRQNum            (CSL_XBAR_INST_DSP1_IRQ_46)					      
#define GPMC_XBarIRQNum    (CSL_XBAR_GPMC_IRQ)

/******************************************************************************
**                      INTERNAL VARIABLE DEFINITIONS
*******************************************************************************/
static void EDMA3INTCConfigure(void);
static volatile unsigned int xferCompFlag = 0;
#define TRANSFERMODE	EDMA3_TRIG_MODE_EVENT        //EDMA3_TRIG_MODE_MANUAL);//EDMA3_TRIG_MODE_EVENT);


/******************************************************************************
**                      INTERNAL FUNCTION DEFINITIONS
*******************************************************************************/

/** @brief Base address of Channel controller  memory mapped registers        */
//#define SOC_EDMA_TPCC__BASE                          (0x43300000U)
/* Virtual and Physical address for EDMA is same in non-M4 core */
//#define EDMA_TPCC_BASE_ADDR                  SOC_EDMA_TPCC__BASE

/******************************************************************************
*                                                                             *
* \brief  This function is used as a callback from EDMA3 Completion Handler.  *
*                                                                             *
* \param  tccNum    TCC number.\n                                             *
*                                                                             *
* \param  status    EDMA tranfer status.\n                                    *
*                                                                             *
* \param  appData   Application Data.\n                                       *
*                                                                             *
* \return none.                                                               *
*                                                                             *
******************************************************************************/
static void callback(unsigned int tccNum, unsigned int status, void *appData)
{
    if(EDMA3_XFER_COMPLETE == status)
    {
        /* Transfer completed successfully                           */
        EDMA3DisableTransfer(EDMA_TPCC_BASE_ADDR, tccNum,//GPMC_EDMA_TCC_NUM,
                            TRANSFERMODE);// EDMA3_TRIG_MODE_MANUAL);//EDMA3_TRIG_MODE_EVENT);
        EDMA3ClrCCErr(EDMA_TPCC_BASE_ADDR, tccNum);//GPMC_EDMA_TCC_NUM);
        xferCompFlag = 1;
    }
}

/******************************************************************************
*                                                                             *
* \brief   Interrupt ISR for Channel controller error.                        *
*                                                                             *
* \note    This function first disables its own interrupt to make it non-     *
*          entrant.                                                           *
*                                                                             *
* \return  None.                                                              *
*                                                                             *
******************************************************************************/
//static void Edma3CCErrorIsr()
//{
//    volatile unsigned int pendingIrqs;
//    volatile unsigned int evtqueNum = 0;
//    volatile unsigned int isIPRH = 0;
//    volatile unsigned int isIPR = 0;
//    volatile unsigned int Cnt = 0u;
//    volatile unsigned int index;
//
//
//    pendingIrqs = 0u;
//    index = 1u;
//
//    isIPR  = EDMA3GetIntrStatus(EDMA_TPCC_BASE_ADDR);
//    isIPRH = EDMA3IntrStatusHighGet(EDMA_TPCC_BASE_ADDR);
//
//
//    if((isIPR | isIPRH ) || (EDMA3QdmaGetErrIntrStatus(EDMA_TPCC_BASE_ADDR) != 0)
//        || (EDMA3GetCCErrStatus(EDMA_TPCC_BASE_ADDR) != 0))
//    {
//        /* Loop for EDMA3CC_ERR_HANDLER_RETRY_COUNT number of time,
//         * breaks when no pending interrupt is found
//         */
//        while ((Cnt < EDMA3CC_ERR_HANDLER_RETRY_COUNT)
//                    && (index != 0u))
//        {
//            index = 0u;
//
//            if(isIPR)
//            {
//                   pendingIrqs = EDMA3GetErrIntrStatus(EDMA_TPCC_BASE_ADDR);
//            }
//            else
//            {
//                   pendingIrqs = EDMA3ErrIntrHighStatusGet(EDMA_TPCC_BASE_ADDR);
//            }
//
//            while (pendingIrqs)
//            {
//                   /*Process all the pending interrupts*/
//                   if(TRUE == (pendingIrqs & 1u))
//                   {
//                        /* Write to EMCR to clear the corresponding EMR bits. */
//                        /* Clear any SER */
//
//                        if(isIPR)
//                        {
//                             EDMA3ClrMissEvt(EDMA_TPCC_BASE_ADDR, index);
//                        }
//                        else
//                        {
//                             EDMA3ClrMissEvt(EDMA_TPCC_BASE_ADDR, index + 32);
//                        }
//                   }
//                   ++index;
//                   pendingIrqs >>= 1u;
//            }
//            index = 0u;
//            pendingIrqs = EDMA3QdmaGetErrIntrStatus(EDMA_TPCC_BASE_ADDR);
//            while (pendingIrqs)
//            {
//                /* Process all the pending interrupts */
//                if(TRUE == (pendingIrqs & 1u))
//                {
//                    /* Here write to QEMCR to clear the corresponding QEMR bits */
//                    /* Clear any QSER */
//                    EDMA3QdmaClrMissEvt(EDMA_TPCC_BASE_ADDR, index);
//                }
//                ++index;
//                pendingIrqs >>= 1u;
//            }
//            index = 0u;
//
//
//            pendingIrqs = EDMA3GetCCErrStatus(EDMA_TPCC_BASE_ADDR);
//            if (pendingIrqs != 0u)
//            {
//            /* Process all the pending CC error interrupts. */
//            /* Queue threshold error for different event queues.*/
//            for (evtqueNum = 0u; evtqueNum < SOC_EDMA3_NUM_EVQUE; evtqueNum++)
//                {
//                if((pendingIrqs & (1u << evtqueNum)) != 0u)
//                {
//                        /* Clear the error interrupt. */
//                        EDMA3ClrCCErr(EDMA_TPCC_BASE_ADDR, (1u << evtqueNum));
//                    }
//                }
//
//            /* Transfer completion code error. */
//            if ((pendingIrqs & (1 << EDMA3CC_CCERR_TCCERR_SHIFT)) != 0u)
//            {
//                EDMA3ClrCCErr(EDMA_TPCC_BASE_ADDR,
//                                      (0x01u << EDMA3CC_CCERR_TCCERR_SHIFT));
//            }
//                ++index;
//            }
//            Cnt++;
//        }
//    }
//}

/******************************************************************************
*                                                                             *
* \brief   ISR for successful transfer completion.                            *
*                                                                             *
* \note    This function first disables its own interrupt to make it non-     *
*          entrant.                                                           *
*                                                                             *
* \return  None.                                                              *
*                                                                             *
******************************************************************************/
static void Edma3CompletionIsr(void)
{
    volatile unsigned int pendingIrqs;
    volatile unsigned int isIPR = 0;
    volatile unsigned int isIPRH = 0;

    unsigned int indexl;
    unsigned int Cnt = 0;

    indexl = 1u;
    isIPR  = EDMA3GetIntrStatus(EDMA_TPCC_BASE_ADDR);
    isIPRH = EDMA3IntrStatusHighGet(EDMA_TPCC_BASE_ADDR);
  //Intc_SystemDisable(46);
    if(isIPR | isIPRH)
    {
        while ((Cnt < EDMA3CC_COMPL_HANDLER_RETRY_COUNT)&& (indexl != 0u))
        {
              indexl = 0u;

              if(isIPR)
              {
                   pendingIrqs = EDMA3GetIntrStatus(EDMA_TPCC_BASE_ADDR);
              }
              else
              {
                   pendingIrqs = EDMA3IntrStatusHighGet(EDMA_TPCC_BASE_ADDR);
              }
              while (pendingIrqs)
              {
                   if(TRUE == (pendingIrqs & 1u))
                   {
                        /**
                         * If the user has not given any callback function
                         * while requesting the TCC, its TCC specific bit
                         * in the IPR register will NOT be cleared.
                         */
                         if(isIPR)
                         {
                              /* Here write to ICR to clear the corresponding 
                                 IPR bits */
                              EDMA3ClrIntr(EDMA_TPCC_BASE_ADDR, indexl);
                              callback(indexl, EDMA3_XFER_COMPLETE, NULL);
                         }
                         else
                         {
                              /* Here write to ICR to clear the corresponding 
                                 IPR bits */
                              EDMA3ClrIntr(EDMA_TPCC_BASE_ADDR, indexl + 32);
                              callback(indexl, EDMA3_XFER_COMPLETE, NULL);
                        }
                   }
              ++indexl;
              pendingIrqs >>= 1u;
             }
             Cnt++;
         }
     }
}

/******************************************************************************
*                                                                             *
* \brief  This function configs the DMA for read.\n                           *
*                                                                             *
* \param  csBaseAddr    Chipselect base address                               *
*                                                                             *
* \param  data          Data pointer for read data                            *
*                                                                             *
* \param  len           Byte count to read                                    *
*                                                                             *
* \return none.                                                               *
*                                                                             *
******************************************************************************/
static unsigned int GPMCNANDRxDmaConfig(unsigned int csBaseAddr, unsigned char *data,
                                unsigned int len)
{
	unsigned int ret=0;
    EDMA3CCPaRAMEntry paramSet;
    
    //EDMA3ClrIntr(EDMA_TPCC_BASE_ADDR, GPMC_EDMA_TCC_NUM);
    
    /* Fill the PaRAM Set with transfer specific information    */
    paramSet.aCnt       = GPMC_NAND_PREFETCH_FIFO_THRLD;
    paramSet.bCnt       = (len/GPMC_NAND_PREFETCH_FIFO_THRLD);
    paramSet.bCntReload = 0u;
    paramSet.cCnt       = 1u;
    paramSet.destAddr   = (unsigned int )(data);
    paramSet.destBIdx   = GPMC_NAND_PREFETCH_FIFO_THRLD;
    paramSet.destCIdx   = 1;
    paramSet.linkAddr   = 0xFFFFu;
    paramSet.srcAddr    = csBaseAddr;
    paramSet.srcBIdx    = 0;
    paramSet.srcCIdx    = 0;
    //paramSet.opt = 0x00000000u;
    ///* Src & Dest are in INCR modes */
    //paramSet.opt &= 0xFFFFFFFCu;
    ///* Setting the Transfer Complete Code(TCC). */
    //paramSet.opt |= (( GPMC_EDMA_TCC_NUM << EDMA_TC_POPT_TCC_SHIFT)
    //                   & EDMA_TC_POPT_TCC_MASK);
    ///* Enabling the Completion Interrupt. */
    //paramSet.opt |= (1 << EDMA_TC_POPT_TCINTEN_SHIFT);
    paramSet.opt = (uint32_t) 0x0; 
    paramSet.opt |= (1 << EDMA_TPCC_OPT_SYNCDIM_SHIFT);  
    paramSet.opt |=                                                    
        ((GPMC_EDMA_TCC_NUM << EDMA_TPCC_OPT_TCC_SHIFT) & EDMA_TPCC_OPT_TCC_MASK);
    paramSet.opt |= (1 << EDMA_TPCC_OPT_TCINTEN_SHIFT);    
        
   /* Map Param Set to Channel */
    //EDMA3ChannelToParamMap(EDMA_TPCC_BASE_ADDR, GPMC_EDMA_TCC_NUM, 1);

        
    /* Now, write the PaRAM Set.                                */
    EDMA3SetPaRAM(EDMA_TPCC_BASE_ADDR, GPMC_EDMA_TCC_NUM, &paramSet);

    
    /* Now enable the transfer                                  */
    ret = EDMA3EnableTransfer(EDMA_TPCC_BASE_ADDR, GPMC_EDMA_TCC_NUM, TRANSFERMODE  );
    
    EDMA3INTCConfigure();
    return ret;
}

/******************************************************************************
*                                                                             *
* \brief  This function configs the DMA for write.\n                          *
*                                                                             *
* \param  csBaseAddr    Chipselect base address                               *
*                                                                             *
* \param  data          Data pointer for write data                           *
*                                                                             *
* \param  len           Byte count to write                                   *
*                                                                             *
* \return none.                                                               *
*                                                                             *
******************************************************************************/
static unsigned int GPMCNANDTxDmaConfig(unsigned int csBaseAddr,
                                unsigned char *data, unsigned int len)
{
    EDMA3CCPaRAMEntry paramSet;
    /* Fill the PaRAM Set with transfer specific information    */
    paramSet.aCnt       = GPMC_NAND_PREFETCH_FIFO_THRLD;
    paramSet.bCnt       = (len/GPMC_NAND_PREFETCH_FIFO_THRLD);
    paramSet.bCntReload = 0u;
    paramSet.cCnt       = 1u;
    //paramSet.destAddr   = nandInfo->nandCtrlInfo.dataRegAddr;
    paramSet.destAddr   = csBaseAddr;
    paramSet.destBIdx   = 0;
    paramSet.destCIdx   = 0;
    paramSet.linkAddr   = 0xFFFFu;
    paramSet.srcAddr    = (unsigned int )(data);
    paramSet.srcBIdx    = GPMC_NAND_PREFETCH_FIFO_THRLD;
    paramSet.srcCIdx    = 1;
    //paramSet.opt = 0x00000000u;
    ///* Src & Dest are in INCR modes */
    //paramSet.opt &= 0xFFFFFFFCu;
    ///* Setting the Transfer Complete Code(TCC). */
    //paramSet.opt |= (( GPMC_EDMA_TCC_NUM << EDMA_TC_POPT_TCC_SHIFT)
    //                   & EDMA_TC_POPT_TCC_MASK);
    ///* Enabling the Completion Interrupt. */
    //paramSet.opt |= (1 << EDMA_TC_POPT_TCINTEN_SHIFT);
    paramSet.opt = (uint32_t) 0x0; 
    paramSet.opt |= (1 << EDMA_TPCC_OPT_SYNCDIM_SHIFT);  
    paramSet.opt |=                                                    
        ((GPMC_EDMA_TCC_NUM << EDMA_TPCC_OPT_TCC_SHIFT) & EDMA_TPCC_OPT_TCC_MASK);
    paramSet.opt |= (1 << EDMA_TPCC_OPT_TCINTEN_SHIFT);    
        
    /* Map Param Set to Channel */
    //EDMA3ChannelToParamMap(EDMA_TPCC_BASE_ADDR, GPMC_EDMA_TCC_NUM, 1);

    
    /* Now, write the PaRAM Set.                                */
    EDMA3SetPaRAM(EDMA_TPCC_BASE_ADDR, GPMC_EDMA_TCC_NUM, &paramSet);
    /* Now enable the transfer                                  */
    return EDMA3EnableTransfer(EDMA_TPCC_BASE_ADDR, GPMC_EDMA_TCC_NUM,TRANSFERMODE);
}

/******************************************************************************
*                                                                             *
* \brief  This function configures the INTC to receive EDMA3 interrupts.      *
*                                                                             *
******************************************************************************/
static void EDMA3INTCConfigure(void)
{
	//Intc_SystemDisable(SYS_INT_EDMACOMPINT);
	//Intc_IntUnregister(SYS_INT_EDMACOMPINT); 
	//Intc_IntDisable();
	//Intc_IntClrPend(SYS_INT_EDMACOMPINT);
	
		  /* XBar configuration */
   	CSL_xbarIrqConfigure(CSL_XBAR_IRQ_CPU_ID_DSP1,
                            GPMC_IRQNum,
                            GPMC_XBarIRQNum);
    /* Initializing the ARM Interrupt Controller. */
    Intc_Init();
 /* Enabling IRQ in CPSR of ARM processor. */
    	Intc_IntEnable(0);//IntMasterIRQEnable();
    	
    /* Registering EDMA3 Channel Controller 0 transfer completion interrupt.  */
    Intc_IntRegister(SYS_INT_EDMACOMPINT, (IntrFuncPtr)Edma3CompletionIsr,NULL);
 
    /* Setting the priority for EDMA3CC0 completion interrupt in AINTC. */
    Intc_IntPrioritySet(SYS_INT_EDMACOMPINT, 1, 0);
    
    /* Registering EDMA3 Channel Controller 0 Error Interrupt. */
//    Intc_IntRegister(SYS_INT_EDMAERRINT, (IntrFuncPtr)Edma3CCErrorIsr,NULL);
    
    /* Setting the priority for EDMA3CC0 Error interrupt in AINTC. */
   // Intc_IntPrioritySet(SYS_INT_EDMAERRINT, 0, AINTC_HOSTINT_ROUTE_IRQ);
       
    /* Enabling the EDMA3CC0 completion interrupt in AINTC. */
    Intc_SystemEnable(SYS_INT_EDMACOMPINT);
   
    /* Enabling the EDMA3CC0 Error interrupt in AINTC. */
//    Intc_SystemEnable(SYS_INT_EDMAERRINT);    

    	
}


/******************************************************************************
**                       GLOBAL FUNCTION DEFINITIONS
*******************************************************************************/

/******************************************************************************
*                                                                             *
* \brief  This function setup the DMA for read/write                          *
*                                                                             *
* \param  nandInfo      Pointer to the strucure containing controller and     *
*                       device info.                                          *
*                                                                             *
* \param  data          Data pointer                                          *
*                                                                             *
* \param  dir           Direction which specifies the direction of transfer   *
*                       i.e read/write.                                       *
*                                                                             *
* \param  len           Byte count                                            *
*                                                                             *
* \return none.                                                               *
*                                                                             *
******************************************************************************/
void GPMCNANDXferSetup(NandInfo_t *nandInfo, unsigned char *data,
                       unsigned int len, NandDmaDir_t dir)
{
    unsigned int currCS = nandInfo->hNandCtrlInfo->currChipSelect;
    unsigned int csBase = nandInfo->hNandCtrlInfo->chipSelectBaseAddr[currCS];
    xferCompFlag  = 0;
    if(dir == NAND_DMA_DIR_READ)
    {
        GPMCNANDRxDmaConfig(csBase, data, len);
    }
    else
    {
        GPMCNANDTxDmaConfig(csBase, data, len);
    }
}

/******************************************************************************
*                                                                             *
* \brief  This function returns the status of the DMA transfer.               *
*                                                                             *
* \param  none.                                                               *
*                                                                             *
* \return DMA Xfer status.                                                    *
*                                                                             *
******************************************************************************/
unsigned int GPMCNANDXferStatusGet()
{
    return (xferCompFlag);
    /*
   unsigned int ret =  ((EDMA3GetIntrStatus(EDMA_TPCC_BASE_ADDR) &
                ((uint32_t) 1U <<GPMC_EDMA_TCC_NUM)) );
       if(ret == ((uint32_t) 1U <<GPMC_EDMA_TCC_NUM) )
       {
       	 EDMA3DisableTransfer(EDMA_TPCC_BASE_ADDR, GPMC_EDMA_TCC_NUM, TRANSFERMODE);
       	 EDMA3ClrIntr(EDMA_TPCC_BASE_ADDR, GPMC_EDMA_TCC_NUM);
       }
       return ret;
       */
}

/******************************************************************************
*                                                                             *
* \brief  This function Initializs the DMA for read/write.                    *
*                                                                             *
* \note unused argument is added for future use.                              *
*                                                                             *
******************************************************************************/
void GPMCNANDEdmaInit(void *unused)
{
	
    	/* Initialization of EDMA3 */  
    	/* Enable EDMA TPTC and TPTC modules */    
    	EDMAsetRegion(REGION_NUMBER);
    	EDMA3Init(EDMA_TPCC_BASE_ADDR, EVTNT_QUEUE_NUM);//EDMA3Init

   	/* Configuring the INTC to receive EDMA3 interrupts. */
    	//EDMA3INTCConfigure();
    	
    	
	CSL_xbarDmaConfigure(	CSL_XBAR_DMA_CPU_ID_EDMA,
				DMA_XBAR_INST,
                            		DMA_XBAR_INST_SRC);
    	
    	/* Request DMA Channel and TCC for NAND data movement. */
    	EDMA3RequestChannel(	EDMA_TPCC_BASE_ADDR,
    				EDMA3_CHANNEL_TYPE_DMA,
    				GPMC_EDMA_TCC_NUM,
    				GPMC_EDMA_TCC_NUM,
    				EVTNT_QUEUE_NUM);
    	//EDMA3ClrIntr(EDMA_TPCC_BASE_ADDR, GPMC_EDMA_TCC_NUM);	
    	EDMA3SetEvt(EDMA_TPCC_BASE_ADDR,GPMC_EDMA_TCC_NUM);
    	    EDMA3EnableDmaEvt(EDMA_TPCC_BASE_ADDR,GPMC_EDMA_TCC_NUM);
    	EDMA3EnableEvtIntr(EDMA_TPCC_BASE_ADDR,GPMC_EDMA_TCC_NUM);
    	EDMA3ClrIntr(EDMA_TPCC_BASE_ADDR,GPMC_EDMA_TCC_NUM);
    			
}

/******************************************************************************
**                              END OF FILE
*******************************************************************************/

